This source file includes following definitions.
- adin_lookup_reg_value
- adin_get_reg_value
- adin_config_rgmii_mode
- adin_config_rmii_mode
- adin_get_downshift
- adin_set_downshift
- adin_get_edpd
- adin_set_edpd
- adin_get_tunable
- adin_set_tunable
- adin_config_init
- adin_phy_ack_intr
- adin_phy_config_intr
- adin_cl45_to_adin_reg
- adin_read_mmd
- adin_write_mmd
- adin_config_mdix
- adin_config_aneg
- adin_mdix_update
- adin_read_status
- adin_soft_reset
- adin_get_sset_count
- adin_get_strings
- adin_read_mmd_stat_regs
- adin_get_stat
- adin_get_stats
- adin_probe
1
2
3
4
5
6
7 #include <linux/kernel.h>
8 #include <linux/bitfield.h>
9 #include <linux/delay.h>
10 #include <linux/errno.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/mii.h>
14 #include <linux/phy.h>
15 #include <linux/property.h>
16
17 #define PHY_ID_ADIN1200 0x0283bc20
18 #define PHY_ID_ADIN1300 0x0283bc30
19
20 #define ADIN1300_MII_EXT_REG_PTR 0x0010
21 #define ADIN1300_MII_EXT_REG_DATA 0x0011
22
23 #define ADIN1300_PHY_CTRL1 0x0012
24 #define ADIN1300_AUTO_MDI_EN BIT(10)
25 #define ADIN1300_MAN_MDIX_EN BIT(9)
26
27 #define ADIN1300_RX_ERR_CNT 0x0014
28
29 #define ADIN1300_PHY_CTRL_STATUS2 0x0015
30 #define ADIN1300_NRG_PD_EN BIT(3)
31 #define ADIN1300_NRG_PD_TX_EN BIT(2)
32 #define ADIN1300_NRG_PD_STATUS BIT(1)
33
34 #define ADIN1300_PHY_CTRL2 0x0016
35 #define ADIN1300_DOWNSPEED_AN_100_EN BIT(11)
36 #define ADIN1300_DOWNSPEED_AN_10_EN BIT(10)
37 #define ADIN1300_GROUP_MDIO_EN BIT(6)
38 #define ADIN1300_DOWNSPEEDS_EN \
39 (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN)
40
41 #define ADIN1300_PHY_CTRL3 0x0017
42 #define ADIN1300_LINKING_EN BIT(13)
43 #define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10)
44
45 #define ADIN1300_INT_MASK_REG 0x0018
46 #define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
47 #define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
48 #define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
49 #define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
50 #define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
51 #define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
52 #define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
53 #define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
54 #define ADIN1300_INT_HW_IRQ_EN BIT(0)
55 #define ADIN1300_INT_MASK_EN \
56 (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN)
57 #define ADIN1300_INT_STATUS_REG 0x0019
58
59 #define ADIN1300_PHY_STATUS1 0x001a
60 #define ADIN1300_PAIR_01_SWAP BIT(11)
61
62
63
64
65
66 #define ADIN1300_EEE_CAP_REG 0x8000
67 #define ADIN1300_EEE_ADV_REG 0x8001
68 #define ADIN1300_EEE_LPABLE_REG 0x8002
69 #define ADIN1300_CLOCK_STOP_REG 0x9400
70 #define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000
71
72 #define ADIN1300_GE_SOFT_RESET_REG 0xff0c
73 #define ADIN1300_GE_SOFT_RESET BIT(0)
74
75 #define ADIN1300_GE_RGMII_CFG_REG 0xff23
76 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
77 #define ADIN1300_GE_RGMII_RX_SEL(x) \
78 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
79 #define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
80 #define ADIN1300_GE_RGMII_GTX_SEL(x) \
81 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
82 #define ADIN1300_GE_RGMII_RXID_EN BIT(2)
83 #define ADIN1300_GE_RGMII_TXID_EN BIT(1)
84 #define ADIN1300_GE_RGMII_EN BIT(0)
85
86
87 #define ADIN1300_RGMII_1_60_NS 0x0001
88 #define ADIN1300_RGMII_1_80_NS 0x0002
89 #define ADIN1300_RGMII_2_00_NS 0x0000
90 #define ADIN1300_RGMII_2_20_NS 0x0006
91 #define ADIN1300_RGMII_2_40_NS 0x0007
92
93 #define ADIN1300_GE_RMII_CFG_REG 0xff24
94 #define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4)
95 #define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \
96 FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x)
97 #define ADIN1300_GE_RMII_EN BIT(0)
98
99
100 #define ADIN1300_RMII_4_BITS 0x0000
101 #define ADIN1300_RMII_8_BITS 0x0001
102 #define ADIN1300_RMII_12_BITS 0x0002
103 #define ADIN1300_RMII_16_BITS 0x0003
104 #define ADIN1300_RMII_20_BITS 0x0004
105 #define ADIN1300_RMII_24_BITS 0x0005
106
107
108
109
110
111
112 struct adin_cfg_reg_map {
113 int cfg;
114 int reg;
115 };
116
117 static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
118 { 1600, ADIN1300_RGMII_1_60_NS },
119 { 1800, ADIN1300_RGMII_1_80_NS },
120 { 2000, ADIN1300_RGMII_2_00_NS },
121 { 2200, ADIN1300_RGMII_2_20_NS },
122 { 2400, ADIN1300_RGMII_2_40_NS },
123 { },
124 };
125
126 static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = {
127 { 4, ADIN1300_RMII_4_BITS },
128 { 8, ADIN1300_RMII_8_BITS },
129 { 12, ADIN1300_RMII_12_BITS },
130 { 16, ADIN1300_RMII_16_BITS },
131 { 20, ADIN1300_RMII_20_BITS },
132 { 24, ADIN1300_RMII_24_BITS },
133 { },
134 };
135
136
137
138
139
140
141
142 struct adin_clause45_mmd_map {
143 int devad;
144 u16 cl45_regnum;
145 u16 adin_regnum;
146 };
147
148 static struct adin_clause45_mmd_map adin_clause45_mmd_map[] = {
149 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG },
150 { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG },
151 { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG },
152 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
153 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
154 };
155
156 struct adin_hw_stat {
157 const char *string;
158 u16 reg1;
159 u16 reg2;
160 };
161
162 static struct adin_hw_stat adin_hw_stats[] = {
163 { "total_frames_checked_count", 0x940A, 0x940B },
164 { "length_error_frames_count", 0x940C },
165 { "alignment_error_frames_count", 0x940D },
166 { "symbol_error_count", 0x940E },
167 { "oversized_frames_count", 0x940F },
168 { "undersized_frames_count", 0x9410 },
169 { "odd_nibble_frames_count", 0x9411 },
170 { "odd_preamble_packet_count", 0x9412 },
171 { "dribble_bits_frames_count", 0x9413 },
172 { "false_carrier_events_count", 0x9414 },
173 };
174
175
176
177
178
179 struct adin_priv {
180 u64 stats[ARRAY_SIZE(adin_hw_stats)];
181 };
182
183 static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
184 {
185 size_t i;
186
187 for (i = 0; tbl[i].cfg; i++) {
188 if (tbl[i].cfg == cfg)
189 return tbl[i].reg;
190 }
191
192 return -EINVAL;
193 }
194
195 static u32 adin_get_reg_value(struct phy_device *phydev,
196 const char *prop_name,
197 const struct adin_cfg_reg_map *tbl,
198 u32 dflt)
199 {
200 struct device *dev = &phydev->mdio.dev;
201 u32 val;
202 int rc;
203
204 if (device_property_read_u32(dev, prop_name, &val))
205 return dflt;
206
207 rc = adin_lookup_reg_value(tbl, val);
208 if (rc < 0) {
209 phydev_warn(phydev,
210 "Unsupported value %u for %s using default (%u)\n",
211 val, prop_name, dflt);
212 return dflt;
213 }
214
215 return rc;
216 }
217
218 static int adin_config_rgmii_mode(struct phy_device *phydev)
219 {
220 u32 val;
221 int reg;
222
223 if (!phy_interface_is_rgmii(phydev))
224 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
225 ADIN1300_GE_RGMII_CFG_REG,
226 ADIN1300_GE_RGMII_EN);
227
228 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
229 if (reg < 0)
230 return reg;
231
232 reg |= ADIN1300_GE_RGMII_EN;
233
234 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
235 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
236 reg |= ADIN1300_GE_RGMII_RXID_EN;
237
238 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
239 adin_rgmii_delays,
240 ADIN1300_RGMII_2_00_NS);
241 reg &= ~ADIN1300_GE_RGMII_RX_MSK;
242 reg |= ADIN1300_GE_RGMII_RX_SEL(val);
243 } else {
244 reg &= ~ADIN1300_GE_RGMII_RXID_EN;
245 }
246
247 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
248 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
249 reg |= ADIN1300_GE_RGMII_TXID_EN;
250
251 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
252 adin_rgmii_delays,
253 ADIN1300_RGMII_2_00_NS);
254 reg &= ~ADIN1300_GE_RGMII_GTX_MSK;
255 reg |= ADIN1300_GE_RGMII_GTX_SEL(val);
256 } else {
257 reg &= ~ADIN1300_GE_RGMII_TXID_EN;
258 }
259
260 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
261 ADIN1300_GE_RGMII_CFG_REG, reg);
262 }
263
264 static int adin_config_rmii_mode(struct phy_device *phydev)
265 {
266 u32 val;
267 int reg;
268
269 if (phydev->interface != PHY_INTERFACE_MODE_RMII)
270 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
271 ADIN1300_GE_RMII_CFG_REG,
272 ADIN1300_GE_RMII_EN);
273
274 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
275 if (reg < 0)
276 return reg;
277
278 reg |= ADIN1300_GE_RMII_EN;
279
280 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits",
281 adin_rmii_fifo_depths,
282 ADIN1300_RMII_8_BITS);
283
284 reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK;
285 reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val);
286
287 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
288 ADIN1300_GE_RMII_CFG_REG, reg);
289 }
290
291 static int adin_get_downshift(struct phy_device *phydev, u8 *data)
292 {
293 int val, cnt, enable;
294
295 val = phy_read(phydev, ADIN1300_PHY_CTRL2);
296 if (val < 0)
297 return val;
298
299 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3);
300 if (cnt < 0)
301 return cnt;
302
303 enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val);
304 cnt = FIELD_GET(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
305
306 *data = (enable && cnt) ? cnt : DOWNSHIFT_DEV_DISABLE;
307
308 return 0;
309 }
310
311 static int adin_set_downshift(struct phy_device *phydev, u8 cnt)
312 {
313 u16 val;
314 int rc;
315
316 if (cnt == DOWNSHIFT_DEV_DISABLE)
317 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,
318 ADIN1300_DOWNSPEEDS_EN);
319
320 if (cnt > 7)
321 return -E2BIG;
322
323 val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
324 val |= ADIN1300_LINKING_EN;
325
326 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3,
327 ADIN1300_LINKING_EN | ADIN1300_DOWNSPEED_RETRIES_MSK,
328 val);
329 if (rc < 0)
330 return rc;
331
332 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,
333 ADIN1300_DOWNSPEEDS_EN);
334 }
335
336 static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval)
337 {
338 int val;
339
340 val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2);
341 if (val < 0)
342 return val;
343
344 if (ADIN1300_NRG_PD_EN & val) {
345 if (val & ADIN1300_NRG_PD_TX_EN)
346
347 *tx_interval = ETHTOOL_PHY_EDPD_DFLT_TX_MSECS;
348 else
349 *tx_interval = ETHTOOL_PHY_EDPD_NO_TX;
350 } else {
351 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
352 }
353
354 return 0;
355 }
356
357 static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)
358 {
359 u16 val;
360
361 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
362 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
363 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN));
364
365 val = ADIN1300_NRG_PD_EN;
366
367 switch (tx_interval) {
368 case 1000:
369
370 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
371 val |= ADIN1300_NRG_PD_TX_EN;
372
373 case ETHTOOL_PHY_EDPD_NO_TX:
374 break;
375 default:
376 return -EINVAL;
377 }
378
379 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2,
380 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN),
381 val);
382 }
383
384 static int adin_get_tunable(struct phy_device *phydev,
385 struct ethtool_tunable *tuna, void *data)
386 {
387 switch (tuna->id) {
388 case ETHTOOL_PHY_DOWNSHIFT:
389 return adin_get_downshift(phydev, data);
390 case ETHTOOL_PHY_EDPD:
391 return adin_get_edpd(phydev, data);
392 default:
393 return -EOPNOTSUPP;
394 }
395 }
396
397 static int adin_set_tunable(struct phy_device *phydev,
398 struct ethtool_tunable *tuna, const void *data)
399 {
400 switch (tuna->id) {
401 case ETHTOOL_PHY_DOWNSHIFT:
402 return adin_set_downshift(phydev, *(const u8 *)data);
403 case ETHTOOL_PHY_EDPD:
404 return adin_set_edpd(phydev, *(const u16 *)data);
405 default:
406 return -EOPNOTSUPP;
407 }
408 }
409
410 static int adin_config_init(struct phy_device *phydev)
411 {
412 int rc;
413
414 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
415
416 rc = adin_config_rgmii_mode(phydev);
417 if (rc < 0)
418 return rc;
419
420 rc = adin_config_rmii_mode(phydev);
421 if (rc < 0)
422 return rc;
423
424 rc = adin_set_downshift(phydev, 4);
425 if (rc < 0)
426 return rc;
427
428 rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
429 if (rc < 0)
430 return rc;
431
432 phydev_dbg(phydev, "PHY is using mode '%s'\n",
433 phy_modes(phydev->interface));
434
435 return 0;
436 }
437
438 static int adin_phy_ack_intr(struct phy_device *phydev)
439 {
440
441 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);
442
443 return rc < 0 ? rc : 0;
444 }
445
446 static int adin_phy_config_intr(struct phy_device *phydev)
447 {
448 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
449 return phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
450 ADIN1300_INT_MASK_EN);
451
452 return phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
453 ADIN1300_INT_MASK_EN);
454 }
455
456 static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad,
457 u16 cl45_regnum)
458 {
459 struct adin_clause45_mmd_map *m;
460 int i;
461
462 if (devad == MDIO_MMD_VEND1)
463 return cl45_regnum;
464
465 for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) {
466 m = &adin_clause45_mmd_map[i];
467 if (m->devad == devad && m->cl45_regnum == cl45_regnum)
468 return m->adin_regnum;
469 }
470
471 phydev_err(phydev,
472 "No translation available for devad: %d reg: %04x\n",
473 devad, cl45_regnum);
474
475 return -EINVAL;
476 }
477
478 static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
479 {
480 struct mii_bus *bus = phydev->mdio.bus;
481 int phy_addr = phydev->mdio.addr;
482 int adin_regnum;
483 int err;
484
485 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
486 if (adin_regnum < 0)
487 return adin_regnum;
488
489 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
490 adin_regnum);
491 if (err)
492 return err;
493
494 return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA);
495 }
496
497 static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
498 u16 val)
499 {
500 struct mii_bus *bus = phydev->mdio.bus;
501 int phy_addr = phydev->mdio.addr;
502 int adin_regnum;
503 int err;
504
505 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
506 if (adin_regnum < 0)
507 return adin_regnum;
508
509 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
510 adin_regnum);
511 if (err)
512 return err;
513
514 return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val);
515 }
516
517 static int adin_config_mdix(struct phy_device *phydev)
518 {
519 bool auto_en, mdix_en;
520 int reg;
521
522 mdix_en = false;
523 auto_en = false;
524 switch (phydev->mdix_ctrl) {
525 case ETH_TP_MDI:
526 break;
527 case ETH_TP_MDI_X:
528 mdix_en = true;
529 break;
530 case ETH_TP_MDI_AUTO:
531 auto_en = true;
532 break;
533 default:
534 return -EINVAL;
535 }
536
537 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
538 if (reg < 0)
539 return reg;
540
541 if (mdix_en)
542 reg |= ADIN1300_MAN_MDIX_EN;
543 else
544 reg &= ~ADIN1300_MAN_MDIX_EN;
545
546 if (auto_en)
547 reg |= ADIN1300_AUTO_MDI_EN;
548 else
549 reg &= ~ADIN1300_AUTO_MDI_EN;
550
551 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
552 }
553
554 static int adin_config_aneg(struct phy_device *phydev)
555 {
556 int ret;
557
558 ret = adin_config_mdix(phydev);
559 if (ret)
560 return ret;
561
562 return genphy_config_aneg(phydev);
563 }
564
565 static int adin_mdix_update(struct phy_device *phydev)
566 {
567 bool auto_en, mdix_en;
568 bool swapped;
569 int reg;
570
571 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
572 if (reg < 0)
573 return reg;
574
575 auto_en = !!(reg & ADIN1300_AUTO_MDI_EN);
576 mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN);
577
578
579 if (!auto_en) {
580 if (mdix_en)
581 phydev->mdix = ETH_TP_MDI_X;
582 else
583 phydev->mdix = ETH_TP_MDI;
584 return 0;
585 }
586
587
588
589
590
591
592 reg = phy_read(phydev, ADIN1300_PHY_STATUS1);
593 if (reg < 0)
594 return reg;
595
596 swapped = !!(reg & ADIN1300_PAIR_01_SWAP);
597
598 if (mdix_en != swapped)
599 phydev->mdix = ETH_TP_MDI_X;
600 else
601 phydev->mdix = ETH_TP_MDI;
602
603 return 0;
604 }
605
606 static int adin_read_status(struct phy_device *phydev)
607 {
608 int ret;
609
610 ret = adin_mdix_update(phydev);
611 if (ret < 0)
612 return ret;
613
614 return genphy_read_status(phydev);
615 }
616
617 static int adin_soft_reset(struct phy_device *phydev)
618 {
619 int rc;
620
621
622 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
623 ADIN1300_GE_SOFT_RESET_REG,
624 ADIN1300_GE_SOFT_RESET);
625 if (rc < 0)
626 return rc;
627
628 msleep(10);
629
630
631 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
632 ADIN1300_GE_SOFT_RESET_REG);
633
634 return rc < 0 ? rc : 0;
635 }
636
637 static int adin_get_sset_count(struct phy_device *phydev)
638 {
639 return ARRAY_SIZE(adin_hw_stats);
640 }
641
642 static void adin_get_strings(struct phy_device *phydev, u8 *data)
643 {
644 int i;
645
646 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) {
647 strlcpy(&data[i * ETH_GSTRING_LEN],
648 adin_hw_stats[i].string, ETH_GSTRING_LEN);
649 }
650 }
651
652 static int adin_read_mmd_stat_regs(struct phy_device *phydev,
653 struct adin_hw_stat *stat,
654 u32 *val)
655 {
656 int ret;
657
658 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
659 if (ret < 0)
660 return ret;
661
662 *val = (ret & 0xffff);
663
664 if (stat->reg2 == 0)
665 return 0;
666
667 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
668 if (ret < 0)
669 return ret;
670
671 *val <<= 16;
672 *val |= (ret & 0xffff);
673
674 return 0;
675 }
676
677 static u64 adin_get_stat(struct phy_device *phydev, int i)
678 {
679 struct adin_hw_stat *stat = &adin_hw_stats[i];
680 struct adin_priv *priv = phydev->priv;
681 u32 val;
682 int ret;
683
684 if (stat->reg1 > 0x1f) {
685 ret = adin_read_mmd_stat_regs(phydev, stat, &val);
686 if (ret < 0)
687 return (u64)(~0);
688 } else {
689 ret = phy_read(phydev, stat->reg1);
690 if (ret < 0)
691 return (u64)(~0);
692 val = (ret & 0xffff);
693 }
694
695 priv->stats[i] += val;
696
697 return priv->stats[i];
698 }
699
700 static void adin_get_stats(struct phy_device *phydev,
701 struct ethtool_stats *stats, u64 *data)
702 {
703 int i, rc;
704
705
706 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT);
707 if (rc < 0)
708 return;
709
710 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++)
711 data[i] = adin_get_stat(phydev, i);
712 }
713
714 static int adin_probe(struct phy_device *phydev)
715 {
716 struct device *dev = &phydev->mdio.dev;
717 struct adin_priv *priv;
718
719 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
720 if (!priv)
721 return -ENOMEM;
722
723 phydev->priv = priv;
724
725 return 0;
726 }
727
728 static struct phy_driver adin_driver[] = {
729 {
730 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200),
731 .name = "ADIN1200",
732 .probe = adin_probe,
733 .config_init = adin_config_init,
734 .soft_reset = adin_soft_reset,
735 .config_aneg = adin_config_aneg,
736 .read_status = adin_read_status,
737 .get_tunable = adin_get_tunable,
738 .set_tunable = adin_set_tunable,
739 .ack_interrupt = adin_phy_ack_intr,
740 .config_intr = adin_phy_config_intr,
741 .get_sset_count = adin_get_sset_count,
742 .get_strings = adin_get_strings,
743 .get_stats = adin_get_stats,
744 .resume = genphy_resume,
745 .suspend = genphy_suspend,
746 .read_mmd = adin_read_mmd,
747 .write_mmd = adin_write_mmd,
748 },
749 {
750 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300),
751 .name = "ADIN1300",
752 .probe = adin_probe,
753 .config_init = adin_config_init,
754 .soft_reset = adin_soft_reset,
755 .config_aneg = adin_config_aneg,
756 .read_status = adin_read_status,
757 .get_tunable = adin_get_tunable,
758 .set_tunable = adin_set_tunable,
759 .ack_interrupt = adin_phy_ack_intr,
760 .config_intr = adin_phy_config_intr,
761 .get_sset_count = adin_get_sset_count,
762 .get_strings = adin_get_strings,
763 .get_stats = adin_get_stats,
764 .resume = genphy_resume,
765 .suspend = genphy_suspend,
766 .read_mmd = adin_read_mmd,
767 .write_mmd = adin_write_mmd,
768 },
769 };
770
771 module_phy_driver(adin_driver);
772
773 static struct mdio_device_id __maybe_unused adin_tbl[] = {
774 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) },
775 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) },
776 { }
777 };
778
779 MODULE_DEVICE_TABLE(mdio, adin_tbl);
780 MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver");
781 MODULE_LICENSE("GPL");