This source file includes following definitions.
- dp83640_gpio_defaults
- broadcast_write
- ext_read
- ext_write
- tdr_write
- phy2rxts
- phy2txts
- periodic_output
- ptp_dp83640_adjfine
- ptp_dp83640_adjtime
- ptp_dp83640_gettime
- ptp_dp83640_settime
- ptp_dp83640_enable
- ptp_dp83640_verify
- enable_status_frames
- is_status_frame
- expired
- prune_rx_ts
- enable_broadcast
- recalibrate
- exts_chan_to_edata
- decode_evnt
- match
- decode_rxts
- decode_txts
- decode_status_frame
- is_sync
- dp83640_free_clocks
- dp83640_clock_init
- choose_this_phy
- dp83640_clock_get
- dp83640_clock_get_bus
- dp83640_clock_put
- dp83640_probe
- dp83640_remove
- dp83640_soft_reset
- dp83640_config_init
- dp83640_ack_interrupt
- dp83640_config_intr
- dp83640_hwtstamp
- rx_timestamp_work
- dp83640_rxtstamp
- dp83640_txtstamp
- dp83640_ts_info
- dp83640_init
- dp83640_exit
1
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6
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/crc32.h>
11 #include <linux/ethtool.h>
12 #include <linux/kernel.h>
13 #include <linux/list.h>
14 #include <linux/mii.h>
15 #include <linux/module.h>
16 #include <linux/net_tstamp.h>
17 #include <linux/netdevice.h>
18 #include <linux/if_vlan.h>
19 #include <linux/phy.h>
20 #include <linux/ptp_classify.h>
21 #include <linux/ptp_clock_kernel.h>
22
23 #include "dp83640_reg.h"
24
25 #define DP83640_PHY_ID 0x20005ce1
26 #define PAGESEL 0x13
27 #define MAX_RXTS 64
28 #define N_EXT_TS 6
29 #define N_PER_OUT 7
30 #define PSF_PTPVER 2
31 #define PSF_EVNT 0x4000
32 #define PSF_RX 0x2000
33 #define PSF_TX 0x1000
34 #define EXT_EVENT 1
35 #define CAL_EVENT 7
36 #define CAL_TRIGGER 1
37 #define DP83640_N_PINS 12
38
39 #define MII_DP83640_MICR 0x11
40 #define MII_DP83640_MISR 0x12
41
42 #define MII_DP83640_MICR_OE 0x1
43 #define MII_DP83640_MICR_IE 0x2
44
45 #define MII_DP83640_MISR_RHF_INT_EN 0x01
46 #define MII_DP83640_MISR_FHF_INT_EN 0x02
47 #define MII_DP83640_MISR_ANC_INT_EN 0x04
48 #define MII_DP83640_MISR_DUP_INT_EN 0x08
49 #define MII_DP83640_MISR_SPD_INT_EN 0x10
50 #define MII_DP83640_MISR_LINK_INT_EN 0x20
51 #define MII_DP83640_MISR_ED_INT_EN 0x40
52 #define MII_DP83640_MISR_LQ_INT_EN 0x80
53
54
55 #define ADJTIME_FIX 16
56
57 #define SKB_TIMESTAMP_TIMEOUT 2
58
59 #if defined(__BIG_ENDIAN)
60 #define ENDIAN_FLAG 0
61 #elif defined(__LITTLE_ENDIAN)
62 #define ENDIAN_FLAG PSF_ENDIAN
63 #endif
64
65 struct dp83640_skb_info {
66 int ptp_type;
67 unsigned long tmo;
68 };
69
70 struct phy_rxts {
71 u16 ns_lo;
72 u16 ns_hi;
73 u16 sec_lo;
74 u16 sec_hi;
75 u16 seqid;
76 u16 msgtype;
77 };
78
79 struct phy_txts {
80 u16 ns_lo;
81 u16 ns_hi;
82 u16 sec_lo;
83 u16 sec_hi;
84 };
85
86 struct rxts {
87 struct list_head list;
88 unsigned long tmo;
89 u64 ns;
90 u16 seqid;
91 u8 msgtype;
92 u16 hash;
93 };
94
95 struct dp83640_clock;
96
97 struct dp83640_private {
98 struct list_head list;
99 struct dp83640_clock *clock;
100 struct phy_device *phydev;
101 struct delayed_work ts_work;
102 int hwts_tx_en;
103 int hwts_rx_en;
104 int layer;
105 int version;
106
107 int cfg0;
108
109 struct phy_txts edata;
110
111 struct list_head rxts;
112 struct list_head rxpool;
113 struct rxts rx_pool_data[MAX_RXTS];
114
115 spinlock_t rx_lock;
116
117 struct sk_buff_head rx_queue;
118 struct sk_buff_head tx_queue;
119 };
120
121 struct dp83640_clock {
122
123 struct list_head list;
124
125 struct mii_bus *bus;
126
127 struct mutex extreg_lock;
128
129 int page;
130
131 struct ptp_clock_info caps;
132
133 struct mutex clock_lock;
134
135 struct dp83640_private *chosen;
136
137 struct list_head phylist;
138
139 struct ptp_clock *ptp_clock;
140 };
141
142
143
144 enum {
145 CALIBRATE_GPIO,
146 PEROUT_GPIO,
147 EXTTS0_GPIO,
148 EXTTS1_GPIO,
149 EXTTS2_GPIO,
150 EXTTS3_GPIO,
151 EXTTS4_GPIO,
152 EXTTS5_GPIO,
153 GPIO_TABLE_SIZE
154 };
155
156 static int chosen_phy = -1;
157 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
158 1, 2, 3, 4, 8, 9, 10, 11
159 };
160
161 module_param(chosen_phy, int, 0444);
162 module_param_array(gpio_tab, ushort, NULL, 0444);
163
164 MODULE_PARM_DESC(chosen_phy, \
165 "The address of the PHY to use for the ancillary clock features");
166 MODULE_PARM_DESC(gpio_tab, \
167 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
168
169 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
170 {
171 int i, index;
172
173 for (i = 0; i < DP83640_N_PINS; i++) {
174 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
175 pd[i].index = i;
176 }
177
178 for (i = 0; i < GPIO_TABLE_SIZE; i++) {
179 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
180 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
181 return;
182 }
183 }
184
185 index = gpio_tab[CALIBRATE_GPIO] - 1;
186 pd[index].func = PTP_PF_PHYSYNC;
187 pd[index].chan = 0;
188
189 index = gpio_tab[PEROUT_GPIO] - 1;
190 pd[index].func = PTP_PF_PEROUT;
191 pd[index].chan = 0;
192
193 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
194 index = gpio_tab[i] - 1;
195 pd[index].func = PTP_PF_EXTTS;
196 pd[index].chan = i - EXTTS0_GPIO;
197 }
198 }
199
200
201 static LIST_HEAD(phyter_clocks);
202 static DEFINE_MUTEX(phyter_clocks_lock);
203
204 static void rx_timestamp_work(struct work_struct *work);
205
206
207
208 #define BROADCAST_ADDR 31
209
210 static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
211 u16 val)
212 {
213 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
214 }
215
216
217 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
218 {
219 struct dp83640_private *dp83640 = phydev->priv;
220 int val;
221
222 if (dp83640->clock->page != page) {
223 broadcast_write(phydev, PAGESEL, page);
224 dp83640->clock->page = page;
225 }
226 val = phy_read(phydev, regnum);
227
228 return val;
229 }
230
231
232 static void ext_write(int broadcast, struct phy_device *phydev,
233 int page, u32 regnum, u16 val)
234 {
235 struct dp83640_private *dp83640 = phydev->priv;
236
237 if (dp83640->clock->page != page) {
238 broadcast_write(phydev, PAGESEL, page);
239 dp83640->clock->page = page;
240 }
241 if (broadcast)
242 broadcast_write(phydev, regnum, val);
243 else
244 phy_write(phydev, regnum, val);
245 }
246
247
248 static int tdr_write(int bc, struct phy_device *dev,
249 const struct timespec64 *ts, u16 cmd)
250 {
251 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);
252 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16);
253 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff);
254 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16);
255
256 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
257
258 return 0;
259 }
260
261
262
263 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
264 {
265 u32 sec;
266
267 sec = p->sec_lo;
268 sec |= p->sec_hi << 16;
269
270 rxts->ns = p->ns_lo;
271 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
272 rxts->ns += ((u64)sec) * 1000000000ULL;
273 rxts->seqid = p->seqid;
274 rxts->msgtype = (p->msgtype >> 12) & 0xf;
275 rxts->hash = p->msgtype & 0x0fff;
276 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
277 }
278
279 static u64 phy2txts(struct phy_txts *p)
280 {
281 u64 ns;
282 u32 sec;
283
284 sec = p->sec_lo;
285 sec |= p->sec_hi << 16;
286
287 ns = p->ns_lo;
288 ns |= (p->ns_hi & 0x3fff) << 16;
289 ns += ((u64)sec) * 1000000000ULL;
290
291 return ns;
292 }
293
294 static int periodic_output(struct dp83640_clock *clock,
295 struct ptp_clock_request *clkreq, bool on,
296 int trigger)
297 {
298 struct dp83640_private *dp83640 = clock->chosen;
299 struct phy_device *phydev = dp83640->phydev;
300 u32 sec, nsec, pwidth;
301 u16 gpio, ptp_trig, val;
302
303 if (on) {
304 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
305 trigger);
306 if (gpio < 1)
307 return -EINVAL;
308 } else {
309 gpio = 0;
310 }
311
312 ptp_trig = TRIG_WR |
313 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
314 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
315 TRIG_PER |
316 TRIG_PULSE;
317
318 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
319
320 if (!on) {
321 val |= TRIG_DIS;
322 mutex_lock(&clock->extreg_lock);
323 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
324 ext_write(0, phydev, PAGE4, PTP_CTL, val);
325 mutex_unlock(&clock->extreg_lock);
326 return 0;
327 }
328
329 sec = clkreq->perout.start.sec;
330 nsec = clkreq->perout.start.nsec;
331 pwidth = clkreq->perout.period.sec * 1000000000UL;
332 pwidth += clkreq->perout.period.nsec;
333 pwidth /= 2;
334
335 mutex_lock(&clock->extreg_lock);
336
337 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
338
339
340 val |= TRIG_LOAD;
341 ext_write(0, phydev, PAGE4, PTP_CTL, val);
342 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff);
343 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16);
344 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff);
345 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16);
346 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
347 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
348
349 if (trigger < 2) {
350 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
351 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
352 }
353
354
355 val &= ~TRIG_LOAD;
356 val |= TRIG_EN;
357 ext_write(0, phydev, PAGE4, PTP_CTL, val);
358
359 mutex_unlock(&clock->extreg_lock);
360 return 0;
361 }
362
363
364
365 static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
366 {
367 struct dp83640_clock *clock =
368 container_of(ptp, struct dp83640_clock, caps);
369 struct phy_device *phydev = clock->chosen->phydev;
370 u64 rate;
371 int neg_adj = 0;
372 u16 hi, lo;
373
374 if (scaled_ppm < 0) {
375 neg_adj = 1;
376 scaled_ppm = -scaled_ppm;
377 }
378 rate = scaled_ppm;
379 rate <<= 13;
380 rate = div_u64(rate, 15625);
381
382 hi = (rate >> 16) & PTP_RATE_HI_MASK;
383 if (neg_adj)
384 hi |= PTP_RATE_DIR;
385
386 lo = rate & 0xffff;
387
388 mutex_lock(&clock->extreg_lock);
389
390 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
391 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
392
393 mutex_unlock(&clock->extreg_lock);
394
395 return 0;
396 }
397
398 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
399 {
400 struct dp83640_clock *clock =
401 container_of(ptp, struct dp83640_clock, caps);
402 struct phy_device *phydev = clock->chosen->phydev;
403 struct timespec64 ts;
404 int err;
405
406 delta += ADJTIME_FIX;
407
408 ts = ns_to_timespec64(delta);
409
410 mutex_lock(&clock->extreg_lock);
411
412 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
413
414 mutex_unlock(&clock->extreg_lock);
415
416 return err;
417 }
418
419 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
420 struct timespec64 *ts)
421 {
422 struct dp83640_clock *clock =
423 container_of(ptp, struct dp83640_clock, caps);
424 struct phy_device *phydev = clock->chosen->phydev;
425 unsigned int val[4];
426
427 mutex_lock(&clock->extreg_lock);
428
429 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
430
431 val[0] = ext_read(phydev, PAGE4, PTP_TDR);
432 val[1] = ext_read(phydev, PAGE4, PTP_TDR);
433 val[2] = ext_read(phydev, PAGE4, PTP_TDR);
434 val[3] = ext_read(phydev, PAGE4, PTP_TDR);
435
436 mutex_unlock(&clock->extreg_lock);
437
438 ts->tv_nsec = val[0] | (val[1] << 16);
439 ts->tv_sec = val[2] | (val[3] << 16);
440
441 return 0;
442 }
443
444 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
445 const struct timespec64 *ts)
446 {
447 struct dp83640_clock *clock =
448 container_of(ptp, struct dp83640_clock, caps);
449 struct phy_device *phydev = clock->chosen->phydev;
450 int err;
451
452 mutex_lock(&clock->extreg_lock);
453
454 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
455
456 mutex_unlock(&clock->extreg_lock);
457
458 return err;
459 }
460
461 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
462 struct ptp_clock_request *rq, int on)
463 {
464 struct dp83640_clock *clock =
465 container_of(ptp, struct dp83640_clock, caps);
466 struct phy_device *phydev = clock->chosen->phydev;
467 unsigned int index;
468 u16 evnt, event_num, gpio_num;
469
470 switch (rq->type) {
471 case PTP_CLK_REQ_EXTTS:
472
473 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
474 PTP_RISING_EDGE |
475 PTP_FALLING_EDGE |
476 PTP_STRICT_FLAGS))
477 return -EOPNOTSUPP;
478
479
480 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
481 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
482 (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
483 return -EOPNOTSUPP;
484
485 index = rq->extts.index;
486 if (index >= N_EXT_TS)
487 return -EINVAL;
488 event_num = EXT_EVENT + index;
489 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
490 if (on) {
491 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
492 PTP_PF_EXTTS, index);
493 if (gpio_num < 1)
494 return -EINVAL;
495 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
496 if (rq->extts.flags & PTP_FALLING_EDGE)
497 evnt |= EVNT_FALL;
498 else
499 evnt |= EVNT_RISE;
500 }
501 mutex_lock(&clock->extreg_lock);
502 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
503 mutex_unlock(&clock->extreg_lock);
504 return 0;
505
506 case PTP_CLK_REQ_PEROUT:
507
508 if (rq->perout.flags)
509 return -EOPNOTSUPP;
510 if (rq->perout.index >= N_PER_OUT)
511 return -EINVAL;
512 return periodic_output(clock, rq, on, rq->perout.index);
513
514 default:
515 break;
516 }
517
518 return -EOPNOTSUPP;
519 }
520
521 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
522 enum ptp_pin_function func, unsigned int chan)
523 {
524 struct dp83640_clock *clock =
525 container_of(ptp, struct dp83640_clock, caps);
526
527 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
528 !list_empty(&clock->phylist))
529 return 1;
530
531 if (func == PTP_PF_PHYSYNC)
532 return 1;
533
534 return 0;
535 }
536
537 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
538 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
539
540 static void enable_status_frames(struct phy_device *phydev, bool on)
541 {
542 struct dp83640_private *dp83640 = phydev->priv;
543 struct dp83640_clock *clock = dp83640->clock;
544 u16 cfg0 = 0, ver;
545
546 if (on)
547 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
548
549 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
550
551 mutex_lock(&clock->extreg_lock);
552
553 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
554 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
555
556 mutex_unlock(&clock->extreg_lock);
557
558 if (!phydev->attached_dev) {
559 phydev_warn(phydev,
560 "expected to find an attached netdevice\n");
561 return;
562 }
563
564 if (on) {
565 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
566 phydev_warn(phydev, "failed to add mc address\n");
567 } else {
568 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
569 phydev_warn(phydev, "failed to delete mc address\n");
570 }
571 }
572
573 static bool is_status_frame(struct sk_buff *skb, int type)
574 {
575 struct ethhdr *h = eth_hdr(skb);
576
577 if (PTP_CLASS_V2_L2 == type &&
578 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
579 return true;
580 else
581 return false;
582 }
583
584 static int expired(struct rxts *rxts)
585 {
586 return time_after(jiffies, rxts->tmo);
587 }
588
589
590 static void prune_rx_ts(struct dp83640_private *dp83640)
591 {
592 struct list_head *this, *next;
593 struct rxts *rxts;
594
595 list_for_each_safe(this, next, &dp83640->rxts) {
596 rxts = list_entry(this, struct rxts, list);
597 if (expired(rxts)) {
598 list_del_init(&rxts->list);
599 list_add(&rxts->list, &dp83640->rxpool);
600 }
601 }
602 }
603
604
605
606 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
607 {
608 int val;
609 phy_write(phydev, PAGESEL, 0);
610 val = phy_read(phydev, PHYCR2);
611 if (on)
612 val |= BC_WRITE;
613 else
614 val &= ~BC_WRITE;
615 phy_write(phydev, PHYCR2, val);
616 phy_write(phydev, PAGESEL, init_page);
617 }
618
619 static void recalibrate(struct dp83640_clock *clock)
620 {
621 s64 now, diff;
622 struct phy_txts event_ts;
623 struct timespec64 ts;
624 struct list_head *this;
625 struct dp83640_private *tmp;
626 struct phy_device *master = clock->chosen->phydev;
627 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
628
629 trigger = CAL_TRIGGER;
630 cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
631 if (cal_gpio < 1) {
632 pr_err("PHY calibration pin not available - PHY is not calibrated.");
633 return;
634 }
635
636 mutex_lock(&clock->extreg_lock);
637
638
639
640
641 list_for_each(this, &clock->phylist) {
642 tmp = list_entry(this, struct dp83640_private, list);
643 enable_broadcast(tmp->phydev, clock->page, 1);
644 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
645 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
646 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
647 }
648 enable_broadcast(master, clock->page, 1);
649 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
650 ext_write(0, master, PAGE5, PSF_CFG0, 0);
651 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
652
653
654
655
656 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
657 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
658 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
659
660 list_for_each(this, &clock->phylist) {
661 tmp = list_entry(this, struct dp83640_private, list);
662 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
663 }
664 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
665
666
667
668
669 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
670 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
671 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
672 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
673
674
675 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
676 val |= TRIG_LOAD;
677 ext_write(0, master, PAGE4, PTP_CTL, val);
678
679
680 val &= ~TRIG_LOAD;
681 val |= TRIG_EN;
682 ext_write(0, master, PAGE4, PTP_CTL, val);
683
684
685 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
686 val |= TRIG_DIS;
687 ext_write(0, master, PAGE4, PTP_CTL, val);
688
689
690
691
692 val = ext_read(master, PAGE4, PTP_STS);
693 phydev_info(master, "master PTP_STS 0x%04hx\n", val);
694 val = ext_read(master, PAGE4, PTP_ESTS);
695 phydev_info(master, "master PTP_ESTS 0x%04hx\n", val);
696 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
697 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
698 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
699 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
700 now = phy2txts(&event_ts);
701
702 list_for_each(this, &clock->phylist) {
703 tmp = list_entry(this, struct dp83640_private, list);
704 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
705 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val);
706 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
707 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val);
708 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
709 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
710 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
711 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
712 diff = now - (s64) phy2txts(&event_ts);
713 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
714 diff);
715 diff += ADJTIME_FIX;
716 ts = ns_to_timespec64(diff);
717 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
718 }
719
720
721
722
723 list_for_each(this, &clock->phylist) {
724 tmp = list_entry(this, struct dp83640_private, list);
725 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
726 }
727 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
728
729 mutex_unlock(&clock->extreg_lock);
730 }
731
732
733
734 static inline u16 exts_chan_to_edata(int ch)
735 {
736 return 1 << ((ch + EXT_EVENT) * 2);
737 }
738
739 static int decode_evnt(struct dp83640_private *dp83640,
740 void *data, int len, u16 ests)
741 {
742 struct phy_txts *phy_txts;
743 struct ptp_clock_event event;
744 int i, parsed;
745 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
746 u16 ext_status = 0;
747
748
749 if (ests & MULT_EVNT)
750 parsed = (words + 2) * sizeof(u16);
751 else
752 parsed = (words + 1) * sizeof(u16);
753
754
755 if (len < parsed)
756 return len;
757
758 if (ests & MULT_EVNT) {
759 ext_status = *(u16 *) data;
760 data += sizeof(ext_status);
761 }
762
763 phy_txts = data;
764
765 switch (words) {
766 case 3:
767 dp83640->edata.sec_hi = phy_txts->sec_hi;
768
769 case 2:
770 dp83640->edata.sec_lo = phy_txts->sec_lo;
771
772 case 1:
773 dp83640->edata.ns_hi = phy_txts->ns_hi;
774
775 case 0:
776 dp83640->edata.ns_lo = phy_txts->ns_lo;
777 }
778
779 if (!ext_status) {
780 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
781 ext_status = exts_chan_to_edata(i);
782 }
783
784 event.type = PTP_CLOCK_EXTTS;
785 event.timestamp = phy2txts(&dp83640->edata);
786
787
788 event.timestamp -= 35;
789
790 for (i = 0; i < N_EXT_TS; i++) {
791 if (ext_status & exts_chan_to_edata(i)) {
792 event.index = i;
793 ptp_clock_event(dp83640->clock->ptp_clock, &event);
794 }
795 }
796
797 return parsed;
798 }
799
800 #define DP83640_PACKET_HASH_OFFSET 20
801 #define DP83640_PACKET_HASH_LEN 10
802
803 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
804 {
805 u16 *seqid, hash;
806 unsigned int offset = 0;
807 u8 *msgtype, *data = skb_mac_header(skb);
808
809
810
811 if (type & PTP_CLASS_VLAN)
812 offset += VLAN_HLEN;
813
814 switch (type & PTP_CLASS_PMASK) {
815 case PTP_CLASS_IPV4:
816 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
817 break;
818 case PTP_CLASS_IPV6:
819 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
820 break;
821 case PTP_CLASS_L2:
822 offset += ETH_HLEN;
823 break;
824 default:
825 return 0;
826 }
827
828 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
829 return 0;
830
831 if (unlikely(type & PTP_CLASS_V1))
832 msgtype = data + offset + OFF_PTP_CONTROL;
833 else
834 msgtype = data + offset;
835 if (rxts->msgtype != (*msgtype & 0xf))
836 return 0;
837
838 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
839 if (rxts->seqid != ntohs(*seqid))
840 return 0;
841
842 hash = ether_crc(DP83640_PACKET_HASH_LEN,
843 data + offset + DP83640_PACKET_HASH_OFFSET) >> 20;
844 if (rxts->hash != hash)
845 return 0;
846
847 return 1;
848 }
849
850 static void decode_rxts(struct dp83640_private *dp83640,
851 struct phy_rxts *phy_rxts)
852 {
853 struct rxts *rxts;
854 struct skb_shared_hwtstamps *shhwtstamps = NULL;
855 struct sk_buff *skb;
856 unsigned long flags;
857 u8 overflow;
858
859 overflow = (phy_rxts->ns_hi >> 14) & 0x3;
860 if (overflow)
861 pr_debug("rx timestamp queue overflow, count %d\n", overflow);
862
863 spin_lock_irqsave(&dp83640->rx_lock, flags);
864
865 prune_rx_ts(dp83640);
866
867 if (list_empty(&dp83640->rxpool)) {
868 pr_debug("rx timestamp pool is empty\n");
869 goto out;
870 }
871 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
872 list_del_init(&rxts->list);
873 phy2rxts(phy_rxts, rxts);
874
875 spin_lock(&dp83640->rx_queue.lock);
876 skb_queue_walk(&dp83640->rx_queue, skb) {
877 struct dp83640_skb_info *skb_info;
878
879 skb_info = (struct dp83640_skb_info *)skb->cb;
880 if (match(skb, skb_info->ptp_type, rxts)) {
881 __skb_unlink(skb, &dp83640->rx_queue);
882 shhwtstamps = skb_hwtstamps(skb);
883 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
884 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
885 list_add(&rxts->list, &dp83640->rxpool);
886 break;
887 }
888 }
889 spin_unlock(&dp83640->rx_queue.lock);
890
891 if (!shhwtstamps)
892 list_add_tail(&rxts->list, &dp83640->rxts);
893 out:
894 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
895
896 if (shhwtstamps)
897 netif_rx_ni(skb);
898 }
899
900 static void decode_txts(struct dp83640_private *dp83640,
901 struct phy_txts *phy_txts)
902 {
903 struct skb_shared_hwtstamps shhwtstamps;
904 struct dp83640_skb_info *skb_info;
905 struct sk_buff *skb;
906 u8 overflow;
907 u64 ns;
908
909
910 again:
911 skb = skb_dequeue(&dp83640->tx_queue);
912 if (!skb) {
913 pr_debug("have timestamp but tx_queue empty\n");
914 return;
915 }
916
917 overflow = (phy_txts->ns_hi >> 14) & 0x3;
918 if (overflow) {
919 pr_debug("tx timestamp queue overflow, count %d\n", overflow);
920 while (skb) {
921 kfree_skb(skb);
922 skb = skb_dequeue(&dp83640->tx_queue);
923 }
924 return;
925 }
926 skb_info = (struct dp83640_skb_info *)skb->cb;
927 if (time_after(jiffies, skb_info->tmo)) {
928 kfree_skb(skb);
929 goto again;
930 }
931
932 ns = phy2txts(phy_txts);
933 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
934 shhwtstamps.hwtstamp = ns_to_ktime(ns);
935 skb_complete_tx_timestamp(skb, &shhwtstamps);
936 }
937
938 static void decode_status_frame(struct dp83640_private *dp83640,
939 struct sk_buff *skb)
940 {
941 struct phy_rxts *phy_rxts;
942 struct phy_txts *phy_txts;
943 u8 *ptr;
944 int len, size;
945 u16 ests, type;
946
947 ptr = skb->data + 2;
948
949 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
950
951 type = *(u16 *)ptr;
952 ests = type & 0x0fff;
953 type = type & 0xf000;
954 len -= sizeof(type);
955 ptr += sizeof(type);
956
957 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
958
959 phy_rxts = (struct phy_rxts *) ptr;
960 decode_rxts(dp83640, phy_rxts);
961 size = sizeof(*phy_rxts);
962
963 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
964
965 phy_txts = (struct phy_txts *) ptr;
966 decode_txts(dp83640, phy_txts);
967 size = sizeof(*phy_txts);
968
969 } else if (PSF_EVNT == type) {
970
971 size = decode_evnt(dp83640, ptr, len, ests);
972
973 } else {
974 size = 0;
975 break;
976 }
977 ptr += size;
978 }
979 }
980
981 static int is_sync(struct sk_buff *skb, int type)
982 {
983 u8 *data = skb->data, *msgtype;
984 unsigned int offset = 0;
985
986 if (type & PTP_CLASS_VLAN)
987 offset += VLAN_HLEN;
988
989 switch (type & PTP_CLASS_PMASK) {
990 case PTP_CLASS_IPV4:
991 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
992 break;
993 case PTP_CLASS_IPV6:
994 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
995 break;
996 case PTP_CLASS_L2:
997 offset += ETH_HLEN;
998 break;
999 default:
1000 return 0;
1001 }
1002
1003 if (type & PTP_CLASS_V1)
1004 offset += OFF_PTP_CONTROL;
1005
1006 if (skb->len < offset + 1)
1007 return 0;
1008
1009 msgtype = data + offset;
1010
1011 return (*msgtype & 0xf) == 0;
1012 }
1013
1014 static void dp83640_free_clocks(void)
1015 {
1016 struct dp83640_clock *clock;
1017 struct list_head *this, *next;
1018
1019 mutex_lock(&phyter_clocks_lock);
1020
1021 list_for_each_safe(this, next, &phyter_clocks) {
1022 clock = list_entry(this, struct dp83640_clock, list);
1023 if (!list_empty(&clock->phylist)) {
1024 pr_warn("phy list non-empty while unloading\n");
1025 BUG();
1026 }
1027 list_del(&clock->list);
1028 mutex_destroy(&clock->extreg_lock);
1029 mutex_destroy(&clock->clock_lock);
1030 put_device(&clock->bus->dev);
1031 kfree(clock->caps.pin_config);
1032 kfree(clock);
1033 }
1034
1035 mutex_unlock(&phyter_clocks_lock);
1036 }
1037
1038 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
1039 {
1040 INIT_LIST_HEAD(&clock->list);
1041 clock->bus = bus;
1042 mutex_init(&clock->extreg_lock);
1043 mutex_init(&clock->clock_lock);
1044 INIT_LIST_HEAD(&clock->phylist);
1045 clock->caps.owner = THIS_MODULE;
1046 sprintf(clock->caps.name, "dp83640 timer");
1047 clock->caps.max_adj = 1953124;
1048 clock->caps.n_alarm = 0;
1049 clock->caps.n_ext_ts = N_EXT_TS;
1050 clock->caps.n_per_out = N_PER_OUT;
1051 clock->caps.n_pins = DP83640_N_PINS;
1052 clock->caps.pps = 0;
1053 clock->caps.adjfine = ptp_dp83640_adjfine;
1054 clock->caps.adjtime = ptp_dp83640_adjtime;
1055 clock->caps.gettime64 = ptp_dp83640_gettime;
1056 clock->caps.settime64 = ptp_dp83640_settime;
1057 clock->caps.enable = ptp_dp83640_enable;
1058 clock->caps.verify = ptp_dp83640_verify;
1059
1060
1061
1062 dp83640_gpio_defaults(clock->caps.pin_config);
1063
1064
1065
1066 get_device(&bus->dev);
1067 }
1068
1069 static int choose_this_phy(struct dp83640_clock *clock,
1070 struct phy_device *phydev)
1071 {
1072 if (chosen_phy == -1 && !clock->chosen)
1073 return 1;
1074
1075 if (chosen_phy == phydev->mdio.addr)
1076 return 1;
1077
1078 return 0;
1079 }
1080
1081 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1082 {
1083 if (clock)
1084 mutex_lock(&clock->clock_lock);
1085 return clock;
1086 }
1087
1088
1089
1090
1091
1092 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1093 {
1094 struct dp83640_clock *clock = NULL, *tmp;
1095 struct list_head *this;
1096
1097 mutex_lock(&phyter_clocks_lock);
1098
1099 list_for_each(this, &phyter_clocks) {
1100 tmp = list_entry(this, struct dp83640_clock, list);
1101 if (tmp->bus == bus) {
1102 clock = tmp;
1103 break;
1104 }
1105 }
1106 if (clock)
1107 goto out;
1108
1109 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1110 if (!clock)
1111 goto out;
1112
1113 clock->caps.pin_config = kcalloc(DP83640_N_PINS,
1114 sizeof(struct ptp_pin_desc),
1115 GFP_KERNEL);
1116 if (!clock->caps.pin_config) {
1117 kfree(clock);
1118 clock = NULL;
1119 goto out;
1120 }
1121 dp83640_clock_init(clock, bus);
1122 list_add_tail(&clock->list, &phyter_clocks);
1123 out:
1124 mutex_unlock(&phyter_clocks_lock);
1125
1126 return dp83640_clock_get(clock);
1127 }
1128
1129 static void dp83640_clock_put(struct dp83640_clock *clock)
1130 {
1131 mutex_unlock(&clock->clock_lock);
1132 }
1133
1134 static int dp83640_probe(struct phy_device *phydev)
1135 {
1136 struct dp83640_clock *clock;
1137 struct dp83640_private *dp83640;
1138 int err = -ENOMEM, i;
1139
1140 if (phydev->mdio.addr == BROADCAST_ADDR)
1141 return 0;
1142
1143 clock = dp83640_clock_get_bus(phydev->mdio.bus);
1144 if (!clock)
1145 goto no_clock;
1146
1147 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1148 if (!dp83640)
1149 goto no_memory;
1150
1151 dp83640->phydev = phydev;
1152 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1153
1154 INIT_LIST_HEAD(&dp83640->rxts);
1155 INIT_LIST_HEAD(&dp83640->rxpool);
1156 for (i = 0; i < MAX_RXTS; i++)
1157 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1158
1159 phydev->priv = dp83640;
1160
1161 spin_lock_init(&dp83640->rx_lock);
1162 skb_queue_head_init(&dp83640->rx_queue);
1163 skb_queue_head_init(&dp83640->tx_queue);
1164
1165 dp83640->clock = clock;
1166
1167 if (choose_this_phy(clock, phydev)) {
1168 clock->chosen = dp83640;
1169 clock->ptp_clock = ptp_clock_register(&clock->caps,
1170 &phydev->mdio.dev);
1171 if (IS_ERR(clock->ptp_clock)) {
1172 err = PTR_ERR(clock->ptp_clock);
1173 goto no_register;
1174 }
1175 } else
1176 list_add_tail(&dp83640->list, &clock->phylist);
1177
1178 dp83640_clock_put(clock);
1179 return 0;
1180
1181 no_register:
1182 clock->chosen = NULL;
1183 kfree(dp83640);
1184 no_memory:
1185 dp83640_clock_put(clock);
1186 no_clock:
1187 return err;
1188 }
1189
1190 static void dp83640_remove(struct phy_device *phydev)
1191 {
1192 struct dp83640_clock *clock;
1193 struct list_head *this, *next;
1194 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1195
1196 if (phydev->mdio.addr == BROADCAST_ADDR)
1197 return;
1198
1199 enable_status_frames(phydev, false);
1200 cancel_delayed_work_sync(&dp83640->ts_work);
1201
1202 skb_queue_purge(&dp83640->rx_queue);
1203 skb_queue_purge(&dp83640->tx_queue);
1204
1205 clock = dp83640_clock_get(dp83640->clock);
1206
1207 if (dp83640 == clock->chosen) {
1208 ptp_clock_unregister(clock->ptp_clock);
1209 clock->chosen = NULL;
1210 } else {
1211 list_for_each_safe(this, next, &clock->phylist) {
1212 tmp = list_entry(this, struct dp83640_private, list);
1213 if (tmp == dp83640) {
1214 list_del_init(&tmp->list);
1215 break;
1216 }
1217 }
1218 }
1219
1220 dp83640_clock_put(clock);
1221 kfree(dp83640);
1222 }
1223
1224 static int dp83640_soft_reset(struct phy_device *phydev)
1225 {
1226 int ret;
1227
1228 ret = genphy_soft_reset(phydev);
1229 if (ret < 0)
1230 return ret;
1231
1232
1233
1234
1235
1236 udelay(10);
1237
1238 return 0;
1239 }
1240
1241 static int dp83640_config_init(struct phy_device *phydev)
1242 {
1243 struct dp83640_private *dp83640 = phydev->priv;
1244 struct dp83640_clock *clock = dp83640->clock;
1245
1246 if (clock->chosen && !list_empty(&clock->phylist))
1247 recalibrate(clock);
1248 else {
1249 mutex_lock(&clock->extreg_lock);
1250 enable_broadcast(phydev, clock->page, 1);
1251 mutex_unlock(&clock->extreg_lock);
1252 }
1253
1254 enable_status_frames(phydev, true);
1255
1256 mutex_lock(&clock->extreg_lock);
1257 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1258 mutex_unlock(&clock->extreg_lock);
1259
1260 return 0;
1261 }
1262
1263 static int dp83640_ack_interrupt(struct phy_device *phydev)
1264 {
1265 int err = phy_read(phydev, MII_DP83640_MISR);
1266
1267 if (err < 0)
1268 return err;
1269
1270 return 0;
1271 }
1272
1273 static int dp83640_config_intr(struct phy_device *phydev)
1274 {
1275 int micr;
1276 int misr;
1277 int err;
1278
1279 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1280 misr = phy_read(phydev, MII_DP83640_MISR);
1281 if (misr < 0)
1282 return misr;
1283 misr |=
1284 (MII_DP83640_MISR_ANC_INT_EN |
1285 MII_DP83640_MISR_DUP_INT_EN |
1286 MII_DP83640_MISR_SPD_INT_EN |
1287 MII_DP83640_MISR_LINK_INT_EN);
1288 err = phy_write(phydev, MII_DP83640_MISR, misr);
1289 if (err < 0)
1290 return err;
1291
1292 micr = phy_read(phydev, MII_DP83640_MICR);
1293 if (micr < 0)
1294 return micr;
1295 micr |=
1296 (MII_DP83640_MICR_OE |
1297 MII_DP83640_MICR_IE);
1298 return phy_write(phydev, MII_DP83640_MICR, micr);
1299 } else {
1300 micr = phy_read(phydev, MII_DP83640_MICR);
1301 if (micr < 0)
1302 return micr;
1303 micr &=
1304 ~(MII_DP83640_MICR_OE |
1305 MII_DP83640_MICR_IE);
1306 err = phy_write(phydev, MII_DP83640_MICR, micr);
1307 if (err < 0)
1308 return err;
1309
1310 misr = phy_read(phydev, MII_DP83640_MISR);
1311 if (misr < 0)
1312 return misr;
1313 misr &=
1314 ~(MII_DP83640_MISR_ANC_INT_EN |
1315 MII_DP83640_MISR_DUP_INT_EN |
1316 MII_DP83640_MISR_SPD_INT_EN |
1317 MII_DP83640_MISR_LINK_INT_EN);
1318 return phy_write(phydev, MII_DP83640_MISR, misr);
1319 }
1320 }
1321
1322 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1323 {
1324 struct dp83640_private *dp83640 = phydev->priv;
1325 struct hwtstamp_config cfg;
1326 u16 txcfg0, rxcfg0;
1327
1328 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1329 return -EFAULT;
1330
1331 if (cfg.flags)
1332 return -EINVAL;
1333
1334 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1335 return -ERANGE;
1336
1337 dp83640->hwts_tx_en = cfg.tx_type;
1338
1339 switch (cfg.rx_filter) {
1340 case HWTSTAMP_FILTER_NONE:
1341 dp83640->hwts_rx_en = 0;
1342 dp83640->layer = 0;
1343 dp83640->version = 0;
1344 break;
1345 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1346 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1347 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1348 dp83640->hwts_rx_en = 1;
1349 dp83640->layer = PTP_CLASS_L4;
1350 dp83640->version = PTP_CLASS_V1;
1351 break;
1352 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1353 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1354 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1355 dp83640->hwts_rx_en = 1;
1356 dp83640->layer = PTP_CLASS_L4;
1357 dp83640->version = PTP_CLASS_V2;
1358 break;
1359 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1360 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1361 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1362 dp83640->hwts_rx_en = 1;
1363 dp83640->layer = PTP_CLASS_L2;
1364 dp83640->version = PTP_CLASS_V2;
1365 break;
1366 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1367 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1368 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1369 dp83640->hwts_rx_en = 1;
1370 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1371 dp83640->version = PTP_CLASS_V2;
1372 break;
1373 default:
1374 return -ERANGE;
1375 }
1376
1377 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1378 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1379
1380 if (dp83640->layer & PTP_CLASS_L2) {
1381 txcfg0 |= TX_L2_EN;
1382 rxcfg0 |= RX_L2_EN;
1383 }
1384 if (dp83640->layer & PTP_CLASS_L4) {
1385 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1386 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1387 }
1388
1389 if (dp83640->hwts_tx_en)
1390 txcfg0 |= TX_TS_EN;
1391
1392 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1393 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1394
1395 if (dp83640->hwts_rx_en)
1396 rxcfg0 |= RX_TS_EN;
1397
1398 mutex_lock(&dp83640->clock->extreg_lock);
1399
1400 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1401 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1402
1403 mutex_unlock(&dp83640->clock->extreg_lock);
1404
1405 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1406 }
1407
1408 static void rx_timestamp_work(struct work_struct *work)
1409 {
1410 struct dp83640_private *dp83640 =
1411 container_of(work, struct dp83640_private, ts_work.work);
1412 struct sk_buff *skb;
1413
1414
1415 while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1416 struct dp83640_skb_info *skb_info;
1417
1418 skb_info = (struct dp83640_skb_info *)skb->cb;
1419 if (!time_after(jiffies, skb_info->tmo)) {
1420 skb_queue_head(&dp83640->rx_queue, skb);
1421 break;
1422 }
1423
1424 netif_rx_ni(skb);
1425 }
1426
1427 if (!skb_queue_empty(&dp83640->rx_queue))
1428 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1429 }
1430
1431 static bool dp83640_rxtstamp(struct phy_device *phydev,
1432 struct sk_buff *skb, int type)
1433 {
1434 struct dp83640_private *dp83640 = phydev->priv;
1435 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1436 struct list_head *this, *next;
1437 struct rxts *rxts;
1438 struct skb_shared_hwtstamps *shhwtstamps = NULL;
1439 unsigned long flags;
1440
1441 if (is_status_frame(skb, type)) {
1442 decode_status_frame(dp83640, skb);
1443 kfree_skb(skb);
1444 return true;
1445 }
1446
1447 if (!dp83640->hwts_rx_en)
1448 return false;
1449
1450 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
1451 return false;
1452
1453 spin_lock_irqsave(&dp83640->rx_lock, flags);
1454 prune_rx_ts(dp83640);
1455 list_for_each_safe(this, next, &dp83640->rxts) {
1456 rxts = list_entry(this, struct rxts, list);
1457 if (match(skb, type, rxts)) {
1458 shhwtstamps = skb_hwtstamps(skb);
1459 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1460 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1461 list_del_init(&rxts->list);
1462 list_add(&rxts->list, &dp83640->rxpool);
1463 break;
1464 }
1465 }
1466 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1467
1468 if (!shhwtstamps) {
1469 skb_info->ptp_type = type;
1470 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1471 skb_queue_tail(&dp83640->rx_queue, skb);
1472 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1473 } else {
1474 netif_rx_ni(skb);
1475 }
1476
1477 return true;
1478 }
1479
1480 static void dp83640_txtstamp(struct phy_device *phydev,
1481 struct sk_buff *skb, int type)
1482 {
1483 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1484 struct dp83640_private *dp83640 = phydev->priv;
1485
1486 switch (dp83640->hwts_tx_en) {
1487
1488 case HWTSTAMP_TX_ONESTEP_SYNC:
1489 if (is_sync(skb, type)) {
1490 kfree_skb(skb);
1491 return;
1492 }
1493
1494 case HWTSTAMP_TX_ON:
1495 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1496 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1497 skb_queue_tail(&dp83640->tx_queue, skb);
1498 break;
1499
1500 case HWTSTAMP_TX_OFF:
1501 default:
1502 kfree_skb(skb);
1503 break;
1504 }
1505 }
1506
1507 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1508 {
1509 struct dp83640_private *dp83640 = dev->priv;
1510
1511 info->so_timestamping =
1512 SOF_TIMESTAMPING_TX_HARDWARE |
1513 SOF_TIMESTAMPING_RX_HARDWARE |
1514 SOF_TIMESTAMPING_RAW_HARDWARE;
1515 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1516 info->tx_types =
1517 (1 << HWTSTAMP_TX_OFF) |
1518 (1 << HWTSTAMP_TX_ON) |
1519 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1520 info->rx_filters =
1521 (1 << HWTSTAMP_FILTER_NONE) |
1522 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1523 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1524 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1525 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1526 return 0;
1527 }
1528
1529 static struct phy_driver dp83640_driver = {
1530 .phy_id = DP83640_PHY_ID,
1531 .phy_id_mask = 0xfffffff0,
1532 .name = "NatSemi DP83640",
1533
1534 .probe = dp83640_probe,
1535 .remove = dp83640_remove,
1536 .soft_reset = dp83640_soft_reset,
1537 .config_init = dp83640_config_init,
1538 .ack_interrupt = dp83640_ack_interrupt,
1539 .config_intr = dp83640_config_intr,
1540 .ts_info = dp83640_ts_info,
1541 .hwtstamp = dp83640_hwtstamp,
1542 .rxtstamp = dp83640_rxtstamp,
1543 .txtstamp = dp83640_txtstamp,
1544 };
1545
1546 static int __init dp83640_init(void)
1547 {
1548 return phy_driver_register(&dp83640_driver, THIS_MODULE);
1549 }
1550
1551 static void __exit dp83640_exit(void)
1552 {
1553 dp83640_free_clocks();
1554 phy_driver_unregister(&dp83640_driver);
1555 }
1556
1557 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1558 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1559 MODULE_LICENSE("GPL");
1560
1561 module_init(dp83640_init);
1562 module_exit(dp83640_exit);
1563
1564 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1565 { DP83640_PHY_ID, 0xfffffff0 },
1566 { }
1567 };
1568
1569 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);