root/drivers/net/phy/national.c

DEFINITIONS

1. ns_exp_read
2. ns_exp_write
3. ns_config_intr
4. ns_ack_interrupt
5. ns_giga_speed_fallback
6. ns_10_base_t_hdx_loopack
7. ns_config_init

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/national.c
   4  *
   5  * Driver for National Semiconductor PHYs
   6  *
   7  * Author: Stuart Menefy <stuart.menefy@st.com>
   8  * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
   9  *
  10  * Copyright (c) 2008 STMicroelectronics Limited
  11  */
  12 
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14 
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/mii.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/netdevice.h>
  21 
  22 #define DEBUG
  23 
  24 /* DP83865 phy identifier values */
  25 #define DP83865_PHY_ID  0x20005c7a
  26 
  27 #define DP83865_INT_STATUS      0x14
  28 #define DP83865_INT_MASK        0x15
  29 #define DP83865_INT_CLEAR       0x17
  30 
  31 #define DP83865_INT_REMOTE_FAULT 0x0008
  32 #define DP83865_INT_ANE_COMPLETED 0x0010
  33 #define DP83865_INT_LINK_CHANGE 0xe000
  34 #define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \
  35                                 DP83865_INT_ANE_COMPLETED | \
  36                                 DP83865_INT_LINK_CHANGE)
  37 
  38 /* Advanced proprietary configuration */
  39 #define NS_EXP_MEM_CTL  0x16
  40 #define NS_EXP_MEM_DATA 0x1d
  41 #define NS_EXP_MEM_ADD  0x1e
  42 
  43 #define LED_CTRL_REG 0x13
  44 #define AN_FALLBACK_AN 0x0001
  45 #define AN_FALLBACK_CRC 0x0002
  46 #define AN_FALLBACK_IE 0x0004
  47 #define ALL_FALLBACK_ON (AN_FALLBACK_AN |  AN_FALLBACK_CRC | AN_FALLBACK_IE)
  48 
  49 enum hdx_loopback {
  50         hdx_loopback_on = 0,
  51         hdx_loopback_off = 1,
  52 };
  53 
  54 static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
  55 {
  56         phy_write(phydev, NS_EXP_MEM_ADD, reg);
  57         return phy_read(phydev, NS_EXP_MEM_DATA);
  58 }
  59 
  60 static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
  61 {
  62         phy_write(phydev, NS_EXP_MEM_ADD, reg);
  63         phy_write(phydev, NS_EXP_MEM_DATA, data);
  64 }
  65 
  66 static int ns_config_intr(struct phy_device *phydev)
  67 {
  68         int err;
  69 
  70         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  71                 err = phy_write(phydev, DP83865_INT_MASK,
  72                                 DP83865_INT_MASK_DEFAULT);
  73         else
  74                 err = phy_write(phydev, DP83865_INT_MASK, 0);
  75 
  76         return err;
  77 }
  78 
  79 static int ns_ack_interrupt(struct phy_device *phydev)
  80 {
  81         int ret = phy_read(phydev, DP83865_INT_STATUS);
  82         if (ret < 0)
  83                 return ret;
  84 
  85         /* Clear the interrupt status bit by writing a “1”
  86          * to the corresponding bit in INT_CLEAR (2:0 are reserved) */
  87         ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
  88 
  89         return ret;
  90 }
  91 
  92 static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
  93 {
  94         int bmcr = phy_read(phydev, MII_BMCR);
  95 
  96         phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
  97 
  98         /* Enable 8 bit expended memory read/write (no auto increment) */
  99         phy_write(phydev, NS_EXP_MEM_CTL, 0);
 100         phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
 101         phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
 102         phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
 103         phy_write(phydev, LED_CTRL_REG, mode);
 104 }
 105 
 106 static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
 107 {
 108         u16 lb_dis = BIT(1);
 109 
 110         if (disable)
 111                 ns_exp_write(phydev, 0x1c0,
 112                              ns_exp_read(phydev, 0x1c0) | lb_dis);
 113         else
 114                 ns_exp_write(phydev, 0x1c0,
 115                              ns_exp_read(phydev, 0x1c0) & ~lb_dis);
 116 
 117         pr_debug("10BASE-T HDX loopback %s\n",
 118                  (ns_exp_read(phydev, 0x1c0) & lb_dis) ? "off" : "on");
 119 }
 120 
 121 static int ns_config_init(struct phy_device *phydev)
 122 {
 123         ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
 124         /* In the latest MAC or switches design, the 10 Mbps loopback
 125            is desired to be turned off. */
 126         ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
 127         return ns_ack_interrupt(phydev);
 128 }
 129 
 130 static struct phy_driver dp83865_driver[] = { {
 131         .phy_id = DP83865_PHY_ID,
 132         .phy_id_mask = 0xfffffff0,
 133         .name = "NatSemi DP83865",
 134         /* PHY_GBIT_FEATURES */
 135         .config_init = ns_config_init,
 136         .ack_interrupt = ns_ack_interrupt,
 137         .config_intr = ns_config_intr,
 138 } };
 139 
 140 module_phy_driver(dp83865_driver);
 141 
 142 MODULE_DESCRIPTION("NatSemi PHY driver");
 143 MODULE_AUTHOR("Stuart Menefy");
 144 MODULE_LICENSE("GPL");
 145 
 146 static struct mdio_device_id __maybe_unused ns_tbl[] = {
 147         { DP83865_PHY_ID, 0xfffffff0 },
 148         { }
 149 };
 150 
 151 MODULE_DEVICE_TABLE(mdio, ns_tbl);