root/drivers/net/phy/micrel.c

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DEFINITIONS

This source file includes following definitions.
  1. kszphy_extended_write
  2. kszphy_extended_read
  3. kszphy_ack_interrupt
  4. kszphy_config_intr
  5. kszphy_rmii_clk_sel
  6. kszphy_setup_led
  7. kszphy_broadcast_disable
  8. kszphy_nand_tree_disable
  9. kszphy_config_reset
  10. kszphy_config_init
  11. ksz8041_config_init
  12. ksz8041_config_aneg
  13. ksz8051_ksz8795_match_phy_device
  14. ksz8051_match_phy_device
  15. ksz8081_config_init
  16. ksz8061_config_init
  17. ksz8795_match_phy_device
  18. ksz9021_load_values_from_of
  19. ksz9021_config_init
  20. ksz9031_of_load_skew_values
  21. ksz9031_center_flp_timing
  22. ksz9031_enable_edpd
  23. ksz9031_config_init
  24. ksz9131_of_load_skew_values
  25. ksz9131_config_init
  26. ksz8873mll_read_status
  27. ksz9031_get_features
  28. ksz9031_read_status
  29. ksz8873mll_config_aneg
  30. kszphy_get_sset_count
  31. kszphy_get_strings
  32. kszphy_get_stat
  33. kszphy_get_stats
  34. kszphy_suspend
  35. kszphy_resume
  36. kszphy_probe

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/micrel.c
   4  *
   5  * Driver for Micrel PHYs
   6  *
   7  * Author: David J. Choi
   8  *
   9  * Copyright (c) 2010-2013 Micrel, Inc.
  10  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  11  *
  12  * Support : Micrel Phys:
  13  *              Giga phys: ksz9021, ksz9031, ksz9131
  14  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  15  *                         ksz8021, ksz8031, ksz8051,
  16  *                         ksz8081, ksz8091,
  17  *                         ksz8061,
  18  *              Switch : ksz8873, ksz886x
  19  *                       ksz9477
  20  */
  21 
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/phy.h>
  25 #include <linux/micrel_phy.h>
  26 #include <linux/of.h>
  27 #include <linux/clk.h>
  28 #include <linux/delay.h>
  29 
  30 /* Operation Mode Strap Override */
  31 #define MII_KSZPHY_OMSO                         0x16
  32 #define KSZPHY_OMSO_FACTORY_TEST                BIT(15)
  33 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  34 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  35 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  36 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  37 
  38 /* general Interrupt control/status reg in vendor specific block. */
  39 #define MII_KSZPHY_INTCS                        0x1B
  40 #define KSZPHY_INTCS_JABBER                     BIT(15)
  41 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  42 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  43 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  44 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  45 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  46 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  47 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  48 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  49                                                 KSZPHY_INTCS_LINK_DOWN)
  50 
  51 /* PHY Control 1 */
  52 #define MII_KSZPHY_CTRL_1                       0x1e
  53 
  54 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
  55 #define MII_KSZPHY_CTRL_2                       0x1f
  56 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
  57 /* bitmap of PHY register to set interrupt mode */
  58 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
  59 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
  60 
  61 /* Write/read to/from extended registers */
  62 #define MII_KSZPHY_EXTREG                       0x0b
  63 #define KSZPHY_EXTREG_WRITE                     0x8000
  64 
  65 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
  66 #define MII_KSZPHY_EXTREG_READ                  0x0d
  67 
  68 /* Extended registers */
  69 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
  70 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
  71 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
  72 
  73 #define PS_TO_REG                               200
  74 
  75 struct kszphy_hw_stat {
  76         const char *string;
  77         u8 reg;
  78         u8 bits;
  79 };
  80 
  81 static struct kszphy_hw_stat kszphy_hw_stats[] = {
  82         { "phy_receive_errors", 21, 16},
  83         { "phy_idle_errors", 10, 8 },
  84 };
  85 
  86 struct kszphy_type {
  87         u32 led_mode_reg;
  88         u16 interrupt_level_mask;
  89         bool has_broadcast_disable;
  90         bool has_nand_tree_disable;
  91         bool has_rmii_ref_clk_sel;
  92 };
  93 
  94 struct kszphy_priv {
  95         const struct kszphy_type *type;
  96         int led_mode;
  97         bool rmii_ref_clk_sel;
  98         bool rmii_ref_clk_sel_val;
  99         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 100 };
 101 
 102 static const struct kszphy_type ksz8021_type = {
 103         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 104         .has_broadcast_disable  = true,
 105         .has_nand_tree_disable  = true,
 106         .has_rmii_ref_clk_sel   = true,
 107 };
 108 
 109 static const struct kszphy_type ksz8041_type = {
 110         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 111 };
 112 
 113 static const struct kszphy_type ksz8051_type = {
 114         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 115         .has_nand_tree_disable  = true,
 116 };
 117 
 118 static const struct kszphy_type ksz8081_type = {
 119         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 120         .has_broadcast_disable  = true,
 121         .has_nand_tree_disable  = true,
 122         .has_rmii_ref_clk_sel   = true,
 123 };
 124 
 125 static const struct kszphy_type ks8737_type = {
 126         .interrupt_level_mask   = BIT(14),
 127 };
 128 
 129 static const struct kszphy_type ksz9021_type = {
 130         .interrupt_level_mask   = BIT(14),
 131 };
 132 
 133 static int kszphy_extended_write(struct phy_device *phydev,
 134                                 u32 regnum, u16 val)
 135 {
 136         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 137         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 138 }
 139 
 140 static int kszphy_extended_read(struct phy_device *phydev,
 141                                 u32 regnum)
 142 {
 143         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 144         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 145 }
 146 
 147 static int kszphy_ack_interrupt(struct phy_device *phydev)
 148 {
 149         /* bit[7..0] int status, which is a read and clear register. */
 150         int rc;
 151 
 152         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 153 
 154         return (rc < 0) ? rc : 0;
 155 }
 156 
 157 static int kszphy_config_intr(struct phy_device *phydev)
 158 {
 159         const struct kszphy_type *type = phydev->drv->driver_data;
 160         int temp;
 161         u16 mask;
 162 
 163         if (type && type->interrupt_level_mask)
 164                 mask = type->interrupt_level_mask;
 165         else
 166                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 167 
 168         /* set the interrupt pin active low */
 169         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 170         if (temp < 0)
 171                 return temp;
 172         temp &= ~mask;
 173         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 174 
 175         /* enable / disable interrupts */
 176         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 177                 temp = KSZPHY_INTCS_ALL;
 178         else
 179                 temp = 0;
 180 
 181         return phy_write(phydev, MII_KSZPHY_INTCS, temp);
 182 }
 183 
 184 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 185 {
 186         int ctrl;
 187 
 188         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 189         if (ctrl < 0)
 190                 return ctrl;
 191 
 192         if (val)
 193                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 194         else
 195                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 196 
 197         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 198 }
 199 
 200 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 201 {
 202         int rc, temp, shift;
 203 
 204         switch (reg) {
 205         case MII_KSZPHY_CTRL_1:
 206                 shift = 14;
 207                 break;
 208         case MII_KSZPHY_CTRL_2:
 209                 shift = 4;
 210                 break;
 211         default:
 212                 return -EINVAL;
 213         }
 214 
 215         temp = phy_read(phydev, reg);
 216         if (temp < 0) {
 217                 rc = temp;
 218                 goto out;
 219         }
 220 
 221         temp &= ~(3 << shift);
 222         temp |= val << shift;
 223         rc = phy_write(phydev, reg, temp);
 224 out:
 225         if (rc < 0)
 226                 phydev_err(phydev, "failed to set led mode\n");
 227 
 228         return rc;
 229 }
 230 
 231 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 232  * unique (non-broadcast) address on a shared bus.
 233  */
 234 static int kszphy_broadcast_disable(struct phy_device *phydev)
 235 {
 236         int ret;
 237 
 238         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 239         if (ret < 0)
 240                 goto out;
 241 
 242         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 243 out:
 244         if (ret)
 245                 phydev_err(phydev, "failed to disable broadcast address\n");
 246 
 247         return ret;
 248 }
 249 
 250 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 251 {
 252         int ret;
 253 
 254         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 255         if (ret < 0)
 256                 goto out;
 257 
 258         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 259                 return 0;
 260 
 261         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 262                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 263 out:
 264         if (ret)
 265                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 266 
 267         return ret;
 268 }
 269 
 270 /* Some config bits need to be set again on resume, handle them here. */
 271 static int kszphy_config_reset(struct phy_device *phydev)
 272 {
 273         struct kszphy_priv *priv = phydev->priv;
 274         int ret;
 275 
 276         if (priv->rmii_ref_clk_sel) {
 277                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 278                 if (ret) {
 279                         phydev_err(phydev,
 280                                    "failed to set rmii reference clock\n");
 281                         return ret;
 282                 }
 283         }
 284 
 285         if (priv->led_mode >= 0)
 286                 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 287 
 288         return 0;
 289 }
 290 
 291 static int kszphy_config_init(struct phy_device *phydev)
 292 {
 293         struct kszphy_priv *priv = phydev->priv;
 294         const struct kszphy_type *type;
 295 
 296         if (!priv)
 297                 return 0;
 298 
 299         type = priv->type;
 300 
 301         if (type->has_broadcast_disable)
 302                 kszphy_broadcast_disable(phydev);
 303 
 304         if (type->has_nand_tree_disable)
 305                 kszphy_nand_tree_disable(phydev);
 306 
 307         return kszphy_config_reset(phydev);
 308 }
 309 
 310 static int ksz8041_config_init(struct phy_device *phydev)
 311 {
 312         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 313 
 314         struct device_node *of_node = phydev->mdio.dev.of_node;
 315 
 316         /* Limit supported and advertised modes in fiber mode */
 317         if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
 318                 phydev->dev_flags |= MICREL_PHY_FXEN;
 319                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
 320                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
 321 
 322                 linkmode_and(phydev->supported, phydev->supported, mask);
 323                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 324                                  phydev->supported);
 325                 linkmode_and(phydev->advertising, phydev->advertising, mask);
 326                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 327                                  phydev->advertising);
 328                 phydev->autoneg = AUTONEG_DISABLE;
 329         }
 330 
 331         return kszphy_config_init(phydev);
 332 }
 333 
 334 static int ksz8041_config_aneg(struct phy_device *phydev)
 335 {
 336         /* Skip auto-negotiation in fiber mode */
 337         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 338                 phydev->speed = SPEED_100;
 339                 return 0;
 340         }
 341 
 342         return genphy_config_aneg(phydev);
 343 }
 344 
 345 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
 346                                             const u32 ksz_phy_id)
 347 {
 348         int ret;
 349 
 350         if ((phydev->phy_id & MICREL_PHY_ID_MASK) != ksz_phy_id)
 351                 return 0;
 352 
 353         ret = phy_read(phydev, MII_BMSR);
 354         if (ret < 0)
 355                 return ret;
 356 
 357         /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
 358          * exact PHY ID. However, they can be told apart by the extended
 359          * capability registers presence. The KSZ8051 PHY has them while
 360          * the switch does not.
 361          */
 362         ret &= BMSR_ERCAP;
 363         if (ksz_phy_id == PHY_ID_KSZ8051)
 364                 return ret;
 365         else
 366                 return !ret;
 367 }
 368 
 369 static int ksz8051_match_phy_device(struct phy_device *phydev)
 370 {
 371         return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ8051);
 372 }
 373 
 374 static int ksz8081_config_init(struct phy_device *phydev)
 375 {
 376         /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
 377          * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
 378          * pull-down is missing, the factory test mode should be cleared by
 379          * manually writing a 0.
 380          */
 381         phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
 382 
 383         return kszphy_config_init(phydev);
 384 }
 385 
 386 static int ksz8061_config_init(struct phy_device *phydev)
 387 {
 388         int ret;
 389 
 390         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 391         if (ret)
 392                 return ret;
 393 
 394         return kszphy_config_init(phydev);
 395 }
 396 
 397 static int ksz8795_match_phy_device(struct phy_device *phydev)
 398 {
 399         return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ87XX);
 400 }
 401 
 402 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 403                                        const struct device_node *of_node,
 404                                        u16 reg,
 405                                        const char *field1, const char *field2,
 406                                        const char *field3, const char *field4)
 407 {
 408         int val1 = -1;
 409         int val2 = -2;
 410         int val3 = -3;
 411         int val4 = -4;
 412         int newval;
 413         int matches = 0;
 414 
 415         if (!of_property_read_u32(of_node, field1, &val1))
 416                 matches++;
 417 
 418         if (!of_property_read_u32(of_node, field2, &val2))
 419                 matches++;
 420 
 421         if (!of_property_read_u32(of_node, field3, &val3))
 422                 matches++;
 423 
 424         if (!of_property_read_u32(of_node, field4, &val4))
 425                 matches++;
 426 
 427         if (!matches)
 428                 return 0;
 429 
 430         if (matches < 4)
 431                 newval = kszphy_extended_read(phydev, reg);
 432         else
 433                 newval = 0;
 434 
 435         if (val1 != -1)
 436                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 437 
 438         if (val2 != -2)
 439                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 440 
 441         if (val3 != -3)
 442                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 443 
 444         if (val4 != -4)
 445                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 446 
 447         return kszphy_extended_write(phydev, reg, newval);
 448 }
 449 
 450 static int ksz9021_config_init(struct phy_device *phydev)
 451 {
 452         const struct device *dev = &phydev->mdio.dev;
 453         const struct device_node *of_node = dev->of_node;
 454         const struct device *dev_walker;
 455 
 456         /* The Micrel driver has a deprecated option to place phy OF
 457          * properties in the MAC node. Walk up the tree of devices to
 458          * find a device with an OF node.
 459          */
 460         dev_walker = &phydev->mdio.dev;
 461         do {
 462                 of_node = dev_walker->of_node;
 463                 dev_walker = dev_walker->parent;
 464 
 465         } while (!of_node && dev_walker);
 466 
 467         if (of_node) {
 468                 ksz9021_load_values_from_of(phydev, of_node,
 469                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 470                                     "txen-skew-ps", "txc-skew-ps",
 471                                     "rxdv-skew-ps", "rxc-skew-ps");
 472                 ksz9021_load_values_from_of(phydev, of_node,
 473                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 474                                     "rxd0-skew-ps", "rxd1-skew-ps",
 475                                     "rxd2-skew-ps", "rxd3-skew-ps");
 476                 ksz9021_load_values_from_of(phydev, of_node,
 477                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 478                                     "txd0-skew-ps", "txd1-skew-ps",
 479                                     "txd2-skew-ps", "txd3-skew-ps");
 480         }
 481         return 0;
 482 }
 483 
 484 #define KSZ9031_PS_TO_REG               60
 485 
 486 /* Extended registers */
 487 /* MMD Address 0x0 */
 488 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 489 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 490 
 491 /* MMD Address 0x2 */
 492 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 493 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 494 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 495 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 496 
 497 /* MMD Address 0x1C */
 498 #define MII_KSZ9031RN_EDPD              0x23
 499 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 500 
 501 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 502                                        const struct device_node *of_node,
 503                                        u16 reg, size_t field_sz,
 504                                        const char *field[], u8 numfields)
 505 {
 506         int val[4] = {-1, -2, -3, -4};
 507         int matches = 0;
 508         u16 mask;
 509         u16 maxval;
 510         u16 newval;
 511         int i;
 512 
 513         for (i = 0; i < numfields; i++)
 514                 if (!of_property_read_u32(of_node, field[i], val + i))
 515                         matches++;
 516 
 517         if (!matches)
 518                 return 0;
 519 
 520         if (matches < numfields)
 521                 newval = phy_read_mmd(phydev, 2, reg);
 522         else
 523                 newval = 0;
 524 
 525         maxval = (field_sz == 4) ? 0xf : 0x1f;
 526         for (i = 0; i < numfields; i++)
 527                 if (val[i] != -(i + 1)) {
 528                         mask = 0xffff;
 529                         mask ^= maxval << (field_sz * i);
 530                         newval = (newval & mask) |
 531                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 532                                         << (field_sz * i));
 533                 }
 534 
 535         return phy_write_mmd(phydev, 2, reg, newval);
 536 }
 537 
 538 /* Center KSZ9031RNX FLP timing at 16ms. */
 539 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 540 {
 541         int result;
 542 
 543         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
 544                                0x0006);
 545         if (result)
 546                 return result;
 547 
 548         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
 549                                0x1A80);
 550         if (result)
 551                 return result;
 552 
 553         return genphy_restart_aneg(phydev);
 554 }
 555 
 556 /* Enable energy-detect power-down mode */
 557 static int ksz9031_enable_edpd(struct phy_device *phydev)
 558 {
 559         int reg;
 560 
 561         reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
 562         if (reg < 0)
 563                 return reg;
 564         return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
 565                              reg | MII_KSZ9031RN_EDPD_ENABLE);
 566 }
 567 
 568 static int ksz9031_config_init(struct phy_device *phydev)
 569 {
 570         const struct device *dev = &phydev->mdio.dev;
 571         const struct device_node *of_node = dev->of_node;
 572         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
 573         static const char *rx_data_skews[4] = {
 574                 "rxd0-skew-ps", "rxd1-skew-ps",
 575                 "rxd2-skew-ps", "rxd3-skew-ps"
 576         };
 577         static const char *tx_data_skews[4] = {
 578                 "txd0-skew-ps", "txd1-skew-ps",
 579                 "txd2-skew-ps", "txd3-skew-ps"
 580         };
 581         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 582         const struct device *dev_walker;
 583         int result;
 584 
 585         result = ksz9031_enable_edpd(phydev);
 586         if (result < 0)
 587                 return result;
 588 
 589         /* The Micrel driver has a deprecated option to place phy OF
 590          * properties in the MAC node. Walk up the tree of devices to
 591          * find a device with an OF node.
 592          */
 593         dev_walker = &phydev->mdio.dev;
 594         do {
 595                 of_node = dev_walker->of_node;
 596                 dev_walker = dev_walker->parent;
 597         } while (!of_node && dev_walker);
 598 
 599         if (of_node) {
 600                 ksz9031_of_load_skew_values(phydev, of_node,
 601                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 602                                 clk_skews, 2);
 603 
 604                 ksz9031_of_load_skew_values(phydev, of_node,
 605                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 606                                 control_skews, 2);
 607 
 608                 ksz9031_of_load_skew_values(phydev, of_node,
 609                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 610                                 rx_data_skews, 4);
 611 
 612                 ksz9031_of_load_skew_values(phydev, of_node,
 613                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 614                                 tx_data_skews, 4);
 615 
 616                 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
 617                  * When the device links in the 1000BASE-T slave mode only,
 618                  * the optional 125MHz reference output clock (CLK125_NDO)
 619                  * has wide duty cycle variation.
 620                  *
 621                  * The optional CLK125_NDO clock does not meet the RGMII
 622                  * 45/55 percent (min/max) duty cycle requirement and therefore
 623                  * cannot be used directly by the MAC side for clocking
 624                  * applications that have setup/hold time requirements on
 625                  * rising and falling clock edges.
 626                  *
 627                  * Workaround:
 628                  * Force the phy to be the master to receive a stable clock
 629                  * which meets the duty cycle requirement.
 630                  */
 631                 if (of_property_read_bool(of_node, "micrel,force-master")) {
 632                         result = phy_read(phydev, MII_CTRL1000);
 633                         if (result < 0)
 634                                 goto err_force_master;
 635 
 636                         /* enable master mode, config & prefer master */
 637                         result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
 638                         result = phy_write(phydev, MII_CTRL1000, result);
 639                         if (result < 0)
 640                                 goto err_force_master;
 641                 }
 642         }
 643 
 644         return ksz9031_center_flp_timing(phydev);
 645 
 646 err_force_master:
 647         phydev_err(phydev, "failed to force the phy to master mode\n");
 648         return result;
 649 }
 650 
 651 #define KSZ9131_SKEW_5BIT_MAX   2400
 652 #define KSZ9131_SKEW_4BIT_MAX   800
 653 #define KSZ9131_OFFSET          700
 654 #define KSZ9131_STEP            100
 655 
 656 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
 657                                        struct device_node *of_node,
 658                                        u16 reg, size_t field_sz,
 659                                        char *field[], u8 numfields)
 660 {
 661         int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
 662                       -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
 663         int skewval, skewmax = 0;
 664         int matches = 0;
 665         u16 maxval;
 666         u16 newval;
 667         u16 mask;
 668         int i;
 669 
 670         /* psec properties in dts should mean x pico seconds */
 671         if (field_sz == 5)
 672                 skewmax = KSZ9131_SKEW_5BIT_MAX;
 673         else
 674                 skewmax = KSZ9131_SKEW_4BIT_MAX;
 675 
 676         for (i = 0; i < numfields; i++)
 677                 if (!of_property_read_s32(of_node, field[i], &skewval)) {
 678                         if (skewval < -KSZ9131_OFFSET)
 679                                 skewval = -KSZ9131_OFFSET;
 680                         else if (skewval > skewmax)
 681                                 skewval = skewmax;
 682 
 683                         val[i] = skewval + KSZ9131_OFFSET;
 684                         matches++;
 685                 }
 686 
 687         if (!matches)
 688                 return 0;
 689 
 690         if (matches < numfields)
 691                 newval = phy_read_mmd(phydev, 2, reg);
 692         else
 693                 newval = 0;
 694 
 695         maxval = (field_sz == 4) ? 0xf : 0x1f;
 696         for (i = 0; i < numfields; i++)
 697                 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
 698                         mask = 0xffff;
 699                         mask ^= maxval << (field_sz * i);
 700                         newval = (newval & mask) |
 701                                 (((val[i] / KSZ9131_STEP) & maxval)
 702                                         << (field_sz * i));
 703                 }
 704 
 705         return phy_write_mmd(phydev, 2, reg, newval);
 706 }
 707 
 708 static int ksz9131_config_init(struct phy_device *phydev)
 709 {
 710         const struct device *dev = &phydev->mdio.dev;
 711         struct device_node *of_node = dev->of_node;
 712         char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
 713         char *rx_data_skews[4] = {
 714                 "rxd0-skew-psec", "rxd1-skew-psec",
 715                 "rxd2-skew-psec", "rxd3-skew-psec"
 716         };
 717         char *tx_data_skews[4] = {
 718                 "txd0-skew-psec", "txd1-skew-psec",
 719                 "txd2-skew-psec", "txd3-skew-psec"
 720         };
 721         char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
 722         const struct device *dev_walker;
 723         int ret;
 724 
 725         dev_walker = &phydev->mdio.dev;
 726         do {
 727                 of_node = dev_walker->of_node;
 728                 dev_walker = dev_walker->parent;
 729         } while (!of_node && dev_walker);
 730 
 731         if (!of_node)
 732                 return 0;
 733 
 734         ret = ksz9131_of_load_skew_values(phydev, of_node,
 735                                           MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 736                                           clk_skews, 2);
 737         if (ret < 0)
 738                 return ret;
 739 
 740         ret = ksz9131_of_load_skew_values(phydev, of_node,
 741                                           MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 742                                           control_skews, 2);
 743         if (ret < 0)
 744                 return ret;
 745 
 746         ret = ksz9131_of_load_skew_values(phydev, of_node,
 747                                           MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 748                                           rx_data_skews, 4);
 749         if (ret < 0)
 750                 return ret;
 751 
 752         ret = ksz9131_of_load_skew_values(phydev, of_node,
 753                                           MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 754                                           tx_data_skews, 4);
 755         if (ret < 0)
 756                 return ret;
 757 
 758         return 0;
 759 }
 760 
 761 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
 762 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
 763 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
 764 static int ksz8873mll_read_status(struct phy_device *phydev)
 765 {
 766         int regval;
 767 
 768         /* dummy read */
 769         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 770 
 771         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 772 
 773         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
 774                 phydev->duplex = DUPLEX_HALF;
 775         else
 776                 phydev->duplex = DUPLEX_FULL;
 777 
 778         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
 779                 phydev->speed = SPEED_10;
 780         else
 781                 phydev->speed = SPEED_100;
 782 
 783         phydev->link = 1;
 784         phydev->pause = phydev->asym_pause = 0;
 785 
 786         return 0;
 787 }
 788 
 789 static int ksz9031_get_features(struct phy_device *phydev)
 790 {
 791         int ret;
 792 
 793         ret = genphy_read_abilities(phydev);
 794         if (ret < 0)
 795                 return ret;
 796 
 797         /* Silicon Errata Sheet (DS80000691D or DS80000692D):
 798          * Whenever the device's Asymmetric Pause capability is set to 1,
 799          * link-up may fail after a link-up to link-down transition.
 800          *
 801          * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
 802          *
 803          * Workaround:
 804          * Do not enable the Asymmetric Pause capability bit.
 805          */
 806         linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
 807 
 808         /* We force setting the Pause capability as the core will force the
 809          * Asymmetric Pause capability to 1 otherwise.
 810          */
 811         linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
 812 
 813         return 0;
 814 }
 815 
 816 static int ksz9031_read_status(struct phy_device *phydev)
 817 {
 818         int err;
 819         int regval;
 820 
 821         err = genphy_read_status(phydev);
 822         if (err)
 823                 return err;
 824 
 825         /* Make sure the PHY is not broken. Read idle error count,
 826          * and reset the PHY if it is maxed out.
 827          */
 828         regval = phy_read(phydev, MII_STAT1000);
 829         if ((regval & 0xFF) == 0xFF) {
 830                 phy_init_hw(phydev);
 831                 phydev->link = 0;
 832                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
 833                         phydev->drv->config_intr(phydev);
 834                 return genphy_config_aneg(phydev);
 835         }
 836 
 837         return 0;
 838 }
 839 
 840 static int ksz8873mll_config_aneg(struct phy_device *phydev)
 841 {
 842         return 0;
 843 }
 844 
 845 static int kszphy_get_sset_count(struct phy_device *phydev)
 846 {
 847         return ARRAY_SIZE(kszphy_hw_stats);
 848 }
 849 
 850 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
 851 {
 852         int i;
 853 
 854         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
 855                 strlcpy(data + i * ETH_GSTRING_LEN,
 856                         kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
 857         }
 858 }
 859 
 860 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
 861 {
 862         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
 863         struct kszphy_priv *priv = phydev->priv;
 864         int val;
 865         u64 ret;
 866 
 867         val = phy_read(phydev, stat.reg);
 868         if (val < 0) {
 869                 ret = U64_MAX;
 870         } else {
 871                 val = val & ((1 << stat.bits) - 1);
 872                 priv->stats[i] += val;
 873                 ret = priv->stats[i];
 874         }
 875 
 876         return ret;
 877 }
 878 
 879 static void kszphy_get_stats(struct phy_device *phydev,
 880                              struct ethtool_stats *stats, u64 *data)
 881 {
 882         int i;
 883 
 884         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
 885                 data[i] = kszphy_get_stat(phydev, i);
 886 }
 887 
 888 static int kszphy_suspend(struct phy_device *phydev)
 889 {
 890         /* Disable PHY Interrupts */
 891         if (phy_interrupt_is_valid(phydev)) {
 892                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
 893                 if (phydev->drv->config_intr)
 894                         phydev->drv->config_intr(phydev);
 895         }
 896 
 897         return genphy_suspend(phydev);
 898 }
 899 
 900 static int kszphy_resume(struct phy_device *phydev)
 901 {
 902         int ret;
 903 
 904         genphy_resume(phydev);
 905 
 906         /* After switching from power-down to normal mode, an internal global
 907          * reset is automatically generated. Wait a minimum of 1 ms before
 908          * read/write access to the PHY registers.
 909          */
 910         usleep_range(1000, 2000);
 911 
 912         ret = kszphy_config_reset(phydev);
 913         if (ret)
 914                 return ret;
 915 
 916         /* Enable PHY Interrupts */
 917         if (phy_interrupt_is_valid(phydev)) {
 918                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
 919                 if (phydev->drv->config_intr)
 920                         phydev->drv->config_intr(phydev);
 921         }
 922 
 923         return 0;
 924 }
 925 
 926 static int kszphy_probe(struct phy_device *phydev)
 927 {
 928         const struct kszphy_type *type = phydev->drv->driver_data;
 929         const struct device_node *np = phydev->mdio.dev.of_node;
 930         struct kszphy_priv *priv;
 931         struct clk *clk;
 932         int ret;
 933 
 934         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 935         if (!priv)
 936                 return -ENOMEM;
 937 
 938         phydev->priv = priv;
 939 
 940         priv->type = type;
 941 
 942         if (type->led_mode_reg) {
 943                 ret = of_property_read_u32(np, "micrel,led-mode",
 944                                 &priv->led_mode);
 945                 if (ret)
 946                         priv->led_mode = -1;
 947 
 948                 if (priv->led_mode > 3) {
 949                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
 950                                    priv->led_mode);
 951                         priv->led_mode = -1;
 952                 }
 953         } else {
 954                 priv->led_mode = -1;
 955         }
 956 
 957         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
 958         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
 959         if (!IS_ERR_OR_NULL(clk)) {
 960                 unsigned long rate = clk_get_rate(clk);
 961                 bool rmii_ref_clk_sel_25_mhz;
 962 
 963                 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
 964                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
 965                                 "micrel,rmii-reference-clock-select-25-mhz");
 966 
 967                 if (rate > 24500000 && rate < 25500000) {
 968                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
 969                 } else if (rate > 49500000 && rate < 50500000) {
 970                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
 971                 } else {
 972                         phydev_err(phydev, "Clock rate out of range: %ld\n",
 973                                    rate);
 974                         return -EINVAL;
 975                 }
 976         }
 977 
 978         /* Support legacy board-file configuration */
 979         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
 980                 priv->rmii_ref_clk_sel = true;
 981                 priv->rmii_ref_clk_sel_val = true;
 982         }
 983 
 984         return 0;
 985 }
 986 
 987 static struct phy_driver ksphy_driver[] = {
 988 {
 989         .phy_id         = PHY_ID_KS8737,
 990         .phy_id_mask    = MICREL_PHY_ID_MASK,
 991         .name           = "Micrel KS8737",
 992         /* PHY_BASIC_FEATURES */
 993         .driver_data    = &ks8737_type,
 994         .config_init    = kszphy_config_init,
 995         .ack_interrupt  = kszphy_ack_interrupt,
 996         .config_intr    = kszphy_config_intr,
 997         .suspend        = genphy_suspend,
 998         .resume         = genphy_resume,
 999 }, {
1000         .phy_id         = PHY_ID_KSZ8021,
1001         .phy_id_mask    = 0x00ffffff,
1002         .name           = "Micrel KSZ8021 or KSZ8031",
1003         /* PHY_BASIC_FEATURES */
1004         .driver_data    = &ksz8021_type,
1005         .probe          = kszphy_probe,
1006         .config_init    = kszphy_config_init,
1007         .ack_interrupt  = kszphy_ack_interrupt,
1008         .config_intr    = kszphy_config_intr,
1009         .get_sset_count = kszphy_get_sset_count,
1010         .get_strings    = kszphy_get_strings,
1011         .get_stats      = kszphy_get_stats,
1012         .suspend        = genphy_suspend,
1013         .resume         = genphy_resume,
1014 }, {
1015         .phy_id         = PHY_ID_KSZ8031,
1016         .phy_id_mask    = 0x00ffffff,
1017         .name           = "Micrel KSZ8031",
1018         /* PHY_BASIC_FEATURES */
1019         .driver_data    = &ksz8021_type,
1020         .probe          = kszphy_probe,
1021         .config_init    = kszphy_config_init,
1022         .ack_interrupt  = kszphy_ack_interrupt,
1023         .config_intr    = kszphy_config_intr,
1024         .get_sset_count = kszphy_get_sset_count,
1025         .get_strings    = kszphy_get_strings,
1026         .get_stats      = kszphy_get_stats,
1027         .suspend        = genphy_suspend,
1028         .resume         = genphy_resume,
1029 }, {
1030         .phy_id         = PHY_ID_KSZ8041,
1031         .phy_id_mask    = MICREL_PHY_ID_MASK,
1032         .name           = "Micrel KSZ8041",
1033         /* PHY_BASIC_FEATURES */
1034         .driver_data    = &ksz8041_type,
1035         .probe          = kszphy_probe,
1036         .config_init    = ksz8041_config_init,
1037         .config_aneg    = ksz8041_config_aneg,
1038         .ack_interrupt  = kszphy_ack_interrupt,
1039         .config_intr    = kszphy_config_intr,
1040         .get_sset_count = kszphy_get_sset_count,
1041         .get_strings    = kszphy_get_strings,
1042         .get_stats      = kszphy_get_stats,
1043         .suspend        = genphy_suspend,
1044         .resume         = genphy_resume,
1045 }, {
1046         .phy_id         = PHY_ID_KSZ8041RNLI,
1047         .phy_id_mask    = MICREL_PHY_ID_MASK,
1048         .name           = "Micrel KSZ8041RNLI",
1049         /* PHY_BASIC_FEATURES */
1050         .driver_data    = &ksz8041_type,
1051         .probe          = kszphy_probe,
1052         .config_init    = kszphy_config_init,
1053         .ack_interrupt  = kszphy_ack_interrupt,
1054         .config_intr    = kszphy_config_intr,
1055         .get_sset_count = kszphy_get_sset_count,
1056         .get_strings    = kszphy_get_strings,
1057         .get_stats      = kszphy_get_stats,
1058         .suspend        = genphy_suspend,
1059         .resume         = genphy_resume,
1060 }, {
1061         .name           = "Micrel KSZ8051",
1062         /* PHY_BASIC_FEATURES */
1063         .driver_data    = &ksz8051_type,
1064         .probe          = kszphy_probe,
1065         .config_init    = kszphy_config_init,
1066         .ack_interrupt  = kszphy_ack_interrupt,
1067         .config_intr    = kszphy_config_intr,
1068         .get_sset_count = kszphy_get_sset_count,
1069         .get_strings    = kszphy_get_strings,
1070         .get_stats      = kszphy_get_stats,
1071         .match_phy_device = ksz8051_match_phy_device,
1072         .suspend        = genphy_suspend,
1073         .resume         = genphy_resume,
1074 }, {
1075         .phy_id         = PHY_ID_KSZ8001,
1076         .name           = "Micrel KSZ8001 or KS8721",
1077         .phy_id_mask    = 0x00fffffc,
1078         /* PHY_BASIC_FEATURES */
1079         .driver_data    = &ksz8041_type,
1080         .probe          = kszphy_probe,
1081         .config_init    = kszphy_config_init,
1082         .ack_interrupt  = kszphy_ack_interrupt,
1083         .config_intr    = kszphy_config_intr,
1084         .get_sset_count = kszphy_get_sset_count,
1085         .get_strings    = kszphy_get_strings,
1086         .get_stats      = kszphy_get_stats,
1087         .suspend        = genphy_suspend,
1088         .resume         = genphy_resume,
1089 }, {
1090         .phy_id         = PHY_ID_KSZ8081,
1091         .name           = "Micrel KSZ8081 or KSZ8091",
1092         .phy_id_mask    = MICREL_PHY_ID_MASK,
1093         /* PHY_BASIC_FEATURES */
1094         .driver_data    = &ksz8081_type,
1095         .probe          = kszphy_probe,
1096         .config_init    = ksz8081_config_init,
1097         .ack_interrupt  = kszphy_ack_interrupt,
1098         .config_intr    = kszphy_config_intr,
1099         .get_sset_count = kszphy_get_sset_count,
1100         .get_strings    = kszphy_get_strings,
1101         .get_stats      = kszphy_get_stats,
1102         .suspend        = kszphy_suspend,
1103         .resume         = kszphy_resume,
1104 }, {
1105         .phy_id         = PHY_ID_KSZ8061,
1106         .name           = "Micrel KSZ8061",
1107         .phy_id_mask    = MICREL_PHY_ID_MASK,
1108         /* PHY_BASIC_FEATURES */
1109         .config_init    = ksz8061_config_init,
1110         .ack_interrupt  = kszphy_ack_interrupt,
1111         .config_intr    = kszphy_config_intr,
1112         .suspend        = genphy_suspend,
1113         .resume         = genphy_resume,
1114 }, {
1115         .phy_id         = PHY_ID_KSZ9021,
1116         .phy_id_mask    = 0x000ffffe,
1117         .name           = "Micrel KSZ9021 Gigabit PHY",
1118         /* PHY_GBIT_FEATURES */
1119         .driver_data    = &ksz9021_type,
1120         .probe          = kszphy_probe,
1121         .get_features   = ksz9031_get_features,
1122         .config_init    = ksz9021_config_init,
1123         .ack_interrupt  = kszphy_ack_interrupt,
1124         .config_intr    = kszphy_config_intr,
1125         .get_sset_count = kszphy_get_sset_count,
1126         .get_strings    = kszphy_get_strings,
1127         .get_stats      = kszphy_get_stats,
1128         .suspend        = genphy_suspend,
1129         .resume         = genphy_resume,
1130         .read_mmd       = genphy_read_mmd_unsupported,
1131         .write_mmd      = genphy_write_mmd_unsupported,
1132 }, {
1133         .phy_id         = PHY_ID_KSZ9031,
1134         .phy_id_mask    = MICREL_PHY_ID_MASK,
1135         .name           = "Micrel KSZ9031 Gigabit PHY",
1136         .driver_data    = &ksz9021_type,
1137         .probe          = kszphy_probe,
1138         .get_features   = ksz9031_get_features,
1139         .config_init    = ksz9031_config_init,
1140         .soft_reset     = genphy_soft_reset,
1141         .read_status    = ksz9031_read_status,
1142         .ack_interrupt  = kszphy_ack_interrupt,
1143         .config_intr    = kszphy_config_intr,
1144         .get_sset_count = kszphy_get_sset_count,
1145         .get_strings    = kszphy_get_strings,
1146         .get_stats      = kszphy_get_stats,
1147         .suspend        = genphy_suspend,
1148         .resume         = kszphy_resume,
1149 }, {
1150         .phy_id         = PHY_ID_KSZ9131,
1151         .phy_id_mask    = MICREL_PHY_ID_MASK,
1152         .name           = "Microchip KSZ9131 Gigabit PHY",
1153         /* PHY_GBIT_FEATURES */
1154         .driver_data    = &ksz9021_type,
1155         .probe          = kszphy_probe,
1156         .config_init    = ksz9131_config_init,
1157         .read_status    = genphy_read_status,
1158         .ack_interrupt  = kszphy_ack_interrupt,
1159         .config_intr    = kszphy_config_intr,
1160         .get_sset_count = kszphy_get_sset_count,
1161         .get_strings    = kszphy_get_strings,
1162         .get_stats      = kszphy_get_stats,
1163         .suspend        = genphy_suspend,
1164         .resume         = kszphy_resume,
1165 }, {
1166         .phy_id         = PHY_ID_KSZ8873MLL,
1167         .phy_id_mask    = MICREL_PHY_ID_MASK,
1168         .name           = "Micrel KSZ8873MLL Switch",
1169         /* PHY_BASIC_FEATURES */
1170         .config_init    = kszphy_config_init,
1171         .config_aneg    = ksz8873mll_config_aneg,
1172         .read_status    = ksz8873mll_read_status,
1173         .suspend        = genphy_suspend,
1174         .resume         = genphy_resume,
1175 }, {
1176         .phy_id         = PHY_ID_KSZ886X,
1177         .phy_id_mask    = MICREL_PHY_ID_MASK,
1178         .name           = "Micrel KSZ886X Switch",
1179         /* PHY_BASIC_FEATURES */
1180         .config_init    = kszphy_config_init,
1181         .suspend        = genphy_suspend,
1182         .resume         = genphy_resume,
1183 }, {
1184         .name           = "Micrel KSZ87XX Switch",
1185         /* PHY_BASIC_FEATURES */
1186         .config_init    = kszphy_config_init,
1187         .config_aneg    = ksz8873mll_config_aneg,
1188         .read_status    = ksz8873mll_read_status,
1189         .match_phy_device = ksz8795_match_phy_device,
1190         .suspend        = genphy_suspend,
1191         .resume         = genphy_resume,
1192 }, {
1193         .phy_id         = PHY_ID_KSZ9477,
1194         .phy_id_mask    = MICREL_PHY_ID_MASK,
1195         .name           = "Microchip KSZ9477",
1196         /* PHY_GBIT_FEATURES */
1197         .config_init    = kszphy_config_init,
1198         .suspend        = genphy_suspend,
1199         .resume         = genphy_resume,
1200 } };
1201 
1202 module_phy_driver(ksphy_driver);
1203 
1204 MODULE_DESCRIPTION("Micrel PHY driver");
1205 MODULE_AUTHOR("David J. Choi");
1206 MODULE_LICENSE("GPL");
1207 
1208 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1209         { PHY_ID_KSZ9021, 0x000ffffe },
1210         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1211         { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
1212         { PHY_ID_KSZ8001, 0x00fffffc },
1213         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1214         { PHY_ID_KSZ8021, 0x00ffffff },
1215         { PHY_ID_KSZ8031, 0x00ffffff },
1216         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1217         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1218         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1219         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1220         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1221         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1222         { }
1223 };
1224 
1225 MODULE_DEVICE_TABLE(mdio, micrel_tbl);

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