root/drivers/net/dsa/mt7530.h

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INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. p5_intf_modes
  2. mt7530_hw_vlan_entry_init
  3. INIT_MT7530_DUMMY_POLL

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
   4  */
   5 
   6 #ifndef __MT7530_H
   7 #define __MT7530_H
   8 
   9 #define MT7530_NUM_PORTS                7
  10 #define MT7530_CPU_PORT                 6
  11 #define MT7530_NUM_FDB_RECORDS          2048
  12 #define MT7530_ALL_MEMBERS              0xff
  13 
  14 enum {
  15         ID_MT7530 = 0,
  16         ID_MT7621 = 1,
  17 };
  18 
  19 #define NUM_TRGMII_CTRL                 5
  20 
  21 #define TRGMII_BASE(x)                  (0x10000 + (x))
  22 
  23 /* Registers to ethsys access */
  24 #define ETHSYS_CLKCFG0                  0x2c
  25 #define  ETHSYS_TRGMII_CLK_SEL362_5     BIT(11)
  26 
  27 #define SYSC_REG_RSTCTRL                0x34
  28 #define  RESET_MCM                      BIT(2)
  29 
  30 /* Registers to mac forward control for unknown frames */
  31 #define MT7530_MFC                      0x10
  32 #define  BC_FFP(x)                      (((x) & 0xff) << 24)
  33 #define  UNM_FFP(x)                     (((x) & 0xff) << 16)
  34 #define  UNM_FFP_MASK                   UNM_FFP(~0)
  35 #define  UNU_FFP(x)                     (((x) & 0xff) << 8)
  36 #define  UNU_FFP_MASK                   UNU_FFP(~0)
  37 #define  CPU_EN                         BIT(7)
  38 #define  CPU_PORT(x)                    ((x) << 4)
  39 #define  CPU_MASK                       (0xf << 4)
  40 
  41 /* Registers for address table access */
  42 #define MT7530_ATA1                     0x74
  43 #define  STATIC_EMP                     0
  44 #define  STATIC_ENT                     3
  45 #define MT7530_ATA2                     0x78
  46 
  47 /* Register for address table write data */
  48 #define MT7530_ATWD                     0x7c
  49 
  50 /* Register for address table control */
  51 #define MT7530_ATC                      0x80
  52 #define  ATC_HASH                       (((x) & 0xfff) << 16)
  53 #define  ATC_BUSY                       BIT(15)
  54 #define  ATC_SRCH_END                   BIT(14)
  55 #define  ATC_SRCH_HIT                   BIT(13)
  56 #define  ATC_INVALID                    BIT(12)
  57 #define  ATC_MAT(x)                     (((x) & 0xf) << 8)
  58 #define  ATC_MAT_MACTAB                 ATC_MAT(0)
  59 
  60 enum mt7530_fdb_cmd {
  61         MT7530_FDB_READ = 0,
  62         MT7530_FDB_WRITE = 1,
  63         MT7530_FDB_FLUSH = 2,
  64         MT7530_FDB_START = 4,
  65         MT7530_FDB_NEXT = 5,
  66 };
  67 
  68 /* Registers for table search read address */
  69 #define MT7530_TSRA1                    0x84
  70 #define  MAC_BYTE_0                     24
  71 #define  MAC_BYTE_1                     16
  72 #define  MAC_BYTE_2                     8
  73 #define  MAC_BYTE_3                     0
  74 #define  MAC_BYTE_MASK                  0xff
  75 
  76 #define MT7530_TSRA2                    0x88
  77 #define  MAC_BYTE_4                     24
  78 #define  MAC_BYTE_5                     16
  79 #define  CVID                           0
  80 #define  CVID_MASK                      0xfff
  81 
  82 #define MT7530_ATRD                     0x8C
  83 #define  AGE_TIMER                      24
  84 #define  AGE_TIMER_MASK                 0xff
  85 #define  PORT_MAP                       4
  86 #define  PORT_MAP_MASK                  0xff
  87 #define  ENT_STATUS                     2
  88 #define  ENT_STATUS_MASK                0x3
  89 
  90 /* Register for vlan table control */
  91 #define MT7530_VTCR                     0x90
  92 #define  VTCR_BUSY                      BIT(31)
  93 #define  VTCR_INVALID                   BIT(16)
  94 #define  VTCR_FUNC(x)                   (((x) & 0xf) << 12)
  95 #define  VTCR_VID                       ((x) & 0xfff)
  96 
  97 enum mt7530_vlan_cmd {
  98         /* Read/Write the specified VID entry from VAWD register based
  99          * on VID.
 100          */
 101         MT7530_VTCR_RD_VID = 0,
 102         MT7530_VTCR_WR_VID = 1,
 103 };
 104 
 105 /* Register for setup vlan and acl write data */
 106 #define MT7530_VAWD1                    0x94
 107 #define  PORT_STAG                      BIT(31)
 108 /* Independent VLAN Learning */
 109 #define  IVL_MAC                        BIT(30)
 110 /* Per VLAN Egress Tag Control */
 111 #define  VTAG_EN                        BIT(28)
 112 /* VLAN Member Control */
 113 #define  PORT_MEM(x)                    (((x) & 0xff) << 16)
 114 /* VLAN Entry Valid */
 115 #define  VLAN_VALID                     BIT(0)
 116 #define  PORT_MEM_SHFT                  16
 117 #define  PORT_MEM_MASK                  0xff
 118 
 119 #define MT7530_VAWD2                    0x98
 120 /* Egress Tag Control */
 121 #define  ETAG_CTRL_P(p, x)              (((x) & 0x3) << ((p) << 1))
 122 #define  ETAG_CTRL_P_MASK(p)            ETAG_CTRL_P(p, 3)
 123 
 124 enum mt7530_vlan_egress_attr {
 125         MT7530_VLAN_EGRESS_UNTAG = 0,
 126         MT7530_VLAN_EGRESS_TAG = 2,
 127         MT7530_VLAN_EGRESS_STACK = 3,
 128 };
 129 
 130 /* Register for port STP state control */
 131 #define MT7530_SSP_P(x)                 (0x2000 + ((x) * 0x100))
 132 #define  FID_PST(x)                     ((x) & 0x3)
 133 #define  FID_PST_MASK                   FID_PST(0x3)
 134 
 135 enum mt7530_stp_state {
 136         MT7530_STP_DISABLED = 0,
 137         MT7530_STP_BLOCKING = 1,
 138         MT7530_STP_LISTENING = 1,
 139         MT7530_STP_LEARNING = 2,
 140         MT7530_STP_FORWARDING  = 3
 141 };
 142 
 143 /* Register for port control */
 144 #define MT7530_PCR_P(x)                 (0x2004 + ((x) * 0x100))
 145 #define  PORT_VLAN(x)                   ((x) & 0x3)
 146 
 147 enum mt7530_port_mode {
 148         /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
 149         MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
 150 
 151         /* Fallback Mode: Forward received frames with ingress ports that do
 152          * not belong to the VLAN member. Frames whose VID is not listed on
 153          * the VLAN table are forwarded by the PCR_MATRIX members.
 154          */
 155         MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
 156 
 157         /* Security Mode: Discard any frame due to ingress membership
 158          * violation or VID missed on the VLAN table.
 159          */
 160         MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
 161 };
 162 
 163 #define  PCR_MATRIX(x)                  (((x) & 0xff) << 16)
 164 #define  PORT_PRI(x)                    (((x) & 0x7) << 24)
 165 #define  EG_TAG(x)                      (((x) & 0x3) << 28)
 166 #define  PCR_MATRIX_MASK                PCR_MATRIX(0xff)
 167 #define  PCR_MATRIX_CLR                 PCR_MATRIX(0)
 168 #define  PCR_PORT_VLAN_MASK             PORT_VLAN(3)
 169 
 170 /* Register for port security control */
 171 #define MT7530_PSC_P(x)                 (0x200c + ((x) * 0x100))
 172 #define  SA_DIS                         BIT(4)
 173 
 174 /* Register for port vlan control */
 175 #define MT7530_PVC_P(x)                 (0x2010 + ((x) * 0x100))
 176 #define  PORT_SPEC_TAG                  BIT(5)
 177 #define  PVC_EG_TAG(x)                  (((x) & 0x7) << 8)
 178 #define  PVC_EG_TAG_MASK                PVC_EG_TAG(7)
 179 #define  VLAN_ATTR(x)                   (((x) & 0x3) << 6)
 180 #define  VLAN_ATTR_MASK                 VLAN_ATTR(3)
 181 
 182 enum mt7530_vlan_port_eg_tag {
 183         MT7530_VLAN_EG_DISABLED = 0,
 184         MT7530_VLAN_EG_CONSISTENT = 1,
 185 };
 186 
 187 enum mt7530_vlan_port_attr {
 188         MT7530_VLAN_USER = 0,
 189         MT7530_VLAN_TRANSPARENT = 3,
 190 };
 191 
 192 #define  STAG_VPID                      (((x) & 0xffff) << 16)
 193 
 194 /* Register for port port-and-protocol based vlan 1 control */
 195 #define MT7530_PPBV1_P(x)               (0x2014 + ((x) * 0x100))
 196 #define  G0_PORT_VID(x)                 (((x) & 0xfff) << 0)
 197 #define  G0_PORT_VID_MASK               G0_PORT_VID(0xfff)
 198 #define  G0_PORT_VID_DEF                G0_PORT_VID(1)
 199 
 200 /* Register for port MAC control register */
 201 #define MT7530_PMCR_P(x)                (0x3000 + ((x) * 0x100))
 202 #define  PMCR_IFG_XMIT(x)               (((x) & 0x3) << 18)
 203 #define  PMCR_EXT_PHY                   BIT(17)
 204 #define  PMCR_MAC_MODE                  BIT(16)
 205 #define  PMCR_FORCE_MODE                BIT(15)
 206 #define  PMCR_TX_EN                     BIT(14)
 207 #define  PMCR_RX_EN                     BIT(13)
 208 #define  PMCR_BACKOFF_EN                BIT(9)
 209 #define  PMCR_BACKPR_EN                 BIT(8)
 210 #define  PMCR_TX_FC_EN                  BIT(5)
 211 #define  PMCR_RX_FC_EN                  BIT(4)
 212 #define  PMCR_FORCE_SPEED_1000          BIT(3)
 213 #define  PMCR_FORCE_SPEED_100           BIT(2)
 214 #define  PMCR_FORCE_FDX                 BIT(1)
 215 #define  PMCR_FORCE_LNK                 BIT(0)
 216 #define  PMCR_SPEED_MASK                (PMCR_FORCE_SPEED_100 | \
 217                                          PMCR_FORCE_SPEED_1000)
 218 
 219 #define MT7530_PMSR_P(x)                (0x3008 + (x) * 0x100)
 220 #define  PMSR_EEE1G                     BIT(7)
 221 #define  PMSR_EEE100M                   BIT(6)
 222 #define  PMSR_RX_FC                     BIT(5)
 223 #define  PMSR_TX_FC                     BIT(4)
 224 #define  PMSR_SPEED_1000                BIT(3)
 225 #define  PMSR_SPEED_100                 BIT(2)
 226 #define  PMSR_SPEED_10                  0x00
 227 #define  PMSR_SPEED_MASK                (PMSR_SPEED_100 | PMSR_SPEED_1000)
 228 #define  PMSR_DPX                       BIT(1)
 229 #define  PMSR_LINK                      BIT(0)
 230 
 231 /* Register for MIB */
 232 #define MT7530_PORT_MIB_COUNTER(x)      (0x4000 + (x) * 0x100)
 233 #define MT7530_MIB_CCR                  0x4fe0
 234 #define  CCR_MIB_ENABLE                 BIT(31)
 235 #define  CCR_RX_OCT_CNT_GOOD            BIT(7)
 236 #define  CCR_RX_OCT_CNT_BAD             BIT(6)
 237 #define  CCR_TX_OCT_CNT_GOOD            BIT(5)
 238 #define  CCR_TX_OCT_CNT_BAD             BIT(4)
 239 #define  CCR_MIB_FLUSH                  (CCR_RX_OCT_CNT_GOOD | \
 240                                          CCR_RX_OCT_CNT_BAD | \
 241                                          CCR_TX_OCT_CNT_GOOD | \
 242                                          CCR_TX_OCT_CNT_BAD)
 243 #define  CCR_MIB_ACTIVATE               (CCR_MIB_ENABLE | \
 244                                          CCR_RX_OCT_CNT_GOOD | \
 245                                          CCR_RX_OCT_CNT_BAD | \
 246                                          CCR_TX_OCT_CNT_GOOD | \
 247                                          CCR_TX_OCT_CNT_BAD)
 248 /* Register for system reset */
 249 #define MT7530_SYS_CTRL                 0x7000
 250 #define  SYS_CTRL_PHY_RST               BIT(2)
 251 #define  SYS_CTRL_SW_RST                BIT(1)
 252 #define  SYS_CTRL_REG_RST               BIT(0)
 253 
 254 /* Register for hw trap status */
 255 #define MT7530_HWTRAP                   0x7800
 256 #define  HWTRAP_XTAL_MASK               (BIT(10) | BIT(9))
 257 #define  HWTRAP_XTAL_25MHZ              (BIT(10) | BIT(9))
 258 #define  HWTRAP_XTAL_40MHZ              (BIT(10))
 259 #define  HWTRAP_XTAL_20MHZ              (BIT(9))
 260 
 261 /* Register for hw trap modification */
 262 #define MT7530_MHWTRAP                  0x7804
 263 #define  MHWTRAP_PHY0_SEL               BIT(20)
 264 #define  MHWTRAP_MANUAL                 BIT(16)
 265 #define  MHWTRAP_P5_MAC_SEL             BIT(13)
 266 #define  MHWTRAP_P6_DIS                 BIT(8)
 267 #define  MHWTRAP_P5_RGMII_MODE          BIT(7)
 268 #define  MHWTRAP_P5_DIS                 BIT(6)
 269 #define  MHWTRAP_PHY_ACCESS             BIT(5)
 270 
 271 /* Register for TOP signal control */
 272 #define MT7530_TOP_SIG_CTRL             0x7808
 273 #define  TOP_SIG_CTRL_NORMAL            (BIT(17) | BIT(16))
 274 
 275 #define MT7530_IO_DRV_CR                0x7810
 276 #define  P5_IO_CLK_DRV(x)               ((x) & 0x3)
 277 #define  P5_IO_DATA_DRV(x)              (((x) & 0x3) << 4)
 278 
 279 #define MT7530_P6ECR                    0x7830
 280 #define  P6_INTF_MODE_MASK              0x3
 281 #define  P6_INTF_MODE(x)                ((x) & 0x3)
 282 
 283 /* Registers for TRGMII on the both side */
 284 #define MT7530_TRGMII_RCK_CTRL          0x7a00
 285 #define  RX_RST                         BIT(31)
 286 #define  RXC_DQSISEL                    BIT(30)
 287 #define  DQSI1_TAP_MASK                 (0x7f << 8)
 288 #define  DQSI0_TAP_MASK                 0x7f
 289 #define  DQSI1_TAP(x)                   (((x) & 0x7f) << 8)
 290 #define  DQSI0_TAP(x)                   ((x) & 0x7f)
 291 
 292 #define MT7530_TRGMII_RCK_RTT           0x7a04
 293 #define  DQS1_GATE                      BIT(31)
 294 #define  DQS0_GATE                      BIT(30)
 295 
 296 #define MT7530_TRGMII_RD(x)             (0x7a10 + (x) * 8)
 297 #define  BSLIP_EN                       BIT(31)
 298 #define  EDGE_CHK                       BIT(30)
 299 #define  RD_TAP_MASK                    0x7f
 300 #define  RD_TAP(x)                      ((x) & 0x7f)
 301 
 302 #define MT7530_TRGMII_TXCTRL            0x7a40
 303 #define  TRAIN_TXEN                     BIT(31)
 304 #define  TXC_INV                        BIT(30)
 305 #define  TX_RST                         BIT(28)
 306 
 307 #define MT7530_TRGMII_TD_ODT(i)         (0x7a54 + 8 * (i))
 308 #define  TD_DM_DRVP(x)                  ((x) & 0xf)
 309 #define  TD_DM_DRVN(x)                  (((x) & 0xf) << 4)
 310 
 311 #define MT7530_TRGMII_TCK_CTRL          0x7a78
 312 #define  TCK_TAP(x)                     (((x) & 0xf) << 8)
 313 
 314 #define MT7530_P5RGMIIRXCR              0x7b00
 315 #define  CSR_RGMII_EDGE_ALIGN           BIT(8)
 316 #define  CSR_RGMII_RXC_0DEG_CFG(x)      ((x) & 0xf)
 317 
 318 #define MT7530_P5RGMIITXCR              0x7b04
 319 #define  CSR_RGMII_TXC_CFG(x)           ((x) & 0x1f)
 320 
 321 #define MT7530_CREV                     0x7ffc
 322 #define  CHIP_NAME_SHIFT                16
 323 #define  MT7530_ID                      0x7530
 324 
 325 /* Registers for core PLL access through mmd indirect */
 326 #define CORE_PLL_GROUP2                 0x401
 327 #define  RG_SYSPLL_EN_NORMAL            BIT(15)
 328 #define  RG_SYSPLL_VODEN                BIT(14)
 329 #define  RG_SYSPLL_LF                   BIT(13)
 330 #define  RG_SYSPLL_RST_DLY(x)           (((x) & 0x3) << 12)
 331 #define  RG_SYSPLL_LVROD_EN             BIT(10)
 332 #define  RG_SYSPLL_PREDIV(x)            (((x) & 0x3) << 8)
 333 #define  RG_SYSPLL_POSDIV(x)            (((x) & 0x3) << 5)
 334 #define  RG_SYSPLL_FBKSEL               BIT(4)
 335 #define  RT_SYSPLL_EN_AFE_OLT           BIT(0)
 336 
 337 #define CORE_PLL_GROUP4                 0x403
 338 #define  RG_SYSPLL_DDSFBK_EN            BIT(12)
 339 #define  RG_SYSPLL_BIAS_EN              BIT(11)
 340 #define  RG_SYSPLL_BIAS_LPF_EN          BIT(10)
 341 
 342 #define CORE_PLL_GROUP5                 0x404
 343 #define  RG_LCDDS_PCW_NCPO1(x)          ((x) & 0xffff)
 344 
 345 #define CORE_PLL_GROUP6                 0x405
 346 #define  RG_LCDDS_PCW_NCPO0(x)          ((x) & 0xffff)
 347 
 348 #define CORE_PLL_GROUP7                 0x406
 349 #define  RG_LCDDS_PWDB                  BIT(15)
 350 #define  RG_LCDDS_ISO_EN                BIT(13)
 351 #define  RG_LCCDS_C(x)                  (((x) & 0x7) << 4)
 352 #define  RG_LCDDS_PCW_NCPO_CHG          BIT(3)
 353 
 354 #define CORE_PLL_GROUP10                0x409
 355 #define  RG_LCDDS_SSC_DELTA(x)          ((x) & 0xfff)
 356 
 357 #define CORE_PLL_GROUP11                0x40a
 358 #define  RG_LCDDS_SSC_DELTA1(x)         ((x) & 0xfff)
 359 
 360 #define CORE_GSWPLL_GRP1                0x40d
 361 #define  RG_GSWPLL_PREDIV(x)            (((x) & 0x3) << 14)
 362 #define  RG_GSWPLL_POSDIV_200M(x)       (((x) & 0x3) << 12)
 363 #define  RG_GSWPLL_EN_PRE               BIT(11)
 364 #define  RG_GSWPLL_FBKSEL               BIT(10)
 365 #define  RG_GSWPLL_BP                   BIT(9)
 366 #define  RG_GSWPLL_BR                   BIT(8)
 367 #define  RG_GSWPLL_FBKDIV_200M(x)       ((x) & 0xff)
 368 
 369 #define CORE_GSWPLL_GRP2                0x40e
 370 #define  RG_GSWPLL_POSDIV_500M(x)       (((x) & 0x3) << 8)
 371 #define  RG_GSWPLL_FBKDIV_500M(x)       ((x) & 0xff)
 372 
 373 #define CORE_TRGMII_GSW_CLK_CG          0x410
 374 #define  REG_GSWCK_EN                   BIT(0)
 375 #define  REG_TRGMIICK_EN                BIT(1)
 376 
 377 #define MIB_DESC(_s, _o, _n)    \
 378         {                       \
 379                 .size = (_s),   \
 380                 .offset = (_o), \
 381                 .name = (_n),   \
 382         }
 383 
 384 struct mt7530_mib_desc {
 385         unsigned int size;
 386         unsigned int offset;
 387         const char *name;
 388 };
 389 
 390 struct mt7530_fdb {
 391         u16 vid;
 392         u8 port_mask;
 393         u8 aging;
 394         u8 mac[6];
 395         bool noarp;
 396 };
 397 
 398 /* struct mt7530_port - This is the main data structure for holding the state
 399  *                      of the port.
 400  * @enable:     The status used for show port is enabled or not.
 401  * @pm:         The matrix used to show all connections with the port.
 402  * @pvid:       The VLAN specified is to be considered a PVID at ingress.  Any
 403  *              untagged frames will be assigned to the related VLAN.
 404  * @vlan_filtering: The flags indicating whether the port that can recognize
 405  *                  VLAN-tagged frames.
 406  */
 407 struct mt7530_port {
 408         bool enable;
 409         u32 pm;
 410         u16 pvid;
 411 };
 412 
 413 /* Port 5 interface select definitions */
 414 enum p5_interface_select {
 415         P5_DISABLED = 0,
 416         P5_INTF_SEL_PHY_P0,
 417         P5_INTF_SEL_PHY_P4,
 418         P5_INTF_SEL_GMAC5,
 419 };
 420 
 421 static const char *p5_intf_modes(unsigned int p5_interface)
 422 {
 423         switch (p5_interface) {
 424         case P5_DISABLED:
 425                 return "DISABLED";
 426         case P5_INTF_SEL_PHY_P0:
 427                 return "PHY P0";
 428         case P5_INTF_SEL_PHY_P4:
 429                 return "PHY P4";
 430         case P5_INTF_SEL_GMAC5:
 431                 return "GMAC5";
 432         default:
 433                 return "unknown";
 434         }
 435 }
 436 
 437 /* struct mt7530_priv - This is the main data structure for holding the state
 438  *                      of the driver
 439  * @dev:                The device pointer
 440  * @ds:                 The pointer to the dsa core structure
 441  * @bus:                The bus used for the device and built-in PHY
 442  * @rstc:               The pointer to reset control used by MCM
 443  * @core_pwr:           The power supplied into the core
 444  * @io_pwr:             The power supplied into the I/O
 445  * @reset:              The descriptor for GPIO line tied to its reset pin
 446  * @mcm:                Flag for distinguishing if standalone IC or module
 447  *                      coupling
 448  * @ports:              Holding the state among ports
 449  * @reg_mutex:          The lock for protecting among process accessing
 450  *                      registers
 451  * @p6_interface        Holding the current port 6 interface
 452  * @p5_intf_sel:        Holding the current port 5 interface select
 453  */
 454 struct mt7530_priv {
 455         struct device           *dev;
 456         struct dsa_switch       *ds;
 457         struct mii_bus          *bus;
 458         struct reset_control    *rstc;
 459         struct regulator        *core_pwr;
 460         struct regulator        *io_pwr;
 461         struct gpio_desc        *reset;
 462         unsigned int            id;
 463         bool                    mcm;
 464         phy_interface_t         p6_interface;
 465         phy_interface_t         p5_interface;
 466         unsigned int            p5_intf_sel;
 467 
 468         struct mt7530_port      ports[MT7530_NUM_PORTS];
 469         /* protect among processes for registers access*/
 470         struct mutex reg_mutex;
 471 };
 472 
 473 struct mt7530_hw_vlan_entry {
 474         int port;
 475         u8  old_members;
 476         bool untagged;
 477 };
 478 
 479 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
 480                                              int port, bool untagged)
 481 {
 482         e->port = port;
 483         e->untagged = untagged;
 484 }
 485 
 486 typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
 487                                struct mt7530_hw_vlan_entry *);
 488 
 489 struct mt7530_hw_stats {
 490         const char      *string;
 491         u16             reg;
 492         u8              sizeof_stat;
 493 };
 494 
 495 struct mt7530_dummy_poll {
 496         struct mt7530_priv *priv;
 497         u32 reg;
 498 };
 499 
 500 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
 501                                           struct mt7530_priv *priv, u32 reg)
 502 {
 503         p->priv = priv;
 504         p->reg = reg;
 505 }
 506 
 507 #endif /* __MT7530_H */

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