root/drivers/net/dsa/mv88e6xxx/ptp.h

INCLUDED FROM

DEFINITIONS

1. mv88e6xxx_hwtstamp_work
2. mv88e6xxx_ptp_setup
3. mv88e6xxx_ptp_free

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Marvell 88E6xxx Switch PTP support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2017 National Instruments
   8  *      Erik Hons <erik.hons@ni.com>
   9  *      Brandon Streiff <brandon.streiff@ni.com>
  10  *      Dane Wagner <dane.wagner@ni.com>
  11  */
  12 
  13 #ifndef _MV88E6XXX_PTP_H
  14 #define _MV88E6XXX_PTP_H
  15 
  16 #include "chip.h"
  17 
  18 /* Offset 0x00: TAI Global Config */
  19 #define MV88E6XXX_TAI_CFG                       0x00
  20 #define MV88E6XXX_TAI_CFG_CAP_OVERWRITE         0x8000
  21 #define MV88E6XXX_TAI_CFG_CAP_CTR_START         0x4000
  22 #define MV88E6XXX_TAI_CFG_EVREQ_FALLING         0x2000
  23 #define MV88E6XXX_TAI_CFG_TRIG_ACTIVE_LO        0x1000
  24 #define MV88E6XXX_TAI_CFG_IRL_ENABLE            0x0400
  25 #define MV88E6XXX_TAI_CFG_TRIG_IRQ_EN           0x0200
  26 #define MV88E6XXX_TAI_CFG_EVREQ_IRQ_EN          0x0100
  27 #define MV88E6XXX_TAI_CFG_TRIG_LOCK             0x0080
  28 #define MV88E6XXX_TAI_CFG_BLOCK_UPDATE          0x0008
  29 #define MV88E6XXX_TAI_CFG_MULTI_PTP             0x0004
  30 #define MV88E6XXX_TAI_CFG_TRIG_MODE_ONESHOT     0x0002
  31 #define MV88E6XXX_TAI_CFG_TRIG_ENABLE           0x0001
  32 
  33 /* Offset 0x01: Timestamp Clock Period (ps) */
  34 #define MV88E6XXX_TAI_CLOCK_PERIOD              0x01
  35 
  36 /* Offset 0x02/0x03: Trigger Generation Amount */
  37 #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO        0x02
  38 #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI        0x03
  39 
  40 /* Offset 0x04: Clock Compensation */
  41 #define MV88E6XXX_TAI_TRIG_CLOCK_COMP           0x04
  42 
  43 /* Offset 0x05: Trigger Configuration */
  44 #define MV88E6XXX_TAI_TRIG_CFG                  0x05
  45 
  46 /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */
  47 #define MV88E6XXX_TAI_IRL_AMOUNT                0x06
  48 
  49 /* Offset 0x07: Ingress Rate Limiter Compensation */
  50 #define MV88E6XXX_TAI_IRL_COMP                  0x07
  51 
  52 /* Offset 0x08: Ingress Rate Limiter Compensation */
  53 #define MV88E6XXX_TAI_IRL_COMP_PS               0x08
  54 
  55 /* Offset 0x09: Event Status */
  56 #define MV88E6XXX_TAI_EVENT_STATUS              0x09
  57 #define MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG     0x4000
  58 #define MV88E6XXX_TAI_EVENT_STATUS_ERROR        0x0200
  59 #define MV88E6XXX_TAI_EVENT_STATUS_VALID        0x0100
  60 #define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK     0x00ff
  61 
  62 /* Offset 0x0A/0x0B: Event Time */
  63 #define MV88E6XXX_TAI_EVENT_TIME_LO             0x0a
  64 #define MV88E6XXX_TAI_EVENT_TYPE_HI             0x0b
  65 
  66 /* Offset 0x0E/0x0F: PTP Global Time */
  67 #define MV88E6XXX_TAI_TIME_LO                   0x0e
  68 #define MV88E6XXX_TAI_TIME_HI                   0x0f
  69 
  70 /* Offset 0x10/0x11: Trig Generation Time */
  71 #define MV88E6XXX_TAI_TRIG_TIME_LO              0x10
  72 #define MV88E6XXX_TAI_TRIG_TIME_HI              0x11
  73 
  74 /* Offset 0x12: Lock Status */
  75 #define MV88E6XXX_TAI_LOCK_STATUS               0x12
  76 
  77 /* Offset 0x00: Ether Type */
  78 #define MV88E6XXX_PTP_GC_ETYPE                  0x00
  79 
  80 /* 6165 Global Control Registers */
  81 /* Offset 0x00: Ether Type */
  82 #define MV88E6XXX_PTP_GC_ETYPE                  0x00
  83 
  84 /* Offset 0x01: Message ID */
  85 #define MV88E6XXX_PTP_GC_MESSAGE_ID             0x01
  86 
  87 /* Offset 0x02: Time Stamp Arrive Time */
  88 #define MV88E6XXX_PTP_GC_TS_ARR_PTR             0x02
  89 
  90 /* Offset 0x03: Port Arrival Interrupt Enable */
  91 #define MV88E6XXX_PTP_GC_PORT_ARR_INT_EN        0x03
  92 
  93 /* Offset 0x04: Port Departure Interrupt Enable */
  94 #define MV88E6XXX_PTP_GC_PORT_DEP_INT_EN        0x04
  95 
  96 /* Offset 0x05: Configuration */
  97 #define MV88E6XXX_PTP_GC_CONFIG                 0x05
  98 #define MV88E6XXX_PTP_GC_CONFIG_DIS_OVERWRITE   BIT(1)
  99 #define MV88E6XXX_PTP_GC_CONFIG_DIS_TS          BIT(0)
 100 
 101 /* Offset 0x8: Interrupt Status */
 102 #define MV88E6XXX_PTP_GC_INT_STATUS             0x08
 103 
 104 /* Offset 0x9/0xa: Global Time */
 105 #define MV88E6XXX_PTP_GC_TIME_LO                0x09
 106 #define MV88E6XXX_PTP_GC_TIME_HI                0x0A
 107 
 108 /* 6165 Per Port Registers */
 109 /* Offset 0: Arrival Time 0 Status */
 110 #define MV88E6165_PORT_PTP_ARR0_STS     0x00
 111 
 112 /* Offset 0x01/0x02: PTP Arrival 0 Time */
 113 #define MV88E6165_PORT_PTP_ARR0_TIME_LO 0x01
 114 #define MV88E6165_PORT_PTP_ARR0_TIME_HI 0x02
 115 
 116 /* Offset 0x03: PTP Arrival 0 Sequence ID */
 117 #define MV88E6165_PORT_PTP_ARR0_SEQID   0x03
 118 
 119 /* Offset 0x04: PTP Arrival 1 Status */
 120 #define MV88E6165_PORT_PTP_ARR1_STS     0x04
 121 
 122 /* Offset 0x05/0x6E: PTP Arrival 1 Time */
 123 #define MV88E6165_PORT_PTP_ARR1_TIME_LO 0x05
 124 #define MV88E6165_PORT_PTP_ARR1_TIME_HI 0x06
 125 
 126 /* Offset 0x07: PTP Arrival 1 Sequence ID */
 127 #define MV88E6165_PORT_PTP_ARR1_SEQID   0x07
 128 
 129 /* Offset 0x08: PTP Departure Status */
 130 #define MV88E6165_PORT_PTP_DEP_STS      0x08
 131 
 132 /* Offset 0x09/0x0a: PTP Deperture Time */
 133 #define MV88E6165_PORT_PTP_DEP_TIME_LO  0x09
 134 #define MV88E6165_PORT_PTP_DEP_TIME_HI  0x0a
 135 
 136 /* Offset 0x0b: PTP Departure Sequence ID */
 137 #define MV88E6165_PORT_PTP_DEP_SEQID    0x0b
 138 
 139 /* Offset 0x0d: Port Status */
 140 #define MV88E6164_PORT_STATUS           0x0d
 141 
 142 #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP
 143 
 144 long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp);
 145 int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip);
 146 void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip);
 147 
 148 #define ptp_to_chip(ptp) container_of(ptp, struct mv88e6xxx_chip,       \
 149                                       ptp_clock_info)
 150 
 151 extern const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops;
 152 extern const struct mv88e6xxx_ptp_ops mv88e6250_ptp_ops;
 153 extern const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops;
 154 
 155 #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */
 156 
 157 static inline long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp)
 158 {
 159         return -1;
 160 }
 161 
 162 static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip)
 163 {
 164         return 0;
 165 }
 166 
 167 static inline void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip)
 168 {
 169 }
 170 
 171 static const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {};
 172 static const struct mv88e6xxx_ptp_ops mv88e6250_ptp_ops = {};
 173 static const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {};
 174 
 175 #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */
 176 
 177 #endif /* _MV88E6XXX_PTP_H */