root/drivers/net/dsa/mv88e6xxx/chip.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. mv88e6xxx_has_pvt
  2. mv88e6xxx_num_databases
  3. mv88e6xxx_num_ports
  4. mv88e6xxx_port_mask
  5. mv88e6xxx_num_gpio
  6. mv88e6xxx_is_invalid_port
  7. mv88e6xxx_reg_lock
  8. mv88e6xxx_reg_unlock
   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Marvell 88E6xxx Ethernet switch single-chip definition
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  */
   7 
   8 #ifndef _MV88E6XXX_CHIP_H
   9 #define _MV88E6XXX_CHIP_H
  10 
  11 #include <linux/idr.h>
  12 #include <linux/if_vlan.h>
  13 #include <linux/irq.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/kthread.h>
  16 #include <linux/phy.h>
  17 #include <linux/ptp_clock_kernel.h>
  18 #include <linux/timecounter.h>
  19 #include <net/dsa.h>
  20 
  21 #define MV88E6XXX_N_FID         4096
  22 
  23 /* PVT limits for 4-bit port and 5-bit switch */
  24 #define MV88E6XXX_MAX_PVT_SWITCHES      32
  25 #define MV88E6XXX_MAX_PVT_PORTS         16
  26 
  27 #define MV88E6XXX_MAX_GPIO      16
  28 
  29 enum mv88e6xxx_egress_mode {
  30         MV88E6XXX_EGRESS_MODE_UNMODIFIED,
  31         MV88E6XXX_EGRESS_MODE_UNTAGGED,
  32         MV88E6XXX_EGRESS_MODE_TAGGED,
  33         MV88E6XXX_EGRESS_MODE_ETHERTYPE,
  34 };
  35 
  36 enum mv88e6xxx_frame_mode {
  37         MV88E6XXX_FRAME_MODE_NORMAL,
  38         MV88E6XXX_FRAME_MODE_DSA,
  39         MV88E6XXX_FRAME_MODE_PROVIDER,
  40         MV88E6XXX_FRAME_MODE_ETHERTYPE,
  41 };
  42 
  43 /* List of supported models */
  44 enum mv88e6xxx_model {
  45         MV88E6085,
  46         MV88E6095,
  47         MV88E6097,
  48         MV88E6123,
  49         MV88E6131,
  50         MV88E6141,
  51         MV88E6161,
  52         MV88E6165,
  53         MV88E6171,
  54         MV88E6172,
  55         MV88E6175,
  56         MV88E6176,
  57         MV88E6185,
  58         MV88E6190,
  59         MV88E6190X,
  60         MV88E6191,
  61         MV88E6220,
  62         MV88E6240,
  63         MV88E6250,
  64         MV88E6290,
  65         MV88E6320,
  66         MV88E6321,
  67         MV88E6341,
  68         MV88E6350,
  69         MV88E6351,
  70         MV88E6352,
  71         MV88E6390,
  72         MV88E6390X,
  73 };
  74 
  75 enum mv88e6xxx_family {
  76         MV88E6XXX_FAMILY_NONE,
  77         MV88E6XXX_FAMILY_6065,  /* 6031 6035 6061 6065 */
  78         MV88E6XXX_FAMILY_6095,  /* 6092 6095 */
  79         MV88E6XXX_FAMILY_6097,  /* 6046 6085 6096 6097 */
  80         MV88E6XXX_FAMILY_6165,  /* 6123 6161 6165 */
  81         MV88E6XXX_FAMILY_6185,  /* 6108 6121 6122 6131 6152 6155 6182 6185 */
  82         MV88E6XXX_FAMILY_6250,  /* 6220 6250 */
  83         MV88E6XXX_FAMILY_6320,  /* 6320 6321 */
  84         MV88E6XXX_FAMILY_6341,  /* 6141 6341 */
  85         MV88E6XXX_FAMILY_6351,  /* 6171 6175 6350 6351 */
  86         MV88E6XXX_FAMILY_6352,  /* 6172 6176 6240 6352 */
  87         MV88E6XXX_FAMILY_6390,  /* 6190 6190X 6191 6290 6390 6390X */
  88 };
  89 
  90 struct mv88e6xxx_ops;
  91 
  92 struct mv88e6xxx_info {
  93         enum mv88e6xxx_family family;
  94         u16 prod_num;
  95         const char *name;
  96         unsigned int num_databases;
  97         unsigned int num_ports;
  98         unsigned int num_internal_phys;
  99         unsigned int num_gpio;
 100         unsigned int max_vid;
 101         unsigned int port_base_addr;
 102         unsigned int phy_base_addr;
 103         unsigned int global1_addr;
 104         unsigned int global2_addr;
 105         unsigned int age_time_coeff;
 106         unsigned int g1_irqs;
 107         unsigned int g2_irqs;
 108         bool pvt;
 109 
 110         /* Mark certain ports as invalid. This is required for example for the
 111          * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
 112          * ports 2-4 are not routet to pins.
 113          */
 114         unsigned int invalid_port_mask;
 115         /* Multi-chip Addressing Mode.
 116          * Some chips respond to only 2 registers of its own SMI device address
 117          * when it is non-zero, and use indirect access to internal registers.
 118          */
 119         bool multi_chip;
 120         /* Dual-chip Addressing Mode
 121          * Some chips respond to only half of the 32 SMI addresses,
 122          * allowing two to coexist on the same SMI interface.
 123          */
 124         bool dual_chip;
 125 
 126         enum dsa_tag_protocol tag_protocol;
 127 
 128         /* Mask for FromPort and ToPort value of PortVec used in ATU Move
 129          * operation. 0 means that the ATU Move operation is not supported.
 130          */
 131         u8 atu_move_port_mask;
 132         const struct mv88e6xxx_ops *ops;
 133 
 134         /* Supports PTP */
 135         bool ptp_support;
 136 };
 137 
 138 struct mv88e6xxx_atu_entry {
 139         u8      state;
 140         bool    trunk;
 141         u16     portvec;
 142         u8      mac[ETH_ALEN];
 143 };
 144 
 145 struct mv88e6xxx_vtu_entry {
 146         u16     vid;
 147         u16     fid;
 148         u8      sid;
 149         bool    valid;
 150         u8      member[DSA_MAX_PORTS];
 151         u8      state[DSA_MAX_PORTS];
 152 };
 153 
 154 struct mv88e6xxx_bus_ops;
 155 struct mv88e6xxx_irq_ops;
 156 struct mv88e6xxx_gpio_ops;
 157 struct mv88e6xxx_avb_ops;
 158 struct mv88e6xxx_ptp_ops;
 159 
 160 struct mv88e6xxx_irq {
 161         u16 masked;
 162         struct irq_chip chip;
 163         struct irq_domain *domain;
 164         unsigned int nirqs;
 165 };
 166 
 167 /* state flags for mv88e6xxx_port_hwtstamp::state */
 168 enum {
 169         MV88E6XXX_HWTSTAMP_ENABLED,
 170         MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
 171 };
 172 
 173 struct mv88e6xxx_port_hwtstamp {
 174         /* Port index */
 175         int port_id;
 176 
 177         /* Timestamping state */
 178         unsigned long state;
 179 
 180         /* Resources for receive timestamping */
 181         struct sk_buff_head rx_queue;
 182         struct sk_buff_head rx_queue2;
 183 
 184         /* Resources for transmit timestamping */
 185         unsigned long tx_tstamp_start;
 186         struct sk_buff *tx_skb;
 187         u16 tx_seq_id;
 188 
 189         /* Current timestamp configuration */
 190         struct hwtstamp_config tstamp_config;
 191 };
 192 
 193 enum mv88e6xxx_policy_mapping {
 194         MV88E6XXX_POLICY_MAPPING_DA,
 195         MV88E6XXX_POLICY_MAPPING_SA,
 196         MV88E6XXX_POLICY_MAPPING_VTU,
 197         MV88E6XXX_POLICY_MAPPING_ETYPE,
 198         MV88E6XXX_POLICY_MAPPING_PPPOE,
 199         MV88E6XXX_POLICY_MAPPING_VBAS,
 200         MV88E6XXX_POLICY_MAPPING_OPT82,
 201         MV88E6XXX_POLICY_MAPPING_UDP,
 202 };
 203 
 204 enum mv88e6xxx_policy_action {
 205         MV88E6XXX_POLICY_ACTION_NORMAL,
 206         MV88E6XXX_POLICY_ACTION_MIRROR,
 207         MV88E6XXX_POLICY_ACTION_TRAP,
 208         MV88E6XXX_POLICY_ACTION_DISCARD,
 209 };
 210 
 211 struct mv88e6xxx_policy {
 212         enum mv88e6xxx_policy_mapping mapping;
 213         enum mv88e6xxx_policy_action action;
 214         struct ethtool_rx_flow_spec fs;
 215         u8 addr[ETH_ALEN];
 216         int port;
 217         u16 vid;
 218 };
 219 
 220 struct mv88e6xxx_port {
 221         struct mv88e6xxx_chip *chip;
 222         int port;
 223         u64 serdes_stats[2];
 224         u64 atu_member_violation;
 225         u64 atu_miss_violation;
 226         u64 atu_full_violation;
 227         u64 vtu_member_violation;
 228         u64 vtu_miss_violation;
 229         u8 cmode;
 230         unsigned int serdes_irq;
 231 };
 232 
 233 struct mv88e6xxx_chip {
 234         const struct mv88e6xxx_info *info;
 235 
 236         /* The dsa_switch this private structure is related to */
 237         struct dsa_switch *ds;
 238 
 239         /* The device this structure is associated to */
 240         struct device *dev;
 241 
 242         /* This mutex protects the access to the switch registers */
 243         struct mutex reg_lock;
 244 
 245         /* The MII bus and the address on the bus that is used to
 246          * communication with the switch
 247          */
 248         const struct mv88e6xxx_bus_ops *smi_ops;
 249         struct mii_bus *bus;
 250         int sw_addr;
 251 
 252         /* Handles automatic disabling and re-enabling of the PHY
 253          * polling unit.
 254          */
 255         const struct mv88e6xxx_bus_ops *phy_ops;
 256         struct mutex            ppu_mutex;
 257         int                     ppu_disabled;
 258         struct work_struct      ppu_work;
 259         struct timer_list       ppu_timer;
 260 
 261         /* This mutex serialises access to the statistics unit.
 262          * Hold this mutex over snapshot + dump sequences.
 263          */
 264         struct mutex    stats_mutex;
 265 
 266         /* A switch may have a GPIO line tied to its reset pin. Parse
 267          * this from the device tree, and use it before performing
 268          * switch soft reset.
 269          */
 270         struct gpio_desc *reset;
 271 
 272         /* set to size of eeprom if supported by the switch */
 273         u32 eeprom_len;
 274 
 275         /* List of mdio busses */
 276         struct list_head mdios;
 277 
 278         /* Policy Control List IDs and rules */
 279         struct idr policies;
 280 
 281         /* There can be two interrupt controllers, which are chained
 282          * off a GPIO as interrupt source
 283          */
 284         struct mv88e6xxx_irq g1_irq;
 285         struct mv88e6xxx_irq g2_irq;
 286         int irq;
 287         int device_irq;
 288         int watchdog_irq;
 289 
 290         int atu_prob_irq;
 291         int vtu_prob_irq;
 292         struct kthread_worker *kworker;
 293         struct kthread_delayed_work irq_poll_work;
 294 
 295         /* GPIO resources */
 296         u8 gpio_data[2];
 297 
 298         /* This cyclecounter abstracts the switch PTP time.
 299          * reg_lock must be held for any operation that read()s.
 300          */
 301         struct cyclecounter     tstamp_cc;
 302         struct timecounter      tstamp_tc;
 303         struct delayed_work     overflow_work;
 304 
 305         struct ptp_clock        *ptp_clock;
 306         struct ptp_clock_info   ptp_clock_info;
 307         struct delayed_work     tai_event_work;
 308         struct ptp_pin_desc     pin_config[MV88E6XXX_MAX_GPIO];
 309         u16 trig_config;
 310         u16 evcap_config;
 311         u16 enable_count;
 312 
 313         /* Per-port timestamping resources. */
 314         struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
 315 
 316         /* Array of port structures. */
 317         struct mv88e6xxx_port ports[DSA_MAX_PORTS];
 318 };
 319 
 320 struct mv88e6xxx_bus_ops {
 321         int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 322         int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 323 };
 324 
 325 struct mv88e6xxx_mdio_bus {
 326         struct mii_bus *bus;
 327         struct mv88e6xxx_chip *chip;
 328         struct list_head list;
 329         bool external;
 330 };
 331 
 332 struct mv88e6xxx_ops {
 333         /* Switch Setup Errata, called early in the switch setup to
 334          * allow any errata actions to be performed
 335          */
 336         int (*setup_errata)(struct mv88e6xxx_chip *chip);
 337 
 338         int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
 339         int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
 340 
 341         /* Ingress Rate Limit unit (IRL) operations */
 342         int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
 343 
 344         int (*get_eeprom)(struct mv88e6xxx_chip *chip,
 345                           struct ethtool_eeprom *eeprom, u8 *data);
 346         int (*set_eeprom)(struct mv88e6xxx_chip *chip,
 347                           struct ethtool_eeprom *eeprom, u8 *data);
 348 
 349         int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
 350 
 351         int (*phy_read)(struct mv88e6xxx_chip *chip,
 352                         struct mii_bus *bus,
 353                         int addr, int reg, u16 *val);
 354         int (*phy_write)(struct mv88e6xxx_chip *chip,
 355                          struct mii_bus *bus,
 356                          int addr, int reg, u16 val);
 357 
 358         /* Priority Override Table operations */
 359         int (*pot_clear)(struct mv88e6xxx_chip *chip);
 360 
 361         /* PHY Polling Unit (PPU) operations */
 362         int (*ppu_enable)(struct mv88e6xxx_chip *chip);
 363         int (*ppu_disable)(struct mv88e6xxx_chip *chip);
 364 
 365         /* Switch Software Reset */
 366         int (*reset)(struct mv88e6xxx_chip *chip);
 367 
 368         /* RGMII Receive/Transmit Timing Control
 369          * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
 370          */
 371         int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
 372                                     phy_interface_t mode);
 373 
 374 #define LINK_FORCED_DOWN        0
 375 #define LINK_FORCED_UP          1
 376 #define LINK_UNFORCED           -2
 377 
 378         /* Port's MAC link state
 379          * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
 380          * or LINK_UNFORCED for normal link detection.
 381          */
 382         int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
 383 
 384 #define DUPLEX_UNFORCED         -2
 385 
 386         /* Port's MAC duplex mode
 387          *
 388          * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
 389          * or DUPLEX_UNFORCED for normal duplex detection.
 390          */
 391         int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
 392 
 393 #define PAUSE_ON                1
 394 #define PAUSE_OFF               0
 395 
 396         /* Enable/disable sending Pause */
 397         int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
 398                               int pause);
 399 
 400 #define SPEED_MAX               INT_MAX
 401 #define SPEED_UNFORCED          -2
 402 
 403         /* Port's MAC speed (in Mbps)
 404          *
 405          * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
 406          * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
 407          */
 408         int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
 409 
 410         /* What interface mode should be used for maximum speed? */
 411         phy_interface_t (*port_max_speed_mode)(int port);
 412 
 413         int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
 414 
 415         int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
 416                                enum mv88e6xxx_policy_mapping mapping,
 417                                enum mv88e6xxx_policy_action action);
 418 
 419         int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
 420                                    enum mv88e6xxx_frame_mode mode);
 421         int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
 422                                       bool unicast, bool multicast);
 423         int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
 424                                    u16 etype);
 425         int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
 426                                    size_t size);
 427 
 428         int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
 429         int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
 430                                 u8 out);
 431         int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
 432         int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
 433         int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
 434 
 435         /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
 436          * Some chips allow this to be configured on specific ports.
 437          */
 438         int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
 439                               phy_interface_t mode);
 440         int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
 441 
 442         /* Some devices have a per port register indicating what is
 443          * the upstream port this port should forward to.
 444          */
 445         int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
 446                                       int upstream_port);
 447         /* Return the port link state, as required by phylink */
 448         int (*port_link_state)(struct mv88e6xxx_chip *chip, int port,
 449                                struct phylink_link_state *state);
 450 
 451         /* Snapshot the statistics for a port. The statistics can then
 452          * be read back a leisure but still with a consistent view.
 453          */
 454         int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
 455 
 456         /* Set the histogram mode for statistics, when the control registers
 457          * are separated out of the STATS_OP register.
 458          */
 459         int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
 460 
 461         /* Return the number of strings describing statistics */
 462         int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
 463         int (*stats_get_strings)(struct mv88e6xxx_chip *chip,  uint8_t *data);
 464         int (*stats_get_stats)(struct mv88e6xxx_chip *chip,  int port,
 465                                uint64_t *data);
 466         int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
 467         int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
 468 
 469 #define MV88E6XXX_CASCADE_PORT_NONE             0xe
 470 #define MV88E6XXX_CASCADE_PORT_MULTIPLE         0xf
 471 
 472         int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
 473 
 474         const struct mv88e6xxx_irq_ops *watchdog_ops;
 475 
 476         int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
 477 
 478         /* Power on/off a SERDES interface */
 479         int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane,
 480                             bool up);
 481 
 482         /* SERDES lane mapping */
 483         u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
 484 
 485         /* SERDES interrupt handling */
 486         unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
 487                                            int port);
 488         int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane,
 489                                  bool enable);
 490         irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
 491                                          u8 lane);
 492 
 493         /* Statistics from the SERDES interface */
 494         int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
 495         int (*serdes_get_strings)(struct mv88e6xxx_chip *chip,  int port,
 496                                   uint8_t *data);
 497         int (*serdes_get_stats)(struct mv88e6xxx_chip *chip,  int port,
 498                                 uint64_t *data);
 499 
 500         /* VLAN Translation Unit operations */
 501         int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
 502                            struct mv88e6xxx_vtu_entry *entry);
 503         int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
 504                              struct mv88e6xxx_vtu_entry *entry);
 505 
 506         /* GPIO operations */
 507         const struct mv88e6xxx_gpio_ops *gpio_ops;
 508 
 509         /* Interface to the AVB/PTP registers */
 510         const struct mv88e6xxx_avb_ops *avb_ops;
 511 
 512         /* Remote Management Unit operations */
 513         int (*rmu_disable)(struct mv88e6xxx_chip *chip);
 514 
 515         /* Precision Time Protocol operations */
 516         const struct mv88e6xxx_ptp_ops *ptp_ops;
 517 
 518         /* Phylink */
 519         void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
 520                                  unsigned long *mask,
 521                                  struct phylink_link_state *state);
 522 };
 523 
 524 struct mv88e6xxx_irq_ops {
 525         /* Action to be performed when the interrupt happens */
 526         int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
 527         /* Setup the hardware to generate the interrupt */
 528         int (*irq_setup)(struct mv88e6xxx_chip *chip);
 529         /* Reset the hardware to stop generating the interrupt */
 530         void (*irq_free)(struct mv88e6xxx_chip *chip);
 531 };
 532 
 533 struct mv88e6xxx_gpio_ops {
 534         /* Get/set data on GPIO pin */
 535         int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
 536         int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
 537                         int value);
 538 
 539         /* get/set GPIO direction */
 540         int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
 541         int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
 542                        bool input);
 543 
 544         /* get/set GPIO pin control */
 545         int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
 546                         int *func);
 547         int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
 548                         int func);
 549 };
 550 
 551 struct mv88e6xxx_avb_ops {
 552         /* Access port-scoped Precision Time Protocol registers */
 553         int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
 554                              u16 *data, int len);
 555         int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
 556                               u16 data);
 557 
 558         /* Access global Precision Time Protocol registers */
 559         int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
 560                         int len);
 561         int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
 562 
 563         /* Access global Time Application Interface registers */
 564         int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
 565                         int len);
 566         int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
 567 };
 568 
 569 struct mv88e6xxx_ptp_ops {
 570         u64 (*clock_read)(const struct cyclecounter *cc);
 571         int (*ptp_enable)(struct ptp_clock_info *ptp,
 572                           struct ptp_clock_request *rq, int on);
 573         int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
 574                           enum ptp_pin_function func, unsigned int chan);
 575         void (*event_work)(struct work_struct *ugly);
 576         int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
 577         int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
 578         int (*global_enable)(struct mv88e6xxx_chip *chip);
 579         int (*global_disable)(struct mv88e6xxx_chip *chip);
 580         int n_ext_ts;
 581         int arr0_sts_reg;
 582         int arr1_sts_reg;
 583         int dep_sts_reg;
 584         u32 rx_filters;
 585         u32 cc_shift;
 586         u32 cc_mult;
 587         u32 cc_mult_num;
 588         u32 cc_mult_dem;
 589 };
 590 
 591 #define STATS_TYPE_PORT         BIT(0)
 592 #define STATS_TYPE_BANK0        BIT(1)
 593 #define STATS_TYPE_BANK1        BIT(2)
 594 
 595 struct mv88e6xxx_hw_stat {
 596         char string[ETH_GSTRING_LEN];
 597         size_t size;
 598         int reg;
 599         int type;
 600 };
 601 
 602 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
 603 {
 604         return chip->info->pvt;
 605 }
 606 
 607 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 608 {
 609         return chip->info->num_databases;
 610 }
 611 
 612 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
 613 {
 614         return chip->info->num_ports;
 615 }
 616 
 617 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
 618 {
 619         return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
 620 }
 621 
 622 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
 623 {
 624         return chip->info->num_gpio;
 625 }
 626 
 627 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
 628 {
 629         return (chip->info->invalid_port_mask & BIT(port)) != 0;
 630 }
 631 
 632 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 633 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 634 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
 635                         u16 mask, u16 val);
 636 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 637                        int bit, int val);
 638 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
 639                              int speed, int duplex, int pause,
 640                              phy_interface_t mode);
 641 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
 642 
 643 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
 644 {
 645         mutex_lock(&chip->reg_lock);
 646 }
 647 
 648 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
 649 {
 650         mutex_unlock(&chip->reg_lock);
 651 }
 652 
 653 #endif /* _MV88E6XXX_CHIP_H */
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