This source file includes following definitions.
- mv88e6xxx_g2_scratch_read
- mv88e6xxx_g2_scratch_write
- mv88e6xxx_g2_scratch_get_bit
- mv88e6xxx_g2_scratch_set_bit
- mv88e6352_g2_scratch_gpio_get_data
- mv88e6352_g2_scratch_gpio_set_data
- mv88e6352_g2_scratch_gpio_get_dir
- mv88e6352_g2_scratch_gpio_set_dir
- mv88e6352_g2_scratch_gpio_get_pctl
- mv88e6352_g2_scratch_gpio_set_pctl
- mv88e6xxx_g2_scratch_gpio_set_smi
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11 #include "chip.h"
12 #include "global2.h"
13
14
15 static int mv88e6xxx_g2_scratch_read(struct mv88e6xxx_chip *chip, int reg,
16 u8 *data)
17 {
18 u16 value;
19 int err;
20
21 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC,
22 reg << 8);
23 if (err)
24 return err;
25
26 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC, &value);
27 if (err)
28 return err;
29
30 *data = (value & MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK);
31
32 return 0;
33 }
34
35 static int mv88e6xxx_g2_scratch_write(struct mv88e6xxx_chip *chip, int reg,
36 u8 data)
37 {
38 u16 value = (reg << 8) | data;
39
40 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC,
41 MV88E6XXX_G2_SCRATCH_MISC_UPDATE | value);
42 }
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48
49
50 static int mv88e6xxx_g2_scratch_get_bit(struct mv88e6xxx_chip *chip,
51 int base_reg, unsigned int offset,
52 int *set)
53 {
54 int reg = base_reg + (offset / 8);
55 u8 mask = (1 << (offset & 0x7));
56 u8 val;
57 int err;
58
59 err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
60 if (err)
61 return err;
62
63 *set = !!(mask & val);
64
65 return 0;
66 }
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75
76 static int mv88e6xxx_g2_scratch_set_bit(struct mv88e6xxx_chip *chip,
77 int base_reg, unsigned int offset,
78 int set)
79 {
80 int reg = base_reg + (offset / 8);
81 u8 mask = (1 << (offset & 0x7));
82 u8 val;
83 int err;
84
85 err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
86 if (err)
87 return err;
88
89 if (set)
90 val |= mask;
91 else
92 val &= ~mask;
93
94 return mv88e6xxx_g2_scratch_write(chip, reg, val);
95 }
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103
104 static int mv88e6352_g2_scratch_gpio_get_data(struct mv88e6xxx_chip *chip,
105 unsigned int pin)
106 {
107 int val = 0;
108 int err;
109
110 err = mv88e6xxx_g2_scratch_get_bit(chip,
111 MV88E6352_G2_SCRATCH_GPIO_DATA0,
112 pin, &val);
113 if (err)
114 return err;
115
116 return val;
117 }
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124
125 static int mv88e6352_g2_scratch_gpio_set_data(struct mv88e6xxx_chip *chip,
126 unsigned int pin, int value)
127 {
128 u8 mask = (1 << (pin & 0x7));
129 int offset = (pin / 8);
130 int reg;
131
132 reg = MV88E6352_G2_SCRATCH_GPIO_DATA0 + offset;
133
134 if (value)
135 chip->gpio_data[offset] |= mask;
136 else
137 chip->gpio_data[offset] &= ~mask;
138
139 return mv88e6xxx_g2_scratch_write(chip, reg, chip->gpio_data[offset]);
140 }
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149 static int mv88e6352_g2_scratch_gpio_get_dir(struct mv88e6xxx_chip *chip,
150 unsigned int pin)
151 {
152 int val = 0;
153 int err;
154
155 err = mv88e6xxx_g2_scratch_get_bit(chip,
156 MV88E6352_G2_SCRATCH_GPIO_DIR0,
157 pin, &val);
158 if (err)
159 return err;
160
161 return val;
162 }
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168
169 static int mv88e6352_g2_scratch_gpio_set_dir(struct mv88e6xxx_chip *chip,
170 unsigned int pin, bool input)
171 {
172 int value = (input ? MV88E6352_G2_SCRATCH_GPIO_DIR_IN :
173 MV88E6352_G2_SCRATCH_GPIO_DIR_OUT);
174
175 return mv88e6xxx_g2_scratch_set_bit(chip,
176 MV88E6352_G2_SCRATCH_GPIO_DIR0,
177 pin, value);
178 }
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187
188 static int mv88e6352_g2_scratch_gpio_get_pctl(struct mv88e6xxx_chip *chip,
189 unsigned int pin, int *func)
190 {
191 int reg = MV88E6352_G2_SCRATCH_GPIO_PCTL0 + (pin / 2);
192 int offset = (pin & 0x1) ? 4 : 0;
193 u8 mask = (0x7 << offset);
194 int err;
195 u8 val;
196
197 err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
198 if (err)
199 return err;
200
201 *func = (val & mask) >> offset;
202
203 return 0;
204 }
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211
212 static int mv88e6352_g2_scratch_gpio_set_pctl(struct mv88e6xxx_chip *chip,
213 unsigned int pin, int func)
214 {
215 int reg = MV88E6352_G2_SCRATCH_GPIO_PCTL0 + (pin / 2);
216 int offset = (pin & 0x1) ? 4 : 0;
217 u8 mask = (0x7 << offset);
218 int err;
219 u8 val;
220
221 err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
222 if (err)
223 return err;
224
225 val = (val & ~mask) | ((func & mask) << offset);
226
227 return mv88e6xxx_g2_scratch_write(chip, reg, val);
228 }
229
230 const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {
231 .get_data = mv88e6352_g2_scratch_gpio_get_data,
232 .set_data = mv88e6352_g2_scratch_gpio_set_data,
233 .get_dir = mv88e6352_g2_scratch_gpio_get_dir,
234 .set_dir = mv88e6352_g2_scratch_gpio_set_dir,
235 .get_pctl = mv88e6352_g2_scratch_gpio_get_pctl,
236 .set_pctl = mv88e6352_g2_scratch_gpio_set_pctl,
237 };
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248 int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
249 bool external)
250 {
251 int misc_cfg = MV88E6352_G2_SCRATCH_MISC_CFG;
252 int config_data1 = MV88E6352_G2_SCRATCH_CONFIG_DATA1;
253 int config_data2 = MV88E6352_G2_SCRATCH_CONFIG_DATA2;
254 bool no_cpu;
255 u8 p0_mode;
256 int err;
257 u8 val;
258
259 err = mv88e6xxx_g2_scratch_read(chip, config_data2, &val);
260 if (err)
261 return err;
262
263 p0_mode = val & MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK;
264
265 if (p0_mode == 0x01 || p0_mode == 0x02)
266 return -EBUSY;
267
268 err = mv88e6xxx_g2_scratch_read(chip, config_data1, &val);
269 if (err)
270 return err;
271
272 no_cpu = !!(val & MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU);
273
274 err = mv88e6xxx_g2_scratch_read(chip, misc_cfg, &val);
275 if (err)
276 return err;
277
278
279 if (!no_cpu)
280 external = !external;
281
282 if (external)
283 val |= MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
284 else
285 val &= ~MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
286
287 return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val);
288 }