drivers/net/dsa/bcm

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
bcm_sf2_imp_setup
bcm_sf2_gphy_enable_set
bcm_sf2_port_intr_enable
bcm_sf2_port_intr_disable
bcm_sf2_port_setup
bcm_sf2_port_disable
bcm_sf2_sw_indir_rw
bcm_sf2_sw_mdio_read
bcm_sf2_sw_mdio_write
bcm_sf2_switch_0_isr
bcm_sf2_switch_1_isr
bcm_sf2_sw_rst
bcm_sf2_intr_disable
bcm_sf2_identify_ports
bcm_sf2_mdio_register
bcm_sf2_mdio_unregister
bcm_sf2_sw_get_phy_flags
bcm_sf2_sw_validate
bcm_sf2_sw_mac_config
bcm_sf2_sw_mac_link_set
bcm_sf2_sw_mac_link_down
bcm_sf2_sw_mac_link_up
bcm_sf2_sw_fixed_state
bcm_sf2_enable_acb
bcm_sf2_sw_suspend
bcm_sf2_sw_resume
bcm_sf2_sw_get_wol
bcm_sf2_sw_set_wol
bcm_sf2_sw_setup
bcm_sf2_core_read8
bcm_sf2_core_read16
bcm_sf2_core_read32
bcm_sf2_core_read64
bcm_sf2_core_write8
bcm_sf2_core_write16
bcm_sf2_core_write32
bcm_sf2_core_write64
bcm_sf2_sw_get_strings
bcm_sf2_sw_get_ethtool_stats
bcm_sf2_sw_get_sset_count
bcm_sf2_sw_probe
bcm_sf2_sw_remove
bcm_sf2_sw_shutdown
bcm_sf2_suspend
bcm_sf2_resume
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Broadcom Starfighter 2 DSA switch driver
   4  *
   5  * Copyright (C) 2014, Broadcom Corporation
   6  */
   7 
   8 #include <linux/list.h>
   9 #include <linux/module.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/phy.h>
  14 #include <linux/phy_fixed.h>
  15 #include <linux/phylink.h>
  16 #include <linux/mii.h>
  17 #include <linux/of.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_net.h>
  21 #include <linux/of_mdio.h>
  22 #include <net/dsa.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_bridge.h>
  25 #include <linux/brcmphy.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/platform_data/b53.h>
  28 
  29 #include "bcm_sf2.h"
  30 #include "bcm_sf2_regs.h"
  31 #include "b53/b53_priv.h"
  32 #include "b53/b53_regs.h"
  33 
  34 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
  35 {
  36         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
  37         unsigned int i;
  38         u32 reg, offset;
  39 
  40         /* Enable the port memories */
  41         reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
  42         reg &= ~P_TXQ_PSM_VDD(port);
  43         core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
  44 
  45         /* Enable forwarding */
  46         core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
  47 
  48         /* Enable IMP port in dumb mode */
  49         reg = core_readl(priv, CORE_SWITCH_CTRL);
  50         reg |= MII_DUMB_FWDG_EN;
  51         core_writel(priv, reg, CORE_SWITCH_CTRL);
  52 
  53         /* Configure Traffic Class to QoS mapping, allow each priority to map
  54          * to a different queue number
  55          */
  56         reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
  57         for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
  58                 reg |= i << (PRT_TO_QID_SHIFT * i);
  59         core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
  60 
  61         b53_brcm_hdr_setup(ds, port);
  62 
  63         if (port == 8) {
  64                 if (priv->type == BCM7445_DEVICE_ID)
  65                         offset = CORE_STS_OVERRIDE_IMP;
  66                 else
  67                         offset = CORE_STS_OVERRIDE_IMP2;
  68 
  69                 /* Force link status for IMP port */
  70                 reg = core_readl(priv, offset);
  71                 reg |= (MII_SW_OR | LINK_STS);
  72                 reg &= ~GMII_SPEED_UP_2G;
  73                 core_writel(priv, reg, offset);
  74 
  75                 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
  76                 reg = core_readl(priv, CORE_IMP_CTL);
  77                 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
  78                 reg &= ~(RX_DIS | TX_DIS);
  79                 core_writel(priv, reg, CORE_IMP_CTL);
  80         } else {
  81                 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
  82                 reg &= ~(RX_DIS | TX_DIS);
  83                 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
  84         }
  85 }
  86 
  87 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
  88 {
  89         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
  90         u32 reg;
  91 
  92         reg = reg_readl(priv, REG_SPHY_CNTRL);
  93         if (enable) {
  94                 reg |= PHY_RESET;
  95                 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
  96                 reg_writel(priv, reg, REG_SPHY_CNTRL);
  97                 udelay(21);
  98                 reg = reg_readl(priv, REG_SPHY_CNTRL);
  99                 reg &= ~PHY_RESET;
 100         } else {
 101                 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
 102                 reg_writel(priv, reg, REG_SPHY_CNTRL);
 103                 mdelay(1);
 104                 reg |= CK25_DIS;
 105         }
 106         reg_writel(priv, reg, REG_SPHY_CNTRL);
 107 
 108         /* Use PHY-driven LED signaling */
 109         if (!enable) {
 110                 reg = reg_readl(priv, REG_LED_CNTRL(0));
 111                 reg |= SPDLNK_SRC_SEL;
 112                 reg_writel(priv, reg, REG_LED_CNTRL(0));
 113         }
 114 }
 115 
 116 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
 117                                             int port)
 118 {
 119         unsigned int off;
 120 
 121         switch (port) {
 122         case 7:
 123                 off = P7_IRQ_OFF;
 124                 break;
 125         case 0:
 126                 /* Port 0 interrupts are located on the first bank */
 127                 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
 128                 return;
 129         default:
 130                 off = P_IRQ_OFF(port);
 131                 break;
 132         }
 133 
 134         intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
 135 }
 136 
 137 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
 138                                              int port)
 139 {
 140         unsigned int off;
 141 
 142         switch (port) {
 143         case 7:
 144                 off = P7_IRQ_OFF;
 145                 break;
 146         case 0:
 147                 /* Port 0 interrupts are located on the first bank */
 148                 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
 149                 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
 150                 return;
 151         default:
 152                 off = P_IRQ_OFF(port);
 153                 break;
 154         }
 155 
 156         intrl2_1_mask_set(priv, P_IRQ_MASK(off));
 157         intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
 158 }
 159 
 160 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
 161                               struct phy_device *phy)
 162 {
 163         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 164         unsigned int i;
 165         u32 reg;
 166 
 167         if (!dsa_is_user_port(ds, port))
 168                 return 0;
 169 
 170         /* Clear the memory power down */
 171         reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
 172         reg &= ~P_TXQ_PSM_VDD(port);
 173         core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
 174 
 175         /* Enable learning */
 176         reg = core_readl(priv, CORE_DIS_LEARN);
 177         reg &= ~BIT(port);
 178         core_writel(priv, reg, CORE_DIS_LEARN);
 179 
 180         /* Enable Broadcom tags for that port if requested */
 181         if (priv->brcm_tag_mask & BIT(port))
 182                 b53_brcm_hdr_setup(ds, port);
 183 
 184         /* Configure Traffic Class to QoS mapping, allow each priority to map
 185          * to a different queue number
 186          */
 187         reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
 188         for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
 189                 reg |= i << (PRT_TO_QID_SHIFT * i);
 190         core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
 191 
 192         /* Re-enable the GPHY and re-apply workarounds */
 193         if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
 194                 bcm_sf2_gphy_enable_set(ds, true);
 195                 if (phy) {
 196                         /* if phy_stop() has been called before, phy
 197                          * will be in halted state, and phy_start()
 198                          * will call resume.
 199                          *
 200                          * the resume path does not configure back
 201                          * autoneg settings, and since we hard reset
 202                          * the phy manually here, we need to reset the
 203                          * state machine also.
 204                          */
 205                         phy->state = PHY_READY;
 206                         phy_init_hw(phy);
 207                 }
 208         }
 209 
 210         /* Enable MoCA port interrupts to get notified */
 211         if (port == priv->moca_port)
 212                 bcm_sf2_port_intr_enable(priv, port);
 213 
 214         /* Set per-queue pause threshold to 32 */
 215         core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
 216 
 217         /* Set ACB threshold to 24 */
 218         for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
 219                 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
 220                                                     SF2_NUM_EGRESS_QUEUES + i));
 221                 reg &= ~XOFF_THRESHOLD_MASK;
 222                 reg |= 24;
 223                 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
 224                                                     SF2_NUM_EGRESS_QUEUES + i));
 225         }
 226 
 227         return b53_enable_port(ds, port, phy);
 228 }
 229 
 230 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
 231 {
 232         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 233         u32 reg;
 234 
 235         /* Disable learning while in WoL mode */
 236         if (priv->wol_ports_mask & (1 << port)) {
 237                 reg = core_readl(priv, CORE_DIS_LEARN);
 238                 reg |= BIT(port);
 239                 core_writel(priv, reg, CORE_DIS_LEARN);
 240                 return;
 241         }
 242 
 243         if (port == priv->moca_port)
 244                 bcm_sf2_port_intr_disable(priv, port);
 245 
 246         if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
 247                 bcm_sf2_gphy_enable_set(ds, false);
 248 
 249         b53_disable_port(ds, port);
 250 
 251         /* Power down the port memory */
 252         reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
 253         reg |= P_TXQ_PSM_VDD(port);
 254         core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
 255 }
 256 
 257 
 258 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
 259                                int regnum, u16 val)
 260 {
 261         int ret = 0;
 262         u32 reg;
 263 
 264         reg = reg_readl(priv, REG_SWITCH_CNTRL);
 265         reg |= MDIO_MASTER_SEL;
 266         reg_writel(priv, reg, REG_SWITCH_CNTRL);
 267 
 268         /* Page << 8 | offset */
 269         reg = 0x70;
 270         reg <<= 2;
 271         core_writel(priv, addr, reg);
 272 
 273         /* Page << 8 | offset */
 274         reg = 0x80 << 8 | regnum << 1;
 275         reg <<= 2;
 276 
 277         if (op)
 278                 ret = core_readl(priv, reg);
 279         else
 280                 core_writel(priv, val, reg);
 281 
 282         reg = reg_readl(priv, REG_SWITCH_CNTRL);
 283         reg &= ~MDIO_MASTER_SEL;
 284         reg_writel(priv, reg, REG_SWITCH_CNTRL);
 285 
 286         return ret & 0xffff;
 287 }
 288 
 289 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
 290 {
 291         struct bcm_sf2_priv *priv = bus->priv;
 292 
 293         /* Intercept reads from Broadcom pseudo-PHY address, else, send
 294          * them to our master MDIO bus controller
 295          */
 296         if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
 297                 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
 298         else
 299                 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
 300 }
 301 
 302 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
 303                                  u16 val)
 304 {
 305         struct bcm_sf2_priv *priv = bus->priv;
 306 
 307         /* Intercept writes to the Broadcom pseudo-PHY address, else,
 308          * send them to our master MDIO bus controller
 309          */
 310         if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
 311                 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
 312         else
 313                 return mdiobus_write_nested(priv->master_mii_bus, addr,
 314                                 regnum, val);
 315 }
 316 
 317 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
 318 {
 319         struct dsa_switch *ds = dev_id;
 320         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 321 
 322         priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
 323                                 ~priv->irq0_mask;
 324         intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
 325 
 326         return IRQ_HANDLED;
 327 }
 328 
 329 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
 330 {
 331         struct dsa_switch *ds = dev_id;
 332         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 333 
 334         priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
 335                                 ~priv->irq1_mask;
 336         intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
 337 
 338         if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
 339                 priv->port_sts[7].link = true;
 340                 dsa_port_phylink_mac_change(ds, 7, true);
 341         }
 342         if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
 343                 priv->port_sts[7].link = false;
 344                 dsa_port_phylink_mac_change(ds, 7, false);
 345         }
 346 
 347         return IRQ_HANDLED;
 348 }
 349 
 350 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
 351 {
 352         unsigned int timeout = 1000;
 353         u32 reg;
 354 
 355         reg = core_readl(priv, CORE_WATCHDOG_CTRL);
 356         reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
 357         core_writel(priv, reg, CORE_WATCHDOG_CTRL);
 358 
 359         do {
 360                 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
 361                 if (!(reg & SOFTWARE_RESET))
 362                         break;
 363 
 364                 usleep_range(1000, 2000);
 365         } while (timeout-- > 0);
 366 
 367         if (timeout == 0)
 368                 return -ETIMEDOUT;
 369 
 370         return 0;
 371 }
 372 
 373 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
 374 {
 375         intrl2_0_mask_set(priv, 0xffffffff);
 376         intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
 377         intrl2_1_mask_set(priv, 0xffffffff);
 378         intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
 379 }
 380 
 381 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
 382                                    struct device_node *dn)
 383 {
 384         struct device_node *port;
 385         int mode;
 386         unsigned int port_num;
 387 
 388         priv->moca_port = -1;
 389 
 390         for_each_available_child_of_node(dn, port) {
 391                 if (of_property_read_u32(port, "reg", &port_num))
 392                         continue;
 393 
 394                 /* Internal PHYs get assigned a specific 'phy-mode' property
 395                  * value: "internal" to help flag them before MDIO probing
 396                  * has completed, since they might be turned off at that
 397                  * time
 398                  */
 399                 mode = of_get_phy_mode(port);
 400                 if (mode < 0)
 401                         continue;
 402 
 403                 if (mode == PHY_INTERFACE_MODE_INTERNAL)
 404                         priv->int_phy_mask |= 1 << port_num;
 405 
 406                 if (mode == PHY_INTERFACE_MODE_MOCA)
 407                         priv->moca_port = port_num;
 408 
 409                 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
 410                         priv->brcm_tag_mask |= 1 << port_num;
 411         }
 412 }
 413 
 414 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
 415 {
 416         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 417         struct device_node *dn;
 418         static int index;
 419         int err;
 420 
 421         /* Find our integrated MDIO bus node */
 422         dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
 423         priv->master_mii_bus = of_mdio_find_bus(dn);
 424         if (!priv->master_mii_bus)
 425                 return -EPROBE_DEFER;
 426 
 427         get_device(&priv->master_mii_bus->dev);
 428         priv->master_mii_dn = dn;
 429 
 430         priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
 431         if (!priv->slave_mii_bus)
 432                 return -ENOMEM;
 433 
 434         priv->slave_mii_bus->priv = priv;
 435         priv->slave_mii_bus->name = "sf2 slave mii";
 436         priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
 437         priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
 438         snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
 439                  index++);
 440         priv->slave_mii_bus->dev.of_node = dn;
 441 
 442         /* Include the pseudo-PHY address to divert reads towards our
 443          * workaround. This is only required for 7445D0, since 7445E0
 444          * disconnects the internal switch pseudo-PHY such that we can use the
 445          * regular SWITCH_MDIO master controller instead.
 446          *
 447          * Here we flag the pseudo PHY as needing special treatment and would
 448          * otherwise make all other PHY read/writes go to the master MDIO bus
 449          * controller that comes with this switch backed by the "mdio-unimac"
 450          * driver.
 451          */
 452         if (of_machine_is_compatible("brcm,bcm7445d0"))
 453                 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
 454         else
 455                 priv->indir_phy_mask = 0;
 456 
 457         ds->phys_mii_mask = priv->indir_phy_mask;
 458         ds->slave_mii_bus = priv->slave_mii_bus;
 459         priv->slave_mii_bus->parent = ds->dev->parent;
 460         priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
 461 
 462         err = mdiobus_register(priv->slave_mii_bus);
 463         if (err && dn)
 464                 of_node_put(dn);
 465 
 466         return err;
 467 }
 468 
 469 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
 470 {
 471         mdiobus_unregister(priv->slave_mii_bus);
 472         of_node_put(priv->master_mii_dn);
 473 }
 474 
 475 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
 476 {
 477         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 478 
 479         /* The BCM7xxx PHY driver expects to find the integrated PHY revision
 480          * in bits 15:8 and the patch level in bits 7:0 which is exactly what
 481          * the REG_PHY_REVISION register layout is.
 482          */
 483 
 484         return priv->hw_params.gphy_rev;
 485 }
 486 
 487 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
 488                                 unsigned long *supported,
 489                                 struct phylink_link_state *state)
 490 {
 491         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 492         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 493 
 494         if (!phy_interface_mode_is_rgmii(state->interface) &&
 495             state->interface != PHY_INTERFACE_MODE_MII &&
 496             state->interface != PHY_INTERFACE_MODE_REVMII &&
 497             state->interface != PHY_INTERFACE_MODE_GMII &&
 498             state->interface != PHY_INTERFACE_MODE_INTERNAL &&
 499             state->interface != PHY_INTERFACE_MODE_MOCA) {
 500                 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
 501                 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
 502                         dev_err(ds->dev,
 503                                 "Unsupported interface: %d for port %d\n",
 504                                 state->interface, port);
 505                 return;
 506         }
 507 
 508         /* Allow all the expected bits */
 509         phylink_set(mask, Autoneg);
 510         phylink_set_port_modes(mask);
 511         phylink_set(mask, Pause);
 512         phylink_set(mask, Asym_Pause);
 513 
 514         /* With the exclusion of MII and Reverse MII, we support Gigabit,
 515          * including Half duplex
 516          */
 517         if (state->interface != PHY_INTERFACE_MODE_MII &&
 518             state->interface != PHY_INTERFACE_MODE_REVMII) {
 519                 phylink_set(mask, 1000baseT_Full);
 520                 phylink_set(mask, 1000baseT_Half);
 521         }
 522 
 523         phylink_set(mask, 10baseT_Half);
 524         phylink_set(mask, 10baseT_Full);
 525         phylink_set(mask, 100baseT_Half);
 526         phylink_set(mask, 100baseT_Full);
 527 
 528         bitmap_and(supported, supported, mask,
 529                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 530         bitmap_and(state->advertising, state->advertising, mask,
 531                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 532 }
 533 
 534 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
 535                                   unsigned int mode,
 536                                   const struct phylink_link_state *state)
 537 {
 538         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 539         u32 id_mode_dis = 0, port_mode;
 540         u32 reg, offset;
 541 
 542         if (port == core_readl(priv, CORE_IMP0_PRT_ID))
 543                 return;
 544 
 545         if (priv->type == BCM7445_DEVICE_ID)
 546                 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
 547         else
 548                 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
 549 
 550         switch (state->interface) {
 551         case PHY_INTERFACE_MODE_RGMII:
 552                 id_mode_dis = 1;
 553                 /* fallthrough */
 554         case PHY_INTERFACE_MODE_RGMII_TXID:
 555                 port_mode = EXT_GPHY;
 556                 break;
 557         case PHY_INTERFACE_MODE_MII:
 558                 port_mode = EXT_EPHY;
 559                 break;
 560         case PHY_INTERFACE_MODE_REVMII:
 561                 port_mode = EXT_REVMII;
 562                 break;
 563         default:
 564                 /* all other PHYs: internal and MoCA */
 565                 goto force_link;
 566         }
 567 
 568         /* Clear id_mode_dis bit, and the existing port mode, let
 569          * RGMII_MODE_EN bet set by mac_link_{up,down}
 570          */
 571         reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
 572         reg &= ~ID_MODE_DIS;
 573         reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
 574         reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
 575 
 576         reg |= port_mode;
 577         if (id_mode_dis)
 578                 reg |= ID_MODE_DIS;
 579 
 580         if (state->pause & MLO_PAUSE_TXRX_MASK) {
 581                 if (state->pause & MLO_PAUSE_TX)
 582                         reg |= TX_PAUSE_EN;
 583                 reg |= RX_PAUSE_EN;
 584         }
 585 
 586         reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
 587 
 588 force_link:
 589         /* Force link settings detected from the PHY */
 590         reg = SW_OVERRIDE;
 591         switch (state->speed) {
 592         case SPEED_1000:
 593                 reg |= SPDSTS_1000 << SPEED_SHIFT;
 594                 break;
 595         case SPEED_100:
 596                 reg |= SPDSTS_100 << SPEED_SHIFT;
 597                 break;
 598         }
 599 
 600         if (state->link)
 601                 reg |= LINK_STS;
 602         if (state->duplex == DUPLEX_FULL)
 603                 reg |= DUPLX_MODE;
 604 
 605         core_writel(priv, reg, offset);
 606 }
 607 
 608 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
 609                                     phy_interface_t interface, bool link)
 610 {
 611         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 612         u32 reg;
 613 
 614         if (!phy_interface_mode_is_rgmii(interface) &&
 615             interface != PHY_INTERFACE_MODE_MII &&
 616             interface != PHY_INTERFACE_MODE_REVMII)
 617                 return;
 618 
 619         /* If the link is down, just disable the interface to conserve power */
 620         reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
 621         if (link)
 622                 reg |= RGMII_MODE_EN;
 623         else
 624                 reg &= ~RGMII_MODE_EN;
 625         reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
 626 }
 627 
 628 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
 629                                      unsigned int mode,
 630                                      phy_interface_t interface)
 631 {
 632         bcm_sf2_sw_mac_link_set(ds, port, interface, false);
 633 }
 634 
 635 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
 636                                    unsigned int mode,
 637                                    phy_interface_t interface,
 638                                    struct phy_device *phydev)
 639 {
 640         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 641         struct ethtool_eee *p = &priv->dev->ports[port].eee;
 642 
 643         bcm_sf2_sw_mac_link_set(ds, port, interface, true);
 644 
 645         if (mode == MLO_AN_PHY && phydev)
 646                 p->eee_enabled = b53_eee_init(ds, port, phydev);
 647 }
 648 
 649 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
 650                                    struct phylink_link_state *status)
 651 {
 652         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 653 
 654         status->link = false;
 655 
 656         /* MoCA port is special as we do not get link status from CORE_LNKSTS,
 657          * which means that we need to force the link at the port override
 658          * level to get the data to flow. We do use what the interrupt handler
 659          * did determine before.
 660          *
 661          * For the other ports, we just force the link status, since this is
 662          * a fixed PHY device.
 663          */
 664         if (port == priv->moca_port) {
 665                 status->link = priv->port_sts[port].link;
 666                 /* For MoCA interfaces, also force a link down notification
 667                  * since some version of the user-space daemon (mocad) use
 668                  * cmd->autoneg to force the link, which messes up the PHY
 669                  * state machine and make it go in PHY_FORCING state instead.
 670                  */
 671                 if (!status->link)
 672                         netif_carrier_off(ds->ports[port].slave);
 673                 status->duplex = DUPLEX_FULL;
 674         } else {
 675                 status->link = true;
 676         }
 677 }
 678 
 679 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
 680 {
 681         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 682         u32 reg;
 683 
 684         /* Enable ACB globally */
 685         reg = acb_readl(priv, ACB_CONTROL);
 686         reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
 687         acb_writel(priv, reg, ACB_CONTROL);
 688         reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
 689         reg |= ACB_EN | ACB_ALGORITHM;
 690         acb_writel(priv, reg, ACB_CONTROL);
 691 }
 692 
 693 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
 694 {
 695         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 696         unsigned int port;
 697 
 698         bcm_sf2_intr_disable(priv);
 699 
 700         /* Disable all ports physically present including the IMP
 701          * port, the other ones have already been disabled during
 702          * bcm_sf2_sw_setup
 703          */
 704         for (port = 0; port < ds->num_ports; port++) {
 705                 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
 706                         bcm_sf2_port_disable(ds, port);
 707         }
 708 
 709         return 0;
 710 }
 711 
 712 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
 713 {
 714         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 715         int ret;
 716 
 717         ret = bcm_sf2_sw_rst(priv);
 718         if (ret) {
 719                 pr_err("%s: failed to software reset switch\n", __func__);
 720                 return ret;
 721         }
 722 
 723         ret = bcm_sf2_cfp_resume(ds);
 724         if (ret)
 725                 return ret;
 726 
 727         if (priv->hw_params.num_gphy == 1)
 728                 bcm_sf2_gphy_enable_set(ds, true);
 729 
 730         ds->ops->setup(ds);
 731 
 732         return 0;
 733 }
 734 
 735 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
 736                                struct ethtool_wolinfo *wol)
 737 {
 738         struct net_device *p = ds->ports[port].cpu_dp->master;
 739         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 740         struct ethtool_wolinfo pwol = { };
 741 
 742         /* Get the parent device WoL settings */
 743         if (p->ethtool_ops->get_wol)
 744                 p->ethtool_ops->get_wol(p, &pwol);
 745 
 746         /* Advertise the parent device supported settings */
 747         wol->supported = pwol.supported;
 748         memset(&wol->sopass, 0, sizeof(wol->sopass));
 749 
 750         if (pwol.wolopts & WAKE_MAGICSECURE)
 751                 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
 752 
 753         if (priv->wol_ports_mask & (1 << port))
 754                 wol->wolopts = pwol.wolopts;
 755         else
 756                 wol->wolopts = 0;
 757 }
 758 
 759 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
 760                               struct ethtool_wolinfo *wol)
 761 {
 762         struct net_device *p = ds->ports[port].cpu_dp->master;
 763         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 764         s8 cpu_port = ds->ports[port].cpu_dp->index;
 765         struct ethtool_wolinfo pwol =  { };
 766 
 767         if (p->ethtool_ops->get_wol)
 768                 p->ethtool_ops->get_wol(p, &pwol);
 769         if (wol->wolopts & ~pwol.supported)
 770                 return -EINVAL;
 771 
 772         if (wol->wolopts)
 773                 priv->wol_ports_mask |= (1 << port);
 774         else
 775                 priv->wol_ports_mask &= ~(1 << port);
 776 
 777         /* If we have at least one port enabled, make sure the CPU port
 778          * is also enabled. If the CPU port is the last one enabled, we disable
 779          * it since this configuration does not make sense.
 780          */
 781         if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
 782                 priv->wol_ports_mask |= (1 << cpu_port);
 783         else
 784                 priv->wol_ports_mask &= ~(1 << cpu_port);
 785 
 786         return p->ethtool_ops->set_wol(p, wol);
 787 }
 788 
 789 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
 790 {
 791         struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 792         unsigned int port;
 793 
 794         /* Enable all valid ports and disable those unused */
 795         for (port = 0; port < priv->hw_params.num_ports; port++) {
 796                 /* IMP port receives special treatment */
 797                 if (dsa_is_user_port(ds, port))
 798                         bcm_sf2_port_setup(ds, port, NULL);
 799                 else if (dsa_is_cpu_port(ds, port))
 800                         bcm_sf2_imp_setup(ds, port);
 801                 else
 802                         bcm_sf2_port_disable(ds, port);
 803         }
 804 
 805         b53_configure_vlan(ds);
 806         bcm_sf2_enable_acb(ds);
 807 
 808         return 0;
 809 }
 810 
 811 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
 812  * register basis so we need to translate that into an address that the
 813  * bus-glue understands.
 814  */
 815 #define SF2_PAGE_REG_MKADDR(page, reg)  ((page) << 10 | (reg) << 2)
 816 
 817 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
 818                               u8 *val)
 819 {
 820         struct bcm_sf2_priv *priv = dev->priv;
 821 
 822         *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
 823 
 824         return 0;
 825 }
 826 
 827 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
 828                                u16 *val)
 829 {
 830         struct bcm_sf2_priv *priv = dev->priv;
 831 
 832         *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
 833 
 834         return 0;
 835 }
 836 
 837 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
 838                                u32 *val)
 839 {
 840         struct bcm_sf2_priv *priv = dev->priv;
 841 
 842         *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
 843 
 844         return 0;
 845 }
 846 
 847 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
 848                                u64 *val)
 849 {
 850         struct bcm_sf2_priv *priv = dev->priv;
 851 
 852         *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
 853 
 854         return 0;
 855 }
 856 
 857 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
 858                                u8 value)
 859 {
 860         struct bcm_sf2_priv *priv = dev->priv;
 861 
 862         core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
 863 
 864         return 0;
 865 }
 866 
 867 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
 868                                 u16 value)
 869 {
 870         struct bcm_sf2_priv *priv = dev->priv;
 871 
 872         core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
 873 
 874         return 0;
 875 }
 876 
 877 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
 878                                 u32 value)
 879 {
 880         struct bcm_sf2_priv *priv = dev->priv;
 881 
 882         core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
 883 
 884         return 0;
 885 }
 886 
 887 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
 888                                 u64 value)
 889 {
 890         struct bcm_sf2_priv *priv = dev->priv;
 891 
 892         core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
 893 
 894         return 0;
 895 }
 896 
 897 static const struct b53_io_ops bcm_sf2_io_ops = {
 898         .read8  = bcm_sf2_core_read8,
 899         .read16 = bcm_sf2_core_read16,
 900         .read32 = bcm_sf2_core_read32,
 901         .read48 = bcm_sf2_core_read64,
 902         .read64 = bcm_sf2_core_read64,
 903         .write8 = bcm_sf2_core_write8,
 904         .write16 = bcm_sf2_core_write16,
 905         .write32 = bcm_sf2_core_write32,
 906         .write48 = bcm_sf2_core_write64,
 907         .write64 = bcm_sf2_core_write64,
 908 };
 909 
 910 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
 911                                    u32 stringset, uint8_t *data)
 912 {
 913         int cnt = b53_get_sset_count(ds, port, stringset);
 914 
 915         b53_get_strings(ds, port, stringset, data);
 916         bcm_sf2_cfp_get_strings(ds, port, stringset,
 917                                 data + cnt * ETH_GSTRING_LEN);
 918 }
 919 
 920 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
 921                                          uint64_t *data)
 922 {
 923         int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
 924 
 925         b53_get_ethtool_stats(ds, port, data);
 926         bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
 927 }
 928 
 929 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
 930                                      int sset)
 931 {
 932         int cnt = b53_get_sset_count(ds, port, sset);
 933 
 934         if (cnt < 0)
 935                 return cnt;
 936 
 937         cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
 938 
 939         return cnt;
 940 }
 941 
 942 static const struct dsa_switch_ops bcm_sf2_ops = {
 943         .get_tag_protocol       = b53_get_tag_protocol,
 944         .setup                  = bcm_sf2_sw_setup,
 945         .get_strings            = bcm_sf2_sw_get_strings,
 946         .get_ethtool_stats      = bcm_sf2_sw_get_ethtool_stats,
 947         .get_sset_count         = bcm_sf2_sw_get_sset_count,
 948         .get_ethtool_phy_stats  = b53_get_ethtool_phy_stats,
 949         .get_phy_flags          = bcm_sf2_sw_get_phy_flags,
 950         .phylink_validate       = bcm_sf2_sw_validate,
 951         .phylink_mac_config     = bcm_sf2_sw_mac_config,
 952         .phylink_mac_link_down  = bcm_sf2_sw_mac_link_down,
 953         .phylink_mac_link_up    = bcm_sf2_sw_mac_link_up,
 954         .phylink_fixed_state    = bcm_sf2_sw_fixed_state,
 955         .suspend                = bcm_sf2_sw_suspend,
 956         .resume                 = bcm_sf2_sw_resume,
 957         .get_wol                = bcm_sf2_sw_get_wol,
 958         .set_wol                = bcm_sf2_sw_set_wol,
 959         .port_enable            = bcm_sf2_port_setup,
 960         .port_disable           = bcm_sf2_port_disable,
 961         .get_mac_eee            = b53_get_mac_eee,
 962         .set_mac_eee            = b53_set_mac_eee,
 963         .port_bridge_join       = b53_br_join,
 964         .port_bridge_leave      = b53_br_leave,
 965         .port_stp_state_set     = b53_br_set_stp_state,
 966         .port_fast_age          = b53_br_fast_age,
 967         .port_vlan_filtering    = b53_vlan_filtering,
 968         .port_vlan_prepare      = b53_vlan_prepare,
 969         .port_vlan_add          = b53_vlan_add,
 970         .port_vlan_del          = b53_vlan_del,
 971         .port_fdb_dump          = b53_fdb_dump,
 972         .port_fdb_add           = b53_fdb_add,
 973         .port_fdb_del           = b53_fdb_del,
 974         .get_rxnfc              = bcm_sf2_get_rxnfc,
 975         .set_rxnfc              = bcm_sf2_set_rxnfc,
 976         .port_mirror_add        = b53_mirror_add,
 977         .port_mirror_del        = b53_mirror_del,
 978 };
 979 
 980 struct bcm_sf2_of_data {
 981         u32 type;
 982         const u16 *reg_offsets;
 983         unsigned int core_reg_align;
 984         unsigned int num_cfp_rules;
 985 };
 986 
 987 /* Register offsets for the SWITCH_REG_* block */
 988 static const u16 bcm_sf2_7445_reg_offsets[] = {
 989         [REG_SWITCH_CNTRL]      = 0x00,
 990         [REG_SWITCH_STATUS]     = 0x04,
 991         [REG_DIR_DATA_WRITE]    = 0x08,
 992         [REG_DIR_DATA_READ]     = 0x0C,
 993         [REG_SWITCH_REVISION]   = 0x18,
 994         [REG_PHY_REVISION]      = 0x1C,
 995         [REG_SPHY_CNTRL]        = 0x2C,
 996         [REG_RGMII_0_CNTRL]     = 0x34,
 997         [REG_RGMII_1_CNTRL]     = 0x40,
 998         [REG_RGMII_2_CNTRL]     = 0x4c,
 999         [REG_LED_0_CNTRL]       = 0x90,
1000         [REG_LED_1_CNTRL]       = 0x94,
1001         [REG_LED_2_CNTRL]       = 0x98,
1002 };
1003 
1004 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1005         .type           = BCM7445_DEVICE_ID,
1006         .core_reg_align = 0,
1007         .reg_offsets    = bcm_sf2_7445_reg_offsets,
1008         .num_cfp_rules  = 256,
1009 };
1010 
1011 static const u16 bcm_sf2_7278_reg_offsets[] = {
1012         [REG_SWITCH_CNTRL]      = 0x00,
1013         [REG_SWITCH_STATUS]     = 0x04,
1014         [REG_DIR_DATA_WRITE]    = 0x08,
1015         [REG_DIR_DATA_READ]     = 0x0c,
1016         [REG_SWITCH_REVISION]   = 0x10,
1017         [REG_PHY_REVISION]      = 0x14,
1018         [REG_SPHY_CNTRL]        = 0x24,
1019         [REG_RGMII_0_CNTRL]     = 0xe0,
1020         [REG_RGMII_1_CNTRL]     = 0xec,
1021         [REG_RGMII_2_CNTRL]     = 0xf8,
1022         [REG_LED_0_CNTRL]       = 0x40,
1023         [REG_LED_1_CNTRL]       = 0x4c,
1024         [REG_LED_2_CNTRL]       = 0x58,
1025 };
1026 
1027 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1028         .type           = BCM7278_DEVICE_ID,
1029         .core_reg_align = 1,
1030         .reg_offsets    = bcm_sf2_7278_reg_offsets,
1031         .num_cfp_rules  = 128,
1032 };
1033 
1034 static const struct of_device_id bcm_sf2_of_match[] = {
1035         { .compatible = "brcm,bcm7445-switch-v4.0",
1036           .data = &bcm_sf2_7445_data
1037         },
1038         { .compatible = "brcm,bcm7278-switch-v4.0",
1039           .data = &bcm_sf2_7278_data
1040         },
1041         { .compatible = "brcm,bcm7278-switch-v4.8",
1042           .data = &bcm_sf2_7278_data
1043         },
1044         { /* sentinel */ },
1045 };
1046 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1047 
1048 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1049 {
1050         const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1051         struct device_node *dn = pdev->dev.of_node;
1052         const struct of_device_id *of_id = NULL;
1053         const struct bcm_sf2_of_data *data;
1054         struct b53_platform_data *pdata;
1055         struct dsa_switch_ops *ops;
1056         struct device_node *ports;
1057         struct bcm_sf2_priv *priv;
1058         struct b53_device *dev;
1059         struct dsa_switch *ds;
1060         void __iomem **base;
1061         unsigned int i;
1062         u32 reg, rev;
1063         int ret;
1064 
1065         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1066         if (!priv)
1067                 return -ENOMEM;
1068 
1069         ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1070         if (!ops)
1071                 return -ENOMEM;
1072 
1073         dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1074         if (!dev)
1075                 return -ENOMEM;
1076 
1077         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1078         if (!pdata)
1079                 return -ENOMEM;
1080 
1081         of_id = of_match_node(bcm_sf2_of_match, dn);
1082         if (!of_id || !of_id->data)
1083                 return -EINVAL;
1084 
1085         data = of_id->data;
1086 
1087         /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1088         priv->type = data->type;
1089         priv->reg_offsets = data->reg_offsets;
1090         priv->core_reg_align = data->core_reg_align;
1091         priv->num_cfp_rules = data->num_cfp_rules;
1092 
1093         /* Auto-detection using standard registers will not work, so
1094          * provide an indication of what kind of device we are for
1095          * b53_common to work with
1096          */
1097         pdata->chip_id = priv->type;
1098         dev->pdata = pdata;
1099 
1100         priv->dev = dev;
1101         ds = dev->ds;
1102         ds->ops = &bcm_sf2_ops;
1103 
1104         /* Advertise the 8 egress queues */
1105         ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1106 
1107         dev_set_drvdata(&pdev->dev, priv);
1108 
1109         spin_lock_init(&priv->indir_lock);
1110         mutex_init(&priv->cfp.lock);
1111         INIT_LIST_HEAD(&priv->cfp.rules_list);
1112 
1113         /* CFP rule #0 cannot be used for specific classifications, flag it as
1114          * permanently used
1115          */
1116         set_bit(0, priv->cfp.used);
1117         set_bit(0, priv->cfp.unique);
1118 
1119         ports = of_find_node_by_name(dn, "ports");
1120         if (ports) {
1121                 bcm_sf2_identify_ports(priv, ports);
1122                 of_node_put(ports);
1123         }
1124 
1125         priv->irq0 = irq_of_parse_and_map(dn, 0);
1126         priv->irq1 = irq_of_parse_and_map(dn, 1);
1127 
1128         base = &priv->core;
1129         for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1130                 *base = devm_platform_ioremap_resource(pdev, i);
1131                 if (IS_ERR(*base)) {
1132                         pr_err("unable to find register: %s\n", reg_names[i]);
1133                         return PTR_ERR(*base);
1134                 }
1135                 base++;
1136         }
1137 
1138         ret = bcm_sf2_sw_rst(priv);
1139         if (ret) {
1140                 pr_err("unable to software reset switch: %d\n", ret);
1141                 return ret;
1142         }
1143 
1144         bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1145 
1146         ret = bcm_sf2_mdio_register(ds);
1147         if (ret) {
1148                 pr_err("failed to register MDIO bus\n");
1149                 return ret;
1150         }
1151 
1152         bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1153 
1154         ret = bcm_sf2_cfp_rst(priv);
1155         if (ret) {
1156                 pr_err("failed to reset CFP\n");
1157                 goto out_mdio;
1158         }
1159 
1160         /* Disable all interrupts and request them */
1161         bcm_sf2_intr_disable(priv);
1162 
1163         ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1164                                "switch_0", ds);
1165         if (ret < 0) {
1166                 pr_err("failed to request switch_0 IRQ\n");
1167                 goto out_mdio;
1168         }
1169 
1170         ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1171                                "switch_1", ds);
1172         if (ret < 0) {
1173                 pr_err("failed to request switch_1 IRQ\n");
1174                 goto out_mdio;
1175         }
1176 
1177         /* Reset the MIB counters */
1178         reg = core_readl(priv, CORE_GMNCFGCFG);
1179         reg |= RST_MIB_CNT;
1180         core_writel(priv, reg, CORE_GMNCFGCFG);
1181         reg &= ~RST_MIB_CNT;
1182         core_writel(priv, reg, CORE_GMNCFGCFG);
1183 
1184         /* Get the maximum number of ports for this switch */
1185         priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1186         if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1187                 priv->hw_params.num_ports = DSA_MAX_PORTS;
1188 
1189         /* Assume a single GPHY setup if we can't read that property */
1190         if (of_property_read_u32(dn, "brcm,num-gphy",
1191                                  &priv->hw_params.num_gphy))
1192                 priv->hw_params.num_gphy = 1;
1193 
1194         rev = reg_readl(priv, REG_SWITCH_REVISION);
1195         priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1196                                         SWITCH_TOP_REV_MASK;
1197         priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1198 
1199         rev = reg_readl(priv, REG_PHY_REVISION);
1200         priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1201 
1202         ret = b53_switch_register(dev);
1203         if (ret)
1204                 goto out_mdio;
1205 
1206         dev_info(&pdev->dev,
1207                  "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1208                  priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1209                  priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1210                  priv->irq0, priv->irq1);
1211 
1212         return 0;
1213 
1214 out_mdio:
1215         bcm_sf2_mdio_unregister(priv);
1216         return ret;
1217 }
1218 
1219 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1220 {
1221         struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1222 
1223         priv->wol_ports_mask = 0;
1224         /* Disable interrupts */
1225         bcm_sf2_intr_disable(priv);
1226         dsa_unregister_switch(priv->dev->ds);
1227         bcm_sf2_cfp_exit(priv->dev->ds);
1228         bcm_sf2_mdio_unregister(priv);
1229 
1230         return 0;
1231 }
1232 
1233 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1234 {
1235         struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1236 
1237         /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1238          * successful MDIO bus scan to occur. If we did turn off the GPHY
1239          * before (e.g: port_disable), this will also power it back on.
1240          *
1241          * Do not rely on kexec_in_progress, just power the PHY on.
1242          */
1243         if (priv->hw_params.num_gphy == 1)
1244                 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1245 }
1246 
1247 #ifdef CONFIG_PM_SLEEP
1248 static int bcm_sf2_suspend(struct device *dev)
1249 {
1250         struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1251 
1252         return dsa_switch_suspend(priv->dev->ds);
1253 }
1254 
1255 static int bcm_sf2_resume(struct device *dev)
1256 {
1257         struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1258 
1259         return dsa_switch_resume(priv->dev->ds);
1260 }
1261 #endif /* CONFIG_PM_SLEEP */
1262 
1263 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1264                          bcm_sf2_suspend, bcm_sf2_resume);
1265 
1266 
1267 static struct platform_driver bcm_sf2_driver = {
1268         .probe  = bcm_sf2_sw_probe,
1269         .remove = bcm_sf2_sw_remove,
1270         .shutdown = bcm_sf2_sw_shutdown,
1271         .driver = {
1272                 .name = "brcm-sf2",
1273                 .of_match_table = bcm_sf2_of_match,
1274                 .pm = &bcm_sf2_pm_ops,
1275         },
1276 };
1277 module_platform_driver(bcm_sf2_driver);
1278 
1279 MODULE_AUTHOR("Broadcom Corporation");
1280 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1281 MODULE_LICENSE("GPL");
1282 MODULE_ALIAS("platform:brcm-sf2");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/dsa/bcm_sf2.c

DEFINITIONS
