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8 #ifndef __KSZ9477_REGS_H
9 #define __KSZ9477_REGS_H
10
11 #define KS_PRIO_M 0x7
12 #define KS_PRIO_S 4
13
14
15 #define REG_CHIP_ID0__1 0x0000
16
17 #define REG_CHIP_ID1__1 0x0001
18
19 #define FAMILY_ID 0x95
20 #define FAMILY_ID_94 0x94
21 #define FAMILY_ID_95 0x95
22 #define FAMILY_ID_85 0x85
23 #define FAMILY_ID_98 0x98
24 #define FAMILY_ID_88 0x88
25
26 #define REG_CHIP_ID2__1 0x0002
27
28 #define CHIP_ID_63 0x63
29 #define CHIP_ID_66 0x66
30 #define CHIP_ID_67 0x67
31 #define CHIP_ID_77 0x77
32 #define CHIP_ID_93 0x93
33 #define CHIP_ID_96 0x96
34 #define CHIP_ID_97 0x97
35
36 #define REG_CHIP_ID3__1 0x0003
37
38 #define SWITCH_REVISION_M 0x0F
39 #define SWITCH_REVISION_S 4
40 #define SWITCH_RESET 0x01
41
42 #define REG_SW_PME_CTRL 0x0006
43
44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
46
47 #define REG_GLOBAL_OPTIONS 0x000F
48
49 #define SW_GIGABIT_ABLE BIT(6)
50 #define SW_REDUNDANCY_ABLE BIT(5)
51 #define SW_AVB_ABLE BIT(4)
52 #define SW_9567_RL_5_2 0xC
53 #define SW_9477_SL_5_2 0xD
54
55 #define SW_9896_GL_5_1 0xB
56 #define SW_9896_RL_5_1 0x8
57 #define SW_9896_SL_5_1 0x9
58
59 #define SW_9895_GL_4_1 0x7
60 #define SW_9895_RL_4_1 0x4
61 #define SW_9895_SL_4_1 0x5
62
63 #define SW_9896_RL_4_2 0x6
64
65 #define SW_9893_RL_2_1 0x0
66 #define SW_9893_SL_2_1 0x1
67 #define SW_9893_GL_2_1 0x3
68
69 #define SW_QW_ABLE BIT(5)
70 #define SW_9893_RN_2_1 0xC
71
72 #define REG_SW_INT_STATUS__4 0x0010
73 #define REG_SW_INT_MASK__4 0x0014
74
75 #define LUE_INT BIT(31)
76 #define TRIG_TS_INT BIT(30)
77 #define APB_TIMEOUT_INT BIT(29)
78
79 #define SWITCH_INT_MASK (TRIG_TS_INT | APB_TIMEOUT_INT)
80
81 #define REG_SW_PORT_INT_STATUS__4 0x0018
82 #define REG_SW_PORT_INT_MASK__4 0x001C
83 #define REG_SW_PHY_INT_STATUS 0x0020
84 #define REG_SW_PHY_INT_ENABLE 0x0024
85
86
87 #define REG_SW_GLOBAL_SERIAL_CTRL_0 0x0100
88 #define SW_SPARE_REG_2 BIT(7)
89 #define SW_SPARE_REG_1 BIT(6)
90 #define SW_SPARE_REG_0 BIT(5)
91 #define SW_BIG_ENDIAN BIT(4)
92 #define SPI_AUTO_EDGE_DETECTION BIT(1)
93 #define SPI_CLOCK_OUT_RISING_EDGE BIT(0)
94
95 #define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103
96 #define SW_ENABLE_REFCLKO BIT(1)
97 #define SW_REFCLKO_IS_125MHZ BIT(0)
98
99 #define REG_SW_IBA__4 0x0104
100
101 #define SW_IBA_ENABLE BIT(31)
102 #define SW_IBA_DA_MATCH BIT(30)
103 #define SW_IBA_INIT BIT(29)
104 #define SW_IBA_QID_M 0xF
105 #define SW_IBA_QID_S 22
106 #define SW_IBA_PORT_M 0x2F
107 #define SW_IBA_PORT_S 16
108 #define SW_IBA_FRAME_TPID_M 0xFFFF
109
110 #define REG_SW_APB_TIMEOUT_ADDR__4 0x0108
111
112 #define APB_TIMEOUT_ACKNOWLEDGE BIT(31)
113
114 #define REG_SW_IBA_SYNC__1 0x010C
115
116 #define REG_SW_IO_STRENGTH__1 0x010D
117 #define SW_DRIVE_STRENGTH_M 0x7
118 #define SW_DRIVE_STRENGTH_2MA 0
119 #define SW_DRIVE_STRENGTH_4MA 1
120 #define SW_DRIVE_STRENGTH_8MA 2
121 #define SW_DRIVE_STRENGTH_12MA 3
122 #define SW_DRIVE_STRENGTH_16MA 4
123 #define SW_DRIVE_STRENGTH_20MA 5
124 #define SW_DRIVE_STRENGTH_24MA 6
125 #define SW_DRIVE_STRENGTH_28MA 7
126 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4
127 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0
128
129 #define REG_SW_IBA_STATUS__4 0x0110
130
131 #define SW_IBA_REQ BIT(31)
132 #define SW_IBA_RESP BIT(30)
133 #define SW_IBA_DA_MISMATCH BIT(14)
134 #define SW_IBA_FMT_MISMATCH BIT(13)
135 #define SW_IBA_CODE_ERROR BIT(12)
136 #define SW_IBA_CMD_ERROR BIT(11)
137 #define SW_IBA_CMD_LOC_M (BIT(6) - 1)
138
139 #define REG_SW_IBA_STATES__4 0x0114
140
141 #define SW_IBA_BUF_STATE_S 30
142 #define SW_IBA_CMD_STATE_S 28
143 #define SW_IBA_RESP_STATE_S 26
144 #define SW_IBA_STATE_M 0x3
145 #define SW_IBA_PACKET_SIZE_M 0x7F
146 #define SW_IBA_PACKET_SIZE_S 16
147 #define SW_IBA_FMT_ID_M 0xFFFF
148
149 #define REG_SW_IBA_RESULT__4 0x0118
150
151 #define SW_IBA_SIZE_S 24
152
153 #define SW_IBA_RETRY_CNT_M (BIT(5) - 1)
154
155
156 #define REG_SW_POWER_MANAGEMENT_CTRL 0x0201
157
158 #define SW_PLL_POWER_DOWN BIT(5)
159 #define SW_POWER_DOWN_MODE 0x3
160 #define SW_ENERGY_DETECTION 1
161 #define SW_SOFT_POWER_DOWN 2
162 #define SW_POWER_SAVING 3
163
164
165 #define REG_SW_OPERATION 0x0300
166
167 #define SW_DOUBLE_TAG BIT(7)
168 #define SW_RESET BIT(1)
169 #define SW_START BIT(0)
170
171 #define REG_SW_MAC_ADDR_0 0x0302
172 #define REG_SW_MAC_ADDR_1 0x0303
173 #define REG_SW_MAC_ADDR_2 0x0304
174 #define REG_SW_MAC_ADDR_3 0x0305
175 #define REG_SW_MAC_ADDR_4 0x0306
176 #define REG_SW_MAC_ADDR_5 0x0307
177
178 #define REG_SW_MTU__2 0x0308
179
180 #define REG_SW_ISP_TPID__2 0x030A
181
182 #define REG_SW_HSR_TPID__2 0x030C
183
184 #define REG_AVB_STRATEGY__2 0x030E
185
186 #define SW_SHAPING_CREDIT_ACCT BIT(1)
187 #define SW_POLICING_CREDIT_ACCT BIT(0)
188
189 #define REG_SW_LUE_CTRL_0 0x0310
190
191 #define SW_VLAN_ENABLE BIT(7)
192 #define SW_DROP_INVALID_VID BIT(6)
193 #define SW_AGE_CNT_M 0x7
194 #define SW_AGE_CNT_S 3
195 #define SW_RESV_MCAST_ENABLE BIT(2)
196 #define SW_HASH_OPTION_M 0x03
197 #define SW_HASH_OPTION_CRC 1
198 #define SW_HASH_OPTION_XOR 2
199 #define SW_HASH_OPTION_DIRECT 3
200
201 #define REG_SW_LUE_CTRL_1 0x0311
202
203 #define UNICAST_LEARN_DISABLE BIT(7)
204 #define SW_SRC_ADDR_FILTER BIT(6)
205 #define SW_FLUSH_STP_TABLE BIT(5)
206 #define SW_FLUSH_MSTP_TABLE BIT(4)
207 #define SW_FWD_MCAST_SRC_ADDR BIT(3)
208 #define SW_AGING_ENABLE BIT(2)
209 #define SW_FAST_AGING BIT(1)
210 #define SW_LINK_AUTO_AGING BIT(0)
211
212 #define REG_SW_LUE_CTRL_2 0x0312
213
214 #define SW_TRAP_DOUBLE_TAG BIT(6)
215 #define SW_EGRESS_VLAN_FILTER_DYN BIT(5)
216 #define SW_EGRESS_VLAN_FILTER_STA BIT(4)
217 #define SW_FLUSH_OPTION_M 0x3
218 #define SW_FLUSH_OPTION_S 2
219 #define SW_FLUSH_OPTION_DYN_MAC 1
220 #define SW_FLUSH_OPTION_STA_MAC 2
221 #define SW_FLUSH_OPTION_BOTH 3
222 #define SW_PRIO_M 0x3
223 #define SW_PRIO_DA 0
224 #define SW_PRIO_SA 1
225 #define SW_PRIO_HIGHEST_DA_SA 2
226 #define SW_PRIO_LOWEST_DA_SA 3
227
228 #define REG_SW_LUE_CTRL_3 0x0313
229
230 #define REG_SW_LUE_INT_STATUS 0x0314
231 #define REG_SW_LUE_INT_ENABLE 0x0315
232
233 #define LEARN_FAIL_INT BIT(2)
234 #define ALMOST_FULL_INT BIT(1)
235 #define WRITE_FAIL_INT BIT(0)
236
237 #define REG_SW_LUE_INDEX_0__2 0x0316
238
239 #define ENTRY_INDEX_M 0x0FFF
240
241 #define REG_SW_LUE_INDEX_1__2 0x0318
242
243 #define FAIL_INDEX_M 0x03FF
244
245 #define REG_SW_LUE_INDEX_2__2 0x031A
246
247 #define REG_SW_LUE_UNK_UCAST_CTRL__4 0x0320
248
249 #define SW_UNK_UCAST_ENABLE BIT(31)
250
251 #define REG_SW_LUE_UNK_MCAST_CTRL__4 0x0324
252
253 #define SW_UNK_MCAST_ENABLE BIT(31)
254
255 #define REG_SW_LUE_UNK_VID_CTRL__4 0x0328
256
257 #define SW_UNK_VID_ENABLE BIT(31)
258
259 #define REG_SW_MAC_CTRL_0 0x0330
260
261 #define SW_NEW_BACKOFF BIT(7)
262 #define SW_CHECK_LENGTH BIT(3)
263 #define SW_PAUSE_UNH_MODE BIT(1)
264 #define SW_AGGR_BACKOFF BIT(0)
265
266 #define REG_SW_MAC_CTRL_1 0x0331
267
268 #define MULTICAST_STORM_DISABLE BIT(6)
269 #define SW_BACK_PRESSURE BIT(5)
270 #define FAIR_FLOW_CTRL BIT(4)
271 #define NO_EXC_COLLISION_DROP BIT(3)
272 #define SW_JUMBO_PACKET BIT(2)
273 #define SW_LEGAL_PACKET_DISABLE BIT(1)
274 #define SW_PASS_SHORT_FRAME BIT(0)
275
276 #define REG_SW_MAC_CTRL_2 0x0332
277
278 #define SW_REPLACE_VID BIT(3)
279 #define BROADCAST_STORM_RATE_HI 0x07
280
281 #define REG_SW_MAC_CTRL_3 0x0333
282
283 #define BROADCAST_STORM_RATE_LO 0xFF
284 #define BROADCAST_STORM_RATE 0x07FF
285
286 #define REG_SW_MAC_CTRL_4 0x0334
287
288 #define SW_PASS_PAUSE BIT(3)
289
290 #define REG_SW_MAC_CTRL_5 0x0335
291
292 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
293
294 #define REG_SW_MAC_CTRL_6 0x0336
295
296 #define SW_MIB_COUNTER_FLUSH BIT(7)
297 #define SW_MIB_COUNTER_FREEZE BIT(6)
298
299 #define REG_SW_MAC_802_1P_MAP_0 0x0338
300 #define REG_SW_MAC_802_1P_MAP_1 0x0339
301 #define REG_SW_MAC_802_1P_MAP_2 0x033A
302 #define REG_SW_MAC_802_1P_MAP_3 0x033B
303
304 #define SW_802_1P_MAP_M KS_PRIO_M
305 #define SW_802_1P_MAP_S KS_PRIO_S
306
307 #define REG_SW_MAC_ISP_CTRL 0x033C
308
309 #define REG_SW_MAC_TOS_CTRL 0x033E
310
311 #define SW_TOS_DSCP_REMARK BIT(1)
312 #define SW_TOS_DSCP_REMAP BIT(0)
313
314 #define REG_SW_MAC_TOS_PRIO_0 0x0340
315 #define REG_SW_MAC_TOS_PRIO_1 0x0341
316 #define REG_SW_MAC_TOS_PRIO_2 0x0342
317 #define REG_SW_MAC_TOS_PRIO_3 0x0343
318 #define REG_SW_MAC_TOS_PRIO_4 0x0344
319 #define REG_SW_MAC_TOS_PRIO_5 0x0345
320 #define REG_SW_MAC_TOS_PRIO_6 0x0346
321 #define REG_SW_MAC_TOS_PRIO_7 0x0347
322 #define REG_SW_MAC_TOS_PRIO_8 0x0348
323 #define REG_SW_MAC_TOS_PRIO_9 0x0349
324 #define REG_SW_MAC_TOS_PRIO_10 0x034A
325 #define REG_SW_MAC_TOS_PRIO_11 0x034B
326 #define REG_SW_MAC_TOS_PRIO_12 0x034C
327 #define REG_SW_MAC_TOS_PRIO_13 0x034D
328 #define REG_SW_MAC_TOS_PRIO_14 0x034E
329 #define REG_SW_MAC_TOS_PRIO_15 0x034F
330 #define REG_SW_MAC_TOS_PRIO_16 0x0350
331 #define REG_SW_MAC_TOS_PRIO_17 0x0351
332 #define REG_SW_MAC_TOS_PRIO_18 0x0352
333 #define REG_SW_MAC_TOS_PRIO_19 0x0353
334 #define REG_SW_MAC_TOS_PRIO_20 0x0354
335 #define REG_SW_MAC_TOS_PRIO_21 0x0355
336 #define REG_SW_MAC_TOS_PRIO_22 0x0356
337 #define REG_SW_MAC_TOS_PRIO_23 0x0357
338 #define REG_SW_MAC_TOS_PRIO_24 0x0358
339 #define REG_SW_MAC_TOS_PRIO_25 0x0359
340 #define REG_SW_MAC_TOS_PRIO_26 0x035A
341 #define REG_SW_MAC_TOS_PRIO_27 0x035B
342 #define REG_SW_MAC_TOS_PRIO_28 0x035C
343 #define REG_SW_MAC_TOS_PRIO_29 0x035D
344 #define REG_SW_MAC_TOS_PRIO_30 0x035E
345 #define REG_SW_MAC_TOS_PRIO_31 0x035F
346
347 #define REG_SW_MRI_CTRL_0 0x0370
348
349 #define SW_IGMP_SNOOP BIT(6)
350 #define SW_IPV6_MLD_OPTION BIT(3)
351 #define SW_IPV6_MLD_SNOOP BIT(2)
352 #define SW_MIRROR_RX_TX BIT(0)
353
354 #define REG_SW_CLASS_D_IP_CTRL__4 0x0374
355
356 #define SW_CLASS_D_IP_ENABLE BIT(31)
357
358 #define REG_SW_MRI_CTRL_8 0x0378
359
360 #define SW_NO_COLOR_S 6
361 #define SW_RED_COLOR_S 4
362 #define SW_YELLOW_COLOR_S 2
363 #define SW_GREEN_COLOR_S 0
364 #define SW_COLOR_M 0x3
365
366 #define REG_SW_QM_CTRL__4 0x0390
367
368 #define PRIO_SCHEME_SELECT_M KS_PRIO_M
369 #define PRIO_SCHEME_SELECT_S 6
370 #define PRIO_MAP_3_HI 0
371 #define PRIO_MAP_2_HI 2
372 #define PRIO_MAP_0_LO 3
373 #define UNICAST_VLAN_BOUNDARY BIT(1)
374
375 #define REG_SW_EEE_QM_CTRL__2 0x03C0
376
377 #define REG_SW_EEE_TXQ_WAIT_TIME__2 0x03C2
378
379
380 #define REG_SW_VLAN_ENTRY__4 0x0400
381
382 #define VLAN_VALID BIT(31)
383 #define VLAN_FORWARD_OPTION BIT(27)
384 #define VLAN_PRIO_M KS_PRIO_M
385 #define VLAN_PRIO_S 24
386 #define VLAN_MSTP_M 0x7
387 #define VLAN_MSTP_S 12
388 #define VLAN_FID_M 0x7F
389
390 #define REG_SW_VLAN_ENTRY_UNTAG__4 0x0404
391 #define REG_SW_VLAN_ENTRY_PORTS__4 0x0408
392
393 #define REG_SW_VLAN_ENTRY_INDEX__2 0x040C
394
395 #define VLAN_INDEX_M 0x0FFF
396
397 #define REG_SW_VLAN_CTRL 0x040E
398
399 #define VLAN_START BIT(7)
400 #define VLAN_ACTION 0x3
401 #define VLAN_WRITE 1
402 #define VLAN_READ 2
403 #define VLAN_CLEAR 3
404
405 #define REG_SW_ALU_INDEX_0 0x0410
406
407 #define ALU_FID_INDEX_S 16
408 #define ALU_MAC_ADDR_HI 0xFFFF
409
410 #define REG_SW_ALU_INDEX_1 0x0414
411
412 #define ALU_DIRECT_INDEX_M (BIT(12) - 1)
413
414 #define REG_SW_ALU_CTRL__4 0x0418
415
416 #define ALU_VALID_CNT_M (BIT(14) - 1)
417 #define ALU_VALID_CNT_S 16
418 #define ALU_START BIT(7)
419 #define ALU_VALID BIT(6)
420 #define ALU_DIRECT BIT(2)
421 #define ALU_ACTION 0x3
422 #define ALU_WRITE 1
423 #define ALU_READ 2
424 #define ALU_SEARCH 3
425
426 #define REG_SW_ALU_STAT_CTRL__4 0x041C
427
428 #define ALU_STAT_INDEX_M (BIT(4) - 1)
429 #define ALU_STAT_INDEX_S 16
430 #define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1)
431 #define ALU_STAT_START BIT(7)
432 #define ALU_RESV_MCAST_ADDR BIT(1)
433 #define ALU_STAT_READ BIT(0)
434
435 #define REG_SW_ALU_VAL_A 0x0420
436
437 #define ALU_V_STATIC_VALID BIT(31)
438 #define ALU_V_SRC_FILTER BIT(30)
439 #define ALU_V_DST_FILTER BIT(29)
440 #define ALU_V_PRIO_AGE_CNT_M (BIT(3) - 1)
441 #define ALU_V_PRIO_AGE_CNT_S 26
442 #define ALU_V_MSTP_M 0x7
443
444 #define REG_SW_ALU_VAL_B 0x0424
445
446 #define ALU_V_OVERRIDE BIT(31)
447 #define ALU_V_USE_FID BIT(30)
448 #define ALU_V_PORT_MAP (BIT(24) - 1)
449
450 #define REG_SW_ALU_VAL_C 0x0428
451
452 #define ALU_V_FID_M (BIT(16) - 1)
453 #define ALU_V_FID_S 16
454 #define ALU_V_MAC_ADDR_HI 0xFFFF
455
456 #define REG_SW_ALU_VAL_D 0x042C
457
458 #define REG_HSR_ALU_INDEX_0 0x0440
459
460 #define REG_HSR_ALU_INDEX_1 0x0444
461
462 #define HSR_DST_MAC_INDEX_LO_S 16
463 #define HSR_SRC_MAC_INDEX_HI 0xFFFF
464
465 #define REG_HSR_ALU_INDEX_2 0x0448
466
467 #define HSR_INDEX_MAX BIT(9)
468 #define HSR_DIRECT_INDEX_M (HSR_INDEX_MAX - 1)
469
470 #define REG_HSR_ALU_INDEX_3 0x044C
471
472 #define HSR_PATH_INDEX_M (BIT(4) - 1)
473
474 #define REG_HSR_ALU_CTRL__4 0x0450
475
476 #define HSR_VALID_CNT_M (BIT(14) - 1)
477 #define HSR_VALID_CNT_S 16
478 #define HSR_START BIT(7)
479 #define HSR_VALID BIT(6)
480 #define HSR_SEARCH_END BIT(5)
481 #define HSR_DIRECT BIT(2)
482 #define HSR_ACTION 0x3
483 #define HSR_WRITE 1
484 #define HSR_READ 2
485 #define HSR_SEARCH 3
486
487 #define REG_HSR_ALU_VAL_A 0x0454
488
489 #define HSR_V_STATIC_VALID BIT(31)
490 #define HSR_V_AGE_CNT_M (BIT(3) - 1)
491 #define HSR_V_AGE_CNT_S 26
492 #define HSR_V_PATH_ID_M (BIT(4) - 1)
493
494 #define REG_HSR_ALU_VAL_B 0x0458
495
496 #define REG_HSR_ALU_VAL_C 0x045C
497
498 #define HSR_V_DST_MAC_ADDR_LO_S 16
499 #define HSR_V_SRC_MAC_ADDR_HI 0xFFFF
500
501 #define REG_HSR_ALU_VAL_D 0x0460
502
503 #define REG_HSR_ALU_VAL_E 0x0464
504
505 #define HSR_V_START_SEQ_1_S 16
506 #define HSR_V_START_SEQ_2_S 0
507
508 #define REG_HSR_ALU_VAL_F 0x0468
509
510 #define HSR_V_EXP_SEQ_1_S 16
511 #define HSR_V_EXP_SEQ_2_S 0
512
513 #define REG_HSR_ALU_VAL_G 0x046C
514
515 #define HSR_V_SEQ_CNT_1_S 16
516 #define HSR_V_SEQ_CNT_2_S 0
517
518 #define HSR_V_SEQ_M (BIT(16) - 1)
519
520
521 #define REG_PTP_CLK_CTRL 0x0500
522
523 #define PTP_STEP_ADJ BIT(6)
524 #define PTP_STEP_DIR BIT(5)
525 #define PTP_READ_TIME BIT(4)
526 #define PTP_LOAD_TIME BIT(3)
527 #define PTP_CLK_ADJ_ENABLE BIT(2)
528 #define PTP_CLK_ENABLE BIT(1)
529 #define PTP_CLK_RESET BIT(0)
530
531 #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
532
533 #define PTP_RTC_SUB_NANOSEC_M 0x0007
534
535 #define REG_PTP_RTC_NANOSEC 0x0504
536 #define REG_PTP_RTC_NANOSEC_H 0x0504
537 #define REG_PTP_RTC_NANOSEC_L 0x0506
538
539 #define REG_PTP_RTC_SEC 0x0508
540 #define REG_PTP_RTC_SEC_H 0x0508
541 #define REG_PTP_RTC_SEC_L 0x050A
542
543 #define REG_PTP_SUBNANOSEC_RATE 0x050C
544 #define REG_PTP_SUBNANOSEC_RATE_H 0x050C
545
546 #define PTP_RATE_DIR BIT(31)
547 #define PTP_TMP_RATE_ENABLE BIT(30)
548
549 #define REG_PTP_SUBNANOSEC_RATE_L 0x050E
550
551 #define REG_PTP_RATE_DURATION 0x0510
552 #define REG_PTP_RATE_DURATION_H 0x0510
553 #define REG_PTP_RATE_DURATION_L 0x0512
554
555 #define REG_PTP_MSG_CONF1 0x0514
556
557 #define PTP_802_1AS BIT(7)
558 #define PTP_ENABLE BIT(6)
559 #define PTP_ETH_ENABLE BIT(5)
560 #define PTP_IPV4_UDP_ENABLE BIT(4)
561 #define PTP_IPV6_UDP_ENABLE BIT(3)
562 #define PTP_TC_P2P BIT(2)
563 #define PTP_MASTER BIT(1)
564 #define PTP_1STEP BIT(0)
565
566 #define REG_PTP_MSG_CONF2 0x0516
567
568 #define PTP_UNICAST_ENABLE BIT(12)
569 #define PTP_ALTERNATE_MASTER BIT(11)
570 #define PTP_ALL_HIGH_PRIO BIT(10)
571 #define PTP_SYNC_CHECK BIT(9)
572 #define PTP_DELAY_CHECK BIT(8)
573 #define PTP_PDELAY_CHECK BIT(7)
574 #define PTP_DROP_SYNC_DELAY_REQ BIT(5)
575 #define PTP_DOMAIN_CHECK BIT(4)
576 #define PTP_UDP_CHECKSUM BIT(2)
577
578 #define REG_PTP_DOMAIN_VERSION 0x0518
579 #define PTP_VERSION_M 0xFF00
580 #define PTP_DOMAIN_M 0x00FF
581
582 #define REG_PTP_UNIT_INDEX__4 0x0520
583
584 #define PTP_UNIT_M 0xF
585
586 #define PTP_GPIO_INDEX_S 16
587 #define PTP_TSI_INDEX_S 8
588 #define PTP_TOU_INDEX_S 0
589
590 #define REG_PTP_TRIG_STATUS__4 0x0524
591
592 #define TRIG_ERROR_S 16
593 #define TRIG_DONE_S 0
594
595 #define REG_PTP_INT_STATUS__4 0x0528
596
597 #define TRIG_INT_S 16
598 #define TS_INT_S 0
599
600 #define TRIG_UNIT_M 0x7
601 #define TS_UNIT_M 0x3
602
603 #define REG_PTP_CTRL_STAT__4 0x052C
604
605 #define GPIO_IN BIT(7)
606 #define GPIO_OUT BIT(6)
607 #define TS_INT_ENABLE BIT(5)
608 #define TRIG_ACTIVE BIT(4)
609 #define TRIG_ENABLE BIT(3)
610 #define TRIG_RESET BIT(2)
611 #define TS_ENABLE BIT(1)
612 #define TS_RESET BIT(0)
613
614 #define GPIO_CTRL_M (GPIO_IN | GPIO_OUT)
615
616 #define TRIG_CTRL_M \
617 (TRIG_ACTIVE | TRIG_ENABLE | TRIG_RESET)
618
619 #define TS_CTRL_M \
620 (TS_INT_ENABLE | TS_ENABLE | TS_RESET)
621
622 #define REG_TRIG_TARGET_NANOSEC 0x0530
623 #define REG_TRIG_TARGET_SEC 0x0534
624
625 #define REG_TRIG_CTRL__4 0x0538
626
627 #define TRIG_CASCADE_ENABLE BIT(31)
628 #define TRIG_CASCADE_TAIL BIT(30)
629 #define TRIG_CASCADE_UPS_M 0xF
630 #define TRIG_CASCADE_UPS_S 26
631 #define TRIG_NOW BIT(25)
632 #define TRIG_NOTIFY BIT(24)
633 #define TRIG_EDGE BIT(23)
634 #define TRIG_PATTERN_S 20
635 #define TRIG_PATTERN_M 0x7
636 #define TRIG_NEG_EDGE 0
637 #define TRIG_POS_EDGE 1
638 #define TRIG_NEG_PULSE 2
639 #define TRIG_POS_PULSE 3
640 #define TRIG_NEG_PERIOD 4
641 #define TRIG_POS_PERIOD 5
642 #define TRIG_REG_OUTPUT 6
643 #define TRIG_GPO_S 16
644 #define TRIG_GPO_M 0xF
645 #define TRIG_CASCADE_ITERATE_CNT_M 0xFFFF
646
647 #define REG_TRIG_CYCLE_WIDTH 0x053C
648
649 #define REG_TRIG_CYCLE_CNT 0x0540
650
651 #define TRIG_CYCLE_CNT_M 0xFFFF
652 #define TRIG_CYCLE_CNT_S 16
653 #define TRIG_BIT_PATTERN_M 0xFFFF
654
655 #define REG_TRIG_ITERATE_TIME 0x0544
656
657 #define REG_TRIG_PULSE_WIDTH__4 0x0548
658
659 #define TRIG_PULSE_WIDTH_M 0x00FFFFFF
660
661 #define REG_TS_CTRL_STAT__4 0x0550
662
663 #define TS_EVENT_DETECT_M 0xF
664 #define TS_EVENT_DETECT_S 17
665 #define TS_EVENT_OVERFLOW BIT(16)
666 #define TS_GPI_M 0xF
667 #define TS_GPI_S 8
668 #define TS_DETECT_RISE BIT(7)
669 #define TS_DETECT_FALL BIT(6)
670 #define TS_DETECT_S 6
671 #define TS_CASCADE_TAIL BIT(5)
672 #define TS_CASCADE_UPS_M 0xF
673 #define TS_CASCADE_UPS_S 1
674 #define TS_CASCADE_ENABLE BIT(0)
675
676 #define DETECT_RISE (TS_DETECT_RISE >> TS_DETECT_S)
677 #define DETECT_FALL (TS_DETECT_FALL >> TS_DETECT_S)
678
679 #define REG_TS_EVENT_0_NANOSEC 0x0554
680 #define REG_TS_EVENT_0_SEC 0x0558
681 #define REG_TS_EVENT_0_SUB_NANOSEC 0x055C
682
683 #define REG_TS_EVENT_1_NANOSEC 0x0560
684 #define REG_TS_EVENT_1_SEC 0x0564
685 #define REG_TS_EVENT_1_SUB_NANOSEC 0x0568
686
687 #define REG_TS_EVENT_2_NANOSEC 0x056C
688 #define REG_TS_EVENT_2_SEC 0x0570
689 #define REG_TS_EVENT_2_SUB_NANOSEC 0x0574
690
691 #define REG_TS_EVENT_3_NANOSEC 0x0578
692 #define REG_TS_EVENT_3_SEC 0x057C
693 #define REG_TS_EVENT_3_SUB_NANOSEC 0x0580
694
695 #define REG_TS_EVENT_4_NANOSEC 0x0584
696 #define REG_TS_EVENT_4_SEC 0x0588
697 #define REG_TS_EVENT_4_SUB_NANOSEC 0x058C
698
699 #define REG_TS_EVENT_5_NANOSEC 0x0590
700 #define REG_TS_EVENT_5_SEC 0x0594
701 #define REG_TS_EVENT_5_SUB_NANOSEC 0x0598
702
703 #define REG_TS_EVENT_6_NANOSEC 0x059C
704 #define REG_TS_EVENT_6_SEC 0x05A0
705 #define REG_TS_EVENT_6_SUB_NANOSEC 0x05A4
706
707 #define REG_TS_EVENT_7_NANOSEC 0x05A8
708 #define REG_TS_EVENT_7_SEC 0x05AC
709 #define REG_TS_EVENT_7_SUB_NANOSEC 0x05B0
710
711 #define TS_EVENT_EDGE_M 0x1
712 #define TS_EVENT_EDGE_S 30
713 #define TS_EVENT_NANOSEC_M (BIT(30) - 1)
714
715 #define TS_EVENT_SUB_NANOSEC_M 0x7
716
717 #define TS_EVENT_SAMPLE \
718 (REG_TS_EVENT_1_NANOSEC - REG_TS_EVENT_0_NANOSEC)
719
720 #define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
721
722 #define REG_GLOBAL_RR_INDEX__1 0x0600
723
724
725 #define REG_DLR_SRC_PORT__4 0x0604
726
727 #define DLR_SRC_PORT_UNICAST BIT(31)
728 #define DLR_SRC_PORT_M 0x3
729 #define DLR_SRC_PORT_BOTH 0
730 #define DLR_SRC_PORT_EACH 1
731
732 #define REG_DLR_IP_ADDR__4 0x0608
733
734 #define REG_DLR_CTRL__1 0x0610
735
736 #define DLR_RESET_SEQ_ID BIT(3)
737 #define DLR_BACKUP_AUTO_ON BIT(2)
738 #define DLR_BEACON_TX_ENABLE BIT(1)
739 #define DLR_ASSIST_ENABLE BIT(0)
740
741 #define REG_DLR_STATE__1 0x0611
742
743 #define DLR_NODE_STATE_M 0x3
744 #define DLR_NODE_STATE_S 1
745 #define DLR_NODE_STATE_IDLE 0
746 #define DLR_NODE_STATE_FAULT 1
747 #define DLR_NODE_STATE_NORMAL 2
748 #define DLR_RING_STATE_FAULT 0
749 #define DLR_RING_STATE_NORMAL 1
750
751 #define REG_DLR_PRECEDENCE__1 0x0612
752
753 #define REG_DLR_BEACON_INTERVAL__4 0x0614
754
755 #define REG_DLR_BEACON_TIMEOUT__4 0x0618
756
757 #define REG_DLR_TIMEOUT_WINDOW__4 0x061C
758
759 #define DLR_TIMEOUT_WINDOW_M (BIT(22) - 1)
760
761 #define REG_DLR_VLAN_ID__2 0x0620
762
763 #define DLR_VLAN_ID_M (BIT(12) - 1)
764
765 #define REG_DLR_DEST_ADDR_0 0x0622
766 #define REG_DLR_DEST_ADDR_1 0x0623
767 #define REG_DLR_DEST_ADDR_2 0x0624
768 #define REG_DLR_DEST_ADDR_3 0x0625
769 #define REG_DLR_DEST_ADDR_4 0x0626
770 #define REG_DLR_DEST_ADDR_5 0x0627
771
772 #define REG_DLR_PORT_MAP__4 0x0628
773
774 #define REG_DLR_CLASS__1 0x062C
775
776 #define DLR_FRAME_QID_M 0x3
777
778
779 #define REG_HSR_PORT_MAP__4 0x0640
780
781 #define REG_HSR_ALU_CTRL_0__1 0x0644
782
783 #define HSR_DUPLICATE_DISCARD BIT(7)
784 #define HSR_NODE_UNICAST BIT(6)
785 #define HSR_AGE_CNT_DEFAULT_M 0x7
786 #define HSR_AGE_CNT_DEFAULT_S 3
787 #define HSR_LEARN_MCAST_DISABLE BIT(2)
788 #define HSR_HASH_OPTION_M 0x3
789 #define HSR_HASH_DISABLE 0
790 #define HSR_HASH_UPPER_BITS 1
791 #define HSR_HASH_LOWER_BITS 2
792 #define HSR_HASH_XOR_BOTH_BITS 3
793
794 #define REG_HSR_ALU_CTRL_1__1 0x0645
795
796 #define HSR_LEARN_UCAST_DISABLE BIT(7)
797 #define HSR_FLUSH_TABLE BIT(5)
798 #define HSR_PROC_MCAST_SRC BIT(3)
799 #define HSR_AGING_ENABLE BIT(2)
800
801 #define REG_HSR_ALU_CTRL_2__2 0x0646
802
803 #define REG_HSR_ALU_AGE_PERIOD__4 0x0648
804
805 #define REG_HSR_ALU_INT_STATUS__1 0x064C
806 #define REG_HSR_ALU_INT_MASK__1 0x064D
807
808 #define HSR_WINDOW_OVERFLOW_INT BIT(3)
809 #define HSR_LEARN_FAIL_INT BIT(2)
810 #define HSR_ALMOST_FULL_INT BIT(1)
811 #define HSR_WRITE_FAIL_INT BIT(0)
812
813 #define REG_HSR_ALU_ENTRY_0__2 0x0650
814
815 #define HSR_ENTRY_INDEX_M (BIT(10) - 1)
816 #define HSR_FAIL_INDEX_M (BIT(8) - 1)
817
818 #define REG_HSR_ALU_ENTRY_1__2 0x0652
819
820 #define HSR_FAIL_LEARN_INDEX_M (BIT(8) - 1)
821
822 #define REG_HSR_ALU_ENTRY_3__2 0x0654
823
824 #define HSR_CPU_ACCESS_ENTRY_INDEX_M (BIT(8) - 1)
825
826
827 #define REG_PORT_DEFAULT_VID 0x0000
828
829 #define REG_PORT_CUSTOM_VID 0x0002
830 #define REG_PORT_AVB_SR_1_VID 0x0004
831 #define REG_PORT_AVB_SR_2_VID 0x0006
832
833 #define REG_PORT_AVB_SR_1_TYPE 0x0008
834 #define REG_PORT_AVB_SR_2_TYPE 0x000A
835
836 #define REG_PORT_PME_STATUS 0x0013
837 #define REG_PORT_PME_CTRL 0x0017
838
839 #define PME_WOL_MAGICPKT BIT(2)
840 #define PME_WOL_LINKUP BIT(1)
841 #define PME_WOL_ENERGY BIT(0)
842
843 #define REG_PORT_INT_STATUS 0x001B
844 #define REG_PORT_INT_MASK 0x001F
845
846 #define PORT_SGMII_INT BIT(3)
847 #define PORT_PTP_INT BIT(2)
848 #define PORT_PHY_INT BIT(1)
849 #define PORT_ACL_INT BIT(0)
850
851 #define PORT_INT_MASK \
852 (PORT_SGMII_INT | PORT_PTP_INT | PORT_PHY_INT | PORT_ACL_INT)
853
854 #define REG_PORT_CTRL_0 0x0020
855
856 #define PORT_MAC_LOOPBACK BIT(7)
857 #define PORT_FORCE_TX_FLOW_CTRL BIT(4)
858 #define PORT_FORCE_RX_FLOW_CTRL BIT(3)
859 #define PORT_TAIL_TAG_ENABLE BIT(2)
860 #define PORT_QUEUE_SPLIT_ENABLE 0x3
861
862 #define REG_PORT_CTRL_1 0x0021
863
864 #define PORT_SRP_ENABLE 0x3
865
866 #define REG_PORT_STATUS_0 0x0030
867
868 #define PORT_INTF_SPEED_M 0x3
869 #define PORT_INTF_SPEED_S 3
870 #define PORT_INTF_FULL_DUPLEX BIT(2)
871 #define PORT_TX_FLOW_CTRL BIT(1)
872 #define PORT_RX_FLOW_CTRL BIT(0)
873
874 #define REG_PORT_STATUS_1 0x0034
875
876
877 #define REG_PORT_PHY_CTRL 0x0100
878
879 #define PORT_PHY_RESET BIT(15)
880 #define PORT_PHY_LOOPBACK BIT(14)
881 #define PORT_SPEED_100MBIT BIT(13)
882 #define PORT_AUTO_NEG_ENABLE BIT(12)
883 #define PORT_POWER_DOWN BIT(11)
884 #define PORT_ISOLATE BIT(10)
885 #define PORT_AUTO_NEG_RESTART BIT(9)
886 #define PORT_FULL_DUPLEX BIT(8)
887 #define PORT_COLLISION_TEST BIT(7)
888 #define PORT_SPEED_1000MBIT BIT(6)
889
890 #define REG_PORT_PHY_STATUS 0x0102
891
892 #define PORT_100BT4_CAPABLE BIT(15)
893 #define PORT_100BTX_FD_CAPABLE BIT(14)
894 #define PORT_100BTX_CAPABLE BIT(13)
895 #define PORT_10BT_FD_CAPABLE BIT(12)
896 #define PORT_10BT_CAPABLE BIT(11)
897 #define PORT_EXTENDED_STATUS BIT(8)
898 #define PORT_MII_SUPPRESS_CAPABLE BIT(6)
899 #define PORT_AUTO_NEG_ACKNOWLEDGE BIT(5)
900 #define PORT_REMOTE_FAULT BIT(4)
901 #define PORT_AUTO_NEG_CAPABLE BIT(3)
902 #define PORT_LINK_STATUS BIT(2)
903 #define PORT_JABBER_DETECT BIT(1)
904 #define PORT_EXTENDED_CAPABILITY BIT(0)
905
906 #define REG_PORT_PHY_ID_HI 0x0104
907 #define REG_PORT_PHY_ID_LO 0x0106
908
909 #define KSZ9477_ID_HI 0x0022
910 #define KSZ9477_ID_LO 0x1622
911
912 #define REG_PORT_PHY_AUTO_NEGOTIATION 0x0108
913
914 #define PORT_AUTO_NEG_NEXT_PAGE BIT(15)
915 #define PORT_AUTO_NEG_REMOTE_FAULT BIT(13)
916 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(11)
917 #define PORT_AUTO_NEG_SYM_PAUSE BIT(10)
918 #define PORT_AUTO_NEG_100BT4 BIT(9)
919 #define PORT_AUTO_NEG_100BTX_FD BIT(8)
920 #define PORT_AUTO_NEG_100BTX BIT(7)
921 #define PORT_AUTO_NEG_10BT_FD BIT(6)
922 #define PORT_AUTO_NEG_10BT BIT(5)
923 #define PORT_AUTO_NEG_SELECTOR 0x001F
924 #define PORT_AUTO_NEG_802_3 0x0001
925
926 #define PORT_AUTO_NEG_PAUSE \
927 (PORT_AUTO_NEG_ASYM_PAUSE | PORT_AUTO_NEG_SYM_PAUSE)
928
929 #define REG_PORT_PHY_REMOTE_CAPABILITY 0x010A
930
931 #define PORT_REMOTE_NEXT_PAGE BIT(15)
932 #define PORT_REMOTE_ACKNOWLEDGE BIT(14)
933 #define PORT_REMOTE_REMOTE_FAULT BIT(13)
934 #define PORT_REMOTE_ASYM_PAUSE BIT(11)
935 #define PORT_REMOTE_SYM_PAUSE BIT(10)
936 #define PORT_REMOTE_100BTX_FD BIT(8)
937 #define PORT_REMOTE_100BTX BIT(7)
938 #define PORT_REMOTE_10BT_FD BIT(6)
939 #define PORT_REMOTE_10BT BIT(5)
940
941 #define REG_PORT_PHY_1000_CTRL 0x0112
942
943 #define PORT_AUTO_NEG_MANUAL BIT(12)
944 #define PORT_AUTO_NEG_MASTER BIT(11)
945 #define PORT_AUTO_NEG_MASTER_PREFERRED BIT(10)
946 #define PORT_AUTO_NEG_1000BT_FD BIT(9)
947 #define PORT_AUTO_NEG_1000BT BIT(8)
948
949 #define REG_PORT_PHY_1000_STATUS 0x0114
950
951 #define PORT_MASTER_FAULT BIT(15)
952 #define PORT_LOCAL_MASTER BIT(14)
953 #define PORT_LOCAL_RX_OK BIT(13)
954 #define PORT_REMOTE_RX_OK BIT(12)
955 #define PORT_REMOTE_1000BT_FD BIT(11)
956 #define PORT_REMOTE_1000BT BIT(10)
957 #define PORT_REMOTE_IDLE_CNT_M 0x0F
958
959 #define PORT_PHY_1000_STATIC_STATUS \
960 (PORT_LOCAL_RX_OK | \
961 PORT_REMOTE_RX_OK | \
962 PORT_REMOTE_1000BT_FD | \
963 PORT_REMOTE_1000BT)
964
965 #define REG_PORT_PHY_MMD_SETUP 0x011A
966
967 #define PORT_MMD_OP_MODE_M 0x3
968 #define PORT_MMD_OP_MODE_S 14
969 #define PORT_MMD_OP_INDEX 0
970 #define PORT_MMD_OP_DATA_NO_INCR 1
971 #define PORT_MMD_OP_DATA_INCR_RW 2
972 #define PORT_MMD_OP_DATA_INCR_W 3
973 #define PORT_MMD_DEVICE_ID_M 0x1F
974
975 #define MMD_SETUP(mode, dev) \
976 (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev))
977
978 #define REG_PORT_PHY_MMD_INDEX_DATA 0x011C
979
980 #define MMD_DEVICE_ID_DSP 1
981
982 #define MMD_DSP_SQI_CHAN_A 0xAC
983 #define MMD_DSP_SQI_CHAN_B 0xAD
984 #define MMD_DSP_SQI_CHAN_C 0xAE
985 #define MMD_DSP_SQI_CHAN_D 0xAF
986
987 #define DSP_SQI_ERR_DETECTED BIT(15)
988 #define DSP_SQI_AVG_ERR 0x7FFF
989
990 #define MMD_DEVICE_ID_COMMON 2
991
992 #define MMD_DEVICE_ID_EEE_ADV 7
993
994 #define MMD_EEE_ADV 0x3C
995 #define EEE_ADV_100MBIT BIT(1)
996 #define EEE_ADV_1GBIT BIT(2)
997
998 #define MMD_EEE_LP_ADV 0x3D
999 #define MMD_EEE_MSG_CODE 0x3F
1000
1001 #define MMD_DEVICE_ID_AFED 0x1C
1002
1003 #define REG_PORT_PHY_EXTENDED_STATUS 0x011E
1004
1005 #define PORT_100BTX_FD_ABLE BIT(15)
1006 #define PORT_100BTX_ABLE BIT(14)
1007 #define PORT_10BT_FD_ABLE BIT(13)
1008 #define PORT_10BT_ABLE BIT(12)
1009
1010 #define REG_PORT_SGMII_ADDR__4 0x0200
1011 #define PORT_SGMII_AUTO_INCR BIT(23)
1012 #define PORT_SGMII_DEVICE_ID_M 0x1F
1013 #define PORT_SGMII_DEVICE_ID_S 16
1014 #define PORT_SGMII_ADDR_M (BIT(21) - 1)
1015
1016 #define REG_PORT_SGMII_DATA__4 0x0204
1017 #define PORT_SGMII_DATA_M (BIT(16) - 1)
1018
1019 #define MMD_DEVICE_ID_PMA 0x01
1020 #define MMD_DEVICE_ID_PCS 0x03
1021 #define MMD_DEVICE_ID_PHY_XS 0x04
1022 #define MMD_DEVICE_ID_DTE_XS 0x05
1023 #define MMD_DEVICE_ID_AN 0x07
1024 #define MMD_DEVICE_ID_VENDOR_CTRL 0x1E
1025 #define MMD_DEVICE_ID_VENDOR_MII 0x1F
1026
1027 #define SR_MII MMD_DEVICE_ID_VENDOR_MII
1028
1029 #define MMD_SR_MII_CTRL 0x0000
1030
1031 #define SR_MII_RESET BIT(15)
1032 #define SR_MII_LOOPBACK BIT(14)
1033 #define SR_MII_SPEED_100MBIT BIT(13)
1034 #define SR_MII_AUTO_NEG_ENABLE BIT(12)
1035 #define SR_MII_POWER_DOWN BIT(11)
1036 #define SR_MII_AUTO_NEG_RESTART BIT(9)
1037 #define SR_MII_FULL_DUPLEX BIT(8)
1038 #define SR_MII_SPEED_1000MBIT BIT(6)
1039
1040 #define MMD_SR_MII_STATUS 0x0001
1041 #define MMD_SR_MII_ID_1 0x0002
1042 #define MMD_SR_MII_ID_2 0x0003
1043 #define MMD_SR_MII_AUTO_NEGOTIATION 0x0004
1044
1045 #define SR_MII_AUTO_NEG_NEXT_PAGE BIT(15)
1046 #define SR_MII_AUTO_NEG_REMOTE_FAULT_M 0x3
1047 #define SR_MII_AUTO_NEG_REMOTE_FAULT_S 12
1048 #define SR_MII_AUTO_NEG_NO_ERROR 0
1049 #define SR_MII_AUTO_NEG_OFFLINE 1
1050 #define SR_MII_AUTO_NEG_LINK_FAILURE 2
1051 #define SR_MII_AUTO_NEG_ERROR 3
1052 #define SR_MII_AUTO_NEG_PAUSE_M 0x3
1053 #define SR_MII_AUTO_NEG_PAUSE_S 7
1054 #define SR_MII_AUTO_NEG_NO_PAUSE 0
1055 #define SR_MII_AUTO_NEG_ASYM_PAUSE_TX 1
1056 #define SR_MII_AUTO_NEG_SYM_PAUSE 2
1057 #define SR_MII_AUTO_NEG_ASYM_PAUSE_RX 3
1058 #define SR_MII_AUTO_NEG_HALF_DUPLEX BIT(6)
1059 #define SR_MII_AUTO_NEG_FULL_DUPLEX BIT(5)
1060
1061 #define MMD_SR_MII_REMOTE_CAPABILITY 0x0005
1062 #define MMD_SR_MII_AUTO_NEG_EXP 0x0006
1063 #define MMD_SR_MII_AUTO_NEG_EXT 0x000F
1064
1065 #define MMD_SR_MII_DIGITAL_CTRL_1 0x8000
1066
1067 #define MMD_SR_MII_AUTO_NEG_CTRL 0x8001
1068
1069 #define SR_MII_8_BIT BIT(8)
1070 #define SR_MII_SGMII_LINK_UP BIT(4)
1071 #define SR_MII_TX_CFG_PHY_MASTER BIT(3)
1072 #define SR_MII_PCS_MODE_M 0x3
1073 #define SR_MII_PCS_MODE_S 1
1074 #define SR_MII_PCS_SGMII 2
1075 #define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0)
1076
1077 #define MMD_SR_MII_AUTO_NEG_STATUS 0x8002
1078
1079 #define SR_MII_STAT_LINK_UP BIT(4)
1080 #define SR_MII_STAT_M 0x3
1081 #define SR_MII_STAT_S 2
1082 #define SR_MII_STAT_10_MBPS 0
1083 #define SR_MII_STAT_100_MBPS 1
1084 #define SR_MII_STAT_1000_MBPS 2
1085 #define SR_MII_STAT_FULL_DUPLEX BIT(1)
1086
1087 #define MMD_SR_MII_PHY_CTRL 0x80A0
1088
1089 #define SR_MII_PHY_LANE_SEL_M 0xF
1090 #define SR_MII_PHY_LANE_SEL_S 8
1091 #define SR_MII_PHY_WRITE BIT(1)
1092 #define SR_MII_PHY_START_BUSY BIT(0)
1093
1094 #define MMD_SR_MII_PHY_ADDR 0x80A1
1095
1096 #define SR_MII_PHY_ADDR_M (BIT(16) - 1)
1097
1098 #define MMD_SR_MII_PHY_DATA 0x80A2
1099
1100 #define SR_MII_PHY_DATA_M (BIT(16) - 1)
1101
1102 #define SR_MII_PHY_JTAG_CHIP_ID_HI 0x000C
1103 #define SR_MII_PHY_JTAG_CHIP_ID_LO 0x000D
1104
1105 #define REG_PORT_PHY_REMOTE_LB_LED 0x0122
1106
1107 #define PORT_REMOTE_LOOPBACK BIT(8)
1108 #define PORT_LED_SELECT (3 << 6)
1109 #define PORT_LED_CTRL (3 << 4)
1110 #define PORT_LED_CTRL_TEST BIT(3)
1111 #define PORT_10BT_PREAMBLE BIT(2)
1112 #define PORT_LINK_MD_10BT_ENABLE BIT(1)
1113 #define PORT_LINK_MD_PASS BIT(0)
1114
1115 #define REG_PORT_PHY_LINK_MD 0x0124
1116
1117 #define PORT_START_CABLE_DIAG BIT(15)
1118 #define PORT_TX_DISABLE BIT(14)
1119 #define PORT_CABLE_DIAG_PAIR_M 0x3
1120 #define PORT_CABLE_DIAG_PAIR_S 12
1121 #define PORT_CABLE_DIAG_SELECT_M 0x3
1122 #define PORT_CABLE_DIAG_SELECT_S 10
1123 #define PORT_CABLE_DIAG_RESULT_M 0x3
1124 #define PORT_CABLE_DIAG_RESULT_S 8
1125 #define PORT_CABLE_STAT_NORMAL 0
1126 #define PORT_CABLE_STAT_OPEN 1
1127 #define PORT_CABLE_STAT_SHORT 2
1128 #define PORT_CABLE_STAT_FAILED 3
1129 #define PORT_CABLE_FAULT_COUNTER 0x00FF
1130
1131 #define REG_PORT_PHY_PMA_STATUS 0x0126
1132
1133 #define PORT_1000_LINK_GOOD BIT(1)
1134 #define PORT_100_LINK_GOOD BIT(0)
1135
1136 #define REG_PORT_PHY_DIGITAL_STATUS 0x0128
1137
1138 #define PORT_LINK_DETECT BIT(14)
1139 #define PORT_SIGNAL_DETECT BIT(13)
1140 #define PORT_PHY_STAT_MDI BIT(12)
1141 #define PORT_PHY_STAT_MASTER BIT(11)
1142
1143 #define REG_PORT_PHY_RXER_COUNTER 0x012A
1144
1145 #define REG_PORT_PHY_INT_ENABLE 0x0136
1146 #define REG_PORT_PHY_INT_STATUS 0x0137
1147
1148 #define JABBER_INT BIT(7)
1149 #define RX_ERR_INT BIT(6)
1150 #define PAGE_RX_INT BIT(5)
1151 #define PARALLEL_DETECT_FAULT_INT BIT(4)
1152 #define LINK_PARTNER_ACK_INT BIT(3)
1153 #define LINK_DOWN_INT BIT(2)
1154 #define REMOTE_FAULT_INT BIT(1)
1155 #define LINK_UP_INT BIT(0)
1156
1157 #define REG_PORT_PHY_DIGITAL_DEBUG_1 0x0138
1158
1159 #define PORT_REG_CLK_SPEED_25_MHZ BIT(14)
1160 #define PORT_PHY_FORCE_MDI BIT(7)
1161 #define PORT_PHY_AUTO_MDIX_DISABLE BIT(6)
1162
1163
1164 #define PORT_PHY_PCS_LOOPBACK BIT(0)
1165
1166 #define REG_PORT_PHY_DIGITAL_DEBUG_2 0x013A
1167
1168 #define REG_PORT_PHY_DIGITAL_DEBUG_3 0x013C
1169
1170 #define PORT_100BT_FIXED_LATENCY BIT(15)
1171
1172 #define REG_PORT_PHY_PHY_CTRL 0x013E
1173
1174 #define PORT_INT_PIN_HIGH BIT(14)
1175 #define PORT_ENABLE_JABBER BIT(9)
1176 #define PORT_STAT_SPEED_1000MBIT BIT(6)
1177 #define PORT_STAT_SPEED_100MBIT BIT(5)
1178 #define PORT_STAT_SPEED_10MBIT BIT(4)
1179 #define PORT_STAT_FULL_DUPLEX BIT(3)
1180
1181
1182 #define PORT_STAT_MASTER BIT(2)
1183 #define PORT_RESET BIT(1)
1184 #define PORT_LINK_STATUS_FAIL BIT(0)
1185
1186
1187 #define REG_PORT_XMII_CTRL_0 0x0300
1188
1189 #define PORT_SGMII_SEL BIT(7)
1190 #define PORT_MII_FULL_DUPLEX BIT(6)
1191 #define PORT_MII_100MBIT BIT(4)
1192 #define PORT_GRXC_ENABLE BIT(0)
1193
1194 #define REG_PORT_XMII_CTRL_1 0x0301
1195
1196 #define PORT_RMII_CLK_SEL BIT(7)
1197
1198 #define PORT_MII_1000MBIT_S1 BIT(6)
1199
1200 #define PORT_MII_NOT_1GBIT BIT(6)
1201 #define PORT_MII_SEL_EDGE BIT(5)
1202 #define PORT_RGMII_ID_IG_ENABLE BIT(4)
1203 #define PORT_RGMII_ID_EG_ENABLE BIT(3)
1204 #define PORT_MII_MAC_MODE BIT(2)
1205 #define PORT_MII_SEL_M 0x3
1206
1207 #define PORT_MII_SEL_S1 0x0
1208 #define PORT_RMII_SEL_S1 0x1
1209 #define PORT_GMII_SEL_S1 0x2
1210 #define PORT_RGMII_SEL_S1 0x3
1211
1212 #define PORT_RGMII_SEL 0x0
1213 #define PORT_RMII_SEL 0x1
1214 #define PORT_GMII_SEL 0x2
1215 #define PORT_MII_SEL 0x3
1216
1217
1218 #define REG_PORT_MAC_CTRL_0 0x0400
1219
1220 #define PORT_BROADCAST_STORM BIT(1)
1221 #define PORT_JUMBO_FRAME BIT(0)
1222
1223 #define REG_PORT_MAC_CTRL_1 0x0401
1224
1225 #define PORT_BACK_PRESSURE BIT(3)
1226 #define PORT_PASS_ALL BIT(0)
1227
1228 #define REG_PORT_MAC_CTRL_2 0x0402
1229
1230 #define PORT_100BT_EEE_DISABLE BIT(7)
1231 #define PORT_1000BT_EEE_DISABLE BIT(6)
1232
1233 #define REG_PORT_MAC_IN_RATE_LIMIT 0x0403
1234
1235 #define PORT_IN_PORT_BASED_S 6
1236 #define PORT_RATE_PACKET_BASED_S 5
1237 #define PORT_IN_FLOW_CTRL_S 4
1238 #define PORT_COUNT_IFG_S 1
1239 #define PORT_COUNT_PREAMBLE_S 0
1240 #define PORT_IN_PORT_BASED BIT(6)
1241 #define PORT_IN_PACKET_BASED BIT(5)
1242 #define PORT_IN_FLOW_CTRL BIT(4)
1243 #define PORT_IN_LIMIT_MODE_M 0x3
1244 #define PORT_IN_LIMIT_MODE_S 2
1245 #define PORT_IN_ALL 0
1246 #define PORT_IN_UNICAST 1
1247 #define PORT_IN_MULTICAST 2
1248 #define PORT_IN_BROADCAST 3
1249 #define PORT_COUNT_IFG BIT(1)
1250 #define PORT_COUNT_PREAMBLE BIT(0)
1251
1252 #define REG_PORT_IN_RATE_0 0x0410
1253 #define REG_PORT_IN_RATE_1 0x0411
1254 #define REG_PORT_IN_RATE_2 0x0412
1255 #define REG_PORT_IN_RATE_3 0x0413
1256 #define REG_PORT_IN_RATE_4 0x0414
1257 #define REG_PORT_IN_RATE_5 0x0415
1258 #define REG_PORT_IN_RATE_6 0x0416
1259 #define REG_PORT_IN_RATE_7 0x0417
1260
1261 #define REG_PORT_OUT_RATE_0 0x0420
1262 #define REG_PORT_OUT_RATE_1 0x0421
1263 #define REG_PORT_OUT_RATE_2 0x0422
1264 #define REG_PORT_OUT_RATE_3 0x0423
1265
1266 #define PORT_RATE_LIMIT_M (BIT(7) - 1)
1267
1268
1269 #define REG_PORT_MIB_CTRL_STAT__4 0x0500
1270
1271 #define MIB_COUNTER_OVERFLOW BIT(31)
1272 #define MIB_COUNTER_VALID BIT(30)
1273 #define MIB_COUNTER_READ BIT(25)
1274 #define MIB_COUNTER_FLUSH_FREEZE BIT(24)
1275 #define MIB_COUNTER_INDEX_M (BIT(8) - 1)
1276 #define MIB_COUNTER_INDEX_S 16
1277 #define MIB_COUNTER_DATA_HI_M 0xF
1278
1279 #define REG_PORT_MIB_DATA 0x0504
1280
1281
1282 #define REG_PORT_ACL_0 0x0600
1283
1284 #define ACL_FIRST_RULE_M 0xF
1285
1286 #define REG_PORT_ACL_1 0x0601
1287
1288 #define ACL_MODE_M 0x3
1289 #define ACL_MODE_S 4
1290 #define ACL_MODE_DISABLE 0
1291 #define ACL_MODE_LAYER_2 1
1292 #define ACL_MODE_LAYER_3 2
1293 #define ACL_MODE_LAYER_4 3
1294 #define ACL_ENABLE_M 0x3
1295 #define ACL_ENABLE_S 2
1296 #define ACL_ENABLE_2_COUNT 0
1297 #define ACL_ENABLE_2_TYPE 1
1298 #define ACL_ENABLE_2_MAC 2
1299 #define ACL_ENABLE_2_BOTH 3
1300 #define ACL_ENABLE_3_IP 1
1301 #define ACL_ENABLE_3_SRC_DST_COMP 2
1302 #define ACL_ENABLE_4_PROTOCOL 0
1303 #define ACL_ENABLE_4_TCP_PORT_COMP 1
1304 #define ACL_ENABLE_4_UDP_PORT_COMP 2
1305 #define ACL_ENABLE_4_TCP_SEQN_COMP 3
1306 #define ACL_SRC BIT(1)
1307 #define ACL_EQUAL BIT(0)
1308
1309 #define REG_PORT_ACL_2 0x0602
1310 #define REG_PORT_ACL_3 0x0603
1311
1312 #define ACL_MAX_PORT 0xFFFF
1313
1314 #define REG_PORT_ACL_4 0x0604
1315 #define REG_PORT_ACL_5 0x0605
1316
1317 #define ACL_MIN_PORT 0xFFFF
1318 #define ACL_IP_ADDR 0xFFFFFFFF
1319 #define ACL_TCP_SEQNUM 0xFFFFFFFF
1320
1321 #define REG_PORT_ACL_6 0x0606
1322
1323 #define ACL_RESERVED 0xF8
1324 #define ACL_PORT_MODE_M 0x3
1325 #define ACL_PORT_MODE_S 1
1326 #define ACL_PORT_MODE_DISABLE 0
1327 #define ACL_PORT_MODE_EITHER 1
1328 #define ACL_PORT_MODE_IN_RANGE 2
1329 #define ACL_PORT_MODE_OUT_OF_RANGE 3
1330
1331 #define REG_PORT_ACL_7 0x0607
1332
1333 #define ACL_TCP_FLAG_ENABLE BIT(0)
1334
1335 #define REG_PORT_ACL_8 0x0608
1336
1337 #define ACL_TCP_FLAG_M 0xFF
1338
1339 #define REG_PORT_ACL_9 0x0609
1340
1341 #define ACL_TCP_FLAG 0xFF
1342 #define ACL_ETH_TYPE 0xFFFF
1343 #define ACL_IP_M 0xFFFFFFFF
1344
1345 #define REG_PORT_ACL_A 0x060A
1346
1347 #define ACL_PRIO_MODE_M 0x3
1348 #define ACL_PRIO_MODE_S 6
1349 #define ACL_PRIO_MODE_DISABLE 0
1350 #define ACL_PRIO_MODE_HIGHER 1
1351 #define ACL_PRIO_MODE_LOWER 2
1352 #define ACL_PRIO_MODE_REPLACE 3
1353 #define ACL_PRIO_M KS_PRIO_M
1354 #define ACL_PRIO_S 3
1355 #define ACL_VLAN_PRIO_REPLACE BIT(2)
1356 #define ACL_VLAN_PRIO_M KS_PRIO_M
1357 #define ACL_VLAN_PRIO_HI_M 0x3
1358
1359 #define REG_PORT_ACL_B 0x060B
1360
1361 #define ACL_VLAN_PRIO_LO_M 0x8
1362 #define ACL_VLAN_PRIO_S 7
1363 #define ACL_MAP_MODE_M 0x3
1364 #define ACL_MAP_MODE_S 5
1365 #define ACL_MAP_MODE_DISABLE 0
1366 #define ACL_MAP_MODE_OR 1
1367 #define ACL_MAP_MODE_AND 2
1368 #define ACL_MAP_MODE_REPLACE 3
1369
1370 #define ACL_CNT_M (BIT(11) - 1)
1371 #define ACL_CNT_S 5
1372
1373 #define REG_PORT_ACL_C 0x060C
1374
1375 #define REG_PORT_ACL_D 0x060D
1376 #define ACL_MSEC_UNIT BIT(6)
1377 #define ACL_INTR_MODE BIT(5)
1378 #define ACL_PORT_MAP 0x7F
1379
1380 #define REG_PORT_ACL_E 0x060E
1381 #define REG_PORT_ACL_F 0x060F
1382
1383 #define REG_PORT_ACL_BYTE_EN_MSB 0x0610
1384 #define REG_PORT_ACL_BYTE_EN_LSB 0x0611
1385
1386 #define ACL_ACTION_START 0xA
1387 #define ACL_ACTION_LEN 4
1388 #define ACL_INTR_CNT_START 0xD
1389 #define ACL_RULESET_START 0xE
1390 #define ACL_RULESET_LEN 2
1391 #define ACL_TABLE_LEN 16
1392
1393 #define ACL_ACTION_ENABLE 0x003C
1394 #define ACL_MATCH_ENABLE 0x7FC3
1395 #define ACL_RULESET_ENABLE 0x8003
1396 #define ACL_BYTE_ENABLE 0xFFFF
1397
1398 #define REG_PORT_ACL_CTRL_0 0x0612
1399
1400 #define PORT_ACL_WRITE_DONE BIT(6)
1401 #define PORT_ACL_READ_DONE BIT(5)
1402 #define PORT_ACL_WRITE BIT(4)
1403 #define PORT_ACL_INDEX_M 0xF
1404
1405 #define REG_PORT_ACL_CTRL_1 0x0613
1406
1407
1408 #define REG_PORT_MRI_MIRROR_CTRL 0x0800
1409
1410 #define PORT_MIRROR_RX BIT(6)
1411 #define PORT_MIRROR_TX BIT(5)
1412 #define PORT_MIRROR_SNIFFER BIT(1)
1413
1414 #define REG_PORT_MRI_PRIO_CTRL 0x0801
1415
1416 #define PORT_HIGHEST_PRIO BIT(7)
1417 #define PORT_OR_PRIO BIT(6)
1418 #define PORT_MAC_PRIO_ENABLE BIT(4)
1419 #define PORT_VLAN_PRIO_ENABLE BIT(3)
1420 #define PORT_802_1P_PRIO_ENABLE BIT(2)
1421 #define PORT_DIFFSERV_PRIO_ENABLE BIT(1)
1422 #define PORT_ACL_PRIO_ENABLE BIT(0)
1423
1424 #define REG_PORT_MRI_MAC_CTRL 0x0802
1425
1426 #define PORT_USER_PRIO_CEILING BIT(7)
1427 #define PORT_DROP_NON_VLAN BIT(4)
1428 #define PORT_DROP_TAG BIT(3)
1429 #define PORT_BASED_PRIO_M KS_PRIO_M
1430 #define PORT_BASED_PRIO_S 0
1431
1432 #define REG_PORT_MRI_AUTHEN_CTRL 0x0803
1433
1434 #define PORT_ACL_ENABLE BIT(2)
1435 #define PORT_AUTHEN_MODE 0x3
1436 #define PORT_AUTHEN_PASS 0
1437 #define PORT_AUTHEN_BLOCK 1
1438 #define PORT_AUTHEN_TRAP 2
1439
1440 #define REG_PORT_MRI_INDEX__4 0x0804
1441
1442 #define MRI_INDEX_P_M 0x7
1443 #define MRI_INDEX_P_S 16
1444 #define MRI_INDEX_Q_M 0x3
1445 #define MRI_INDEX_Q_S 0
1446
1447 #define REG_PORT_MRI_TC_MAP__4 0x0808
1448
1449 #define PORT_TC_MAP_M 0xf
1450 #define PORT_TC_MAP_S 4
1451
1452 #define REG_PORT_MRI_POLICE_CTRL__4 0x080C
1453
1454 #define POLICE_DROP_ALL BIT(10)
1455 #define POLICE_PACKET_TYPE_M 0x3
1456 #define POLICE_PACKET_TYPE_S 8
1457 #define POLICE_PACKET_DROPPED 0
1458 #define POLICE_PACKET_GREEN 1
1459 #define POLICE_PACKET_YELLOW 2
1460 #define POLICE_PACKET_RED 3
1461 #define PORT_BASED_POLICING BIT(7)
1462 #define NON_DSCP_COLOR_M 0x3
1463 #define NON_DSCP_COLOR_S 5
1464 #define COLOR_MARK_ENABLE BIT(4)
1465 #define COLOR_REMAP_ENABLE BIT(3)
1466 #define POLICE_DROP_SRP BIT(2)
1467 #define POLICE_COLOR_NOT_AWARE BIT(1)
1468 #define POLICE_ENABLE BIT(0)
1469
1470 #define REG_PORT_POLICE_COLOR_0__4 0x0810
1471 #define REG_PORT_POLICE_COLOR_1__4 0x0814
1472 #define REG_PORT_POLICE_COLOR_2__4 0x0818
1473 #define REG_PORT_POLICE_COLOR_3__4 0x081C
1474
1475 #define POLICE_COLOR_MAP_S 2
1476 #define POLICE_COLOR_MAP_M (BIT(POLICE_COLOR_MAP_S) - 1)
1477
1478 #define REG_PORT_POLICE_RATE__4 0x0820
1479
1480 #define POLICE_CIR_S 16
1481 #define POLICE_PIR_S 0
1482
1483 #define REG_PORT_POLICE_BURST_SIZE__4 0x0824
1484
1485 #define POLICE_BURST_SIZE_M 0x3FFF
1486 #define POLICE_CBS_S 16
1487 #define POLICE_PBS_S 0
1488
1489 #define REG_PORT_WRED_PM_CTRL_0__4 0x0830
1490
1491 #define WRED_PM_CTRL_M (BIT(11) - 1)
1492
1493 #define WRED_PM_MAX_THRESHOLD_S 16
1494 #define WRED_PM_MIN_THRESHOLD_S 0
1495
1496 #define REG_PORT_WRED_PM_CTRL_1__4 0x0834
1497
1498 #define WRED_PM_MULTIPLIER_S 16
1499 #define WRED_PM_AVG_QUEUE_SIZE_S 0
1500
1501 #define REG_PORT_WRED_QUEUE_CTRL_0__4 0x0840
1502 #define REG_PORT_WRED_QUEUE_CTRL_1__4 0x0844
1503
1504 #define REG_PORT_WRED_QUEUE_PMON__4 0x0848
1505
1506 #define WRED_RANDOM_DROP_ENABLE BIT(31)
1507 #define WRED_PMON_FLUSH BIT(30)
1508 #define WRED_DROP_GYR_DISABLE BIT(29)
1509 #define WRED_DROP_YR_DISABLE BIT(28)
1510 #define WRED_DROP_R_DISABLE BIT(27)
1511 #define WRED_DROP_ALL BIT(26)
1512 #define WRED_PMON_M (BIT(24) - 1)
1513
1514
1515
1516 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900
1517
1518 #define REG_PORT_MTI_QUEUE_CTRL_0__4 0x0904
1519
1520 #define MTI_PVID_REPLACE BIT(0)
1521
1522 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914
1523
1524 #define MTI_SCHEDULE_MODE_M 0x3
1525 #define MTI_SCHEDULE_MODE_S 6
1526 #define MTI_SCHEDULE_STRICT_PRIO 0
1527 #define MTI_SCHEDULE_WRR 2
1528 #define MTI_SHAPING_M 0x3
1529 #define MTI_SHAPING_S 4
1530 #define MTI_SHAPING_OFF 0
1531 #define MTI_SHAPING_SRP 1
1532 #define MTI_SHAPING_TIME_AWARE 2
1533
1534 #define REG_PORT_MTI_QUEUE_CTRL_1 0x0915
1535
1536 #define MTI_TX_RATIO_M (BIT(7) - 1)
1537
1538 #define REG_PORT_MTI_QUEUE_CTRL_2__2 0x0916
1539 #define REG_PORT_MTI_HI_WATER_MARK 0x0916
1540 #define REG_PORT_MTI_QUEUE_CTRL_3__2 0x0918
1541 #define REG_PORT_MTI_LO_WATER_MARK 0x0918
1542 #define REG_PORT_MTI_QUEUE_CTRL_4__2 0x091A
1543 #define REG_PORT_MTI_CREDIT_INCREMENT 0x091A
1544
1545
1546
1547 #define REG_PORT_QM_CTRL__4 0x0A00
1548
1549 #define PORT_QM_DROP_PRIO_M 0x3
1550
1551 #define REG_PORT_VLAN_MEMBERSHIP__4 0x0A04
1552
1553 #define REG_PORT_QM_QUEUE_INDEX__4 0x0A08
1554
1555 #define PORT_QM_QUEUE_INDEX_S 24
1556 #define PORT_QM_BURST_SIZE_S 16
1557 #define PORT_QM_MIN_RESV_SPACE_M (BIT(11) - 1)
1558
1559 #define REG_PORT_QM_WATER_MARK__4 0x0A0C
1560
1561 #define PORT_QM_HI_WATER_MARK_S 16
1562 #define PORT_QM_LO_WATER_MARK_S 0
1563 #define PORT_QM_WATER_MARK_M (BIT(11) - 1)
1564
1565 #define REG_PORT_QM_TX_CNT_0__4 0x0A10
1566
1567 #define PORT_QM_TX_CNT_USED_S 0
1568 #define PORT_QM_TX_CNT_M (BIT(11) - 1)
1569
1570 #define REG_PORT_QM_TX_CNT_1__4 0x0A14
1571
1572 #define PORT_QM_TX_CNT_CALCULATED_S 16
1573 #define PORT_QM_TX_CNT_AVAIL_S 0
1574
1575
1576 #define REG_PORT_LUE_CTRL 0x0B00
1577
1578 #define PORT_VLAN_LOOKUP_VID_0 BIT(7)
1579 #define PORT_INGRESS_FILTER BIT(6)
1580 #define PORT_DISCARD_NON_VID BIT(5)
1581 #define PORT_MAC_BASED_802_1X BIT(4)
1582 #define PORT_SRC_ADDR_FILTER BIT(3)
1583
1584 #define REG_PORT_LUE_MSTP_INDEX 0x0B01
1585
1586 #define REG_PORT_LUE_MSTP_STATE 0x0B04
1587
1588 #define PORT_TX_ENABLE BIT(2)
1589 #define PORT_RX_ENABLE BIT(1)
1590 #define PORT_LEARN_DISABLE BIT(0)
1591
1592
1593
1594 #define REG_PTP_PORT_RX_DELAY__2 0x0C00
1595 #define REG_PTP_PORT_TX_DELAY__2 0x0C02
1596 #define REG_PTP_PORT_ASYM_DELAY__2 0x0C04
1597
1598 #define REG_PTP_PORT_XDELAY_TS 0x0C08
1599 #define REG_PTP_PORT_XDELAY_TS_H 0x0C08
1600 #define REG_PTP_PORT_XDELAY_TS_L 0x0C0A
1601
1602 #define REG_PTP_PORT_SYNC_TS 0x0C0C
1603 #define REG_PTP_PORT_SYNC_TS_H 0x0C0C
1604 #define REG_PTP_PORT_SYNC_TS_L 0x0C0E
1605
1606 #define REG_PTP_PORT_PDRESP_TS 0x0C10
1607 #define REG_PTP_PORT_PDRESP_TS_H 0x0C10
1608 #define REG_PTP_PORT_PDRESP_TS_L 0x0C12
1609
1610 #define REG_PTP_PORT_TX_INT_STATUS__2 0x0C14
1611 #define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C16
1612
1613 #define PTP_PORT_SYNC_INT BIT(15)
1614 #define PTP_PORT_XDELAY_REQ_INT BIT(14)
1615 #define PTP_PORT_PDELAY_RESP_INT BIT(13)
1616
1617 #define REG_PTP_PORT_LINK_DELAY__4 0x0C18
1618
1619 #define PRIO_QUEUES 4
1620 #define RX_PRIO_QUEUES 8
1621
1622 #define KS_PRIO_IN_REG 2
1623
1624 #define TOTAL_PORT_NUM 7
1625
1626 #define KSZ9477_COUNTER_NUM 0x20
1627 #define TOTAL_KSZ9477_COUNTER_NUM (KSZ9477_COUNTER_NUM + 2 + 2)
1628
1629 #define SWITCH_COUNTER_NUM KSZ9477_COUNTER_NUM
1630 #define TOTAL_SWITCH_COUNTER_NUM TOTAL_KSZ9477_COUNTER_NUM
1631
1632 #define P_BCAST_STORM_CTRL REG_PORT_MAC_CTRL_0
1633 #define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL
1634 #define P_MIRROR_CTRL REG_PORT_MRI_MIRROR_CTRL
1635 #define P_STP_CTRL REG_PORT_LUE_MSTP_STATE
1636 #define P_PHY_CTRL REG_PORT_PHY_CTRL
1637 #define P_NEG_RESTART_CTRL REG_PORT_PHY_CTRL
1638 #define P_LINK_STATUS REG_PORT_PHY_STATUS
1639 #define P_SPEED_STATUS REG_PORT_PHY_PHY_CTRL
1640 #define P_RATE_LIMIT_CTRL REG_PORT_MAC_IN_RATE_LIMIT
1641
1642 #define S_LINK_AGING_CTRL REG_SW_LUE_CTRL_1
1643 #define S_MIRROR_CTRL REG_SW_MRI_CTRL_0
1644 #define S_REPLACE_VID_CTRL REG_SW_MAC_CTRL_2
1645 #define S_802_1P_PRIO_CTRL REG_SW_MAC_802_1P_MAP_0
1646 #define S_TOS_PRIO_CTRL REG_SW_MAC_TOS_PRIO_0
1647 #define S_FLUSH_TABLE_CTRL REG_SW_LUE_CTRL_1
1648
1649 #define SW_FLUSH_DYN_MAC_TABLE SW_FLUSH_MSTP_TABLE
1650
1651 #define MAX_TIMESTAMP_UNIT 2
1652 #define MAX_TRIG_UNIT 3
1653 #define MAX_TIMESTAMP_EVENT_UNIT 8
1654 #define MAX_GPIO 4
1655
1656 #define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1)
1657 #define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1)
1658
1659
1660 #define BROADCAST_STORM_PROT_RATE 10
1661
1662
1663 #define BROADCAST_STORM_VALUE 9969
1664
1665 #endif