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9 #ifndef __KSZ8795_REG_H
10 #define __KSZ8795_REG_H
11
12 #define KS_PORT_M 0x1F
13
14 #define KS_PRIO_M 0x3
15 #define KS_PRIO_S 2
16
17 #define REG_CHIP_ID0 0x00
18
19 #define FAMILY_ID 0x87
20
21 #define REG_CHIP_ID1 0x01
22
23 #define SW_CHIP_ID_M 0xF0
24 #define SW_CHIP_ID_S 4
25 #define SW_REVISION_M 0x0E
26 #define SW_REVISION_S 1
27 #define SW_START 0x01
28
29 #define CHIP_ID_94 0x60
30 #define CHIP_ID_95 0x90
31
32 #define REG_SW_CTRL_0 0x02
33
34 #define SW_NEW_BACKOFF BIT(7)
35 #define SW_GLOBAL_RESET BIT(6)
36 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
37 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
38 #define SW_LINK_AUTO_AGING BIT(0)
39
40 #define REG_SW_CTRL_1 0x03
41
42 #define SW_HUGE_PACKET BIT(6)
43 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
44 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
45 #define SW_CHECK_LENGTH BIT(3)
46 #define SW_AGING_ENABLE BIT(2)
47 #define SW_FAST_AGING BIT(1)
48 #define SW_AGGR_BACKOFF BIT(0)
49
50 #define REG_SW_CTRL_2 0x04
51
52 #define UNICAST_VLAN_BOUNDARY BIT(7)
53 #define MULTICAST_STORM_DISABLE BIT(6)
54 #define SW_BACK_PRESSURE BIT(5)
55 #define FAIR_FLOW_CTRL BIT(4)
56 #define NO_EXC_COLLISION_DROP BIT(3)
57 #define SW_LEGAL_PACKET_DISABLE BIT(1)
58
59 #define REG_SW_CTRL_3 0x05
60 #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3)
61
62 #define SW_VLAN_ENABLE BIT(7)
63 #define SW_IGMP_SNOOP BIT(6)
64 #define SW_MIRROR_RX_TX BIT(0)
65
66 #define REG_SW_CTRL_4 0x06
67
68 #define SW_HALF_DUPLEX_FLOW_CTRL BIT(7)
69 #define SW_HALF_DUPLEX BIT(6)
70 #define SW_FLOW_CTRL BIT(5)
71 #define SW_10_MBIT BIT(4)
72 #define SW_REPLACE_VID BIT(3)
73 #define BROADCAST_STORM_RATE_HI 0x07
74
75 #define REG_SW_CTRL_5 0x07
76
77 #define BROADCAST_STORM_RATE_LO 0xFF
78 #define BROADCAST_STORM_RATE 0x07FF
79
80 #define REG_SW_CTRL_6 0x08
81
82 #define SW_MIB_COUNTER_FLUSH BIT(7)
83 #define SW_MIB_COUNTER_FREEZE BIT(6)
84 #define SW_MIB_COUNTER_CTRL_ENABLE KS_PORT_M
85
86 #define REG_SW_CTRL_9 0x0B
87
88 #define SPI_CLK_125_MHZ 0x80
89 #define SPI_CLK_62_5_MHZ 0x40
90 #define SPI_CLK_31_25_MHZ 0x00
91
92 #define SW_LED_MODE_M 0x3
93 #define SW_LED_MODE_S 4
94 #define SW_LED_LINK_ACT_SPEED 0
95 #define SW_LED_LINK_ACT 1
96 #define SW_LED_LINK_ACT_DUPLEX 2
97 #define SW_LED_LINK_DUPLEX 3
98
99 #define REG_SW_CTRL_10 0x0C
100
101 #define SW_TAIL_TAG_ENABLE BIT(1)
102 #define SW_PASS_PAUSE BIT(0)
103
104 #define REG_SW_CTRL_11 0x0D
105
106 #define REG_POWER_MANAGEMENT_1 0x0E
107
108 #define SW_PLL_POWER_DOWN BIT(5)
109 #define SW_POWER_MANAGEMENT_MODE_M 0x3
110 #define SW_POWER_MANAGEMENT_MODE_S 3
111 #define SW_POWER_NORMAL 0
112 #define SW_ENERGY_DETECTION 1
113 #define SW_SOFTWARE_POWER_DOWN 2
114
115 #define REG_POWER_MANAGEMENT_2 0x0F
116
117 #define REG_PORT_1_CTRL_0 0x10
118 #define REG_PORT_2_CTRL_0 0x20
119 #define REG_PORT_3_CTRL_0 0x30
120 #define REG_PORT_4_CTRL_0 0x40
121 #define REG_PORT_5_CTRL_0 0x50
122
123 #define PORT_BROADCAST_STORM BIT(7)
124 #define PORT_DIFFSERV_ENABLE BIT(6)
125 #define PORT_802_1P_ENABLE BIT(5)
126 #define PORT_BASED_PRIO_S 3
127 #define PORT_BASED_PRIO_M KS_PRIO_M
128 #define PORT_BASED_PRIO_0 0
129 #define PORT_BASED_PRIO_1 1
130 #define PORT_BASED_PRIO_2 2
131 #define PORT_BASED_PRIO_3 3
132 #define PORT_INSERT_TAG BIT(2)
133 #define PORT_REMOVE_TAG BIT(1)
134 #define PORT_QUEUE_SPLIT_L BIT(0)
135
136 #define REG_PORT_1_CTRL_1 0x11
137 #define REG_PORT_2_CTRL_1 0x21
138 #define REG_PORT_3_CTRL_1 0x31
139 #define REG_PORT_4_CTRL_1 0x41
140 #define REG_PORT_5_CTRL_1 0x51
141
142 #define PORT_MIRROR_SNIFFER BIT(7)
143 #define PORT_MIRROR_RX BIT(6)
144 #define PORT_MIRROR_TX BIT(5)
145 #define PORT_VLAN_MEMBERSHIP KS_PORT_M
146
147 #define REG_PORT_1_CTRL_2 0x12
148 #define REG_PORT_2_CTRL_2 0x22
149 #define REG_PORT_3_CTRL_2 0x32
150 #define REG_PORT_4_CTRL_2 0x42
151 #define REG_PORT_5_CTRL_2 0x52
152
153 #define PORT_802_1P_REMAPPING BIT(7)
154 #define PORT_INGRESS_FILTER BIT(6)
155 #define PORT_DISCARD_NON_VID BIT(5)
156 #define PORT_FORCE_FLOW_CTRL BIT(4)
157 #define PORT_BACK_PRESSURE BIT(3)
158 #define PORT_TX_ENABLE BIT(2)
159 #define PORT_RX_ENABLE BIT(1)
160 #define PORT_LEARN_DISABLE BIT(0)
161
162 #define REG_PORT_1_CTRL_3 0x13
163 #define REG_PORT_2_CTRL_3 0x23
164 #define REG_PORT_3_CTRL_3 0x33
165 #define REG_PORT_4_CTRL_3 0x43
166 #define REG_PORT_5_CTRL_3 0x53
167 #define REG_PORT_1_CTRL_4 0x14
168 #define REG_PORT_2_CTRL_4 0x24
169 #define REG_PORT_3_CTRL_4 0x34
170 #define REG_PORT_4_CTRL_4 0x44
171 #define REG_PORT_5_CTRL_4 0x54
172
173 #define PORT_DEFAULT_VID 0x0001
174
175 #define REG_PORT_1_CTRL_5 0x15
176 #define REG_PORT_2_CTRL_5 0x25
177 #define REG_PORT_3_CTRL_5 0x35
178 #define REG_PORT_4_CTRL_5 0x45
179 #define REG_PORT_5_CTRL_5 0x55
180
181 #define PORT_ACL_ENABLE BIT(2)
182 #define PORT_AUTHEN_MODE 0x3
183 #define PORT_AUTHEN_PASS 0
184 #define PORT_AUTHEN_BLOCK 1
185 #define PORT_AUTHEN_TRAP 2
186
187 #define REG_PORT_5_CTRL_6 0x56
188
189 #define PORT_MII_INTERNAL_CLOCK BIT(7)
190 #define PORT_GMII_1GPS_MODE BIT(6)
191 #define PORT_RGMII_ID_IN_ENABLE BIT(4)
192 #define PORT_RGMII_ID_OUT_ENABLE BIT(3)
193 #define PORT_GMII_MAC_MODE BIT(2)
194 #define PORT_INTERFACE_TYPE 0x3
195 #define PORT_INTERFACE_MII 0
196 #define PORT_INTERFACE_RMII 1
197 #define PORT_INTERFACE_GMII 2
198 #define PORT_INTERFACE_RGMII 3
199
200 #define REG_PORT_1_CTRL_7 0x17
201 #define REG_PORT_2_CTRL_7 0x27
202 #define REG_PORT_3_CTRL_7 0x37
203 #define REG_PORT_4_CTRL_7 0x47
204
205 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(5)
206 #define PORT_AUTO_NEG_SYM_PAUSE BIT(4)
207 #define PORT_AUTO_NEG_100BTX_FD BIT(3)
208 #define PORT_AUTO_NEG_100BTX BIT(2)
209 #define PORT_AUTO_NEG_10BT_FD BIT(1)
210 #define PORT_AUTO_NEG_10BT BIT(0)
211
212 #define REG_PORT_1_STATUS_0 0x18
213 #define REG_PORT_2_STATUS_0 0x28
214 #define REG_PORT_3_STATUS_0 0x38
215 #define REG_PORT_4_STATUS_0 0x48
216
217
218 #define PORT_FIBER_MODE BIT(7)
219
220 #define PORT_REMOTE_ASYM_PAUSE BIT(5)
221 #define PORT_REMOTE_SYM_PAUSE BIT(4)
222 #define PORT_REMOTE_100BTX_FD BIT(3)
223 #define PORT_REMOTE_100BTX BIT(2)
224 #define PORT_REMOTE_10BT_FD BIT(1)
225 #define PORT_REMOTE_10BT BIT(0)
226
227 #define REG_PORT_1_STATUS_1 0x19
228 #define REG_PORT_2_STATUS_1 0x29
229 #define REG_PORT_3_STATUS_1 0x39
230 #define REG_PORT_4_STATUS_1 0x49
231
232 #define PORT_HP_MDIX BIT(7)
233 #define PORT_REVERSED_POLARITY BIT(5)
234 #define PORT_TX_FLOW_CTRL BIT(4)
235 #define PORT_RX_FLOW_CTRL BIT(3)
236 #define PORT_STAT_SPEED_100MBIT BIT(2)
237 #define PORT_STAT_FULL_DUPLEX BIT(1)
238
239 #define PORT_REMOTE_FAULT BIT(0)
240
241 #define REG_PORT_1_LINK_MD_CTRL 0x1A
242 #define REG_PORT_2_LINK_MD_CTRL 0x2A
243 #define REG_PORT_3_LINK_MD_CTRL 0x3A
244 #define REG_PORT_4_LINK_MD_CTRL 0x4A
245
246 #define PORT_CABLE_10M_SHORT BIT(7)
247 #define PORT_CABLE_DIAG_RESULT_M 0x3
248 #define PORT_CABLE_DIAG_RESULT_S 5
249 #define PORT_CABLE_STAT_NORMAL 0
250 #define PORT_CABLE_STAT_OPEN 1
251 #define PORT_CABLE_STAT_SHORT 2
252 #define PORT_CABLE_STAT_FAILED 3
253 #define PORT_START_CABLE_DIAG BIT(4)
254 #define PORT_FORCE_LINK BIT(3)
255 #define PORT_POWER_SAVING BIT(2)
256 #define PORT_PHY_REMOTE_LOOPBACK BIT(1)
257 #define PORT_CABLE_FAULT_COUNTER_H 0x01
258
259 #define REG_PORT_1_LINK_MD_RESULT 0x1B
260 #define REG_PORT_2_LINK_MD_RESULT 0x2B
261 #define REG_PORT_3_LINK_MD_RESULT 0x3B
262 #define REG_PORT_4_LINK_MD_RESULT 0x4B
263
264 #define PORT_CABLE_FAULT_COUNTER_L 0xFF
265 #define PORT_CABLE_FAULT_COUNTER 0x1FF
266
267 #define REG_PORT_1_CTRL_9 0x1C
268 #define REG_PORT_2_CTRL_9 0x2C
269 #define REG_PORT_3_CTRL_9 0x3C
270 #define REG_PORT_4_CTRL_9 0x4C
271
272 #define PORT_AUTO_NEG_DISABLE BIT(7)
273 #define PORT_FORCE_100_MBIT BIT(6)
274 #define PORT_FORCE_FULL_DUPLEX BIT(5)
275
276 #define REG_PORT_1_CTRL_10 0x1D
277 #define REG_PORT_2_CTRL_10 0x2D
278 #define REG_PORT_3_CTRL_10 0x3D
279 #define REG_PORT_4_CTRL_10 0x4D
280
281 #define PORT_LED_OFF BIT(7)
282 #define PORT_TX_DISABLE BIT(6)
283 #define PORT_AUTO_NEG_RESTART BIT(5)
284 #define PORT_POWER_DOWN BIT(3)
285 #define PORT_AUTO_MDIX_DISABLE BIT(2)
286 #define PORT_FORCE_MDIX BIT(1)
287 #define PORT_MAC_LOOPBACK BIT(0)
288
289 #define REG_PORT_1_STATUS_2 0x1E
290 #define REG_PORT_2_STATUS_2 0x2E
291 #define REG_PORT_3_STATUS_2 0x3E
292 #define REG_PORT_4_STATUS_2 0x4E
293
294 #define PORT_MDIX_STATUS BIT(7)
295 #define PORT_AUTO_NEG_COMPLETE BIT(6)
296 #define PORT_STAT_LINK_GOOD BIT(5)
297
298 #define REG_PORT_1_STATUS_3 0x1F
299 #define REG_PORT_2_STATUS_3 0x2F
300 #define REG_PORT_3_STATUS_3 0x3F
301 #define REG_PORT_4_STATUS_3 0x4F
302
303 #define PORT_PHY_LOOPBACK BIT(7)
304 #define PORT_PHY_ISOLATE BIT(5)
305 #define PORT_PHY_SOFT_RESET BIT(4)
306 #define PORT_PHY_FORCE_LINK BIT(3)
307 #define PORT_PHY_MODE_M 0x7
308 #define PHY_MODE_IN_AUTO_NEG 1
309 #define PHY_MODE_10BT_HALF 2
310 #define PHY_MODE_100BT_HALF 3
311 #define PHY_MODE_10BT_FULL 5
312 #define PHY_MODE_100BT_FULL 6
313 #define PHY_MODE_ISOLDATE 7
314
315 #define REG_PORT_CTRL_0 0x00
316 #define REG_PORT_CTRL_1 0x01
317 #define REG_PORT_CTRL_2 0x02
318 #define REG_PORT_CTRL_VID 0x03
319
320 #define REG_PORT_CTRL_5 0x05
321
322 #define REG_PORT_CTRL_7 0x07
323 #define REG_PORT_STATUS_0 0x08
324 #define REG_PORT_STATUS_1 0x09
325 #define REG_PORT_LINK_MD_CTRL 0x0A
326 #define REG_PORT_LINK_MD_RESULT 0x0B
327 #define REG_PORT_CTRL_9 0x0C
328 #define REG_PORT_CTRL_10 0x0D
329 #define REG_PORT_STATUS_2 0x0E
330 #define REG_PORT_STATUS_3 0x0F
331
332 #define REG_PORT_CTRL_12 0xA0
333 #define REG_PORT_CTRL_13 0xA1
334 #define REG_PORT_RATE_CTRL_3 0xA2
335 #define REG_PORT_RATE_CTRL_2 0xA3
336 #define REG_PORT_RATE_CTRL_1 0xA4
337 #define REG_PORT_RATE_CTRL_0 0xA5
338 #define REG_PORT_RATE_LIMIT 0xA6
339 #define REG_PORT_IN_RATE_0 0xA7
340 #define REG_PORT_IN_RATE_1 0xA8
341 #define REG_PORT_IN_RATE_2 0xA9
342 #define REG_PORT_IN_RATE_3 0xAA
343 #define REG_PORT_OUT_RATE_0 0xAB
344 #define REG_PORT_OUT_RATE_1 0xAC
345 #define REG_PORT_OUT_RATE_2 0xAD
346 #define REG_PORT_OUT_RATE_3 0xAE
347
348 #define PORT_CTRL_ADDR(port, addr) \
349 ((addr) + REG_PORT_1_CTRL_0 + (port) * \
350 (REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0))
351
352 #define REG_SW_MAC_ADDR_0 0x68
353 #define REG_SW_MAC_ADDR_1 0x69
354 #define REG_SW_MAC_ADDR_2 0x6A
355 #define REG_SW_MAC_ADDR_3 0x6B
356 #define REG_SW_MAC_ADDR_4 0x6C
357 #define REG_SW_MAC_ADDR_5 0x6D
358
359 #define REG_IND_CTRL_0 0x6E
360
361 #define TABLE_EXT_SELECT_S 5
362 #define TABLE_EEE_V 1
363 #define TABLE_ACL_V 2
364 #define TABLE_PME_V 4
365 #define TABLE_LINK_MD_V 5
366 #define TABLE_EEE (TABLE_EEE_V << TABLE_EXT_SELECT_S)
367 #define TABLE_ACL (TABLE_ACL_V << TABLE_EXT_SELECT_S)
368 #define TABLE_PME (TABLE_PME_V << TABLE_EXT_SELECT_S)
369 #define TABLE_LINK_MD (TABLE_LINK_MD << TABLE_EXT_SELECT_S)
370 #define TABLE_READ BIT(4)
371 #define TABLE_SELECT_S 2
372 #define TABLE_STATIC_MAC_V 0
373 #define TABLE_VLAN_V 1
374 #define TABLE_DYNAMIC_MAC_V 2
375 #define TABLE_MIB_V 3
376 #define TABLE_STATIC_MAC (TABLE_STATIC_MAC_V << TABLE_SELECT_S)
377 #define TABLE_VLAN (TABLE_VLAN_V << TABLE_SELECT_S)
378 #define TABLE_DYNAMIC_MAC (TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S)
379 #define TABLE_MIB (TABLE_MIB_V << TABLE_SELECT_S)
380
381 #define REG_IND_CTRL_1 0x6F
382
383 #define TABLE_ENTRY_MASK 0x03FF
384 #define TABLE_EXT_ENTRY_MASK 0x0FFF
385
386 #define REG_IND_DATA_8 0x70
387 #define REG_IND_DATA_7 0x71
388 #define REG_IND_DATA_6 0x72
389 #define REG_IND_DATA_5 0x73
390 #define REG_IND_DATA_4 0x74
391 #define REG_IND_DATA_3 0x75
392 #define REG_IND_DATA_2 0x76
393 #define REG_IND_DATA_1 0x77
394 #define REG_IND_DATA_0 0x78
395
396 #define REG_IND_DATA_PME_EEE_ACL 0xA0
397
398 #define REG_IND_DATA_CHECK REG_IND_DATA_6
399 #define REG_IND_MIB_CHECK REG_IND_DATA_4
400 #define REG_IND_DATA_HI REG_IND_DATA_7
401 #define REG_IND_DATA_LO REG_IND_DATA_3
402
403 #define REG_INT_STATUS 0x7C
404 #define REG_INT_ENABLE 0x7D
405
406 #define INT_PME BIT(4)
407
408 #define REG_ACL_INT_STATUS 0x7E
409 #define REG_ACL_INT_ENABLE 0x7F
410
411 #define INT_PORT_5 BIT(4)
412 #define INT_PORT_4 BIT(3)
413 #define INT_PORT_3 BIT(2)
414 #define INT_PORT_2 BIT(1)
415 #define INT_PORT_1 BIT(0)
416
417 #define INT_PORT_ALL \
418 (INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1)
419
420 #define REG_SW_CTRL_12 0x80
421 #define REG_SW_CTRL_13 0x81
422
423 #define SWITCH_802_1P_MASK 3
424 #define SWITCH_802_1P_BASE 3
425 #define SWITCH_802_1P_SHIFT 2
426
427 #define SW_802_1P_MAP_M KS_PRIO_M
428 #define SW_802_1P_MAP_S KS_PRIO_S
429
430 #define REG_SWITCH_CTRL_14 0x82
431
432 #define SW_PRIO_MAPPING_M KS_PRIO_M
433 #define SW_PRIO_MAPPING_S 6
434 #define SW_PRIO_MAP_3_HI 0
435 #define SW_PRIO_MAP_2_HI 2
436 #define SW_PRIO_MAP_0_LO 3
437
438 #define REG_SW_CTRL_15 0x83
439 #define REG_SW_CTRL_16 0x84
440 #define REG_SW_CTRL_17 0x85
441 #define REG_SW_CTRL_18 0x86
442
443 #define SW_SELF_ADDR_FILTER_ENABLE BIT(6)
444
445 #define REG_SW_UNK_UCAST_CTRL 0x83
446 #define REG_SW_UNK_MCAST_CTRL 0x84
447 #define REG_SW_UNK_VID_CTRL 0x85
448 #define REG_SW_UNK_IP_MCAST_CTRL 0x86
449
450 #define SW_UNK_FWD_ENABLE BIT(5)
451 #define SW_UNK_FWD_MAP KS_PORT_M
452
453 #define REG_SW_CTRL_19 0x87
454
455 #define SW_IN_RATE_LIMIT_PERIOD_M 0x3
456 #define SW_IN_RATE_LIMIT_PERIOD_S 4
457 #define SW_IN_RATE_LIMIT_16_MS 0
458 #define SW_IN_RATE_LIMIT_64_MS 1
459 #define SW_IN_RATE_LIMIT_256_MS 2
460 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
461 #define SW_INS_TAG_ENABLE BIT(2)
462
463 #define REG_TOS_PRIO_CTRL_0 0x90
464 #define REG_TOS_PRIO_CTRL_1 0x91
465 #define REG_TOS_PRIO_CTRL_2 0x92
466 #define REG_TOS_PRIO_CTRL_3 0x93
467 #define REG_TOS_PRIO_CTRL_4 0x94
468 #define REG_TOS_PRIO_CTRL_5 0x95
469 #define REG_TOS_PRIO_CTRL_6 0x96
470 #define REG_TOS_PRIO_CTRL_7 0x97
471 #define REG_TOS_PRIO_CTRL_8 0x98
472 #define REG_TOS_PRIO_CTRL_9 0x99
473 #define REG_TOS_PRIO_CTRL_10 0x9A
474 #define REG_TOS_PRIO_CTRL_11 0x9B
475 #define REG_TOS_PRIO_CTRL_12 0x9C
476 #define REG_TOS_PRIO_CTRL_13 0x9D
477 #define REG_TOS_PRIO_CTRL_14 0x9E
478 #define REG_TOS_PRIO_CTRL_15 0x9F
479
480 #define TOS_PRIO_M KS_PRIO_M
481 #define TOS_PRIO_S KS_PRIO_S
482
483 #define REG_SW_CTRL_20 0xA3
484
485 #define SW_GMII_DRIVE_STRENGTH_S 4
486 #define SW_DRIVE_STRENGTH_M 0x7
487 #define SW_DRIVE_STRENGTH_2MA 0
488 #define SW_DRIVE_STRENGTH_4MA 1
489 #define SW_DRIVE_STRENGTH_8MA 2
490 #define SW_DRIVE_STRENGTH_12MA 3
491 #define SW_DRIVE_STRENGTH_16MA 4
492 #define SW_DRIVE_STRENGTH_20MA 5
493 #define SW_DRIVE_STRENGTH_24MA 6
494 #define SW_DRIVE_STRENGTH_28MA 7
495 #define SW_MII_DRIVE_STRENGTH_S 0
496
497 #define REG_SW_CTRL_21 0xA4
498
499 #define SW_IPV6_MLD_OPTION BIT(3)
500 #define SW_IPV6_MLD_SNOOP BIT(2)
501
502 #define REG_PORT_1_CTRL_12 0xB0
503 #define REG_PORT_2_CTRL_12 0xC0
504 #define REG_PORT_3_CTRL_12 0xD0
505 #define REG_PORT_4_CTRL_12 0xE0
506 #define REG_PORT_5_CTRL_12 0xF0
507
508 #define PORT_PASS_ALL BIT(6)
509 #define PORT_INS_TAG_FOR_PORT_5_S 3
510 #define PORT_INS_TAG_FOR_PORT_5 BIT(3)
511 #define PORT_INS_TAG_FOR_PORT_4 BIT(2)
512 #define PORT_INS_TAG_FOR_PORT_3 BIT(1)
513 #define PORT_INS_TAG_FOR_PORT_2 BIT(0)
514
515 #define REG_PORT_1_CTRL_13 0xB1
516 #define REG_PORT_2_CTRL_13 0xC1
517 #define REG_PORT_3_CTRL_13 0xD1
518 #define REG_PORT_4_CTRL_13 0xE1
519 #define REG_PORT_5_CTRL_13 0xF1
520
521 #define PORT_QUEUE_SPLIT_H BIT(1)
522 #define PORT_QUEUE_SPLIT_1 0
523 #define PORT_QUEUE_SPLIT_2 1
524 #define PORT_QUEUE_SPLIT_4 2
525 #define PORT_DROP_TAG BIT(0)
526
527 #define REG_PORT_1_CTRL_14 0xB2
528 #define REG_PORT_2_CTRL_14 0xC2
529 #define REG_PORT_3_CTRL_14 0xD2
530 #define REG_PORT_4_CTRL_14 0xE2
531 #define REG_PORT_5_CTRL_14 0xF2
532 #define REG_PORT_1_CTRL_15 0xB3
533 #define REG_PORT_2_CTRL_15 0xC3
534 #define REG_PORT_3_CTRL_15 0xD3
535 #define REG_PORT_4_CTRL_15 0xE3
536 #define REG_PORT_5_CTRL_15 0xF3
537 #define REG_PORT_1_CTRL_16 0xB4
538 #define REG_PORT_2_CTRL_16 0xC4
539 #define REG_PORT_3_CTRL_16 0xD4
540 #define REG_PORT_4_CTRL_16 0xE4
541 #define REG_PORT_5_CTRL_16 0xF4
542 #define REG_PORT_1_CTRL_17 0xB5
543 #define REG_PORT_2_CTRL_17 0xC5
544 #define REG_PORT_3_CTRL_17 0xD5
545 #define REG_PORT_4_CTRL_17 0xE5
546 #define REG_PORT_5_CTRL_17 0xF5
547
548 #define REG_PORT_1_RATE_CTRL_3 0xB2
549 #define REG_PORT_1_RATE_CTRL_2 0xB3
550 #define REG_PORT_1_RATE_CTRL_1 0xB4
551 #define REG_PORT_1_RATE_CTRL_0 0xB5
552 #define REG_PORT_2_RATE_CTRL_3 0xC2
553 #define REG_PORT_2_RATE_CTRL_2 0xC3
554 #define REG_PORT_2_RATE_CTRL_1 0xC4
555 #define REG_PORT_2_RATE_CTRL_0 0xC5
556 #define REG_PORT_3_RATE_CTRL_3 0xD2
557 #define REG_PORT_3_RATE_CTRL_2 0xD3
558 #define REG_PORT_3_RATE_CTRL_1 0xD4
559 #define REG_PORT_3_RATE_CTRL_0 0xD5
560 #define REG_PORT_4_RATE_CTRL_3 0xE2
561 #define REG_PORT_4_RATE_CTRL_2 0xE3
562 #define REG_PORT_4_RATE_CTRL_1 0xE4
563 #define REG_PORT_4_RATE_CTRL_0 0xE5
564 #define REG_PORT_5_RATE_CTRL_3 0xF2
565 #define REG_PORT_5_RATE_CTRL_2 0xF3
566 #define REG_PORT_5_RATE_CTRL_1 0xF4
567 #define REG_PORT_5_RATE_CTRL_0 0xF5
568
569 #define RATE_CTRL_ENABLE BIT(7)
570 #define RATE_RATIO_M (BIT(7) - 1)
571
572 #define PORT_OUT_RATE_ENABLE BIT(7)
573
574 #define REG_PORT_1_RATE_LIMIT 0xB6
575 #define REG_PORT_2_RATE_LIMIT 0xC6
576 #define REG_PORT_3_RATE_LIMIT 0xD6
577 #define REG_PORT_4_RATE_LIMIT 0xE6
578 #define REG_PORT_5_RATE_LIMIT 0xF6
579
580 #define PORT_IN_PORT_BASED_S 6
581 #define PORT_RATE_PACKET_BASED_S 5
582 #define PORT_IN_FLOW_CTRL_S 4
583 #define PORT_IN_LIMIT_MODE_M 0x3
584 #define PORT_IN_LIMIT_MODE_S 2
585 #define PORT_COUNT_IFG_S 1
586 #define PORT_COUNT_PREAMBLE_S 0
587 #define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S)
588 #define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S)
589 #define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S)
590 #define PORT_IN_ALL 0
591 #define PORT_IN_UNICAST 1
592 #define PORT_IN_MULTICAST 2
593 #define PORT_IN_BROADCAST 3
594 #define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S)
595 #define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S)
596
597 #define REG_PORT_1_IN_RATE_0 0xB7
598 #define REG_PORT_2_IN_RATE_0 0xC7
599 #define REG_PORT_3_IN_RATE_0 0xD7
600 #define REG_PORT_4_IN_RATE_0 0xE7
601 #define REG_PORT_5_IN_RATE_0 0xF7
602 #define REG_PORT_1_IN_RATE_1 0xB8
603 #define REG_PORT_2_IN_RATE_1 0xC8
604 #define REG_PORT_3_IN_RATE_1 0xD8
605 #define REG_PORT_4_IN_RATE_1 0xE8
606 #define REG_PORT_5_IN_RATE_1 0xF8
607 #define REG_PORT_1_IN_RATE_2 0xB9
608 #define REG_PORT_2_IN_RATE_2 0xC9
609 #define REG_PORT_3_IN_RATE_2 0xD9
610 #define REG_PORT_4_IN_RATE_2 0xE9
611 #define REG_PORT_5_IN_RATE_2 0xF9
612 #define REG_PORT_1_IN_RATE_3 0xBA
613 #define REG_PORT_2_IN_RATE_3 0xCA
614 #define REG_PORT_3_IN_RATE_3 0xDA
615 #define REG_PORT_4_IN_RATE_3 0xEA
616 #define REG_PORT_5_IN_RATE_3 0xFA
617
618 #define PORT_IN_RATE_ENABLE BIT(7)
619 #define PORT_RATE_LIMIT_M (BIT(7) - 1)
620
621 #define REG_PORT_1_OUT_RATE_0 0xBB
622 #define REG_PORT_2_OUT_RATE_0 0xCB
623 #define REG_PORT_3_OUT_RATE_0 0xDB
624 #define REG_PORT_4_OUT_RATE_0 0xEB
625 #define REG_PORT_5_OUT_RATE_0 0xFB
626 #define REG_PORT_1_OUT_RATE_1 0xBC
627 #define REG_PORT_2_OUT_RATE_1 0xCC
628 #define REG_PORT_3_OUT_RATE_1 0xDC
629 #define REG_PORT_4_OUT_RATE_1 0xEC
630 #define REG_PORT_5_OUT_RATE_1 0xFC
631 #define REG_PORT_1_OUT_RATE_2 0xBD
632 #define REG_PORT_2_OUT_RATE_2 0xCD
633 #define REG_PORT_3_OUT_RATE_2 0xDD
634 #define REG_PORT_4_OUT_RATE_2 0xED
635 #define REG_PORT_5_OUT_RATE_2 0xFD
636 #define REG_PORT_1_OUT_RATE_3 0xBE
637 #define REG_PORT_2_OUT_RATE_3 0xCE
638 #define REG_PORT_3_OUT_RATE_3 0xDE
639 #define REG_PORT_4_OUT_RATE_3 0xEE
640 #define REG_PORT_5_OUT_RATE_3 0xFE
641
642
643
644 #define SW_PME_OUTPUT_ENABLE BIT(1)
645 #define SW_PME_ACTIVE_HIGH BIT(0)
646
647 #define PORT_MAGIC_PACKET_DETECT BIT(2)
648 #define PORT_LINK_UP_DETECT BIT(1)
649 #define PORT_ENERGY_DETECT BIT(0)
650
651
652
653 #define ACL_FIRST_RULE_M 0xF
654
655 #define ACL_MODE_M 0x3
656 #define ACL_MODE_S 4
657 #define ACL_MODE_DISABLE 0
658 #define ACL_MODE_LAYER_2 1
659 #define ACL_MODE_LAYER_3 2
660 #define ACL_MODE_LAYER_4 3
661 #define ACL_ENABLE_M 0x3
662 #define ACL_ENABLE_S 2
663 #define ACL_ENABLE_2_COUNT 0
664 #define ACL_ENABLE_2_TYPE 1
665 #define ACL_ENABLE_2_MAC 2
666 #define ACL_ENABLE_2_BOTH 3
667 #define ACL_ENABLE_3_IP 1
668 #define ACL_ENABLE_3_SRC_DST_COMP 2
669 #define ACL_ENABLE_4_PROTOCOL 0
670 #define ACL_ENABLE_4_TCP_PORT_COMP 1
671 #define ACL_ENABLE_4_UDP_PORT_COMP 2
672 #define ACL_ENABLE_4_TCP_SEQN_COMP 3
673 #define ACL_SRC BIT(1)
674 #define ACL_EQUAL BIT(0)
675
676 #define ACL_MAX_PORT 0xFFFF
677
678 #define ACL_MIN_PORT 0xFFFF
679 #define ACL_IP_ADDR 0xFFFFFFFF
680 #define ACL_TCP_SEQNUM 0xFFFFFFFF
681
682 #define ACL_RESERVED 0xF8
683 #define ACL_PORT_MODE_M 0x3
684 #define ACL_PORT_MODE_S 1
685 #define ACL_PORT_MODE_DISABLE 0
686 #define ACL_PORT_MODE_EITHER 1
687 #define ACL_PORT_MODE_IN_RANGE 2
688 #define ACL_PORT_MODE_OUT_OF_RANGE 3
689
690 #define ACL_TCP_FLAG_ENABLE BIT(0)
691
692 #define ACL_TCP_FLAG_M 0xFF
693
694 #define ACL_TCP_FLAG 0xFF
695 #define ACL_ETH_TYPE 0xFFFF
696 #define ACL_IP_M 0xFFFFFFFF
697
698 #define ACL_PRIO_MODE_M 0x3
699 #define ACL_PRIO_MODE_S 6
700 #define ACL_PRIO_MODE_DISABLE 0
701 #define ACL_PRIO_MODE_HIGHER 1
702 #define ACL_PRIO_MODE_LOWER 2
703 #define ACL_PRIO_MODE_REPLACE 3
704 #define ACL_PRIO_M 0x7
705 #define ACL_PRIO_S 3
706 #define ACL_VLAN_PRIO_REPLACE BIT(2)
707 #define ACL_VLAN_PRIO_M 0x7
708 #define ACL_VLAN_PRIO_HI_M 0x3
709
710 #define ACL_VLAN_PRIO_LO_M 0x8
711 #define ACL_VLAN_PRIO_S 7
712 #define ACL_MAP_MODE_M 0x3
713 #define ACL_MAP_MODE_S 5
714 #define ACL_MAP_MODE_DISABLE 0
715 #define ACL_MAP_MODE_OR 1
716 #define ACL_MAP_MODE_AND 2
717 #define ACL_MAP_MODE_REPLACE 3
718 #define ACL_MAP_PORT_M 0x1F
719
720 #define ACL_CNT_M (BIT(11) - 1)
721 #define ACL_CNT_S 5
722 #define ACL_MSEC_UNIT BIT(4)
723 #define ACL_INTR_MODE BIT(3)
724
725 #define REG_PORT_ACL_BYTE_EN_MSB 0x10
726
727 #define ACL_BYTE_EN_MSB_M 0x3F
728
729 #define REG_PORT_ACL_BYTE_EN_LSB 0x11
730
731 #define ACL_ACTION_START 0xA
732 #define ACL_ACTION_LEN 2
733 #define ACL_INTR_CNT_START 0xB
734 #define ACL_RULESET_START 0xC
735 #define ACL_RULESET_LEN 2
736 #define ACL_TABLE_LEN 14
737
738 #define ACL_ACTION_ENABLE 0x000C
739 #define ACL_MATCH_ENABLE 0x1FF0
740 #define ACL_RULESET_ENABLE 0x2003
741 #define ACL_BYTE_ENABLE ((ACL_BYTE_EN_MSB_M << 8) | 0xFF)
742 #define ACL_MODE_ENABLE (0x10 << 8)
743
744 #define REG_PORT_ACL_CTRL_0 0x12
745
746 #define PORT_ACL_WRITE_DONE BIT(6)
747 #define PORT_ACL_READ_DONE BIT(5)
748 #define PORT_ACL_WRITE BIT(4)
749 #define PORT_ACL_INDEX_M 0xF
750
751 #define REG_PORT_ACL_CTRL_1 0x13
752
753 #define PORT_ACL_FORCE_DLR_MISS BIT(0)
754
755 #ifndef PHY_REG_CTRL
756 #define PHY_REG_CTRL 0
757
758 #define PHY_RESET BIT(15)
759 #define PHY_LOOPBACK BIT(14)
760 #define PHY_SPEED_100MBIT BIT(13)
761 #define PHY_AUTO_NEG_ENABLE BIT(12)
762 #define PHY_POWER_DOWN BIT(11)
763 #define PHY_MII_DISABLE BIT(10)
764 #define PHY_AUTO_NEG_RESTART BIT(9)
765 #define PHY_FULL_DUPLEX BIT(8)
766 #define PHY_COLLISION_TEST_NOT BIT(7)
767 #define PHY_HP_MDIX BIT(5)
768 #define PHY_FORCE_MDIX BIT(4)
769 #define PHY_AUTO_MDIX_DISABLE BIT(3)
770 #define PHY_REMOTE_FAULT_DISABLE BIT(2)
771 #define PHY_TRANSMIT_DISABLE BIT(1)
772 #define PHY_LED_DISABLE BIT(0)
773
774 #define PHY_REG_STATUS 1
775
776 #define PHY_100BT4_CAPABLE BIT(15)
777 #define PHY_100BTX_FD_CAPABLE BIT(14)
778 #define PHY_100BTX_CAPABLE BIT(13)
779 #define PHY_10BT_FD_CAPABLE BIT(12)
780 #define PHY_10BT_CAPABLE BIT(11)
781 #define PHY_MII_SUPPRESS_CAPABLE_NOT BIT(6)
782 #define PHY_AUTO_NEG_ACKNOWLEDGE BIT(5)
783 #define PHY_REMOTE_FAULT BIT(4)
784 #define PHY_AUTO_NEG_CAPABLE BIT(3)
785 #define PHY_LINK_STATUS BIT(2)
786 #define PHY_JABBER_DETECT_NOT BIT(1)
787 #define PHY_EXTENDED_CAPABILITY BIT(0)
788
789 #define PHY_REG_ID_1 2
790 #define PHY_REG_ID_2 3
791
792 #define PHY_REG_AUTO_NEGOTIATION 4
793
794 #define PHY_AUTO_NEG_NEXT_PAGE_NOT BIT(15)
795 #define PHY_AUTO_NEG_REMOTE_FAULT_NOT BIT(13)
796 #define PHY_AUTO_NEG_SYM_PAUSE BIT(10)
797 #define PHY_AUTO_NEG_100BT4 BIT(9)
798 #define PHY_AUTO_NEG_100BTX_FD BIT(8)
799 #define PHY_AUTO_NEG_100BTX BIT(7)
800 #define PHY_AUTO_NEG_10BT_FD BIT(6)
801 #define PHY_AUTO_NEG_10BT BIT(5)
802 #define PHY_AUTO_NEG_SELECTOR 0x001F
803 #define PHY_AUTO_NEG_802_3 0x0001
804
805 #define PHY_REG_REMOTE_CAPABILITY 5
806
807 #define PHY_REMOTE_NEXT_PAGE_NOT BIT(15)
808 #define PHY_REMOTE_ACKNOWLEDGE_NOT BIT(14)
809 #define PHY_REMOTE_REMOTE_FAULT_NOT BIT(13)
810 #define PHY_REMOTE_SYM_PAUSE BIT(10)
811 #define PHY_REMOTE_100BTX_FD BIT(8)
812 #define PHY_REMOTE_100BTX BIT(7)
813 #define PHY_REMOTE_10BT_FD BIT(6)
814 #define PHY_REMOTE_10BT BIT(5)
815 #endif
816
817 #define KSZ8795_ID_HI 0x0022
818 #define KSZ8795_ID_LO 0x1550
819
820 #define KSZ8795_SW_ID 0x8795
821
822 #define PHY_REG_LINK_MD 0x1D
823
824 #define PHY_START_CABLE_DIAG BIT(15)
825 #define PHY_CABLE_DIAG_RESULT 0x6000
826 #define PHY_CABLE_STAT_NORMAL 0x0000
827 #define PHY_CABLE_STAT_OPEN 0x2000
828 #define PHY_CABLE_STAT_SHORT 0x4000
829 #define PHY_CABLE_STAT_FAILED 0x6000
830 #define PHY_CABLE_10M_SHORT BIT(12)
831 #define PHY_CABLE_FAULT_COUNTER 0x01FF
832
833 #define PHY_REG_PHY_CTRL 0x1F
834
835 #define PHY_MODE_M 0x7
836 #define PHY_MODE_S 8
837 #define PHY_STAT_REVERSED_POLARITY BIT(5)
838 #define PHY_STAT_MDIX BIT(4)
839 #define PHY_FORCE_LINK BIT(3)
840 #define PHY_POWER_SAVING_ENABLE BIT(2)
841 #define PHY_REMOTE_LOOPBACK BIT(1)
842
843
844
845 #define PRIO_QUEUES 4
846
847 #define KS_PRIO_IN_REG 4
848
849 #define TOTAL_PORT_NUM 5
850
851
852 #define SWITCH_PORT_NUM (TOTAL_PORT_NUM - 1)
853
854 #define KSZ8795_COUNTER_NUM 0x20
855 #define TOTAL_KSZ8795_COUNTER_NUM (KSZ8795_COUNTER_NUM + 4)
856
857 #define SWITCH_COUNTER_NUM KSZ8795_COUNTER_NUM
858 #define TOTAL_SWITCH_COUNTER_NUM TOTAL_KSZ8795_COUNTER_NUM
859
860
861
862 #define P_BCAST_STORM_CTRL REG_PORT_CTRL_0
863 #define P_PRIO_CTRL REG_PORT_CTRL_0
864 #define P_TAG_CTRL REG_PORT_CTRL_0
865 #define P_MIRROR_CTRL REG_PORT_CTRL_1
866 #define P_802_1P_CTRL REG_PORT_CTRL_2
867 #define P_STP_CTRL REG_PORT_CTRL_2
868 #define P_LOCAL_CTRL REG_PORT_CTRL_7
869 #define P_REMOTE_STATUS REG_PORT_STATUS_0
870 #define P_FORCE_CTRL REG_PORT_CTRL_9
871 #define P_NEG_RESTART_CTRL REG_PORT_CTRL_10
872 #define P_SPEED_STATUS REG_PORT_STATUS_1
873 #define P_LINK_STATUS REG_PORT_STATUS_2
874 #define P_PASS_ALL_CTRL REG_PORT_CTRL_12
875 #define P_INS_SRC_PVID_CTRL REG_PORT_CTRL_12
876 #define P_DROP_TAG_CTRL REG_PORT_CTRL_13
877 #define P_RATE_LIMIT_CTRL REG_PORT_RATE_LIMIT
878
879 #define S_UNKNOWN_DA_CTRL REG_SWITCH_CTRL_12
880 #define S_FORWARD_INVALID_VID_CTRL REG_FORWARD_INVALID_VID
881
882 #define S_FLUSH_TABLE_CTRL REG_SW_CTRL_0
883 #define S_LINK_AGING_CTRL REG_SW_CTRL_0
884 #define S_HUGE_PACKET_CTRL REG_SW_CTRL_1
885 #define S_MIRROR_CTRL REG_SW_CTRL_3
886 #define S_REPLACE_VID_CTRL REG_SW_CTRL_4
887 #define S_PASS_PAUSE_CTRL REG_SW_CTRL_10
888 #define S_TAIL_TAG_CTRL REG_SW_CTRL_10
889 #define S_802_1P_PRIO_CTRL REG_SW_CTRL_12
890 #define S_TOS_PRIO_CTRL REG_TOS_PRIO_CTRL_0
891 #define S_IPV6_MLD_CTRL REG_SW_CTRL_21
892
893 #define IND_ACC_TABLE(table) ((table) << 8)
894
895
896 #define BROADCAST_STORM_PROT_RATE 10
897
898
899 #define BROADCAST_STORM_VALUE 9969
900
901
902
903
904
905
906
907
908
909
910 #define STATIC_MAC_TABLE_ADDR 0x0000FFFF
911 #define STATIC_MAC_TABLE_FWD_PORTS 0x001F0000
912 #define STATIC_MAC_TABLE_VALID 0x00200000
913 #define STATIC_MAC_TABLE_OVERRIDE 0x00400000
914 #define STATIC_MAC_TABLE_USE_FID 0x00800000
915 #define STATIC_MAC_TABLE_FID 0x7F000000
916
917 #define STATIC_MAC_FWD_PORTS_S 16
918 #define STATIC_MAC_FID_S 24
919
920
921
922
923
924
925
926 #define VLAN_TABLE_FID 0x007F
927 #define VLAN_TABLE_MEMBERSHIP 0x0F80
928 #define VLAN_TABLE_VALID 0x1000
929
930 #define VLAN_TABLE_MEMBERSHIP_S 7
931 #define VLAN_TABLE_S 16
932
933
934
935
936
937
938
939
940
941
942
943 #define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
944 #define DYNAMIC_MAC_TABLE_FID 0x007F0000
945 #define DYNAMIC_MAC_TABLE_SRC_PORT 0x07000000
946 #define DYNAMIC_MAC_TABLE_TIMESTAMP 0x18000000
947 #define DYNAMIC_MAC_TABLE_ENTRIES 0xE0000000
948
949 #define DYNAMIC_MAC_TABLE_NOT_READY 0x80
950
951 #define DYNAMIC_MAC_TABLE_ENTRIES_H 0x7F
952 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x80
953
954 #define DYNAMIC_MAC_FID_S 16
955 #define DYNAMIC_MAC_SRC_PORT_S 24
956 #define DYNAMIC_MAC_TIMESTAMP_S 27
957 #define DYNAMIC_MAC_ENTRIES_S 29
958 #define DYNAMIC_MAC_ENTRIES_H_S 3
959
960
961
962
963
964
965
966
967
968 #define MIB_COUNTER_OVERFLOW BIT(6)
969 #define MIB_COUNTER_VALID BIT(5)
970
971 #define MIB_COUNTER_VALUE 0x3FFFFFFF
972
973 #define KS_MIB_TOTAL_RX_0 0x100
974 #define KS_MIB_TOTAL_TX_0 0x101
975 #define KS_MIB_PACKET_DROPPED_RX_0 0x102
976 #define KS_MIB_PACKET_DROPPED_TX_0 0x103
977 #define KS_MIB_TOTAL_RX_1 0x104
978 #define KS_MIB_TOTAL_TX_1 0x105
979 #define KS_MIB_PACKET_DROPPED_TX_1 0x106
980 #define KS_MIB_PACKET_DROPPED_RX_1 0x107
981 #define KS_MIB_TOTAL_RX_2 0x108
982 #define KS_MIB_TOTAL_TX_2 0x109
983 #define KS_MIB_PACKET_DROPPED_TX_2 0x10A
984 #define KS_MIB_PACKET_DROPPED_RX_2 0x10B
985 #define KS_MIB_TOTAL_RX_3 0x10C
986 #define KS_MIB_TOTAL_TX_3 0x10D
987 #define KS_MIB_PACKET_DROPPED_TX_3 0x10E
988 #define KS_MIB_PACKET_DROPPED_RX_3 0x10F
989 #define KS_MIB_TOTAL_RX_4 0x110
990 #define KS_MIB_TOTAL_TX_4 0x111
991 #define KS_MIB_PACKET_DROPPED_TX_4 0x112
992 #define KS_MIB_PACKET_DROPPED_RX_4 0x113
993
994 #define MIB_PACKET_DROPPED 0x0000FFFF
995
996 #define MIB_TOTAL_BYTES_H 0x0000000F
997
998 #define TAIL_TAG_OVERRIDE BIT(6)
999 #define TAIL_TAG_LOOKUP BIT(7)
1000
1001 #define VLAN_TABLE_ENTRIES (4096 / 4)
1002 #define FID_ENTRIES 128
1003
1004 #endif