drivers/net/dsa/mt7530.c

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This source file includes following definitions.
core_read_mmd_indirect
core_write_mmd_indirect
core_write
core_rmw
core_set
core_clear
mt7530_mii_write
mt7530_mii_read
mt7530_write
_mt7530_read
mt7530_read
mt7530_rmw
mt7530_set
mt7530_clear
mt7530_fdb_cmd
mt7530_fdb_read
mt7530_fdb_write
mt7530_pad_clk_setup
mt7530_mib_reset
mt7530_port_set_status
mt7530_phy_read
mt7530_phy_write
mt7530_get_strings
mt7530_get_ethtool_stats
mt7530_get_sset_count
mt7530_setup_port5
mt7530_cpu_port_enable
mt7530_port_enable
mt7530_port_disable
mt7530_stp_state_set
mt7530_port_bridge_join
mt7530_port_set_vlan_unaware
mt7530_port_set_vlan_aware
mt7530_port_bridge_leave
mt7530_port_fdb_add
mt7530_port_fdb_del
mt7530_port_fdb_dump
mt7530_vlan_cmd
mt7530_port_vlan_filtering
mt7530_port_vlan_prepare
mt7530_hw_vlan_add
mt7530_hw_vlan_del
mt7530_hw_vlan_update
mt7530_port_vlan_add
mt7530_port_vlan_del
mtk_get_tag_protocol
mt7530_setup
mt7530_phylink_mac_config
mt7530_phylink_mac_link_down
mt7530_phylink_mac_link_up
mt7530_phylink_validate
mt7530_phylink_mac_link_state
mt7530_probe
mt7530_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Mediatek MT7530 DSA Switch driver
   4  * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
   5  */
   6 #include <linux/etherdevice.h>
   7 #include <linux/if_bridge.h>
   8 #include <linux/iopoll.h>
   9 #include <linux/mdio.h>
  10 #include <linux/mfd/syscon.h>
  11 #include <linux/module.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/of_mdio.h>
  14 #include <linux/of_net.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/phylink.h>
  17 #include <linux/regmap.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/gpio/consumer.h>
  21 #include <net/dsa.h>
  22 
  23 #include "mt7530.h"
  24 
  25 /* String, offset, and register size in bytes if different from 4 bytes */
  26 static const struct mt7530_mib_desc mt7530_mib[] = {
  27         MIB_DESC(1, 0x00, "TxDrop"),
  28         MIB_DESC(1, 0x04, "TxCrcErr"),
  29         MIB_DESC(1, 0x08, "TxUnicast"),
  30         MIB_DESC(1, 0x0c, "TxMulticast"),
  31         MIB_DESC(1, 0x10, "TxBroadcast"),
  32         MIB_DESC(1, 0x14, "TxCollision"),
  33         MIB_DESC(1, 0x18, "TxSingleCollision"),
  34         MIB_DESC(1, 0x1c, "TxMultipleCollision"),
  35         MIB_DESC(1, 0x20, "TxDeferred"),
  36         MIB_DESC(1, 0x24, "TxLateCollision"),
  37         MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
  38         MIB_DESC(1, 0x2c, "TxPause"),
  39         MIB_DESC(1, 0x30, "TxPktSz64"),
  40         MIB_DESC(1, 0x34, "TxPktSz65To127"),
  41         MIB_DESC(1, 0x38, "TxPktSz128To255"),
  42         MIB_DESC(1, 0x3c, "TxPktSz256To511"),
  43         MIB_DESC(1, 0x40, "TxPktSz512To1023"),
  44         MIB_DESC(1, 0x44, "Tx1024ToMax"),
  45         MIB_DESC(2, 0x48, "TxBytes"),
  46         MIB_DESC(1, 0x60, "RxDrop"),
  47         MIB_DESC(1, 0x64, "RxFiltering"),
  48         MIB_DESC(1, 0x6c, "RxMulticast"),
  49         MIB_DESC(1, 0x70, "RxBroadcast"),
  50         MIB_DESC(1, 0x74, "RxAlignErr"),
  51         MIB_DESC(1, 0x78, "RxCrcErr"),
  52         MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
  53         MIB_DESC(1, 0x80, "RxFragErr"),
  54         MIB_DESC(1, 0x84, "RxOverSzErr"),
  55         MIB_DESC(1, 0x88, "RxJabberErr"),
  56         MIB_DESC(1, 0x8c, "RxPause"),
  57         MIB_DESC(1, 0x90, "RxPktSz64"),
  58         MIB_DESC(1, 0x94, "RxPktSz65To127"),
  59         MIB_DESC(1, 0x98, "RxPktSz128To255"),
  60         MIB_DESC(1, 0x9c, "RxPktSz256To511"),
  61         MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
  62         MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
  63         MIB_DESC(2, 0xa8, "RxBytes"),
  64         MIB_DESC(1, 0xb0, "RxCtrlDrop"),
  65         MIB_DESC(1, 0xb4, "RxIngressDrop"),
  66         MIB_DESC(1, 0xb8, "RxArlDrop"),
  67 };
  68 
  69 static int
  70 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
  71 {
  72         struct mii_bus *bus = priv->bus;
  73         int value, ret;
  74 
  75         /* Write the desired MMD Devad */
  76         ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
  77         if (ret < 0)
  78                 goto err;
  79 
  80         /* Write the desired MMD register address */
  81         ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
  82         if (ret < 0)
  83                 goto err;
  84 
  85         /* Select the Function : DATA with no post increment */
  86         ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
  87         if (ret < 0)
  88                 goto err;
  89 
  90         /* Read the content of the MMD's selected register */
  91         value = bus->read(bus, 0, MII_MMD_DATA);
  92 
  93         return value;
  94 err:
  95         dev_err(&bus->dev,  "failed to read mmd register\n");
  96 
  97         return ret;
  98 }
  99 
 100 static int
 101 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
 102                         int devad, u32 data)
 103 {
 104         struct mii_bus *bus = priv->bus;
 105         int ret;
 106 
 107         /* Write the desired MMD Devad */
 108         ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
 109         if (ret < 0)
 110                 goto err;
 111 
 112         /* Write the desired MMD register address */
 113         ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
 114         if (ret < 0)
 115                 goto err;
 116 
 117         /* Select the Function : DATA with no post increment */
 118         ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
 119         if (ret < 0)
 120                 goto err;
 121 
 122         /* Write the data into MMD's selected register */
 123         ret = bus->write(bus, 0, MII_MMD_DATA, data);
 124 err:
 125         if (ret < 0)
 126                 dev_err(&bus->dev,
 127                         "failed to write mmd register\n");
 128         return ret;
 129 }
 130 
 131 static void
 132 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
 133 {
 134         struct mii_bus *bus = priv->bus;
 135 
 136         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 137 
 138         core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
 139 
 140         mutex_unlock(&bus->mdio_lock);
 141 }
 142 
 143 static void
 144 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
 145 {
 146         struct mii_bus *bus = priv->bus;
 147         u32 val;
 148 
 149         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 150 
 151         val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
 152         val &= ~mask;
 153         val |= set;
 154         core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
 155 
 156         mutex_unlock(&bus->mdio_lock);
 157 }
 158 
 159 static void
 160 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
 161 {
 162         core_rmw(priv, reg, 0, val);
 163 }
 164 
 165 static void
 166 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
 167 {
 168         core_rmw(priv, reg, val, 0);
 169 }
 170 
 171 static int
 172 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
 173 {
 174         struct mii_bus *bus = priv->bus;
 175         u16 page, r, lo, hi;
 176         int ret;
 177 
 178         page = (reg >> 6) & 0x3ff;
 179         r  = (reg >> 2) & 0xf;
 180         lo = val & 0xffff;
 181         hi = val >> 16;
 182 
 183         /* MT7530 uses 31 as the pseudo port */
 184         ret = bus->write(bus, 0x1f, 0x1f, page);
 185         if (ret < 0)
 186                 goto err;
 187 
 188         ret = bus->write(bus, 0x1f, r,  lo);
 189         if (ret < 0)
 190                 goto err;
 191 
 192         ret = bus->write(bus, 0x1f, 0x10, hi);
 193 err:
 194         if (ret < 0)
 195                 dev_err(&bus->dev,
 196                         "failed to write mt7530 register\n");
 197         return ret;
 198 }
 199 
 200 static u32
 201 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
 202 {
 203         struct mii_bus *bus = priv->bus;
 204         u16 page, r, lo, hi;
 205         int ret;
 206 
 207         page = (reg >> 6) & 0x3ff;
 208         r = (reg >> 2) & 0xf;
 209 
 210         /* MT7530 uses 31 as the pseudo port */
 211         ret = bus->write(bus, 0x1f, 0x1f, page);
 212         if (ret < 0) {
 213                 dev_err(&bus->dev,
 214                         "failed to read mt7530 register\n");
 215                 return ret;
 216         }
 217 
 218         lo = bus->read(bus, 0x1f, r);
 219         hi = bus->read(bus, 0x1f, 0x10);
 220 
 221         return (hi << 16) | (lo & 0xffff);
 222 }
 223 
 224 static void
 225 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
 226 {
 227         struct mii_bus *bus = priv->bus;
 228 
 229         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 230 
 231         mt7530_mii_write(priv, reg, val);
 232 
 233         mutex_unlock(&bus->mdio_lock);
 234 }
 235 
 236 static u32
 237 _mt7530_read(struct mt7530_dummy_poll *p)
 238 {
 239         struct mii_bus          *bus = p->priv->bus;
 240         u32 val;
 241 
 242         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 243 
 244         val = mt7530_mii_read(p->priv, p->reg);
 245 
 246         mutex_unlock(&bus->mdio_lock);
 247 
 248         return val;
 249 }
 250 
 251 static u32
 252 mt7530_read(struct mt7530_priv *priv, u32 reg)
 253 {
 254         struct mt7530_dummy_poll p;
 255 
 256         INIT_MT7530_DUMMY_POLL(&p, priv, reg);
 257         return _mt7530_read(&p);
 258 }
 259 
 260 static void
 261 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
 262            u32 mask, u32 set)
 263 {
 264         struct mii_bus *bus = priv->bus;
 265         u32 val;
 266 
 267         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 268 
 269         val = mt7530_mii_read(priv, reg);
 270         val &= ~mask;
 271         val |= set;
 272         mt7530_mii_write(priv, reg, val);
 273 
 274         mutex_unlock(&bus->mdio_lock);
 275 }
 276 
 277 static void
 278 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
 279 {
 280         mt7530_rmw(priv, reg, 0, val);
 281 }
 282 
 283 static void
 284 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
 285 {
 286         mt7530_rmw(priv, reg, val, 0);
 287 }
 288 
 289 static int
 290 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
 291 {
 292         u32 val;
 293         int ret;
 294         struct mt7530_dummy_poll p;
 295 
 296         /* Set the command operating upon the MAC address entries */
 297         val = ATC_BUSY | ATC_MAT(0) | cmd;
 298         mt7530_write(priv, MT7530_ATC, val);
 299 
 300         INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
 301         ret = readx_poll_timeout(_mt7530_read, &p, val,
 302                                  !(val & ATC_BUSY), 20, 20000);
 303         if (ret < 0) {
 304                 dev_err(priv->dev, "reset timeout\n");
 305                 return ret;
 306         }
 307 
 308         /* Additional sanity for read command if the specified
 309          * entry is invalid
 310          */
 311         val = mt7530_read(priv, MT7530_ATC);
 312         if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
 313                 return -EINVAL;
 314 
 315         if (rsp)
 316                 *rsp = val;
 317 
 318         return 0;
 319 }
 320 
 321 static void
 322 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
 323 {
 324         u32 reg[3];
 325         int i;
 326 
 327         /* Read from ARL table into an array */
 328         for (i = 0; i < 3; i++) {
 329                 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
 330 
 331                 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
 332                         __func__, __LINE__, i, reg[i]);
 333         }
 334 
 335         fdb->vid = (reg[1] >> CVID) & CVID_MASK;
 336         fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
 337         fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
 338         fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
 339         fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
 340         fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
 341         fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
 342         fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
 343         fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
 344         fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
 345 }
 346 
 347 static void
 348 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
 349                  u8 port_mask, const u8 *mac,
 350                  u8 aging, u8 type)
 351 {
 352         u32 reg[3] = { 0 };
 353         int i;
 354 
 355         reg[1] |= vid & CVID_MASK;
 356         reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
 357         reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
 358         /* STATIC_ENT indicate that entry is static wouldn't
 359          * be aged out and STATIC_EMP specified as erasing an
 360          * entry
 361          */
 362         reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
 363         reg[1] |= mac[5] << MAC_BYTE_5;
 364         reg[1] |= mac[4] << MAC_BYTE_4;
 365         reg[0] |= mac[3] << MAC_BYTE_3;
 366         reg[0] |= mac[2] << MAC_BYTE_2;
 367         reg[0] |= mac[1] << MAC_BYTE_1;
 368         reg[0] |= mac[0] << MAC_BYTE_0;
 369 
 370         /* Write array into the ARL table */
 371         for (i = 0; i < 3; i++)
 372                 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
 373 }
 374 
 375 static int
 376 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
 377 {
 378         struct mt7530_priv *priv = ds->priv;
 379         u32 ncpo1, ssc_delta, trgint, i, xtal;
 380 
 381         xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
 382 
 383         if (xtal == HWTRAP_XTAL_20MHZ) {
 384                 dev_err(priv->dev,
 385                         "%s: MT7530 with a 20MHz XTAL is not supported!\n",
 386                         __func__);
 387                 return -EINVAL;
 388         }
 389 
 390         switch (mode) {
 391         case PHY_INTERFACE_MODE_RGMII:
 392                 trgint = 0;
 393                 /* PLL frequency: 125MHz */
 394                 ncpo1 = 0x0c80;
 395                 break;
 396         case PHY_INTERFACE_MODE_TRGMII:
 397                 trgint = 1;
 398                 if (priv->id == ID_MT7621) {
 399                         /* PLL frequency: 150MHz: 1.2GBit */
 400                         if (xtal == HWTRAP_XTAL_40MHZ)
 401                                 ncpo1 = 0x0780;
 402                         if (xtal == HWTRAP_XTAL_25MHZ)
 403                                 ncpo1 = 0x0a00;
 404                 } else { /* PLL frequency: 250MHz: 2.0Gbit */
 405                         if (xtal == HWTRAP_XTAL_40MHZ)
 406                                 ncpo1 = 0x0c80;
 407                         if (xtal == HWTRAP_XTAL_25MHZ)
 408                                 ncpo1 = 0x1400;
 409                 }
 410                 break;
 411         default:
 412                 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
 413                 return -EINVAL;
 414         }
 415 
 416         if (xtal == HWTRAP_XTAL_25MHZ)
 417                 ssc_delta = 0x57;
 418         else
 419                 ssc_delta = 0x87;
 420 
 421         mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
 422                    P6_INTF_MODE(trgint));
 423 
 424         /* Lower Tx Driving for TRGMII path */
 425         for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
 426                 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
 427                              TD_DM_DRVP(8) | TD_DM_DRVN(8));
 428 
 429         /* Setup core clock for MT7530 */
 430         if (!trgint) {
 431                 /* Disable MT7530 core clock */
 432                 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
 433 
 434                 /* Disable PLL, since phy_device has not yet been created
 435                  * provided for phy_[read,write]_mmd_indirect is called, we
 436                  * provide our own core_write_mmd_indirect to complete this
 437                  * function.
 438                  */
 439                 core_write_mmd_indirect(priv,
 440                                         CORE_GSWPLL_GRP1,
 441                                         MDIO_MMD_VEND2,
 442                                         0);
 443 
 444                 /* Set core clock into 500Mhz */
 445                 core_write(priv, CORE_GSWPLL_GRP2,
 446                            RG_GSWPLL_POSDIV_500M(1) |
 447                            RG_GSWPLL_FBKDIV_500M(25));
 448 
 449                 /* Enable PLL */
 450                 core_write(priv, CORE_GSWPLL_GRP1,
 451                            RG_GSWPLL_EN_PRE |
 452                            RG_GSWPLL_POSDIV_200M(2) |
 453                            RG_GSWPLL_FBKDIV_200M(32));
 454 
 455                 /* Enable MT7530 core clock */
 456                 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
 457         }
 458 
 459         /* Setup the MT7530 TRGMII Tx Clock */
 460         core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
 461         core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
 462         core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
 463         core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
 464         core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
 465         core_write(priv, CORE_PLL_GROUP4,
 466                    RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
 467                    RG_SYSPLL_BIAS_LPF_EN);
 468         core_write(priv, CORE_PLL_GROUP2,
 469                    RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
 470                    RG_SYSPLL_POSDIV(1));
 471         core_write(priv, CORE_PLL_GROUP7,
 472                    RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
 473                    RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
 474         core_set(priv, CORE_TRGMII_GSW_CLK_CG,
 475                  REG_GSWCK_EN | REG_TRGMIICK_EN);
 476 
 477         if (!trgint)
 478                 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
 479                         mt7530_rmw(priv, MT7530_TRGMII_RD(i),
 480                                    RD_TAP_MASK, RD_TAP(16));
 481         return 0;
 482 }
 483 
 484 static void
 485 mt7530_mib_reset(struct dsa_switch *ds)
 486 {
 487         struct mt7530_priv *priv = ds->priv;
 488 
 489         mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
 490         mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
 491 }
 492 
 493 static void
 494 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable)
 495 {
 496         u32 mask = PMCR_TX_EN | PMCR_RX_EN | PMCR_FORCE_LNK;
 497 
 498         if (enable)
 499                 mt7530_set(priv, MT7530_PMCR_P(port), mask);
 500         else
 501                 mt7530_clear(priv, MT7530_PMCR_P(port), mask);
 502 }
 503 
 504 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
 505 {
 506         struct mt7530_priv *priv = ds->priv;
 507 
 508         return mdiobus_read_nested(priv->bus, port, regnum);
 509 }
 510 
 511 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
 512                             u16 val)
 513 {
 514         struct mt7530_priv *priv = ds->priv;
 515 
 516         return mdiobus_write_nested(priv->bus, port, regnum, val);
 517 }
 518 
 519 static void
 520 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 521                    uint8_t *data)
 522 {
 523         int i;
 524 
 525         if (stringset != ETH_SS_STATS)
 526                 return;
 527 
 528         for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
 529                 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
 530                         ETH_GSTRING_LEN);
 531 }
 532 
 533 static void
 534 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
 535                          uint64_t *data)
 536 {
 537         struct mt7530_priv *priv = ds->priv;
 538         const struct mt7530_mib_desc *mib;
 539         u32 reg, i;
 540         u64 hi;
 541 
 542         for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
 543                 mib = &mt7530_mib[i];
 544                 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
 545 
 546                 data[i] = mt7530_read(priv, reg);
 547                 if (mib->size == 2) {
 548                         hi = mt7530_read(priv, reg + 4);
 549                         data[i] |= hi << 32;
 550                 }
 551         }
 552 }
 553 
 554 static int
 555 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
 556 {
 557         if (sset != ETH_SS_STATS)
 558                 return 0;
 559 
 560         return ARRAY_SIZE(mt7530_mib);
 561 }
 562 
 563 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
 564 {
 565         struct mt7530_priv *priv = ds->priv;
 566         u8 tx_delay = 0;
 567         int val;
 568 
 569         mutex_lock(&priv->reg_mutex);
 570 
 571         val = mt7530_read(priv, MT7530_MHWTRAP);
 572 
 573         val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
 574         val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
 575 
 576         switch (priv->p5_intf_sel) {
 577         case P5_INTF_SEL_PHY_P0:
 578                 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
 579                 val |= MHWTRAP_PHY0_SEL;
 580                 /* fall through */
 581         case P5_INTF_SEL_PHY_P4:
 582                 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
 583                 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
 584 
 585                 /* Setup the MAC by default for the cpu port */
 586                 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
 587                 break;
 588         case P5_INTF_SEL_GMAC5:
 589                 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
 590                 val &= ~MHWTRAP_P5_DIS;
 591                 break;
 592         case P5_DISABLED:
 593                 interface = PHY_INTERFACE_MODE_NA;
 594                 break;
 595         default:
 596                 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
 597                         priv->p5_intf_sel);
 598                 goto unlock_exit;
 599         }
 600 
 601         /* Setup RGMII settings */
 602         if (phy_interface_mode_is_rgmii(interface)) {
 603                 val |= MHWTRAP_P5_RGMII_MODE;
 604 
 605                 /* P5 RGMII RX Clock Control: delay setting for 1000M */
 606                 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
 607 
 608                 /* Don't set delay in DSA mode */
 609                 if (!dsa_is_dsa_port(priv->ds, 5) &&
 610                     (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
 611                      interface == PHY_INTERFACE_MODE_RGMII_ID))
 612                         tx_delay = 4; /* n * 0.5 ns */
 613 
 614                 /* P5 RGMII TX Clock Control: delay x */
 615                 mt7530_write(priv, MT7530_P5RGMIITXCR,
 616                              CSR_RGMII_TXC_CFG(0x10 + tx_delay));
 617 
 618                 /* reduce P5 RGMII Tx driving, 8mA */
 619                 mt7530_write(priv, MT7530_IO_DRV_CR,
 620                              P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
 621         }
 622 
 623         mt7530_write(priv, MT7530_MHWTRAP, val);
 624 
 625         dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
 626                 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
 627 
 628         priv->p5_interface = interface;
 629 
 630 unlock_exit:
 631         mutex_unlock(&priv->reg_mutex);
 632 }
 633 
 634 static int
 635 mt7530_cpu_port_enable(struct mt7530_priv *priv,
 636                        int port)
 637 {
 638         /* Enable Mediatek header mode on the cpu port */
 639         mt7530_write(priv, MT7530_PVC_P(port),
 640                      PORT_SPEC_TAG);
 641 
 642         /* Unknown multicast frame forwarding to the cpu port */
 643         mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
 644 
 645         /* Set CPU port number */
 646         if (priv->id == ID_MT7621)
 647                 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
 648 
 649         /* CPU port gets connected to all user ports of
 650          * the switch
 651          */
 652         mt7530_write(priv, MT7530_PCR_P(port),
 653                      PCR_MATRIX(dsa_user_ports(priv->ds)));
 654 
 655         return 0;
 656 }
 657 
 658 static int
 659 mt7530_port_enable(struct dsa_switch *ds, int port,
 660                    struct phy_device *phy)
 661 {
 662         struct mt7530_priv *priv = ds->priv;
 663 
 664         if (!dsa_is_user_port(ds, port))
 665                 return 0;
 666 
 667         mutex_lock(&priv->reg_mutex);
 668 
 669         /* Allow the user port gets connected to the cpu port and also
 670          * restore the port matrix if the port is the member of a certain
 671          * bridge.
 672          */
 673         priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
 674         priv->ports[port].enable = true;
 675         mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
 676                    priv->ports[port].pm);
 677         mt7530_port_set_status(priv, port, 0);
 678 
 679         mutex_unlock(&priv->reg_mutex);
 680 
 681         return 0;
 682 }
 683 
 684 static void
 685 mt7530_port_disable(struct dsa_switch *ds, int port)
 686 {
 687         struct mt7530_priv *priv = ds->priv;
 688 
 689         if (!dsa_is_user_port(ds, port))
 690                 return;
 691 
 692         mutex_lock(&priv->reg_mutex);
 693 
 694         /* Clear up all port matrix which could be restored in the next
 695          * enablement for the port.
 696          */
 697         priv->ports[port].enable = false;
 698         mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
 699                    PCR_MATRIX_CLR);
 700         mt7530_port_set_status(priv, port, 0);
 701 
 702         mutex_unlock(&priv->reg_mutex);
 703 }
 704 
 705 static void
 706 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
 707 {
 708         struct mt7530_priv *priv = ds->priv;
 709         u32 stp_state;
 710 
 711         switch (state) {
 712         case BR_STATE_DISABLED:
 713                 stp_state = MT7530_STP_DISABLED;
 714                 break;
 715         case BR_STATE_BLOCKING:
 716                 stp_state = MT7530_STP_BLOCKING;
 717                 break;
 718         case BR_STATE_LISTENING:
 719                 stp_state = MT7530_STP_LISTENING;
 720                 break;
 721         case BR_STATE_LEARNING:
 722                 stp_state = MT7530_STP_LEARNING;
 723                 break;
 724         case BR_STATE_FORWARDING:
 725         default:
 726                 stp_state = MT7530_STP_FORWARDING;
 727                 break;
 728         }
 729 
 730         mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
 731 }
 732 
 733 static int
 734 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
 735                         struct net_device *bridge)
 736 {
 737         struct mt7530_priv *priv = ds->priv;
 738         u32 port_bitmap = BIT(MT7530_CPU_PORT);
 739         int i;
 740 
 741         mutex_lock(&priv->reg_mutex);
 742 
 743         for (i = 0; i < MT7530_NUM_PORTS; i++) {
 744                 /* Add this port to the port matrix of the other ports in the
 745                  * same bridge. If the port is disabled, port matrix is kept
 746                  * and not being setup until the port becomes enabled.
 747                  */
 748                 if (dsa_is_user_port(ds, i) && i != port) {
 749                         if (dsa_to_port(ds, i)->bridge_dev != bridge)
 750                                 continue;
 751                         if (priv->ports[i].enable)
 752                                 mt7530_set(priv, MT7530_PCR_P(i),
 753                                            PCR_MATRIX(BIT(port)));
 754                         priv->ports[i].pm |= PCR_MATRIX(BIT(port));
 755 
 756                         port_bitmap |= BIT(i);
 757                 }
 758         }
 759 
 760         /* Add the all other ports to this port matrix. */
 761         if (priv->ports[port].enable)
 762                 mt7530_rmw(priv, MT7530_PCR_P(port),
 763                            PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
 764         priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
 765 
 766         mutex_unlock(&priv->reg_mutex);
 767 
 768         return 0;
 769 }
 770 
 771 static void
 772 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
 773 {
 774         struct mt7530_priv *priv = ds->priv;
 775         bool all_user_ports_removed = true;
 776         int i;
 777 
 778         /* When a port is removed from the bridge, the port would be set up
 779          * back to the default as is at initial boot which is a VLAN-unaware
 780          * port.
 781          */
 782         mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
 783                    MT7530_PORT_MATRIX_MODE);
 784         mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
 785                    VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
 786                    PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
 787 
 788         for (i = 0; i < MT7530_NUM_PORTS; i++) {
 789                 if (dsa_is_user_port(ds, i) &&
 790                     dsa_port_is_vlan_filtering(&ds->ports[i])) {
 791                         all_user_ports_removed = false;
 792                         break;
 793                 }
 794         }
 795 
 796         /* CPU port also does the same thing until all user ports belonging to
 797          * the CPU port get out of VLAN filtering mode.
 798          */
 799         if (all_user_ports_removed) {
 800                 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
 801                              PCR_MATRIX(dsa_user_ports(priv->ds)));
 802                 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
 803                              | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
 804         }
 805 }
 806 
 807 static void
 808 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
 809 {
 810         struct mt7530_priv *priv = ds->priv;
 811 
 812         /* The real fabric path would be decided on the membership in the
 813          * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
 814          * means potential VLAN can be consisting of certain subset of all
 815          * ports.
 816          */
 817         mt7530_rmw(priv, MT7530_PCR_P(port),
 818                    PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
 819 
 820         /* Trapped into security mode allows packet forwarding through VLAN
 821          * table lookup. CPU port is set to fallback mode to let untagged
 822          * frames pass through.
 823          */
 824         if (dsa_is_cpu_port(ds, port))
 825                 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
 826                            MT7530_PORT_FALLBACK_MODE);
 827         else
 828                 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
 829                            MT7530_PORT_SECURITY_MODE);
 830 
 831         /* Set the port as a user port which is to be able to recognize VID
 832          * from incoming packets before fetching entry within the VLAN table.
 833          */
 834         mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
 835                    VLAN_ATTR(MT7530_VLAN_USER) |
 836                    PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
 837 }
 838 
 839 static void
 840 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
 841                          struct net_device *bridge)
 842 {
 843         struct mt7530_priv *priv = ds->priv;
 844         int i;
 845 
 846         mutex_lock(&priv->reg_mutex);
 847 
 848         for (i = 0; i < MT7530_NUM_PORTS; i++) {
 849                 /* Remove this port from the port matrix of the other ports
 850                  * in the same bridge. If the port is disabled, port matrix
 851                  * is kept and not being setup until the port becomes enabled.
 852                  * And the other port's port matrix cannot be broken when the
 853                  * other port is still a VLAN-aware port.
 854                  */
 855                 if (dsa_is_user_port(ds, i) && i != port &&
 856                    !dsa_port_is_vlan_filtering(&ds->ports[i])) {
 857                         if (dsa_to_port(ds, i)->bridge_dev != bridge)
 858                                 continue;
 859                         if (priv->ports[i].enable)
 860                                 mt7530_clear(priv, MT7530_PCR_P(i),
 861                                              PCR_MATRIX(BIT(port)));
 862                         priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
 863                 }
 864         }
 865 
 866         /* Set the cpu port to be the only one in the port matrix of
 867          * this port.
 868          */
 869         if (priv->ports[port].enable)
 870                 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
 871                            PCR_MATRIX(BIT(MT7530_CPU_PORT)));
 872         priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
 873 
 874         mutex_unlock(&priv->reg_mutex);
 875 }
 876 
 877 static int
 878 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
 879                     const unsigned char *addr, u16 vid)
 880 {
 881         struct mt7530_priv *priv = ds->priv;
 882         int ret;
 883         u8 port_mask = BIT(port);
 884 
 885         mutex_lock(&priv->reg_mutex);
 886         mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
 887         ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
 888         mutex_unlock(&priv->reg_mutex);
 889 
 890         return ret;
 891 }
 892 
 893 static int
 894 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
 895                     const unsigned char *addr, u16 vid)
 896 {
 897         struct mt7530_priv *priv = ds->priv;
 898         int ret;
 899         u8 port_mask = BIT(port);
 900 
 901         mutex_lock(&priv->reg_mutex);
 902         mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
 903         ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
 904         mutex_unlock(&priv->reg_mutex);
 905 
 906         return ret;
 907 }
 908 
 909 static int
 910 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
 911                      dsa_fdb_dump_cb_t *cb, void *data)
 912 {
 913         struct mt7530_priv *priv = ds->priv;
 914         struct mt7530_fdb _fdb = { 0 };
 915         int cnt = MT7530_NUM_FDB_RECORDS;
 916         int ret = 0;
 917         u32 rsp = 0;
 918 
 919         mutex_lock(&priv->reg_mutex);
 920 
 921         ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
 922         if (ret < 0)
 923                 goto err;
 924 
 925         do {
 926                 if (rsp & ATC_SRCH_HIT) {
 927                         mt7530_fdb_read(priv, &_fdb);
 928                         if (_fdb.port_mask & BIT(port)) {
 929                                 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
 930                                          data);
 931                                 if (ret < 0)
 932                                         break;
 933                         }
 934                 }
 935         } while (--cnt &&
 936                  !(rsp & ATC_SRCH_END) &&
 937                  !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
 938 err:
 939         mutex_unlock(&priv->reg_mutex);
 940 
 941         return 0;
 942 }
 943 
 944 static int
 945 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
 946 {
 947         struct mt7530_dummy_poll p;
 948         u32 val;
 949         int ret;
 950 
 951         val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
 952         mt7530_write(priv, MT7530_VTCR, val);
 953 
 954         INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
 955         ret = readx_poll_timeout(_mt7530_read, &p, val,
 956                                  !(val & VTCR_BUSY), 20, 20000);
 957         if (ret < 0) {
 958                 dev_err(priv->dev, "poll timeout\n");
 959                 return ret;
 960         }
 961 
 962         val = mt7530_read(priv, MT7530_VTCR);
 963         if (val & VTCR_INVALID) {
 964                 dev_err(priv->dev, "read VTCR invalid\n");
 965                 return -EINVAL;
 966         }
 967 
 968         return 0;
 969 }
 970 
 971 static int
 972 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
 973                            bool vlan_filtering)
 974 {
 975         if (vlan_filtering) {
 976                 /* The port is being kept as VLAN-unaware port when bridge is
 977                  * set up with vlan_filtering not being set, Otherwise, the
 978                  * port and the corresponding CPU port is required the setup
 979                  * for becoming a VLAN-aware port.
 980                  */
 981                 mt7530_port_set_vlan_aware(ds, port);
 982                 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
 983         } else {
 984                 mt7530_port_set_vlan_unaware(ds, port);
 985         }
 986 
 987         return 0;
 988 }
 989 
 990 static int
 991 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
 992                          const struct switchdev_obj_port_vlan *vlan)
 993 {
 994         /* nothing needed */
 995 
 996         return 0;
 997 }
 998 
 999 static void
1000 mt7530_hw_vlan_add(struct mt7530_priv *priv,
1001                    struct mt7530_hw_vlan_entry *entry)
1002 {
1003         u8 new_members;
1004         u32 val;
1005 
1006         new_members = entry->old_members | BIT(entry->port) |
1007                       BIT(MT7530_CPU_PORT);
1008 
1009         /* Validate the entry with independent learning, create egress tag per
1010          * VLAN and joining the port as one of the port members.
1011          */
1012         val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1013         mt7530_write(priv, MT7530_VAWD1, val);
1014 
1015         /* Decide whether adding tag or not for those outgoing packets from the
1016          * port inside the VLAN.
1017          */
1018         val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1019                                 MT7530_VLAN_EGRESS_TAG;
1020         mt7530_rmw(priv, MT7530_VAWD2,
1021                    ETAG_CTRL_P_MASK(entry->port),
1022                    ETAG_CTRL_P(entry->port, val));
1023 
1024         /* CPU port is always taken as a tagged port for serving more than one
1025          * VLANs across and also being applied with egress type stack mode for
1026          * that VLAN tags would be appended after hardware special tag used as
1027          * DSA tag.
1028          */
1029         mt7530_rmw(priv, MT7530_VAWD2,
1030                    ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1031                    ETAG_CTRL_P(MT7530_CPU_PORT,
1032                                MT7530_VLAN_EGRESS_STACK));
1033 }
1034 
1035 static void
1036 mt7530_hw_vlan_del(struct mt7530_priv *priv,
1037                    struct mt7530_hw_vlan_entry *entry)
1038 {
1039         u8 new_members;
1040         u32 val;
1041 
1042         new_members = entry->old_members & ~BIT(entry->port);
1043 
1044         val = mt7530_read(priv, MT7530_VAWD1);
1045         if (!(val & VLAN_VALID)) {
1046                 dev_err(priv->dev,
1047                         "Cannot be deleted due to invalid entry\n");
1048                 return;
1049         }
1050 
1051         /* If certain member apart from CPU port is still alive in the VLAN,
1052          * the entry would be kept valid. Otherwise, the entry is got to be
1053          * disabled.
1054          */
1055         if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1056                 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1057                       VLAN_VALID;
1058                 mt7530_write(priv, MT7530_VAWD1, val);
1059         } else {
1060                 mt7530_write(priv, MT7530_VAWD1, 0);
1061                 mt7530_write(priv, MT7530_VAWD2, 0);
1062         }
1063 }
1064 
1065 static void
1066 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1067                       struct mt7530_hw_vlan_entry *entry,
1068                       mt7530_vlan_op vlan_op)
1069 {
1070         u32 val;
1071 
1072         /* Fetch entry */
1073         mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1074 
1075         val = mt7530_read(priv, MT7530_VAWD1);
1076 
1077         entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1078 
1079         /* Manipulate entry */
1080         vlan_op(priv, entry);
1081 
1082         /* Flush result to hardware */
1083         mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1084 }
1085 
1086 static void
1087 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1088                      const struct switchdev_obj_port_vlan *vlan)
1089 {
1090         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1091         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1092         struct mt7530_hw_vlan_entry new_entry;
1093         struct mt7530_priv *priv = ds->priv;
1094         u16 vid;
1095 
1096         /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1097          * being set.
1098          */
1099         if (!dsa_port_is_vlan_filtering(&ds->ports[port]))
1100                 return;
1101 
1102         mutex_lock(&priv->reg_mutex);
1103 
1104         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1105                 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1106                 mt7530_hw_vlan_update(priv, vid, &new_entry,
1107                                       mt7530_hw_vlan_add);
1108         }
1109 
1110         if (pvid) {
1111                 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1112                            G0_PORT_VID(vlan->vid_end));
1113                 priv->ports[port].pvid = vlan->vid_end;
1114         }
1115 
1116         mutex_unlock(&priv->reg_mutex);
1117 }
1118 
1119 static int
1120 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1121                      const struct switchdev_obj_port_vlan *vlan)
1122 {
1123         struct mt7530_hw_vlan_entry target_entry;
1124         struct mt7530_priv *priv = ds->priv;
1125         u16 vid, pvid;
1126 
1127         /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1128          * being set.
1129          */
1130         if (!dsa_port_is_vlan_filtering(&ds->ports[port]))
1131                 return 0;
1132 
1133         mutex_lock(&priv->reg_mutex);
1134 
1135         pvid = priv->ports[port].pvid;
1136         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1137                 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1138                 mt7530_hw_vlan_update(priv, vid, &target_entry,
1139                                       mt7530_hw_vlan_del);
1140 
1141                 /* PVID is being restored to the default whenever the PVID port
1142                  * is being removed from the VLAN.
1143                  */
1144                 if (pvid == vid)
1145                         pvid = G0_PORT_VID_DEF;
1146         }
1147 
1148         mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1149         priv->ports[port].pvid = pvid;
1150 
1151         mutex_unlock(&priv->reg_mutex);
1152 
1153         return 0;
1154 }
1155 
1156 static enum dsa_tag_protocol
1157 mtk_get_tag_protocol(struct dsa_switch *ds, int port)
1158 {
1159         struct mt7530_priv *priv = ds->priv;
1160 
1161         if (port != MT7530_CPU_PORT) {
1162                 dev_warn(priv->dev,
1163                          "port not matched with tagging CPU port\n");
1164                 return DSA_TAG_PROTO_NONE;
1165         } else {
1166                 return DSA_TAG_PROTO_MTK;
1167         }
1168 }
1169 
1170 static int
1171 mt7530_setup(struct dsa_switch *ds)
1172 {
1173         struct mt7530_priv *priv = ds->priv;
1174         struct device_node *phy_node;
1175         struct device_node *mac_np;
1176         struct mt7530_dummy_poll p;
1177         phy_interface_t interface;
1178         struct device_node *dn;
1179         u32 id, val;
1180         int ret, i;
1181 
1182         /* The parent node of master netdev which holds the common system
1183          * controller also is the container for two GMACs nodes representing
1184          * as two netdev instances.
1185          */
1186         dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent;
1187 
1188         if (priv->id == ID_MT7530) {
1189                 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1190                 ret = regulator_enable(priv->core_pwr);
1191                 if (ret < 0) {
1192                         dev_err(priv->dev,
1193                                 "Failed to enable core power: %d\n", ret);
1194                         return ret;
1195                 }
1196 
1197                 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1198                 ret = regulator_enable(priv->io_pwr);
1199                 if (ret < 0) {
1200                         dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1201                                 ret);
1202                         return ret;
1203                 }
1204         }
1205 
1206         /* Reset whole chip through gpio pin or memory-mapped registers for
1207          * different type of hardware
1208          */
1209         if (priv->mcm) {
1210                 reset_control_assert(priv->rstc);
1211                 usleep_range(1000, 1100);
1212                 reset_control_deassert(priv->rstc);
1213         } else {
1214                 gpiod_set_value_cansleep(priv->reset, 0);
1215                 usleep_range(1000, 1100);
1216                 gpiod_set_value_cansleep(priv->reset, 1);
1217         }
1218 
1219         /* Waiting for MT7530 got to stable */
1220         INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1221         ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1222                                  20, 1000000);
1223         if (ret < 0) {
1224                 dev_err(priv->dev, "reset timeout\n");
1225                 return ret;
1226         }
1227 
1228         id = mt7530_read(priv, MT7530_CREV);
1229         id >>= CHIP_NAME_SHIFT;
1230         if (id != MT7530_ID) {
1231                 dev_err(priv->dev, "chip %x can't be supported\n", id);
1232                 return -ENODEV;
1233         }
1234 
1235         /* Reset the switch through internal reset */
1236         mt7530_write(priv, MT7530_SYS_CTRL,
1237                      SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1238                      SYS_CTRL_REG_RST);
1239 
1240         /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1241         val = mt7530_read(priv, MT7530_MHWTRAP);
1242         val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1243         val |= MHWTRAP_MANUAL;
1244         mt7530_write(priv, MT7530_MHWTRAP, val);
1245 
1246         priv->p6_interface = PHY_INTERFACE_MODE_NA;
1247 
1248         /* Enable and reset MIB counters */
1249         mt7530_mib_reset(ds);
1250 
1251         for (i = 0; i < MT7530_NUM_PORTS; i++) {
1252                 /* Disable forwarding by default on all ports */
1253                 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1254                            PCR_MATRIX_CLR);
1255 
1256                 if (dsa_is_cpu_port(ds, i))
1257                         mt7530_cpu_port_enable(priv, i);
1258                 else
1259                         mt7530_port_disable(ds, i);
1260 
1261                 /* Enable consistent egress tag */
1262                 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1263                            PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1264         }
1265 
1266         /* Setup port 5 */
1267         priv->p5_intf_sel = P5_DISABLED;
1268         interface = PHY_INTERFACE_MODE_NA;
1269 
1270         if (!dsa_is_unused_port(ds, 5)) {
1271                 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
1272                 interface = of_get_phy_mode(ds->ports[5].dn);
1273         } else {
1274                 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
1275                 for_each_child_of_node(dn, mac_np) {
1276                         if (!of_device_is_compatible(mac_np,
1277                                                      "mediatek,eth-mac"))
1278                                 continue;
1279 
1280                         ret = of_property_read_u32(mac_np, "reg", &id);
1281                         if (ret < 0 || id != 1)
1282                                 continue;
1283 
1284                         phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
1285                         if (!phy_node)
1286                                 continue;
1287 
1288                         if (phy_node->parent == priv->dev->of_node->parent) {
1289                                 interface = of_get_phy_mode(mac_np);
1290                                 id = of_mdio_parse_addr(ds->dev, phy_node);
1291                                 if (id == 0)
1292                                         priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
1293                                 if (id == 4)
1294                                         priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
1295                         }
1296                         of_node_put(phy_node);
1297                         break;
1298                 }
1299         }
1300 
1301         mt7530_setup_port5(ds, interface);
1302 
1303         /* Flush the FDB table */
1304         ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1305         if (ret < 0)
1306                 return ret;
1307 
1308         return 0;
1309 }
1310 
1311 static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
1312                                       unsigned int mode,
1313                                       const struct phylink_link_state *state)
1314 {
1315         struct mt7530_priv *priv = ds->priv;
1316         u32 mcr_cur, mcr_new;
1317 
1318         switch (port) {
1319         case 0: /* Internal phy */
1320         case 1:
1321         case 2:
1322         case 3:
1323         case 4:
1324                 if (state->interface != PHY_INTERFACE_MODE_GMII)
1325                         return;
1326                 break;
1327         case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1328                 if (priv->p5_interface == state->interface)
1329                         break;
1330                 if (!phy_interface_mode_is_rgmii(state->interface) &&
1331                     state->interface != PHY_INTERFACE_MODE_MII &&
1332                     state->interface != PHY_INTERFACE_MODE_GMII)
1333                         return;
1334 
1335                 mt7530_setup_port5(ds, state->interface);
1336                 break;
1337         case 6: /* 1st cpu port */
1338                 if (priv->p6_interface == state->interface)
1339                         break;
1340 
1341                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1342                     state->interface != PHY_INTERFACE_MODE_TRGMII)
1343                         return;
1344 
1345                 /* Setup TX circuit incluing relevant PAD and driving */
1346                 mt7530_pad_clk_setup(ds, state->interface);
1347 
1348                 priv->p6_interface = state->interface;
1349                 break;
1350         default:
1351                 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1352                 return;
1353         }
1354 
1355         if (phylink_autoneg_inband(mode)) {
1356                 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1357                         __func__);
1358                 return;
1359         }
1360 
1361         mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
1362         mcr_new = mcr_cur;
1363         mcr_new &= ~(PMCR_FORCE_SPEED_1000 | PMCR_FORCE_SPEED_100 |
1364                      PMCR_FORCE_FDX | PMCR_TX_FC_EN | PMCR_RX_FC_EN);
1365         mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
1366                    PMCR_BACKPR_EN | PMCR_FORCE_MODE;
1367 
1368         /* Are we connected to external phy */
1369         if (port == 5 && dsa_is_user_port(ds, 5))
1370                 mcr_new |= PMCR_EXT_PHY;
1371 
1372         switch (state->speed) {
1373         case SPEED_1000:
1374                 mcr_new |= PMCR_FORCE_SPEED_1000;
1375                 break;
1376         case SPEED_100:
1377                 mcr_new |= PMCR_FORCE_SPEED_100;
1378                 break;
1379         }
1380         if (state->duplex == DUPLEX_FULL) {
1381                 mcr_new |= PMCR_FORCE_FDX;
1382                 if (state->pause & MLO_PAUSE_TX)
1383                         mcr_new |= PMCR_TX_FC_EN;
1384                 if (state->pause & MLO_PAUSE_RX)
1385                         mcr_new |= PMCR_RX_FC_EN;
1386         }
1387 
1388         if (mcr_new != mcr_cur)
1389                 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
1390 }
1391 
1392 static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port,
1393                                          unsigned int mode,
1394                                          phy_interface_t interface)
1395 {
1396         struct mt7530_priv *priv = ds->priv;
1397 
1398         mt7530_port_set_status(priv, port, 0);
1399 }
1400 
1401 static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port,
1402                                        unsigned int mode,
1403                                        phy_interface_t interface,
1404                                        struct phy_device *phydev)
1405 {
1406         struct mt7530_priv *priv = ds->priv;
1407 
1408         mt7530_port_set_status(priv, port, 1);
1409 }
1410 
1411 static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
1412                                     unsigned long *supported,
1413                                     struct phylink_link_state *state)
1414 {
1415         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1416 
1417         switch (port) {
1418         case 0: /* Internal phy */
1419         case 1:
1420         case 2:
1421         case 3:
1422         case 4:
1423                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1424                     state->interface != PHY_INTERFACE_MODE_GMII)
1425                         goto unsupported;
1426                 break;
1427         case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1428                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1429                     !phy_interface_mode_is_rgmii(state->interface) &&
1430                     state->interface != PHY_INTERFACE_MODE_MII &&
1431                     state->interface != PHY_INTERFACE_MODE_GMII)
1432                         goto unsupported;
1433                 break;
1434         case 6: /* 1st cpu port */
1435                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1436                     state->interface != PHY_INTERFACE_MODE_RGMII &&
1437                     state->interface != PHY_INTERFACE_MODE_TRGMII)
1438                         goto unsupported;
1439                 break;
1440         default:
1441                 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1442 unsupported:
1443                 linkmode_zero(supported);
1444                 return;
1445         }
1446 
1447         phylink_set_port_modes(mask);
1448         phylink_set(mask, Autoneg);
1449 
1450         if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
1451                 phylink_set(mask, 1000baseT_Full);
1452         } else {
1453                 phylink_set(mask, 10baseT_Half);
1454                 phylink_set(mask, 10baseT_Full);
1455                 phylink_set(mask, 100baseT_Half);
1456                 phylink_set(mask, 100baseT_Full);
1457 
1458                 if (state->interface != PHY_INTERFACE_MODE_MII) {
1459                         phylink_set(mask, 1000baseT_Half);
1460                         phylink_set(mask, 1000baseT_Full);
1461                         if (port == 5)
1462                                 phylink_set(mask, 1000baseX_Full);
1463                 }
1464         }
1465 
1466         phylink_set(mask, Pause);
1467         phylink_set(mask, Asym_Pause);
1468 
1469         linkmode_and(supported, supported, mask);
1470         linkmode_and(state->advertising, state->advertising, mask);
1471 }
1472 
1473 static int
1474 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
1475                               struct phylink_link_state *state)
1476 {
1477         struct mt7530_priv *priv = ds->priv;
1478         u32 pmsr;
1479 
1480         if (port < 0 || port >= MT7530_NUM_PORTS)
1481                 return -EINVAL;
1482 
1483         pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
1484 
1485         state->link = (pmsr & PMSR_LINK);
1486         state->an_complete = state->link;
1487         state->duplex = !!(pmsr & PMSR_DPX);
1488 
1489         switch (pmsr & PMSR_SPEED_MASK) {
1490         case PMSR_SPEED_10:
1491                 state->speed = SPEED_10;
1492                 break;
1493         case PMSR_SPEED_100:
1494                 state->speed = SPEED_100;
1495                 break;
1496         case PMSR_SPEED_1000:
1497                 state->speed = SPEED_1000;
1498                 break;
1499         default:
1500                 state->speed = SPEED_UNKNOWN;
1501                 break;
1502         }
1503 
1504         state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
1505         if (pmsr & PMSR_RX_FC)
1506                 state->pause |= MLO_PAUSE_RX;
1507         if (pmsr & PMSR_TX_FC)
1508                 state->pause |= MLO_PAUSE_TX;
1509 
1510         return 1;
1511 }
1512 
1513 static const struct dsa_switch_ops mt7530_switch_ops = {
1514         .get_tag_protocol       = mtk_get_tag_protocol,
1515         .setup                  = mt7530_setup,
1516         .get_strings            = mt7530_get_strings,
1517         .phy_read               = mt7530_phy_read,
1518         .phy_write              = mt7530_phy_write,
1519         .get_ethtool_stats      = mt7530_get_ethtool_stats,
1520         .get_sset_count         = mt7530_get_sset_count,
1521         .port_enable            = mt7530_port_enable,
1522         .port_disable           = mt7530_port_disable,
1523         .port_stp_state_set     = mt7530_stp_state_set,
1524         .port_bridge_join       = mt7530_port_bridge_join,
1525         .port_bridge_leave      = mt7530_port_bridge_leave,
1526         .port_fdb_add           = mt7530_port_fdb_add,
1527         .port_fdb_del           = mt7530_port_fdb_del,
1528         .port_fdb_dump          = mt7530_port_fdb_dump,
1529         .port_vlan_filtering    = mt7530_port_vlan_filtering,
1530         .port_vlan_prepare      = mt7530_port_vlan_prepare,
1531         .port_vlan_add          = mt7530_port_vlan_add,
1532         .port_vlan_del          = mt7530_port_vlan_del,
1533         .phylink_validate       = mt7530_phylink_validate,
1534         .phylink_mac_link_state = mt7530_phylink_mac_link_state,
1535         .phylink_mac_config     = mt7530_phylink_mac_config,
1536         .phylink_mac_link_down  = mt7530_phylink_mac_link_down,
1537         .phylink_mac_link_up    = mt7530_phylink_mac_link_up,
1538 };
1539 
1540 static const struct of_device_id mt7530_of_match[] = {
1541         { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, },
1542         { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, },
1543         { /* sentinel */ },
1544 };
1545 MODULE_DEVICE_TABLE(of, mt7530_of_match);
1546 
1547 static int
1548 mt7530_probe(struct mdio_device *mdiodev)
1549 {
1550         struct mt7530_priv *priv;
1551         struct device_node *dn;
1552 
1553         dn = mdiodev->dev.of_node;
1554 
1555         priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1556         if (!priv)
1557                 return -ENOMEM;
1558 
1559         priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
1560         if (!priv->ds)
1561                 return -ENOMEM;
1562 
1563         /* Use medatek,mcm property to distinguish hardware type that would
1564          * casues a little bit differences on power-on sequence.
1565          */
1566         priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1567         if (priv->mcm) {
1568                 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1569 
1570                 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1571                 if (IS_ERR(priv->rstc)) {
1572                         dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1573                         return PTR_ERR(priv->rstc);
1574                 }
1575         }
1576 
1577         /* Get the hardware identifier from the devicetree node.
1578          * We will need it for some of the clock and regulator setup.
1579          */
1580         priv->id = (unsigned int)(unsigned long)
1581                 of_device_get_match_data(&mdiodev->dev);
1582 
1583         if (priv->id == ID_MT7530) {
1584                 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1585                 if (IS_ERR(priv->core_pwr))
1586                         return PTR_ERR(priv->core_pwr);
1587 
1588                 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1589                 if (IS_ERR(priv->io_pwr))
1590                         return PTR_ERR(priv->io_pwr);
1591         }
1592 
1593         /* Not MCM that indicates switch works as the remote standalone
1594          * integrated circuit so the GPIO pin would be used to complete
1595          * the reset, otherwise memory-mapped register accessing used
1596          * through syscon provides in the case of MCM.
1597          */
1598         if (!priv->mcm) {
1599                 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1600                                                       GPIOD_OUT_LOW);
1601                 if (IS_ERR(priv->reset)) {
1602                         dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1603                         return PTR_ERR(priv->reset);
1604                 }
1605         }
1606 
1607         priv->bus = mdiodev->bus;
1608         priv->dev = &mdiodev->dev;
1609         priv->ds->priv = priv;
1610         priv->ds->ops = &mt7530_switch_ops;
1611         mutex_init(&priv->reg_mutex);
1612         dev_set_drvdata(&mdiodev->dev, priv);
1613 
1614         return dsa_register_switch(priv->ds);
1615 }
1616 
1617 static void
1618 mt7530_remove(struct mdio_device *mdiodev)
1619 {
1620         struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1621         int ret = 0;
1622 
1623         ret = regulator_disable(priv->core_pwr);
1624         if (ret < 0)
1625                 dev_err(priv->dev,
1626                         "Failed to disable core power: %d\n", ret);
1627 
1628         ret = regulator_disable(priv->io_pwr);
1629         if (ret < 0)
1630                 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1631                         ret);
1632 
1633         dsa_unregister_switch(priv->ds);
1634         mutex_destroy(&priv->reg_mutex);
1635 }
1636 
1637 static struct mdio_driver mt7530_mdio_driver = {
1638         .probe  = mt7530_probe,
1639         .remove = mt7530_remove,
1640         .mdiodrv.driver = {
1641                 .name = "mt7530",
1642                 .of_match_table = mt7530_of_match,
1643         },
1644 };
1645 
1646 mdio_module_driver(mt7530_mdio_driver);
1647 
1648 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1649 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1650 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/dsa/mt7530.c

DEFINITIONS
