drivers/net/can/sja1000/plx

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This source file includes following definitions.
plx_pci_read_reg
plx_pci_write_reg
plx_pci_check_sja1000
plx_pci_reset_common
plx9056_pci_reset_common
plx_pci_reset_marathon_pci
plx_pci_reset_marathon_pcie
plx_pci_reset_asem_dual_can_raw
plx_pci_del_card
plx_pci_add_card
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
   4  *
   5  * Derived from the ems_pci.c driver:
   6  *      Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
   7  *      Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
   8  *      Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
   9  */
  10 
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/delay.h>
  16 #include <linux/slab.h>
  17 #include <linux/pci.h>
  18 #include <linux/can/dev.h>
  19 #include <linux/io.h>
  20 
  21 #include "sja1000.h"
  22 
  23 #define DRV_NAME  "sja1000_plx_pci"
  24 
  25 MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
  26 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
  27                    "the SJA1000 chips");
  28 MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
  29                         "Adlink PCI-7841/cPCI-7841 SE, "
  30                         "Marathon CAN-bus-PCI, "
  31                         "Marathon CAN-bus-PCIe, "
  32                         "TEWS TECHNOLOGIES TPMC810, "
  33                         "esd CAN-PCI/CPCI/PCI104/200, "
  34                         "esd CAN-PCI/PMC/266, "
  35                         "esd CAN-PCIe/2000, "
  36                         "Connect Tech Inc. CANpro/104-Plus Opto (CRG001), "
  37                         "IXXAT PC-I 04/PCI, "
  38                         "ELCUS CAN-200-PCI, "
  39                         "ASEM DUAL CAN-RAW")
  40 MODULE_LICENSE("GPL v2");
  41 
  42 #define PLX_PCI_MAX_CHAN 2
  43 
  44 struct plx_pci_card {
  45         int channels;                   /* detected channels count */
  46         struct net_device *net_dev[PLX_PCI_MAX_CHAN];
  47         void __iomem *conf_addr;
  48 
  49         /* Pointer to device-dependent reset function */
  50         void (*reset_func)(struct pci_dev *pdev);
  51 };
  52 
  53 #define PLX_PCI_CAN_CLOCK (16000000 / 2)
  54 
  55 /* PLX9030/9050/9052 registers */
  56 #define PLX_INTCSR      0x4c            /* Interrupt Control/Status */
  57 #define PLX_CNTRL       0x50            /* User I/O, Direct Slave Response,
  58                                          * Serial EEPROM, and Initialization
  59                                          * Control register
  60                                          */
  61 
  62 #define PLX_LINT1_EN    0x1             /* Local interrupt 1 enable */
  63 #define PLX_LINT1_POL   (1 << 1)        /* Local interrupt 1 polarity */
  64 #define PLX_LINT2_EN    (1 << 3)        /* Local interrupt 2 enable */
  65 #define PLX_LINT2_POL   (1 << 4)        /* Local interrupt 2 polarity */
  66 #define PLX_PCI_INT_EN  (1 << 6)        /* PCI Interrupt Enable */
  67 #define PLX_PCI_RESET   (1 << 30)       /* PCI Adapter Software Reset */
  68 
  69 /* PLX9056 registers */
  70 #define PLX9056_INTCSR  0x68            /* Interrupt Control/Status */
  71 #define PLX9056_CNTRL   0x6c            /* Control / Software Reset */
  72 
  73 #define PLX9056_LINTI   (1 << 11)
  74 #define PLX9056_PCI_INT_EN (1 << 8)
  75 #define PLX9056_PCI_RCR (1 << 29)       /* Read Configuration Registers */
  76 
  77 /*
  78  * The board configuration is probably following:
  79  * RX1 is connected to ground.
  80  * TX1 is not connected.
  81  * CLKO is not connected.
  82  * Setting the OCR register to 0xDA is a good idea.
  83  * This means normal output mode, push-pull and the correct polarity.
  84  */
  85 #define PLX_PCI_OCR     (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
  86 
  87 /* OCR setting for ASEM Dual CAN raw */
  88 #define ASEM_PCI_OCR    0xfe
  89 
  90 /*
  91  * In the CDR register, you should set CBP to 1.
  92  * You will probably also want to set the clock divider value to 7
  93  * (meaning direct oscillator output) because the second SJA1000 chip
  94  * is driven by the first one CLKOUT output.
  95  */
  96 #define PLX_PCI_CDR                     (CDR_CBP | CDR_CLKOUT_MASK)
  97 
  98 /* SJA1000 Control Register in the BasicCAN Mode */
  99 #define REG_CR                          0x00
 100 
 101 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
 102 #define REG_CR_BASICCAN_INITIAL         0x21
 103 #define REG_CR_BASICCAN_INITIAL_MASK    0xa1
 104 #define REG_SR_BASICCAN_INITIAL         0x0c
 105 #define REG_IR_BASICCAN_INITIAL         0xe0
 106 
 107 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
 108 #define REG_MOD_PELICAN_INITIAL         0x01
 109 #define REG_SR_PELICAN_INITIAL          0x3c
 110 #define REG_IR_PELICAN_INITIAL          0x00
 111 
 112 #define ADLINK_PCI_VENDOR_ID            0x144A
 113 #define ADLINK_PCI_DEVICE_ID            0x7841
 114 
 115 #define ESD_PCI_SUB_SYS_ID_PCI200       0x0004
 116 #define ESD_PCI_SUB_SYS_ID_PCI266       0x0009
 117 #define ESD_PCI_SUB_SYS_ID_PMC266       0x000e
 118 #define ESD_PCI_SUB_SYS_ID_CPCI200      0x010b
 119 #define ESD_PCI_SUB_SYS_ID_PCIE2000     0x0200
 120 #define ESD_PCI_SUB_SYS_ID_PCI104200    0x0501
 121 
 122 #define CAN200PCI_DEVICE_ID             0x9030
 123 #define CAN200PCI_VENDOR_ID             0x10b5
 124 #define CAN200PCI_SUB_DEVICE_ID         0x0301
 125 #define CAN200PCI_SUB_VENDOR_ID         0xe1c5
 126 
 127 #define IXXAT_PCI_VENDOR_ID             0x10b5
 128 #define IXXAT_PCI_DEVICE_ID             0x9050
 129 #define IXXAT_PCI_SUB_SYS_ID            0x2540
 130 
 131 #define MARATHON_PCI_DEVICE_ID          0x2715
 132 #define MARATHON_PCIE_DEVICE_ID         0x3432
 133 
 134 #define TEWS_PCI_VENDOR_ID              0x1498
 135 #define TEWS_PCI_DEVICE_ID_TMPC810      0x032A
 136 
 137 #define CTI_PCI_VENDOR_ID               0x12c4
 138 #define CTI_PCI_DEVICE_ID_CRG001        0x0900
 139 
 140 #define MOXA_PCI_VENDOR_ID              0x1393
 141 #define MOXA_PCI_DEVICE_ID              0x0100
 142 
 143 #define ASEM_RAW_CAN_VENDOR_ID          0x10b5
 144 #define ASEM_RAW_CAN_DEVICE_ID          0x9030
 145 #define ASEM_RAW_CAN_SUB_VENDOR_ID      0x3000
 146 #define ASEM_RAW_CAN_SUB_DEVICE_ID      0x1001
 147 #define ASEM_RAW_CAN_SUB_DEVICE_ID_BIS  0x1002
 148 #define ASEM_RAW_CAN_RST_REGISTER       0x54
 149 #define ASEM_RAW_CAN_RST_MASK_CAN1      0x20
 150 #define ASEM_RAW_CAN_RST_MASK_CAN2      0x04
 151 
 152 static void plx_pci_reset_common(struct pci_dev *pdev);
 153 static void plx9056_pci_reset_common(struct pci_dev *pdev);
 154 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev);
 155 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev);
 156 static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev);
 157 
 158 struct plx_pci_channel_map {
 159         u32 bar;
 160         u32 offset;
 161         u32 size;               /* 0x00 - auto, e.g. length of entire bar */
 162 };
 163 
 164 struct plx_pci_card_info {
 165         const char *name;
 166         int channel_count;
 167         u32 can_clock;
 168         u8 ocr;                 /* output control register */
 169         u8 cdr;                 /* clock divider register */
 170 
 171         /* Parameters for mapping local configuration space */
 172         struct plx_pci_channel_map conf_map;
 173 
 174         /* Parameters for mapping the SJA1000 chips */
 175         struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];
 176 
 177         /* Pointer to device-dependent reset function */
 178         void (*reset_func)(struct pci_dev *pdev);
 179 };
 180 
 181 static struct plx_pci_card_info plx_pci_card_info_adlink = {
 182         "Adlink PCI-7841/cPCI-7841", 2,
 183         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 184         {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
 185         &plx_pci_reset_common
 186         /* based on PLX9052 */
 187 };
 188 
 189 static struct plx_pci_card_info plx_pci_card_info_adlink_se = {
 190         "Adlink PCI-7841/cPCI-7841 SE", 2,
 191         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 192         {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
 193         &plx_pci_reset_common
 194         /* based on PLX9052 */
 195 };
 196 
 197 static struct plx_pci_card_info plx_pci_card_info_esd200 = {
 198         "esd CAN-PCI/CPCI/PCI104/200", 2,
 199         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 200         {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
 201         &plx_pci_reset_common
 202         /* based on PLX9030/9050 */
 203 };
 204 
 205 static struct plx_pci_card_info plx_pci_card_info_esd266 = {
 206         "esd CAN-PCI/PMC/266", 2,
 207         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 208         {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
 209         &plx9056_pci_reset_common
 210         /* based on PLX9056 */
 211 };
 212 
 213 static struct plx_pci_card_info plx_pci_card_info_esd2000 = {
 214         "esd CAN-PCIe/2000", 2,
 215         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 216         {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
 217         &plx9056_pci_reset_common
 218         /* based on PEX8311 */
 219 };
 220 
 221 static struct plx_pci_card_info plx_pci_card_info_ixxat = {
 222         "IXXAT PC-I 04/PCI", 2,
 223         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 224         {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} },
 225         &plx_pci_reset_common
 226         /* based on PLX9050 */
 227 };
 228 
 229 static struct plx_pci_card_info plx_pci_card_info_marathon_pci = {
 230         "Marathon CAN-bus-PCI", 2,
 231         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 232         {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
 233         &plx_pci_reset_marathon_pci
 234         /* based on PLX9052 */
 235 };
 236 
 237 static struct plx_pci_card_info plx_pci_card_info_marathon_pcie = {
 238         "Marathon CAN-bus-PCIe", 2,
 239         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 240         {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {3, 0x80, 0x00} },
 241         &plx_pci_reset_marathon_pcie
 242         /* based on PEX8311 */
 243 };
 244 
 245 static struct plx_pci_card_info plx_pci_card_info_tews = {
 246         "TEWS TECHNOLOGIES TPMC810", 2,
 247         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 248         {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
 249         &plx_pci_reset_common
 250         /* based on PLX9030 */
 251 };
 252 
 253 static struct plx_pci_card_info plx_pci_card_info_cti = {
 254         "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2,
 255         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 256         {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
 257         &plx_pci_reset_common
 258         /* based on PLX9030 */
 259 };
 260 
 261 static struct plx_pci_card_info plx_pci_card_info_elcus = {
 262         "Eclus CAN-200-PCI", 2,
 263         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 264         {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} },
 265         &plx_pci_reset_common
 266         /* based on PLX9030 */
 267 };
 268 
 269 static struct plx_pci_card_info plx_pci_card_info_moxa = {
 270         "MOXA", 2,
 271         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 272         {0, 0x00, 0x00}, { {0, 0x00, 0x80}, {1, 0x00, 0x80} },
 273         &plx_pci_reset_common
 274          /* based on PLX9052 */
 275 };
 276 
 277 static struct plx_pci_card_info plx_pci_card_info_asem_dual_can = {
 278         "ASEM Dual CAN raw PCI", 2,
 279         PLX_PCI_CAN_CLOCK, ASEM_PCI_OCR, PLX_PCI_CDR,
 280         {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
 281         &plx_pci_reset_asem_dual_can_raw
 282         /* based on PLX9030 */
 283 };
 284 
 285 static const struct pci_device_id plx_pci_tbl[] = {
 286         {
 287                 /* Adlink PCI-7841/cPCI-7841 */
 288                 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
 289                 PCI_ANY_ID, PCI_ANY_ID,
 290                 PCI_CLASS_NETWORK_OTHER << 8, ~0,
 291                 (kernel_ulong_t)&plx_pci_card_info_adlink
 292         },
 293         {
 294                 /* Adlink PCI-7841/cPCI-7841 SE */
 295                 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
 296                 PCI_ANY_ID, PCI_ANY_ID,
 297                 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
 298                 (kernel_ulong_t)&plx_pci_card_info_adlink_se
 299         },
 300         {
 301                 /* esd CAN-PCI/200 */
 302                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
 303                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200,
 304                 0, 0,
 305                 (kernel_ulong_t)&plx_pci_card_info_esd200
 306         },
 307         {
 308                 /* esd CAN-CPCI/200 */
 309                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
 310                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200,
 311                 0, 0,
 312                 (kernel_ulong_t)&plx_pci_card_info_esd200
 313         },
 314         {
 315                 /* esd CAN-PCI104/200 */
 316                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
 317                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200,
 318                 0, 0,
 319                 (kernel_ulong_t)&plx_pci_card_info_esd200
 320         },
 321         {
 322                 /* esd CAN-PCI/266 */
 323                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
 324                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266,
 325                 0, 0,
 326                 (kernel_ulong_t)&plx_pci_card_info_esd266
 327         },
 328         {
 329                 /* esd CAN-PMC/266 */
 330                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
 331                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266,
 332                 0, 0,
 333                 (kernel_ulong_t)&plx_pci_card_info_esd266
 334         },
 335         {
 336                 /* esd CAN-PCIE/2000 */
 337                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
 338                 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000,
 339                 0, 0,
 340                 (kernel_ulong_t)&plx_pci_card_info_esd2000
 341         },
 342         {
 343                 /* IXXAT PC-I 04/PCI card */
 344                 IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID,
 345                 PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID,
 346                 0, 0,
 347                 (kernel_ulong_t)&plx_pci_card_info_ixxat
 348         },
 349         {
 350                 /* Marathon CAN-bus-PCI card */
 351                 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
 352                 PCI_ANY_ID, PCI_ANY_ID,
 353                 0, 0,
 354                 (kernel_ulong_t)&plx_pci_card_info_marathon_pci
 355         },
 356         {
 357                 /* Marathon CAN-bus-PCIe card */
 358                 PCI_VENDOR_ID_PLX, MARATHON_PCIE_DEVICE_ID,
 359                 PCI_ANY_ID, PCI_ANY_ID,
 360                 0, 0,
 361                 (kernel_ulong_t)&plx_pci_card_info_marathon_pcie
 362         },
 363         {
 364                 /* TEWS TECHNOLOGIES TPMC810 card */
 365                 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
 366                 PCI_ANY_ID, PCI_ANY_ID,
 367                 0, 0,
 368                 (kernel_ulong_t)&plx_pci_card_info_tews
 369         },
 370         {
 371                 /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */
 372                 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
 373                 CTI_PCI_VENDOR_ID, CTI_PCI_DEVICE_ID_CRG001,
 374                 0, 0,
 375                 (kernel_ulong_t)&plx_pci_card_info_cti
 376         },
 377         {
 378                 /* Elcus CAN-200-PCI */
 379                 CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID,
 380                 CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID,
 381                 0, 0,
 382                 (kernel_ulong_t)&plx_pci_card_info_elcus
 383         },
 384         {
 385                 /* moxa */
 386                 MOXA_PCI_VENDOR_ID, MOXA_PCI_DEVICE_ID,
 387                 PCI_ANY_ID, PCI_ANY_ID,
 388                 0, 0,
 389                 (kernel_ulong_t)&plx_pci_card_info_moxa
 390         },
 391         {
 392                 /* ASEM Dual CAN raw */
 393                 ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID,
 394                 ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID,
 395                 0, 0,
 396                 (kernel_ulong_t)&plx_pci_card_info_asem_dual_can
 397         },
 398         {
 399                 /* ASEM Dual CAN raw -new model */
 400                 ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID,
 401                 ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID_BIS,
 402                 0, 0,
 403                 (kernel_ulong_t)&plx_pci_card_info_asem_dual_can
 404         },
 405         { 0,}
 406 };
 407 MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
 408 
 409 static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
 410 {
 411         return ioread8(priv->reg_base + port);
 412 }
 413 
 414 static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
 415 {
 416         iowrite8(val, priv->reg_base + port);
 417 }
 418 
 419 /*
 420  * Check if a CAN controller is present at the specified location
 421  * by trying to switch 'em from the Basic mode into the PeliCAN mode.
 422  * Also check states of some registers in reset mode.
 423  */
 424 static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
 425 {
 426         int flag = 0;
 427 
 428         /*
 429          * Check registers after hardware reset (the Basic mode)
 430          * See states on p. 10 of the Datasheet.
 431          */
 432         if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
 433             REG_CR_BASICCAN_INITIAL &&
 434             (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) &&
 435             (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL))
 436                 flag = 1;
 437 
 438         /* Bring the SJA1000 into the PeliCAN mode*/
 439         priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
 440 
 441         /*
 442          * Check registers after reset in the PeliCAN mode.
 443          * See states on p. 23 of the Datasheet.
 444          */
 445         if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL &&
 446             priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL &&
 447             priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL)
 448                 return flag;
 449 
 450         return 0;
 451 }
 452 
 453 /*
 454  * PLX9030/50/52 software reset
 455  * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
 456  * For most cards it's enough for reset the SJA1000 chips.
 457  */
 458 static void plx_pci_reset_common(struct pci_dev *pdev)
 459 {
 460         struct plx_pci_card *card = pci_get_drvdata(pdev);
 461         u32 cntrl;
 462 
 463         cntrl = ioread32(card->conf_addr + PLX_CNTRL);
 464         cntrl |= PLX_PCI_RESET;
 465         iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
 466         udelay(100);
 467         cntrl ^= PLX_PCI_RESET;
 468         iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
 469 };
 470 
 471 /*
 472  * PLX9056 software reset
 473  * Assert LRESET# and reset device(s) on the Local Bus (if wired).
 474  */
 475 static void plx9056_pci_reset_common(struct pci_dev *pdev)
 476 {
 477         struct plx_pci_card *card = pci_get_drvdata(pdev);
 478         u32 cntrl;
 479 
 480         /* issue a local bus reset */
 481         cntrl = ioread32(card->conf_addr + PLX9056_CNTRL);
 482         cntrl |= PLX_PCI_RESET;
 483         iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
 484         udelay(100);
 485         cntrl ^= PLX_PCI_RESET;
 486         iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
 487 
 488         /* reload local configuration from EEPROM */
 489         cntrl |= PLX9056_PCI_RCR;
 490         iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
 491 
 492         /*
 493          * There is no safe way to poll for the end
 494          * of reconfiguration process. Waiting for 10ms
 495          * is safe.
 496          */
 497         mdelay(10);
 498 
 499         cntrl ^= PLX9056_PCI_RCR;
 500         iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
 501 };
 502 
 503 /* Special reset function for Marathon CAN-bus-PCI card */
 504 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev)
 505 {
 506         void __iomem *reset_addr;
 507         int i;
 508         static const int reset_bar[2] = {3, 5};
 509 
 510         plx_pci_reset_common(pdev);
 511 
 512         for (i = 0; i < 2; i++) {
 513                 reset_addr = pci_iomap(pdev, reset_bar[i], 0);
 514                 if (!reset_addr) {
 515                         dev_err(&pdev->dev, "Failed to remap reset "
 516                                 "space %d (BAR%d)\n", i, reset_bar[i]);
 517                 } else {
 518                         /* reset the SJA1000 chip */
 519                         iowrite8(0x1, reset_addr);
 520                         udelay(100);
 521                         pci_iounmap(pdev, reset_addr);
 522                 }
 523         }
 524 }
 525 
 526 /* Special reset function for Marathon CAN-bus-PCIe card */
 527 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev)
 528 {
 529         void __iomem *addr;
 530         void __iomem *reset_addr;
 531         int i;
 532 
 533         plx9056_pci_reset_common(pdev);
 534 
 535         for (i = 0; i < 2; i++) {
 536                 struct plx_pci_channel_map *chan_map =
 537                         &plx_pci_card_info_marathon_pcie.chan_map_tbl[i];
 538                 addr = pci_iomap(pdev, chan_map->bar, chan_map->size);
 539                 if (!addr) {
 540                         dev_err(&pdev->dev, "Failed to remap reset "
 541                                 "space %d (BAR%d)\n", i, chan_map->bar);
 542                 } else {
 543                         /* reset the SJA1000 chip */
 544                         #define MARATHON_PCIE_RESET_OFFSET 32
 545                         reset_addr = addr + chan_map->offset +
 546                                      MARATHON_PCIE_RESET_OFFSET;
 547                         iowrite8(0x1, reset_addr);
 548                         udelay(100);
 549                         pci_iounmap(pdev, addr);
 550                 }
 551         }
 552 }
 553 
 554 /* Special reset function for ASEM Dual CAN raw card */
 555 static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev)
 556 {
 557         void __iomem *bar0_addr;
 558         u8 tmpval;
 559 
 560         plx_pci_reset_common(pdev);
 561 
 562         bar0_addr = pci_iomap(pdev, 0, 0);
 563         if (!bar0_addr) {
 564                 dev_err(&pdev->dev, "Failed to remap reset space 0 (BAR0)\n");
 565                 return;
 566         }
 567 
 568         /* reset the two SJA1000 chips */
 569         tmpval = ioread8(bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
 570         tmpval &= ~(ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2);
 571         iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
 572         usleep_range(300, 400);
 573         tmpval |= ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2;
 574         iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
 575         usleep_range(300, 400);
 576         pci_iounmap(pdev, bar0_addr);
 577 }
 578 
 579 static void plx_pci_del_card(struct pci_dev *pdev)
 580 {
 581         struct plx_pci_card *card = pci_get_drvdata(pdev);
 582         struct net_device *dev;
 583         struct sja1000_priv *priv;
 584         int i = 0;
 585 
 586         for (i = 0; i < PLX_PCI_MAX_CHAN; i++) {
 587                 dev = card->net_dev[i];
 588                 if (!dev)
 589                         continue;
 590 
 591                 dev_info(&pdev->dev, "Removing %s\n", dev->name);
 592                 unregister_sja1000dev(dev);
 593                 priv = netdev_priv(dev);
 594                 if (priv->reg_base)
 595                         pci_iounmap(pdev, priv->reg_base);
 596                 free_sja1000dev(dev);
 597         }
 598 
 599         card->reset_func(pdev);
 600 
 601         /*
 602          * Disable interrupts from PCI-card and disable local
 603          * interrupts
 604          */
 605         if (pdev->device != PCI_DEVICE_ID_PLX_9056 &&
 606             pdev->device != MARATHON_PCIE_DEVICE_ID)
 607                 iowrite32(0x0, card->conf_addr + PLX_INTCSR);
 608         else
 609                 iowrite32(0x0, card->conf_addr + PLX9056_INTCSR);
 610 
 611         if (card->conf_addr)
 612                 pci_iounmap(pdev, card->conf_addr);
 613 
 614         kfree(card);
 615 
 616         pci_disable_device(pdev);
 617 }
 618 
 619 /*
 620  * Probe PLX90xx based device for the SJA1000 chips and register each
 621  * available CAN channel to SJA1000 Socket-CAN subsystem.
 622  */
 623 static int plx_pci_add_card(struct pci_dev *pdev,
 624                             const struct pci_device_id *ent)
 625 {
 626         struct sja1000_priv *priv;
 627         struct net_device *dev;
 628         struct plx_pci_card *card;
 629         struct plx_pci_card_info *ci;
 630         int err, i;
 631         u32 val;
 632         void __iomem *addr;
 633 
 634         ci = (struct plx_pci_card_info *)ent->driver_data;
 635 
 636         if (pci_enable_device(pdev) < 0) {
 637                 dev_err(&pdev->dev, "Failed to enable PCI device\n");
 638                 return -ENODEV;
 639         }
 640 
 641         dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
 642                  ci->name, PCI_SLOT(pdev->devfn));
 643 
 644         /* Allocate card structures to hold addresses, ... */
 645         card = kzalloc(sizeof(*card), GFP_KERNEL);
 646         if (!card) {
 647                 pci_disable_device(pdev);
 648                 return -ENOMEM;
 649         }
 650 
 651         pci_set_drvdata(pdev, card);
 652 
 653         card->channels = 0;
 654 
 655         /* Remap PLX90xx configuration space */
 656         addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
 657         if (!addr) {
 658                 err = -ENOMEM;
 659                 dev_err(&pdev->dev, "Failed to remap configuration space "
 660                         "(BAR%d)\n", ci->conf_map.bar);
 661                 goto failure_cleanup;
 662         }
 663         card->conf_addr = addr + ci->conf_map.offset;
 664 
 665         ci->reset_func(pdev);
 666         card->reset_func = ci->reset_func;
 667 
 668         /* Detect available channels */
 669         for (i = 0; i < ci->channel_count; i++) {
 670                 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];
 671 
 672                 dev = alloc_sja1000dev(0);
 673                 if (!dev) {
 674                         err = -ENOMEM;
 675                         goto failure_cleanup;
 676                 }
 677 
 678                 card->net_dev[i] = dev;
 679                 priv = netdev_priv(dev);
 680                 priv->priv = card;
 681                 priv->irq_flags = IRQF_SHARED;
 682 
 683                 dev->irq = pdev->irq;
 684 
 685                 /*
 686                  * Remap IO space of the SJA1000 chips
 687                  * This is device-dependent mapping
 688                  */
 689                 addr = pci_iomap(pdev, cm->bar, cm->size);
 690                 if (!addr) {
 691                         err = -ENOMEM;
 692                         dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
 693                         goto failure_cleanup;
 694                 }
 695 
 696                 priv->reg_base = addr + cm->offset;
 697                 priv->read_reg = plx_pci_read_reg;
 698                 priv->write_reg = plx_pci_write_reg;
 699 
 700                 /* Check if channel is present */
 701                 if (plx_pci_check_sja1000(priv)) {
 702                         priv->can.clock.freq = ci->can_clock;
 703                         priv->ocr = ci->ocr;
 704                         priv->cdr = ci->cdr;
 705 
 706                         SET_NETDEV_DEV(dev, &pdev->dev);
 707                         dev->dev_id = i;
 708 
 709                         /* Register SJA1000 device */
 710                         err = register_sja1000dev(dev);
 711                         if (err) {
 712                                 dev_err(&pdev->dev, "Registering device failed "
 713                                         "(err=%d)\n", err);
 714                                 goto failure_cleanup;
 715                         }
 716 
 717                         card->channels++;
 718 
 719                         dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
 720                                  "registered as %s\n", i + 1, priv->reg_base,
 721                                  dev->irq, dev->name);
 722                 } else {
 723                         dev_err(&pdev->dev, "Channel #%d not detected\n",
 724                                 i + 1);
 725                         free_sja1000dev(dev);
 726                         card->net_dev[i] = NULL;
 727                 }
 728         }
 729 
 730         if (!card->channels) {
 731                 err = -ENODEV;
 732                 goto failure_cleanup;
 733         }
 734 
 735         /*
 736          * Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
 737          * Local_2 interrupts from the SJA1000 chips
 738          */
 739         if (pdev->device != PCI_DEVICE_ID_PLX_9056 &&
 740             pdev->device != MARATHON_PCIE_DEVICE_ID) {
 741                 val = ioread32(card->conf_addr + PLX_INTCSR);
 742                 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH)
 743                         val |= PLX_LINT1_EN | PLX_PCI_INT_EN;
 744                 else
 745                         val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN;
 746                 iowrite32(val, card->conf_addr + PLX_INTCSR);
 747         } else {
 748                 iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN,
 749                           card->conf_addr + PLX9056_INTCSR);
 750         }
 751         return 0;
 752 
 753 failure_cleanup:
 754         dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
 755 
 756         plx_pci_del_card(pdev);
 757 
 758         return err;
 759 }
 760 
 761 static struct pci_driver plx_pci_driver = {
 762         .name = DRV_NAME,
 763         .id_table = plx_pci_tbl,
 764         .probe = plx_pci_add_card,
 765         .remove = plx_pci_del_card,
 766 };
 767 
 768 module_pci_driver(plx_pci_driver);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/can/sja1000/plx_pci.c

DEFINITIONS
