drivers/net/can/sja1000/ems

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This source file includes following definitions.
ems_pci_v1_readb
ems_pci_v1_read_reg
ems_pci_v1_write_reg
ems_pci_v1_post_irq
ems_pci_v2_read_reg
ems_pci_v2_write_reg
ems_pci_v2_post_irq
ems_pci_check_chan
ems_pci_del_card
ems_pci_card_reset
ems_pci_add_card
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
   4  * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
   5  * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
   6  */
   7 
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/pci.h>
  15 #include <linux/can/dev.h>
  16 #include <linux/io.h>
  17 
  18 #include "sja1000.h"
  19 
  20 #define DRV_NAME  "ems_pci"
  21 
  22 MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
  23 MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
  24 MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card");
  25 MODULE_LICENSE("GPL v2");
  26 
  27 #define EMS_PCI_V1_MAX_CHAN 2
  28 #define EMS_PCI_V2_MAX_CHAN 4
  29 #define EMS_PCI_MAX_CHAN    EMS_PCI_V2_MAX_CHAN
  30 
  31 struct ems_pci_card {
  32         int version;
  33         int channels;
  34 
  35         struct pci_dev *pci_dev;
  36         struct net_device *net_dev[EMS_PCI_MAX_CHAN];
  37 
  38         void __iomem *conf_addr;
  39         void __iomem *base_addr;
  40 };
  41 
  42 #define EMS_PCI_CAN_CLOCK (16000000 / 2)
  43 
  44 /*
  45  * Register definitions and descriptions are from LinCAN 0.3.3.
  46  *
  47  * PSB4610 PITA-2 bridge control registers
  48  */
  49 #define PITA2_ICR           0x00        /* Interrupt Control Register */
  50 #define PITA2_ICR_INT0      0x00000002  /* [RC] INT0 Active/Clear */
  51 #define PITA2_ICR_INT0_EN   0x00020000  /* [RW] Enable INT0 */
  52 
  53 #define PITA2_MISC          0x1c        /* Miscellaneous Register */
  54 #define PITA2_MISC_CONFIG   0x04000000  /* Multiplexed parallel interface */
  55 
  56 /*
  57  * Register definitions for the PLX 9030
  58  */
  59 #define PLX_ICSR            0x4c   /* Interrupt Control/Status register */
  60 #define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
  61 #define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
  62 #define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
  63 #define PLX_ICSR_ENA_CLR    (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
  64                              PLX_ICSR_LINTI1_CLR)
  65 
  66 /*
  67  * The board configuration is probably following:
  68  * RX1 is connected to ground.
  69  * TX1 is not connected.
  70  * CLKO is not connected.
  71  * Setting the OCR register to 0xDA is a good idea.
  72  * This means normal output mode, push-pull and the correct polarity.
  73  */
  74 #define EMS_PCI_OCR         (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
  75 
  76 /*
  77  * In the CDR register, you should set CBP to 1.
  78  * You will probably also want to set the clock divider value to 7
  79  * (meaning direct oscillator output) because the second SJA1000 chip
  80  * is driven by the first one CLKOUT output.
  81  */
  82 #define EMS_PCI_CDR             (CDR_CBP | CDR_CLKOUT_MASK)
  83 
  84 #define EMS_PCI_V1_BASE_BAR     1
  85 #define EMS_PCI_V1_CONF_SIZE    4096 /* size of PITA control area */
  86 #define EMS_PCI_V2_BASE_BAR     2
  87 #define EMS_PCI_V2_CONF_SIZE    128 /* size of PLX control area */
  88 #define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
  89 #define EMS_PCI_CAN_CTRL_SIZE   0x200 /* memory size for each controller */
  90 
  91 #define EMS_PCI_BASE_SIZE  4096 /* size of controller area */
  92 
  93 static const struct pci_device_id ems_pci_tbl[] = {
  94         /* CPC-PCI v1 */
  95         {PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
  96         /* CPC-PCI v2 */
  97         {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
  98         /* CPC-104P v2 */
  99         {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
 100         {0,}
 101 };
 102 MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
 103 
 104 /*
 105  * Helper to read internal registers from card logic (not CAN)
 106  */
 107 static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
 108 {
 109         return readb(card->base_addr + (port * 4));
 110 }
 111 
 112 static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
 113 {
 114         return readb(priv->reg_base + (port * 4));
 115 }
 116 
 117 static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
 118                                  int port, u8 val)
 119 {
 120         writeb(val, priv->reg_base + (port * 4));
 121 }
 122 
 123 static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
 124 {
 125         struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
 126 
 127         /* reset int flag of pita */
 128         writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
 129                card->conf_addr + PITA2_ICR);
 130 }
 131 
 132 static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
 133 {
 134         return readb(priv->reg_base + port);
 135 }
 136 
 137 static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
 138                                  int port, u8 val)
 139 {
 140         writeb(val, priv->reg_base + port);
 141 }
 142 
 143 static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
 144 {
 145         struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
 146 
 147         writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
 148 }
 149 
 150 /*
 151  * Check if a CAN controller is present at the specified location
 152  * by trying to set 'em into the PeliCAN mode
 153  */
 154 static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
 155 {
 156         unsigned char res;
 157 
 158         /* Make sure SJA1000 is in reset mode */
 159         priv->write_reg(priv, SJA1000_MOD, 1);
 160 
 161         priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
 162 
 163         /* read reset-values */
 164         res = priv->read_reg(priv, SJA1000_CDR);
 165 
 166         if (res == CDR_PELICAN)
 167                 return 1;
 168 
 169         return 0;
 170 }
 171 
 172 static void ems_pci_del_card(struct pci_dev *pdev)
 173 {
 174         struct ems_pci_card *card = pci_get_drvdata(pdev);
 175         struct net_device *dev;
 176         int i = 0;
 177 
 178         for (i = 0; i < card->channels; i++) {
 179                 dev = card->net_dev[i];
 180 
 181                 if (!dev)
 182                         continue;
 183 
 184                 dev_info(&pdev->dev, "Removing %s.\n", dev->name);
 185                 unregister_sja1000dev(dev);
 186                 free_sja1000dev(dev);
 187         }
 188 
 189         if (card->base_addr != NULL)
 190                 pci_iounmap(card->pci_dev, card->base_addr);
 191 
 192         if (card->conf_addr != NULL)
 193                 pci_iounmap(card->pci_dev, card->conf_addr);
 194 
 195         kfree(card);
 196 
 197         pci_disable_device(pdev);
 198 }
 199 
 200 static void ems_pci_card_reset(struct ems_pci_card *card)
 201 {
 202         /* Request board reset */
 203         writeb(0, card->base_addr);
 204 }
 205 
 206 /*
 207  * Probe PCI device for EMS CAN signature and register each available
 208  * CAN channel to SJA1000 Socket-CAN subsystem.
 209  */
 210 static int ems_pci_add_card(struct pci_dev *pdev,
 211                             const struct pci_device_id *ent)
 212 {
 213         struct sja1000_priv *priv;
 214         struct net_device *dev;
 215         struct ems_pci_card *card;
 216         int max_chan, conf_size, base_bar;
 217         int err, i;
 218 
 219         /* Enabling PCI device */
 220         if (pci_enable_device(pdev) < 0) {
 221                 dev_err(&pdev->dev, "Enabling PCI device failed\n");
 222                 return -ENODEV;
 223         }
 224 
 225         /* Allocating card structures to hold addresses, ... */
 226         card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
 227         if (card == NULL) {
 228                 pci_disable_device(pdev);
 229                 return -ENOMEM;
 230         }
 231 
 232         pci_set_drvdata(pdev, card);
 233 
 234         card->pci_dev = pdev;
 235 
 236         card->channels = 0;
 237 
 238         if (pdev->vendor == PCI_VENDOR_ID_PLX) {
 239                 card->version = 2; /* CPC-PCI v2 */
 240                 max_chan = EMS_PCI_V2_MAX_CHAN;
 241                 base_bar = EMS_PCI_V2_BASE_BAR;
 242                 conf_size = EMS_PCI_V2_CONF_SIZE;
 243         } else {
 244                 card->version = 1; /* CPC-PCI v1 */
 245                 max_chan = EMS_PCI_V1_MAX_CHAN;
 246                 base_bar = EMS_PCI_V1_BASE_BAR;
 247                 conf_size = EMS_PCI_V1_CONF_SIZE;
 248         }
 249 
 250         /* Remap configuration space and controller memory area */
 251         card->conf_addr = pci_iomap(pdev, 0, conf_size);
 252         if (card->conf_addr == NULL) {
 253                 err = -ENOMEM;
 254                 goto failure_cleanup;
 255         }
 256 
 257         card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
 258         if (card->base_addr == NULL) {
 259                 err = -ENOMEM;
 260                 goto failure_cleanup;
 261         }
 262 
 263         if (card->version == 1) {
 264                 /* Configure PITA-2 parallel interface (enable MUX) */
 265                 writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
 266 
 267                 /* Check for unique EMS CAN signature */
 268                 if (ems_pci_v1_readb(card, 0) != 0x55 ||
 269                     ems_pci_v1_readb(card, 1) != 0xAA ||
 270                     ems_pci_v1_readb(card, 2) != 0x01 ||
 271                     ems_pci_v1_readb(card, 3) != 0xCB ||
 272                     ems_pci_v1_readb(card, 4) != 0x11) {
 273                         dev_err(&pdev->dev,
 274                                 "Not EMS Dr. Thomas Wuensche interface\n");
 275                         err = -ENODEV;
 276                         goto failure_cleanup;
 277                 }
 278         }
 279 
 280         ems_pci_card_reset(card);
 281 
 282         /* Detect available channels */
 283         for (i = 0; i < max_chan; i++) {
 284                 dev = alloc_sja1000dev(0);
 285                 if (dev == NULL) {
 286                         err = -ENOMEM;
 287                         goto failure_cleanup;
 288                 }
 289 
 290                 card->net_dev[i] = dev;
 291                 priv = netdev_priv(dev);
 292                 priv->priv = card;
 293                 priv->irq_flags = IRQF_SHARED;
 294 
 295                 dev->irq = pdev->irq;
 296                 priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
 297                                         + (i * EMS_PCI_CAN_CTRL_SIZE);
 298                 if (card->version == 1) {
 299                         priv->read_reg  = ems_pci_v1_read_reg;
 300                         priv->write_reg = ems_pci_v1_write_reg;
 301                         priv->post_irq  = ems_pci_v1_post_irq;
 302                 } else {
 303                         priv->read_reg  = ems_pci_v2_read_reg;
 304                         priv->write_reg = ems_pci_v2_write_reg;
 305                         priv->post_irq  = ems_pci_v2_post_irq;
 306                 }
 307 
 308                 /* Check if channel is present */
 309                 if (ems_pci_check_chan(priv)) {
 310                         priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
 311                         priv->ocr = EMS_PCI_OCR;
 312                         priv->cdr = EMS_PCI_CDR;
 313 
 314                         SET_NETDEV_DEV(dev, &pdev->dev);
 315                         dev->dev_id = i;
 316 
 317                         if (card->version == 1)
 318                                 /* reset int flag of pita */
 319                                 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
 320                                        card->conf_addr + PITA2_ICR);
 321                         else
 322                                 /* enable IRQ in PLX 9030 */
 323                                 writel(PLX_ICSR_ENA_CLR,
 324                                        card->conf_addr + PLX_ICSR);
 325 
 326                         /* Register SJA1000 device */
 327                         err = register_sja1000dev(dev);
 328                         if (err) {
 329                                 dev_err(&pdev->dev, "Registering device failed "
 330                                                         "(err=%d)\n", err);
 331                                 free_sja1000dev(dev);
 332                                 goto failure_cleanup;
 333                         }
 334 
 335                         card->channels++;
 336 
 337                         dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
 338                                         i + 1, priv->reg_base, dev->irq);
 339                 } else {
 340                         free_sja1000dev(dev);
 341                 }
 342         }
 343 
 344         return 0;
 345 
 346 failure_cleanup:
 347         dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
 348 
 349         ems_pci_del_card(pdev);
 350 
 351         return err;
 352 }
 353 
 354 static struct pci_driver ems_pci_driver = {
 355         .name = DRV_NAME,
 356         .id_table = ems_pci_tbl,
 357         .probe = ems_pci_add_card,
 358         .remove = ems_pci_del_card,
 359 };
 360 
 361 module_pci_driver(ems_pci_driver);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/can/sja1000/ems_pci.c

DEFINITIONS
