drivers/net/can/flexcan.c

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This source file includes following definitions.
flexcan_read_be
flexcan_write_be
flexcan_read_le
flexcan_write_le
flexcan_get_mb
flexcan_low_power_enter_ack
flexcan_low_power_exit_ack
flexcan_enable_wakeup_irq
flexcan_enter_stop_mode
flexcan_exit_stop_mode
flexcan_error_irq_enable
flexcan_error_irq_disable
flexcan_clks_enable
flexcan_clks_disable
flexcan_transceiver_enable
flexcan_transceiver_disable
flexcan_chip_enable
flexcan_chip_disable
flexcan_chip_freeze
flexcan_chip_unfreeze
flexcan_chip_softreset
__flexcan_get_berr_counter
flexcan_get_berr_counter
flexcan_start_xmit
flexcan_irq_bus_err
flexcan_irq_state
rx_offload_to_priv
flexcan_mailbox_read
flexcan_read_reg_iflag_rx
flexcan_irq
flexcan_set_bittiming
flexcan_chip_start
flexcan_chip_stop
flexcan_open
flexcan_close
flexcan_set_mode
register_flexcandev
unregister_flexcandev
flexcan_setup_stop_mode
flexcan_probe
flexcan_remove
flexcan_suspend
flexcan_resume
flexcan_runtime_suspend
flexcan_runtime_resume
flexcan_noirq_suspend
flexcan_noirq_resume
   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // flexcan.c - FLEXCAN CAN controller driver
   4 //
   5 // Copyright (c) 2005-2006 Varma Electronics Oy
   6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
   7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   8 // Copyright (c) 2014 David Jander, Protonic Holland
   9 //
  10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11 
  12 #include <linux/netdevice.h>
  13 #include <linux/can.h>
  14 #include <linux/can/dev.h>
  15 #include <linux/can/error.h>
  16 #include <linux/can/led.h>
  17 #include <linux/can/rx-offload.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/regulator/consumer.h>
  29 #include <linux/regmap.h>
  30 
  31 #define DRV_NAME                        "flexcan"
  32 
  33 /* 8 for RX fifo and 2 error handling */
  34 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  35 
  36 /* FLEXCAN module configuration register (CANMCR) bits */
  37 #define FLEXCAN_MCR_MDIS                BIT(31)
  38 #define FLEXCAN_MCR_FRZ                 BIT(30)
  39 #define FLEXCAN_MCR_FEN                 BIT(29)
  40 #define FLEXCAN_MCR_HALT                BIT(28)
  41 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  42 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  43 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  44 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  45 #define FLEXCAN_MCR_SUPV                BIT(23)
  46 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  47 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  48 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  49 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  50 #define FLEXCAN_MCR_DOZE                BIT(18)
  51 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  52 #define FLEXCAN_MCR_IRMQ                BIT(16)
  53 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  54 #define FLEXCAN_MCR_AEN                 BIT(12)
  55 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  56 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0x7f)
  57 #define FLEXCAN_MCR_IDAM_A              (0x0 << 8)
  58 #define FLEXCAN_MCR_IDAM_B              (0x1 << 8)
  59 #define FLEXCAN_MCR_IDAM_C              (0x2 << 8)
  60 #define FLEXCAN_MCR_IDAM_D              (0x3 << 8)
  61 
  62 /* FLEXCAN control register (CANCTRL) bits */
  63 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  64 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  65 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  66 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  67 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  68 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  69 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  70 #define FLEXCAN_CTRL_LPB                BIT(12)
  71 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  72 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  73 #define FLEXCAN_CTRL_SMP                BIT(7)
  74 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  75 #define FLEXCAN_CTRL_TSYN               BIT(5)
  76 #define FLEXCAN_CTRL_LBUF               BIT(4)
  77 #define FLEXCAN_CTRL_LOM                BIT(3)
  78 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  79 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  80 #define FLEXCAN_CTRL_ERR_STATE \
  81         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  82          FLEXCAN_CTRL_BOFF_MSK)
  83 #define FLEXCAN_CTRL_ERR_ALL \
  84         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  85 
  86 /* FLEXCAN control register 2 (CTRL2) bits */
  87 #define FLEXCAN_CTRL2_ECRWRE            BIT(29)
  88 #define FLEXCAN_CTRL2_WRMFRZ            BIT(28)
  89 #define FLEXCAN_CTRL2_RFFN(x)           (((x) & 0x0f) << 24)
  90 #define FLEXCAN_CTRL2_TASD(x)           (((x) & 0x1f) << 19)
  91 #define FLEXCAN_CTRL2_MRP               BIT(18)
  92 #define FLEXCAN_CTRL2_RRS               BIT(17)
  93 #define FLEXCAN_CTRL2_EACEN             BIT(16)
  94 
  95 /* FLEXCAN memory error control register (MECR) bits */
  96 #define FLEXCAN_MECR_ECRWRDIS           BIT(31)
  97 #define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
  98 #define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
  99 #define FLEXCAN_MECR_CEI_MSK            BIT(16)
 100 #define FLEXCAN_MECR_HAERRIE            BIT(15)
 101 #define FLEXCAN_MECR_FAERRIE            BIT(14)
 102 #define FLEXCAN_MECR_EXTERRIE           BIT(13)
 103 #define FLEXCAN_MECR_RERRDIS            BIT(9)
 104 #define FLEXCAN_MECR_ECCDIS             BIT(8)
 105 #define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
 106 
 107 /* FLEXCAN error and status register (ESR) bits */
 108 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
 109 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
 110 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
 111 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
 112 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
 113 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 114 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 115 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 116 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 117 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 118 #define FLEXCAN_ESR_IDLE                BIT(7)
 119 #define FLEXCAN_ESR_TXRX                BIT(6)
 120 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 121 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 122 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 123 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 124 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 125 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 126 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 127 #define FLEXCAN_ESR_ERR_BUS \
 128         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 129          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 130          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 131 #define FLEXCAN_ESR_ERR_STATE \
 132         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 133 #define FLEXCAN_ESR_ERR_ALL \
 134         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 135 #define FLEXCAN_ESR_ALL_INT \
 136         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 137          FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
 138          FLEXCAN_ESR_WAK_INT)
 139 
 140 /* FLEXCAN interrupt flag register (IFLAG) bits */
 141 /* Errata ERR005829 step7: Reserve first valid MB */
 142 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO         8
 143 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP    0
 144 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST       (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
 145 #define FLEXCAN_IFLAG_MB(x)             BIT((x) & 0x1f)
 146 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 147 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 148 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 149 
 150 /* FLEXCAN message buffers */
 151 #define FLEXCAN_MB_CODE_MASK            (0xf << 24)
 152 #define FLEXCAN_MB_CODE_RX_BUSY_BIT     (0x1 << 24)
 153 #define FLEXCAN_MB_CODE_RX_INACTIVE     (0x0 << 24)
 154 #define FLEXCAN_MB_CODE_RX_EMPTY        (0x4 << 24)
 155 #define FLEXCAN_MB_CODE_RX_FULL         (0x2 << 24)
 156 #define FLEXCAN_MB_CODE_RX_OVERRUN      (0x6 << 24)
 157 #define FLEXCAN_MB_CODE_RX_RANSWER      (0xa << 24)
 158 
 159 #define FLEXCAN_MB_CODE_TX_INACTIVE     (0x8 << 24)
 160 #define FLEXCAN_MB_CODE_TX_ABORT        (0x9 << 24)
 161 #define FLEXCAN_MB_CODE_TX_DATA         (0xc << 24)
 162 #define FLEXCAN_MB_CODE_TX_TANSWER      (0xe << 24)
 163 
 164 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 165 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 166 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 167 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 168 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 169 
 170 #define FLEXCAN_TIMEOUT_US              (250)
 171 
 172 /* FLEXCAN hardware feature flags
 173  *
 174  * Below is some version info we got:
 175  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
 176  *                                Filter? connected?  Passive detection  ception in MB
 177  *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no
 178  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
 179  *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no
 180  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
 181  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
 182  *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?
 183  * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes
 184  *
 185  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 186  */
 187 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
 188 #define FLEXCAN_QUIRK_DISABLE_RXFG      BIT(2) /* Disable RX FIFO Global mask */
 189 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
 190 #define FLEXCAN_QUIRK_DISABLE_MECR      BIT(4) /* Disable Memory error detection */
 191 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
 192 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
 193 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN        BIT(7) /* default to BE register access */
 194 #define FLEXCAN_QUIRK_SETUP_STOP_MODE           BIT(8) /* Setup stop mode to support wakeup */
 195 
 196 /* Structure of the message buffer */
 197 struct flexcan_mb {
 198         u32 can_ctrl;
 199         u32 can_id;
 200         u32 data[];
 201 };
 202 
 203 /* Structure of the hardware registers */
 204 struct flexcan_regs {
 205         u32 mcr;                /* 0x00 */
 206         u32 ctrl;               /* 0x04 */
 207         u32 timer;              /* 0x08 */
 208         u32 _reserved1;         /* 0x0c */
 209         u32 rxgmask;            /* 0x10 */
 210         u32 rx14mask;           /* 0x14 */
 211         u32 rx15mask;           /* 0x18 */
 212         u32 ecr;                /* 0x1c */
 213         u32 esr;                /* 0x20 */
 214         u32 imask2;             /* 0x24 */
 215         u32 imask1;             /* 0x28 */
 216         u32 iflag2;             /* 0x2c */
 217         u32 iflag1;             /* 0x30 */
 218         union {                 /* 0x34 */
 219                 u32 gfwr_mx28;  /* MX28, MX53 */
 220                 u32 ctrl2;      /* MX6, VF610 */
 221         };
 222         u32 esr2;               /* 0x38 */
 223         u32 imeur;              /* 0x3c */
 224         u32 lrfr;               /* 0x40 */
 225         u32 crcr;               /* 0x44 */
 226         u32 rxfgmask;           /* 0x48 */
 227         u32 rxfir;              /* 0x4c */
 228         u32 _reserved3[12];     /* 0x50 */
 229         u8 mb[2][512];          /* 0x80 */
 230         /* FIFO-mode:
 231          *                      MB
 232          * 0x080...0x08f        0       RX message buffer
 233          * 0x090...0x0df        1-5     reserverd
 234          * 0x0e0...0x0ff        6-7     8 entry ID table
 235          *                              (mx25, mx28, mx35, mx53)
 236          * 0x0e0...0x2df        6-7..37 8..128 entry ID table
 237          *                              size conf'ed via ctrl2::RFFN
 238          *                              (mx6, vf610)
 239          */
 240         u32 _reserved4[256];    /* 0x480 */
 241         u32 rximr[64];          /* 0x880 */
 242         u32 _reserved5[24];     /* 0x980 */
 243         u32 gfwr_mx6;           /* 0x9e0 - MX6 */
 244         u32 _reserved6[63];     /* 0x9e4 */
 245         u32 mecr;               /* 0xae0 */
 246         u32 erriar;             /* 0xae4 */
 247         u32 erridpr;            /* 0xae8 */
 248         u32 errippr;            /* 0xaec */
 249         u32 rerrar;             /* 0xaf0 */
 250         u32 rerrdr;             /* 0xaf4 */
 251         u32 rerrsynr;           /* 0xaf8 */
 252         u32 errsr;              /* 0xafc */
 253 };
 254 
 255 struct flexcan_devtype_data {
 256         u32 quirks;             /* quirks needed for different IP cores */
 257 };
 258 
 259 struct flexcan_stop_mode {
 260         struct regmap *gpr;
 261         u8 req_gpr;
 262         u8 req_bit;
 263         u8 ack_gpr;
 264         u8 ack_bit;
 265 };
 266 
 267 struct flexcan_priv {
 268         struct can_priv can;
 269         struct can_rx_offload offload;
 270         struct device *dev;
 271 
 272         struct flexcan_regs __iomem *regs;
 273         struct flexcan_mb __iomem *tx_mb;
 274         struct flexcan_mb __iomem *tx_mb_reserved;
 275         u8 tx_mb_idx;
 276         u8 mb_count;
 277         u8 mb_size;
 278         u8 clk_src;     /* clock source of CAN Protocol Engine */
 279 
 280         u32 reg_ctrl_default;
 281         u32 reg_imask1_default;
 282         u32 reg_imask2_default;
 283 
 284         struct clk *clk_ipg;
 285         struct clk *clk_per;
 286         const struct flexcan_devtype_data *devtype_data;
 287         struct regulator *reg_xceiver;
 288         struct flexcan_stop_mode stm;
 289 
 290         /* Read and Write APIs */
 291         u32 (*read)(void __iomem *addr);
 292         void (*write)(u32 val, void __iomem *addr);
 293 };
 294 
 295 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 296         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 297                 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 298                 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
 299 };
 300 
 301 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 302         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 303                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 304 };
 305 
 306 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 307         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 308 };
 309 
 310 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 311         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 312                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 313                 FLEXCAN_QUIRK_SETUP_STOP_MODE,
 314 };
 315 
 316 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 317         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 318                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
 319                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 320 };
 321 
 322 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 323         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 324                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 325                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 326 };
 327 
 328 static const struct can_bittiming_const flexcan_bittiming_const = {
 329         .name = DRV_NAME,
 330         .tseg1_min = 4,
 331         .tseg1_max = 16,
 332         .tseg2_min = 2,
 333         .tseg2_max = 8,
 334         .sjw_max = 4,
 335         .brp_min = 1,
 336         .brp_max = 256,
 337         .brp_inc = 1,
 338 };
 339 
 340 /* FlexCAN module is essentially modelled as a little-endian IP in most
 341  * SoCs, i.e the registers as well as the message buffer areas are
 342  * implemented in a little-endian fashion.
 343  *
 344  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 345  * module in a big-endian fashion (i.e the registers as well as the
 346  * message buffer areas are implemented in a big-endian way).
 347  *
 348  * In addition, the FlexCAN module can be found on SoCs having ARM or
 349  * PPC cores. So, we need to abstract off the register read/write
 350  * functions, ensuring that these cater to all the combinations of module
 351  * endianness and underlying CPU endianness.
 352  */
 353 static inline u32 flexcan_read_be(void __iomem *addr)
 354 {
 355         return ioread32be(addr);
 356 }
 357 
 358 static inline void flexcan_write_be(u32 val, void __iomem *addr)
 359 {
 360         iowrite32be(val, addr);
 361 }
 362 
 363 static inline u32 flexcan_read_le(void __iomem *addr)
 364 {
 365         return ioread32(addr);
 366 }
 367 
 368 static inline void flexcan_write_le(u32 val, void __iomem *addr)
 369 {
 370         iowrite32(val, addr);
 371 }
 372 
 373 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
 374                                                  u8 mb_index)
 375 {
 376         u8 bank_size;
 377         bool bank;
 378 
 379         if (WARN_ON(mb_index >= priv->mb_count))
 380                 return NULL;
 381 
 382         bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
 383 
 384         bank = mb_index >= bank_size;
 385         if (bank)
 386                 mb_index -= bank_size;
 387 
 388         return (struct flexcan_mb __iomem *)
 389                 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
 390 }
 391 
 392 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
 393 {
 394         struct flexcan_regs __iomem *regs = priv->regs;
 395         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 396 
 397         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 398                 udelay(10);
 399 
 400         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 401                 return -ETIMEDOUT;
 402 
 403         return 0;
 404 }
 405 
 406 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
 407 {
 408         struct flexcan_regs __iomem *regs = priv->regs;
 409         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 410 
 411         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 412                 udelay(10);
 413 
 414         if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 415                 return -ETIMEDOUT;
 416 
 417         return 0;
 418 }
 419 
 420 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
 421 {
 422         struct flexcan_regs __iomem *regs = priv->regs;
 423         u32 reg_mcr;
 424 
 425         reg_mcr = priv->read(&regs->mcr);
 426 
 427         if (enable)
 428                 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
 429         else
 430                 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
 431 
 432         priv->write(reg_mcr, &regs->mcr);
 433 }
 434 
 435 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
 436 {
 437         struct flexcan_regs __iomem *regs = priv->regs;
 438         u32 reg_mcr;
 439 
 440         reg_mcr = priv->read(&regs->mcr);
 441         reg_mcr |= FLEXCAN_MCR_SLF_WAK;
 442         priv->write(reg_mcr, &regs->mcr);
 443 
 444         /* enable stop request */
 445         regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 446                            1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
 447 
 448         return flexcan_low_power_enter_ack(priv);
 449 }
 450 
 451 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
 452 {
 453         struct flexcan_regs __iomem *regs = priv->regs;
 454         u32 reg_mcr;
 455 
 456         /* remove stop request */
 457         regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 458                            1 << priv->stm.req_bit, 0);
 459 
 460 
 461         reg_mcr = priv->read(&regs->mcr);
 462         reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
 463         priv->write(reg_mcr, &regs->mcr);
 464 
 465         return flexcan_low_power_exit_ack(priv);
 466 }
 467 
 468 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 469 {
 470         struct flexcan_regs __iomem *regs = priv->regs;
 471         u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 472 
 473         priv->write(reg_ctrl, &regs->ctrl);
 474 }
 475 
 476 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 477 {
 478         struct flexcan_regs __iomem *regs = priv->regs;
 479         u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 480 
 481         priv->write(reg_ctrl, &regs->ctrl);
 482 }
 483 
 484 static int flexcan_clks_enable(const struct flexcan_priv *priv)
 485 {
 486         int err;
 487 
 488         err = clk_prepare_enable(priv->clk_ipg);
 489         if (err)
 490                 return err;
 491 
 492         err = clk_prepare_enable(priv->clk_per);
 493         if (err)
 494                 clk_disable_unprepare(priv->clk_ipg);
 495 
 496         return err;
 497 }
 498 
 499 static void flexcan_clks_disable(const struct flexcan_priv *priv)
 500 {
 501         clk_disable_unprepare(priv->clk_per);
 502         clk_disable_unprepare(priv->clk_ipg);
 503 }
 504 
 505 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 506 {
 507         if (!priv->reg_xceiver)
 508                 return 0;
 509 
 510         return regulator_enable(priv->reg_xceiver);
 511 }
 512 
 513 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 514 {
 515         if (!priv->reg_xceiver)
 516                 return 0;
 517 
 518         return regulator_disable(priv->reg_xceiver);
 519 }
 520 
 521 static int flexcan_chip_enable(struct flexcan_priv *priv)
 522 {
 523         struct flexcan_regs __iomem *regs = priv->regs;
 524         u32 reg;
 525 
 526         reg = priv->read(&regs->mcr);
 527         reg &= ~FLEXCAN_MCR_MDIS;
 528         priv->write(reg, &regs->mcr);
 529 
 530         return flexcan_low_power_exit_ack(priv);
 531 }
 532 
 533 static int flexcan_chip_disable(struct flexcan_priv *priv)
 534 {
 535         struct flexcan_regs __iomem *regs = priv->regs;
 536         u32 reg;
 537 
 538         reg = priv->read(&regs->mcr);
 539         reg |= FLEXCAN_MCR_MDIS;
 540         priv->write(reg, &regs->mcr);
 541 
 542         return flexcan_low_power_enter_ack(priv);
 543 }
 544 
 545 static int flexcan_chip_freeze(struct flexcan_priv *priv)
 546 {
 547         struct flexcan_regs __iomem *regs = priv->regs;
 548         unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 549         u32 reg;
 550 
 551         reg = priv->read(&regs->mcr);
 552         reg |= FLEXCAN_MCR_HALT;
 553         priv->write(reg, &regs->mcr);
 554 
 555         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 556                 udelay(100);
 557 
 558         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 559                 return -ETIMEDOUT;
 560 
 561         return 0;
 562 }
 563 
 564 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 565 {
 566         struct flexcan_regs __iomem *regs = priv->regs;
 567         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 568         u32 reg;
 569 
 570         reg = priv->read(&regs->mcr);
 571         reg &= ~FLEXCAN_MCR_HALT;
 572         priv->write(reg, &regs->mcr);
 573 
 574         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 575                 udelay(10);
 576 
 577         if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 578                 return -ETIMEDOUT;
 579 
 580         return 0;
 581 }
 582 
 583 static int flexcan_chip_softreset(struct flexcan_priv *priv)
 584 {
 585         struct flexcan_regs __iomem *regs = priv->regs;
 586         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 587 
 588         priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 589         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 590                 udelay(10);
 591 
 592         if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 593                 return -ETIMEDOUT;
 594 
 595         return 0;
 596 }
 597 
 598 static int __flexcan_get_berr_counter(const struct net_device *dev,
 599                                       struct can_berr_counter *bec)
 600 {
 601         const struct flexcan_priv *priv = netdev_priv(dev);
 602         struct flexcan_regs __iomem *regs = priv->regs;
 603         u32 reg = priv->read(&regs->ecr);
 604 
 605         bec->txerr = (reg >> 0) & 0xff;
 606         bec->rxerr = (reg >> 8) & 0xff;
 607 
 608         return 0;
 609 }
 610 
 611 static int flexcan_get_berr_counter(const struct net_device *dev,
 612                                     struct can_berr_counter *bec)
 613 {
 614         const struct flexcan_priv *priv = netdev_priv(dev);
 615         int err;
 616 
 617         err = pm_runtime_get_sync(priv->dev);
 618         if (err < 0)
 619                 return err;
 620 
 621         err = __flexcan_get_berr_counter(dev, bec);
 622 
 623         pm_runtime_put(priv->dev);
 624 
 625         return err;
 626 }
 627 
 628 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 629 {
 630         const struct flexcan_priv *priv = netdev_priv(dev);
 631         struct can_frame *cf = (struct can_frame *)skb->data;
 632         u32 can_id;
 633         u32 data;
 634         u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
 635         int i;
 636 
 637         if (can_dropped_invalid_skb(dev, skb))
 638                 return NETDEV_TX_OK;
 639 
 640         netif_stop_queue(dev);
 641 
 642         if (cf->can_id & CAN_EFF_FLAG) {
 643                 can_id = cf->can_id & CAN_EFF_MASK;
 644                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 645         } else {
 646                 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
 647         }
 648 
 649         if (cf->can_id & CAN_RTR_FLAG)
 650                 ctrl |= FLEXCAN_MB_CNT_RTR;
 651 
 652         for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
 653                 data = be32_to_cpup((__be32 *)&cf->data[i]);
 654                 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
 655         }
 656 
 657         can_put_echo_skb(skb, dev, 0);
 658 
 659         priv->write(can_id, &priv->tx_mb->can_id);
 660         priv->write(ctrl, &priv->tx_mb->can_ctrl);
 661 
 662         /* Errata ERR005829 step8:
 663          * Write twice INACTIVE(0x8) code to first MB.
 664          */
 665         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 666                     &priv->tx_mb_reserved->can_ctrl);
 667         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 668                     &priv->tx_mb_reserved->can_ctrl);
 669 
 670         return NETDEV_TX_OK;
 671 }
 672 
 673 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 674 {
 675         struct flexcan_priv *priv = netdev_priv(dev);
 676         struct flexcan_regs __iomem *regs = priv->regs;
 677         struct sk_buff *skb;
 678         struct can_frame *cf;
 679         bool rx_errors = false, tx_errors = false;
 680         u32 timestamp;
 681         int err;
 682 
 683         timestamp = priv->read(&regs->timer) << 16;
 684 
 685         skb = alloc_can_err_skb(dev, &cf);
 686         if (unlikely(!skb))
 687                 return;
 688 
 689         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 690 
 691         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 692                 netdev_dbg(dev, "BIT1_ERR irq\n");
 693                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 694                 tx_errors = true;
 695         }
 696         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 697                 netdev_dbg(dev, "BIT0_ERR irq\n");
 698                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 699                 tx_errors = true;
 700         }
 701         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 702                 netdev_dbg(dev, "ACK_ERR irq\n");
 703                 cf->can_id |= CAN_ERR_ACK;
 704                 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 705                 tx_errors = true;
 706         }
 707         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 708                 netdev_dbg(dev, "CRC_ERR irq\n");
 709                 cf->data[2] |= CAN_ERR_PROT_BIT;
 710                 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 711                 rx_errors = true;
 712         }
 713         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 714                 netdev_dbg(dev, "FRM_ERR irq\n");
 715                 cf->data[2] |= CAN_ERR_PROT_FORM;
 716                 rx_errors = true;
 717         }
 718         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 719                 netdev_dbg(dev, "STF_ERR irq\n");
 720                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 721                 rx_errors = true;
 722         }
 723 
 724         priv->can.can_stats.bus_error++;
 725         if (rx_errors)
 726                 dev->stats.rx_errors++;
 727         if (tx_errors)
 728                 dev->stats.tx_errors++;
 729 
 730         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 731         if (err)
 732                 dev->stats.rx_fifo_errors++;
 733 }
 734 
 735 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 736 {
 737         struct flexcan_priv *priv = netdev_priv(dev);
 738         struct flexcan_regs __iomem *regs = priv->regs;
 739         struct sk_buff *skb;
 740         struct can_frame *cf;
 741         enum can_state new_state, rx_state, tx_state;
 742         int flt;
 743         struct can_berr_counter bec;
 744         u32 timestamp;
 745         int err;
 746 
 747         timestamp = priv->read(&regs->timer) << 16;
 748 
 749         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 750         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 751                 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 752                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 753                 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 754                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 755                 new_state = max(tx_state, rx_state);
 756         } else {
 757                 __flexcan_get_berr_counter(dev, &bec);
 758                 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 759                         CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 760                 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 761                 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 762         }
 763 
 764         /* state hasn't changed */
 765         if (likely(new_state == priv->can.state))
 766                 return;
 767 
 768         skb = alloc_can_err_skb(dev, &cf);
 769         if (unlikely(!skb))
 770                 return;
 771 
 772         can_change_state(dev, cf, tx_state, rx_state);
 773 
 774         if (unlikely(new_state == CAN_STATE_BUS_OFF))
 775                 can_bus_off(dev);
 776 
 777         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 778         if (err)
 779                 dev->stats.rx_fifo_errors++;
 780 }
 781 
 782 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 783 {
 784         return container_of(offload, struct flexcan_priv, offload);
 785 }
 786 
 787 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
 788                                          struct can_frame *cf,
 789                                          u32 *timestamp, unsigned int n)
 790 {
 791         struct flexcan_priv *priv = rx_offload_to_priv(offload);
 792         struct flexcan_regs __iomem *regs = priv->regs;
 793         struct flexcan_mb __iomem *mb;
 794         u32 reg_ctrl, reg_id, reg_iflag1;
 795         int i;
 796 
 797         mb = flexcan_get_mb(priv, n);
 798 
 799         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 800                 u32 code;
 801 
 802                 do {
 803                         reg_ctrl = priv->read(&mb->can_ctrl);
 804                 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 805 
 806                 /* is this MB empty? */
 807                 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
 808                 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
 809                     (code != FLEXCAN_MB_CODE_RX_OVERRUN))
 810                         return 0;
 811 
 812                 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
 813                         /* This MB was overrun, we lost data */
 814                         offload->dev->stats.rx_over_errors++;
 815                         offload->dev->stats.rx_errors++;
 816                 }
 817         } else {
 818                 reg_iflag1 = priv->read(&regs->iflag1);
 819                 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 820                         return 0;
 821 
 822                 reg_ctrl = priv->read(&mb->can_ctrl);
 823         }
 824 
 825         /* increase timstamp to full 32 bit */
 826         *timestamp = reg_ctrl << 16;
 827 
 828         reg_id = priv->read(&mb->can_id);
 829         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 830                 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 831         else
 832                 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
 833 
 834         if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
 835                 cf->can_id |= CAN_RTR_FLAG;
 836         cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 837 
 838         for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
 839                 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
 840                 *(__be32 *)(cf->data + i) = data;
 841         }
 842 
 843         /* mark as read */
 844         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 845                 /* Clear IRQ */
 846                 if (n < 32)
 847                         priv->write(BIT(n), &regs->iflag1);
 848                 else
 849                         priv->write(BIT(n - 32), &regs->iflag2);
 850         } else {
 851                 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 852         }
 853 
 854         /* Read the Free Running Timer. It is optional but recommended
 855          * to unlock Mailbox as soon as possible and make it available
 856          * for reception.
 857          */
 858         priv->read(&regs->timer);
 859 
 860         return 1;
 861 }
 862 
 863 
 864 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 865 {
 866         struct flexcan_regs __iomem *regs = priv->regs;
 867         u32 iflag1, iflag2;
 868 
 869         iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
 870                 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
 871         iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
 872 
 873         return (u64)iflag2 << 32 | iflag1;
 874 }
 875 
 876 static irqreturn_t flexcan_irq(int irq, void *dev_id)
 877 {
 878         struct net_device *dev = dev_id;
 879         struct net_device_stats *stats = &dev->stats;
 880         struct flexcan_priv *priv = netdev_priv(dev);
 881         struct flexcan_regs __iomem *regs = priv->regs;
 882         irqreturn_t handled = IRQ_NONE;
 883         u32 reg_iflag2, reg_esr;
 884         enum can_state last_state = priv->can.state;
 885 
 886         /* reception interrupt */
 887         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 888                 u64 reg_iflag;
 889                 int ret;
 890 
 891                 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
 892                         handled = IRQ_HANDLED;
 893                         ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
 894                                                                    reg_iflag);
 895                         if (!ret)
 896                                 break;
 897                 }
 898         } else {
 899                 u32 reg_iflag1;
 900 
 901                 reg_iflag1 = priv->read(&regs->iflag1);
 902                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
 903                         handled = IRQ_HANDLED;
 904                         can_rx_offload_irq_offload_fifo(&priv->offload);
 905                 }
 906 
 907                 /* FIFO overflow interrupt */
 908                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 909                         handled = IRQ_HANDLED;
 910                         priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
 911                                     &regs->iflag1);
 912                         dev->stats.rx_over_errors++;
 913                         dev->stats.rx_errors++;
 914                 }
 915         }
 916 
 917         reg_iflag2 = priv->read(&regs->iflag2);
 918 
 919         /* transmission complete interrupt */
 920         if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
 921                 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
 922 
 923                 handled = IRQ_HANDLED;
 924                 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
 925                                                                0, reg_ctrl << 16);
 926                 stats->tx_packets++;
 927                 can_led_event(dev, CAN_LED_EVENT_TX);
 928 
 929                 /* after sending a RTR frame MB is in RX mode */
 930                 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 931                             &priv->tx_mb->can_ctrl);
 932                 priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag2);
 933                 netif_wake_queue(dev);
 934         }
 935 
 936         reg_esr = priv->read(&regs->esr);
 937 
 938         /* ACK all bus error and state change IRQ sources */
 939         if (reg_esr & FLEXCAN_ESR_ALL_INT) {
 940                 handled = IRQ_HANDLED;
 941                 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 942         }
 943 
 944         /* state change interrupt or broken error state quirk fix is enabled */
 945         if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
 946             (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 947                                            FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
 948                 flexcan_irq_state(dev, reg_esr);
 949 
 950         /* bus error IRQ - handle if bus error reporting is activated */
 951         if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
 952             (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
 953                 flexcan_irq_bus_err(dev, reg_esr);
 954 
 955         /* availability of error interrupt among state transitions in case
 956          * bus error reporting is de-activated and
 957          * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
 958          *  +--------------------------------------------------------------+
 959          *  | +----------------------------------------------+ [stopped /  |
 960          *  | |                                              |  sleeping] -+
 961          *  +-+-> active <-> warning <-> passive -> bus off -+
 962          *        ___________^^^^^^^^^^^^_______________________________
 963          *        disabled(1)  enabled             disabled
 964          *
 965          * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
 966          */
 967         if ((last_state != priv->can.state) &&
 968             (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
 969             !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
 970                 switch (priv->can.state) {
 971                 case CAN_STATE_ERROR_ACTIVE:
 972                         if (priv->devtype_data->quirks &
 973                             FLEXCAN_QUIRK_BROKEN_WERR_STATE)
 974                                 flexcan_error_irq_enable(priv);
 975                         else
 976                                 flexcan_error_irq_disable(priv);
 977                         break;
 978 
 979                 case CAN_STATE_ERROR_WARNING:
 980                         flexcan_error_irq_enable(priv);
 981                         break;
 982 
 983                 case CAN_STATE_ERROR_PASSIVE:
 984                 case CAN_STATE_BUS_OFF:
 985                         flexcan_error_irq_disable(priv);
 986                         break;
 987 
 988                 default:
 989                         break;
 990                 }
 991         }
 992 
 993         return handled;
 994 }
 995 
 996 static void flexcan_set_bittiming(struct net_device *dev)
 997 {
 998         const struct flexcan_priv *priv = netdev_priv(dev);
 999         const struct can_bittiming *bt = &priv->can.bittiming;
1000         struct flexcan_regs __iomem *regs = priv->regs;
1001         u32 reg;
1002 
1003         reg = priv->read(&regs->ctrl);
1004         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1005                  FLEXCAN_CTRL_RJW(0x3) |
1006                  FLEXCAN_CTRL_PSEG1(0x7) |
1007                  FLEXCAN_CTRL_PSEG2(0x7) |
1008                  FLEXCAN_CTRL_PROPSEG(0x7) |
1009                  FLEXCAN_CTRL_LPB |
1010                  FLEXCAN_CTRL_SMP |
1011                  FLEXCAN_CTRL_LOM);
1012 
1013         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1014                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1015                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1016                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1017                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1018 
1019         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1020                 reg |= FLEXCAN_CTRL_LPB;
1021         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1022                 reg |= FLEXCAN_CTRL_LOM;
1023         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1024                 reg |= FLEXCAN_CTRL_SMP;
1025 
1026         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1027         priv->write(reg, &regs->ctrl);
1028 
1029         /* print chip status */
1030         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1031                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1032 }
1033 
1034 /* flexcan_chip_start
1035  *
1036  * this functions is entered with clocks enabled
1037  *
1038  */
1039 static int flexcan_chip_start(struct net_device *dev)
1040 {
1041         struct flexcan_priv *priv = netdev_priv(dev);
1042         struct flexcan_regs __iomem *regs = priv->regs;
1043         u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1044         int err, i;
1045         struct flexcan_mb __iomem *mb;
1046 
1047         /* enable module */
1048         err = flexcan_chip_enable(priv);
1049         if (err)
1050                 return err;
1051 
1052         /* soft reset */
1053         err = flexcan_chip_softreset(priv);
1054         if (err)
1055                 goto out_chip_disable;
1056 
1057         flexcan_set_bittiming(dev);
1058 
1059         /* MCR
1060          *
1061          * enable freeze
1062          * halt now
1063          * only supervisor access
1064          * enable warning int
1065          * enable individual RX masking
1066          * choose format C
1067          * set max mailbox number
1068          */
1069         reg_mcr = priv->read(&regs->mcr);
1070         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1071         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1072                 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1073                 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1074 
1075         /* MCR
1076          *
1077          * FIFO:
1078          * - disable for timestamp mode
1079          * - enable for FIFO mode
1080          */
1081         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1082                 reg_mcr &= ~FLEXCAN_MCR_FEN;
1083         else
1084                 reg_mcr |= FLEXCAN_MCR_FEN;
1085 
1086         /* MCR
1087          *
1088          * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1089          *       asserted because this will impede the self reception
1090          *       of a transmitted message. This is not documented in
1091          *       earlier versions of flexcan block guide.
1092          *
1093          * Self Reception:
1094          * - enable Self Reception for loopback mode
1095          *   (by clearing "Self Reception Disable" bit)
1096          * - disable for normal operation
1097          */
1098         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1099                 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1100         else
1101                 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1102 
1103         netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1104         priv->write(reg_mcr, &regs->mcr);
1105 
1106         /* CTRL
1107          *
1108          * disable timer sync feature
1109          *
1110          * disable auto busoff recovery
1111          * transmit lowest buffer first
1112          *
1113          * enable tx and rx warning interrupt
1114          * enable bus off interrupt
1115          * (== FLEXCAN_CTRL_ERR_STATE)
1116          */
1117         reg_ctrl = priv->read(&regs->ctrl);
1118         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1119         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1120                 FLEXCAN_CTRL_ERR_STATE;
1121 
1122         /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1123          * on most Flexcan cores, too. Otherwise we don't get
1124          * any error warning or passive interrupts.
1125          */
1126         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1127             priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1128                 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1129         else
1130                 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1131 
1132         /* save for later use */
1133         priv->reg_ctrl_default = reg_ctrl;
1134         /* leave interrupts disabled for now */
1135         reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1136         netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1137         priv->write(reg_ctrl, &regs->ctrl);
1138 
1139         if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1140                 reg_ctrl2 = priv->read(&regs->ctrl2);
1141                 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1142                 priv->write(reg_ctrl2, &regs->ctrl2);
1143         }
1144 
1145         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1146                 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1147                         mb = flexcan_get_mb(priv, i);
1148                         priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1149                                     &mb->can_ctrl);
1150                 }
1151         } else {
1152                 /* clear and invalidate unused mailboxes first */
1153                 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1154                         mb = flexcan_get_mb(priv, i);
1155                         priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1156                                     &mb->can_ctrl);
1157                 }
1158         }
1159 
1160         /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1161         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1162                     &priv->tx_mb_reserved->can_ctrl);
1163 
1164         /* mark TX mailbox as INACTIVE */
1165         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1166                     &priv->tx_mb->can_ctrl);
1167 
1168         /* acceptance mask/acceptance code (accept everything) */
1169         priv->write(0x0, &regs->rxgmask);
1170         priv->write(0x0, &regs->rx14mask);
1171         priv->write(0x0, &regs->rx15mask);
1172 
1173         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1174                 priv->write(0x0, &regs->rxfgmask);
1175 
1176         /* clear acceptance filters */
1177         for (i = 0; i < priv->mb_count; i++)
1178                 priv->write(0, &regs->rximr[i]);
1179 
1180         /* On Vybrid, disable memory error detection interrupts
1181          * and freeze mode.
1182          * This also works around errata e5295 which generates
1183          * false positive memory errors and put the device in
1184          * freeze mode.
1185          */
1186         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1187                 /* Follow the protocol as described in "Detection
1188                  * and Correction of Memory Errors" to write to
1189                  * MECR register
1190                  */
1191                 reg_ctrl2 = priv->read(&regs->ctrl2);
1192                 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1193                 priv->write(reg_ctrl2, &regs->ctrl2);
1194 
1195                 reg_mecr = priv->read(&regs->mecr);
1196                 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1197                 priv->write(reg_mecr, &regs->mecr);
1198                 reg_mecr |= FLEXCAN_MECR_ECCDIS;
1199                 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1200                               FLEXCAN_MECR_FANCEI_MSK);
1201                 priv->write(reg_mecr, &regs->mecr);
1202         }
1203 
1204         err = flexcan_transceiver_enable(priv);
1205         if (err)
1206                 goto out_chip_disable;
1207 
1208         /* synchronize with the can bus */
1209         err = flexcan_chip_unfreeze(priv);
1210         if (err)
1211                 goto out_transceiver_disable;
1212 
1213         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1214 
1215         /* enable interrupts atomically */
1216         disable_irq(dev->irq);
1217         priv->write(priv->reg_ctrl_default, &regs->ctrl);
1218         priv->write(priv->reg_imask1_default, &regs->imask1);
1219         priv->write(priv->reg_imask2_default, &regs->imask2);
1220         enable_irq(dev->irq);
1221 
1222         /* print chip status */
1223         netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1224                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1225 
1226         return 0;
1227 
1228  out_transceiver_disable:
1229         flexcan_transceiver_disable(priv);
1230  out_chip_disable:
1231         flexcan_chip_disable(priv);
1232         return err;
1233 }
1234 
1235 /* flexcan_chip_stop
1236  *
1237  * this functions is entered with clocks enabled
1238  */
1239 static void flexcan_chip_stop(struct net_device *dev)
1240 {
1241         struct flexcan_priv *priv = netdev_priv(dev);
1242         struct flexcan_regs __iomem *regs = priv->regs;
1243 
1244         /* freeze + disable module */
1245         flexcan_chip_freeze(priv);
1246         flexcan_chip_disable(priv);
1247 
1248         /* Disable all interrupts */
1249         priv->write(0, &regs->imask2);
1250         priv->write(0, &regs->imask1);
1251         priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1252                     &regs->ctrl);
1253 
1254         flexcan_transceiver_disable(priv);
1255         priv->can.state = CAN_STATE_STOPPED;
1256 }
1257 
1258 static int flexcan_open(struct net_device *dev)
1259 {
1260         struct flexcan_priv *priv = netdev_priv(dev);
1261         int err;
1262 
1263         err = pm_runtime_get_sync(priv->dev);
1264         if (err < 0)
1265                 return err;
1266 
1267         err = open_candev(dev);
1268         if (err)
1269                 goto out_runtime_put;
1270 
1271         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1272         if (err)
1273                 goto out_close;
1274 
1275         priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1276         priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1277                          (sizeof(priv->regs->mb[1]) / priv->mb_size);
1278 
1279         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1280                 priv->tx_mb_reserved =
1281                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1282         else
1283                 priv->tx_mb_reserved =
1284                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1285         priv->tx_mb_idx = priv->mb_count - 1;
1286         priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1287 
1288         priv->reg_imask1_default = 0;
1289         priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1290 
1291         priv->offload.mailbox_read = flexcan_mailbox_read;
1292 
1293         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1294                 u64 imask;
1295 
1296                 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1297                 priv->offload.mb_last = priv->mb_count - 2;
1298 
1299                 imask = GENMASK_ULL(priv->offload.mb_last,
1300                                     priv->offload.mb_first);
1301                 priv->reg_imask1_default |= imask;
1302                 priv->reg_imask2_default |= imask >> 32;
1303 
1304                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1305         } else {
1306                 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1307                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1308                 err = can_rx_offload_add_fifo(dev, &priv->offload,
1309                                               FLEXCAN_NAPI_WEIGHT);
1310         }
1311         if (err)
1312                 goto out_free_irq;
1313 
1314         /* start chip and queuing */
1315         err = flexcan_chip_start(dev);
1316         if (err)
1317                 goto out_offload_del;
1318 
1319         can_led_event(dev, CAN_LED_EVENT_OPEN);
1320 
1321         can_rx_offload_enable(&priv->offload);
1322         netif_start_queue(dev);
1323 
1324         return 0;
1325 
1326  out_offload_del:
1327         can_rx_offload_del(&priv->offload);
1328  out_free_irq:
1329         free_irq(dev->irq, dev);
1330  out_close:
1331         close_candev(dev);
1332  out_runtime_put:
1333         pm_runtime_put(priv->dev);
1334 
1335         return err;
1336 }
1337 
1338 static int flexcan_close(struct net_device *dev)
1339 {
1340         struct flexcan_priv *priv = netdev_priv(dev);
1341 
1342         netif_stop_queue(dev);
1343         can_rx_offload_disable(&priv->offload);
1344         flexcan_chip_stop(dev);
1345 
1346         can_rx_offload_del(&priv->offload);
1347         free_irq(dev->irq, dev);
1348 
1349         close_candev(dev);
1350         pm_runtime_put(priv->dev);
1351 
1352         can_led_event(dev, CAN_LED_EVENT_STOP);
1353 
1354         return 0;
1355 }
1356 
1357 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1358 {
1359         int err;
1360 
1361         switch (mode) {
1362         case CAN_MODE_START:
1363                 err = flexcan_chip_start(dev);
1364                 if (err)
1365                         return err;
1366 
1367                 netif_wake_queue(dev);
1368                 break;
1369 
1370         default:
1371                 return -EOPNOTSUPP;
1372         }
1373 
1374         return 0;
1375 }
1376 
1377 static const struct net_device_ops flexcan_netdev_ops = {
1378         .ndo_open       = flexcan_open,
1379         .ndo_stop       = flexcan_close,
1380         .ndo_start_xmit = flexcan_start_xmit,
1381         .ndo_change_mtu = can_change_mtu,
1382 };
1383 
1384 static int register_flexcandev(struct net_device *dev)
1385 {
1386         struct flexcan_priv *priv = netdev_priv(dev);
1387         struct flexcan_regs __iomem *regs = priv->regs;
1388         u32 reg, err;
1389 
1390         err = flexcan_clks_enable(priv);
1391         if (err)
1392                 return err;
1393 
1394         /* select "bus clock", chip must be disabled */
1395         err = flexcan_chip_disable(priv);
1396         if (err)
1397                 goto out_clks_disable;
1398 
1399         reg = priv->read(&regs->ctrl);
1400         if (priv->clk_src)
1401                 reg |= FLEXCAN_CTRL_CLK_SRC;
1402         else
1403                 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1404         priv->write(reg, &regs->ctrl);
1405 
1406         err = flexcan_chip_enable(priv);
1407         if (err)
1408                 goto out_chip_disable;
1409 
1410         /* set freeze, halt and activate FIFO, restrict register access */
1411         reg = priv->read(&regs->mcr);
1412         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1413                 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1414         priv->write(reg, &regs->mcr);
1415 
1416         /* Currently we only support newer versions of this core
1417          * featuring a RX hardware FIFO (although this driver doesn't
1418          * make use of it on some cores). Older cores, found on some
1419          * Coldfire derivates are not tested.
1420          */
1421         reg = priv->read(&regs->mcr);
1422         if (!(reg & FLEXCAN_MCR_FEN)) {
1423                 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1424                 err = -ENODEV;
1425                 goto out_chip_disable;
1426         }
1427 
1428         err = register_candev(dev);
1429         if (err)
1430                 goto out_chip_disable;
1431 
1432         /* Disable core and let pm_runtime_put() disable the clocks.
1433          * If CONFIG_PM is not enabled, the clocks will stay powered.
1434          */
1435         flexcan_chip_disable(priv);
1436         pm_runtime_put(priv->dev);
1437 
1438         return 0;
1439 
1440  out_chip_disable:
1441         flexcan_chip_disable(priv);
1442  out_clks_disable:
1443         flexcan_clks_disable(priv);
1444         return err;
1445 }
1446 
1447 static void unregister_flexcandev(struct net_device *dev)
1448 {
1449         unregister_candev(dev);
1450 }
1451 
1452 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1453 {
1454         struct net_device *dev = platform_get_drvdata(pdev);
1455         struct device_node *np = pdev->dev.of_node;
1456         struct device_node *gpr_np;
1457         struct flexcan_priv *priv;
1458         phandle phandle;
1459         u32 out_val[5];
1460         int ret;
1461 
1462         if (!np)
1463                 return -EINVAL;
1464 
1465         /* stop mode property format is:
1466          * <&gpr req_gpr req_bit ack_gpr ack_bit>.
1467          */
1468         ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1469                                          ARRAY_SIZE(out_val));
1470         if (ret) {
1471                 dev_dbg(&pdev->dev, "no stop-mode property\n");
1472                 return ret;
1473         }
1474         phandle = *out_val;
1475 
1476         gpr_np = of_find_node_by_phandle(phandle);
1477         if (!gpr_np) {
1478                 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1479                 return -ENODEV;
1480         }
1481 
1482         priv = netdev_priv(dev);
1483         priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1484         if (IS_ERR(priv->stm.gpr)) {
1485                 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1486                 ret = PTR_ERR(priv->stm.gpr);
1487                 goto out_put_node;
1488         }
1489 
1490         priv->stm.req_gpr = out_val[1];
1491         priv->stm.req_bit = out_val[2];
1492         priv->stm.ack_gpr = out_val[3];
1493         priv->stm.ack_bit = out_val[4];
1494 
1495         dev_dbg(&pdev->dev,
1496                 "gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
1497                 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
1498                 priv->stm.ack_gpr, priv->stm.ack_bit);
1499 
1500         device_set_wakeup_capable(&pdev->dev, true);
1501 
1502         if (of_property_read_bool(np, "wakeup-source"))
1503                 device_set_wakeup_enable(&pdev->dev, true);
1504 
1505         return 0;
1506 
1507 out_put_node:
1508         of_node_put(gpr_np);
1509         return ret;
1510 }
1511 
1512 static const struct of_device_id flexcan_of_match[] = {
1513         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1514         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1515         { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1516         { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1517         { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1518         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1519         { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1520         { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1521         { /* sentinel */ },
1522 };
1523 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1524 
1525 static const struct platform_device_id flexcan_id_table[] = {
1526         { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1527         { /* sentinel */ },
1528 };
1529 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1530 
1531 static int flexcan_probe(struct platform_device *pdev)
1532 {
1533         const struct of_device_id *of_id;
1534         const struct flexcan_devtype_data *devtype_data;
1535         struct net_device *dev;
1536         struct flexcan_priv *priv;
1537         struct regulator *reg_xceiver;
1538         struct resource *mem;
1539         struct clk *clk_ipg = NULL, *clk_per = NULL;
1540         struct flexcan_regs __iomem *regs;
1541         int err, irq;
1542         u8 clk_src = 1;
1543         u32 clock_freq = 0;
1544 
1545         reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1546         if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1547                 return -EPROBE_DEFER;
1548         else if (IS_ERR(reg_xceiver))
1549                 reg_xceiver = NULL;
1550 
1551         if (pdev->dev.of_node) {
1552                 of_property_read_u32(pdev->dev.of_node,
1553                                      "clock-frequency", &clock_freq);
1554                 of_property_read_u8(pdev->dev.of_node,
1555                                     "fsl,clk-source", &clk_src);
1556         }
1557 
1558         if (!clock_freq) {
1559                 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1560                 if (IS_ERR(clk_ipg)) {
1561                         dev_err(&pdev->dev, "no ipg clock defined\n");
1562                         return PTR_ERR(clk_ipg);
1563                 }
1564 
1565                 clk_per = devm_clk_get(&pdev->dev, "per");
1566                 if (IS_ERR(clk_per)) {
1567                         dev_err(&pdev->dev, "no per clock defined\n");
1568                         return PTR_ERR(clk_per);
1569                 }
1570                 clock_freq = clk_get_rate(clk_per);
1571         }
1572 
1573         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1574         irq = platform_get_irq(pdev, 0);
1575         if (irq <= 0)
1576                 return -ENODEV;
1577 
1578         regs = devm_ioremap_resource(&pdev->dev, mem);
1579         if (IS_ERR(regs))
1580                 return PTR_ERR(regs);
1581 
1582         of_id = of_match_device(flexcan_of_match, &pdev->dev);
1583         if (of_id) {
1584                 devtype_data = of_id->data;
1585         } else if (platform_get_device_id(pdev)->driver_data) {
1586                 devtype_data = (struct flexcan_devtype_data *)
1587                         platform_get_device_id(pdev)->driver_data;
1588         } else {
1589                 return -ENODEV;
1590         }
1591 
1592         dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1593         if (!dev)
1594                 return -ENOMEM;
1595 
1596         platform_set_drvdata(pdev, dev);
1597         SET_NETDEV_DEV(dev, &pdev->dev);
1598 
1599         dev->netdev_ops = &flexcan_netdev_ops;
1600         dev->irq = irq;
1601         dev->flags |= IFF_ECHO;
1602 
1603         priv = netdev_priv(dev);
1604 
1605         if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1606             devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1607                 priv->read = flexcan_read_be;
1608                 priv->write = flexcan_write_be;
1609         } else {
1610                 priv->read = flexcan_read_le;
1611                 priv->write = flexcan_write_le;
1612         }
1613 
1614         priv->dev = &pdev->dev;
1615         priv->can.clock.freq = clock_freq;
1616         priv->can.bittiming_const = &flexcan_bittiming_const;
1617         priv->can.do_set_mode = flexcan_set_mode;
1618         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1619         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1620                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1621                 CAN_CTRLMODE_BERR_REPORTING;
1622         priv->regs = regs;
1623         priv->clk_ipg = clk_ipg;
1624         priv->clk_per = clk_per;
1625         priv->clk_src = clk_src;
1626         priv->devtype_data = devtype_data;
1627         priv->reg_xceiver = reg_xceiver;
1628 
1629         pm_runtime_get_noresume(&pdev->dev);
1630         pm_runtime_set_active(&pdev->dev);
1631         pm_runtime_enable(&pdev->dev);
1632 
1633         err = register_flexcandev(dev);
1634         if (err) {
1635                 dev_err(&pdev->dev, "registering netdev failed\n");
1636                 goto failed_register;
1637         }
1638 
1639         devm_can_led_init(dev);
1640 
1641         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
1642                 err = flexcan_setup_stop_mode(pdev);
1643                 if (err)
1644                         dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
1645         }
1646 
1647         return 0;
1648 
1649  failed_register:
1650         free_candev(dev);
1651         return err;
1652 }
1653 
1654 static int flexcan_remove(struct platform_device *pdev)
1655 {
1656         struct net_device *dev = platform_get_drvdata(pdev);
1657 
1658         unregister_flexcandev(dev);
1659         pm_runtime_disable(&pdev->dev);
1660         free_candev(dev);
1661 
1662         return 0;
1663 }
1664 
1665 static int __maybe_unused flexcan_suspend(struct device *device)
1666 {
1667         struct net_device *dev = dev_get_drvdata(device);
1668         struct flexcan_priv *priv = netdev_priv(dev);
1669         int err = 0;
1670 
1671         if (netif_running(dev)) {
1672                 /* if wakeup is enabled, enter stop mode
1673                  * else enter disabled mode.
1674                  */
1675                 if (device_may_wakeup(device)) {
1676                         enable_irq_wake(dev->irq);
1677                         err = flexcan_enter_stop_mode(priv);
1678                         if (err)
1679                                 return err;
1680                 } else {
1681                         err = flexcan_chip_disable(priv);
1682                         if (err)
1683                                 return err;
1684 
1685                         err = pm_runtime_force_suspend(device);
1686                 }
1687                 netif_stop_queue(dev);
1688                 netif_device_detach(dev);
1689         }
1690         priv->can.state = CAN_STATE_SLEEPING;
1691 
1692         return err;
1693 }
1694 
1695 static int __maybe_unused flexcan_resume(struct device *device)
1696 {
1697         struct net_device *dev = dev_get_drvdata(device);
1698         struct flexcan_priv *priv = netdev_priv(dev);
1699         int err = 0;
1700 
1701         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1702         if (netif_running(dev)) {
1703                 netif_device_attach(dev);
1704                 netif_start_queue(dev);
1705                 if (device_may_wakeup(device)) {
1706                         disable_irq_wake(dev->irq);
1707                         err = flexcan_exit_stop_mode(priv);
1708                         if (err)
1709                                 return err;
1710                 } else {
1711                         err = pm_runtime_force_resume(device);
1712                         if (err)
1713                                 return err;
1714 
1715                         err = flexcan_chip_enable(priv);
1716                 }
1717         }
1718 
1719         return err;
1720 }
1721 
1722 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
1723 {
1724         struct net_device *dev = dev_get_drvdata(device);
1725         struct flexcan_priv *priv = netdev_priv(dev);
1726 
1727         flexcan_clks_disable(priv);
1728 
1729         return 0;
1730 }
1731 
1732 static int __maybe_unused flexcan_runtime_resume(struct device *device)
1733 {
1734         struct net_device *dev = dev_get_drvdata(device);
1735         struct flexcan_priv *priv = netdev_priv(dev);
1736 
1737         return flexcan_clks_enable(priv);
1738 }
1739 
1740 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
1741 {
1742         struct net_device *dev = dev_get_drvdata(device);
1743         struct flexcan_priv *priv = netdev_priv(dev);
1744 
1745         if (netif_running(dev) && device_may_wakeup(device))
1746                 flexcan_enable_wakeup_irq(priv, true);
1747 
1748         return 0;
1749 }
1750 
1751 static int __maybe_unused flexcan_noirq_resume(struct device *device)
1752 {
1753         struct net_device *dev = dev_get_drvdata(device);
1754         struct flexcan_priv *priv = netdev_priv(dev);
1755 
1756         if (netif_running(dev) && device_may_wakeup(device))
1757                 flexcan_enable_wakeup_irq(priv, false);
1758 
1759         return 0;
1760 }
1761 
1762 static const struct dev_pm_ops flexcan_pm_ops = {
1763         SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
1764         SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
1765         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
1766 };
1767 
1768 static struct platform_driver flexcan_driver = {
1769         .driver = {
1770                 .name = DRV_NAME,
1771                 .pm = &flexcan_pm_ops,
1772                 .of_match_table = flexcan_of_match,
1773         },
1774         .probe = flexcan_probe,
1775         .remove = flexcan_remove,
1776         .id_table = flexcan_id_table,
1777 };
1778 
1779 module_platform_driver(flexcan_driver);
1780 
1781 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1782               "Marc Kleine-Budde <kernel@pengutronix.de>");
1783 MODULE_LICENSE("GPL v2");
1784 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/can/flexcan.c

DEFINITIONS
