This source file includes following definitions.
- mcp251x_clean
- mcp251x_spi_trans
- mcp251x_read_reg
- mcp251x_read_2regs
- mcp251x_write_reg
- mcp251x_write_bits
- mcp251x_hw_tx_frame
- mcp251x_hw_tx
- mcp251x_hw_rx_frame
- mcp251x_hw_rx
- mcp251x_hw_sleep
- mcp251x_hard_start_xmit
- mcp251x_do_set_mode
- mcp251x_set_normal_mode
- mcp251x_do_set_bittiming
- mcp251x_setup
- mcp251x_hw_reset
- mcp251x_hw_probe
- mcp251x_power_enable
- mcp251x_stop
- mcp251x_error_skb
- mcp251x_tx_work_handler
- mcp251x_restart_work_handler
- mcp251x_can_ist
- mcp251x_open
- mcp251x_can_probe
- mcp251x_can_remove
- mcp251x_can_suspend
- mcp251x_can_resume
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22 #include <linux/can/core.h>
23 #include <linux/can/dev.h>
24 #include <linux/can/led.h>
25 #include <linux/can/platform/mcp251x.h>
26 #include <linux/clk.h>
27 #include <linux/completion.h>
28 #include <linux/delay.h>
29 #include <linux/device.h>
30 #include <linux/freezer.h>
31 #include <linux/interrupt.h>
32 #include <linux/io.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/netdevice.h>
36 #include <linux/property.h>
37 #include <linux/platform_device.h>
38 #include <linux/slab.h>
39 #include <linux/spi/spi.h>
40 #include <linux/uaccess.h>
41 #include <linux/regulator/consumer.h>
42
43
44 #define INSTRUCTION_WRITE 0x02
45 #define INSTRUCTION_READ 0x03
46 #define INSTRUCTION_BIT_MODIFY 0x05
47 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
48 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
49 #define INSTRUCTION_RESET 0xC0
50 #define RTS_TXB0 0x01
51 #define RTS_TXB1 0x02
52 #define RTS_TXB2 0x04
53 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
54
55
56 #define CANSTAT 0x0e
57 #define CANCTRL 0x0f
58 # define CANCTRL_REQOP_MASK 0xe0
59 # define CANCTRL_REQOP_CONF 0x80
60 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
61 # define CANCTRL_REQOP_LOOPBACK 0x40
62 # define CANCTRL_REQOP_SLEEP 0x20
63 # define CANCTRL_REQOP_NORMAL 0x00
64 # define CANCTRL_OSM 0x08
65 # define CANCTRL_ABAT 0x10
66 #define TEC 0x1c
67 #define REC 0x1d
68 #define CNF1 0x2a
69 # define CNF1_SJW_SHIFT 6
70 #define CNF2 0x29
71 # define CNF2_BTLMODE 0x80
72 # define CNF2_SAM 0x40
73 # define CNF2_PS1_SHIFT 3
74 #define CNF3 0x28
75 # define CNF3_SOF 0x08
76 # define CNF3_WAKFIL 0x04
77 # define CNF3_PHSEG2_MASK 0x07
78 #define CANINTE 0x2b
79 # define CANINTE_MERRE 0x80
80 # define CANINTE_WAKIE 0x40
81 # define CANINTE_ERRIE 0x20
82 # define CANINTE_TX2IE 0x10
83 # define CANINTE_TX1IE 0x08
84 # define CANINTE_TX0IE 0x04
85 # define CANINTE_RX1IE 0x02
86 # define CANINTE_RX0IE 0x01
87 #define CANINTF 0x2c
88 # define CANINTF_MERRF 0x80
89 # define CANINTF_WAKIF 0x40
90 # define CANINTF_ERRIF 0x20
91 # define CANINTF_TX2IF 0x10
92 # define CANINTF_TX1IF 0x08
93 # define CANINTF_TX0IF 0x04
94 # define CANINTF_RX1IF 0x02
95 # define CANINTF_RX0IF 0x01
96 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
97 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
98 # define CANINTF_ERR (CANINTF_ERRIF)
99 #define EFLG 0x2d
100 # define EFLG_EWARN 0x01
101 # define EFLG_RXWAR 0x02
102 # define EFLG_TXWAR 0x04
103 # define EFLG_RXEP 0x08
104 # define EFLG_TXEP 0x10
105 # define EFLG_TXBO 0x20
106 # define EFLG_RX0OVR 0x40
107 # define EFLG_RX1OVR 0x80
108 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
109 # define TXBCTRL_ABTF 0x40
110 # define TXBCTRL_MLOA 0x20
111 # define TXBCTRL_TXERR 0x10
112 # define TXBCTRL_TXREQ 0x08
113 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
114 # define SIDH_SHIFT 3
115 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
116 # define SIDL_SID_MASK 7
117 # define SIDL_SID_SHIFT 5
118 # define SIDL_EXIDE_SHIFT 3
119 # define SIDL_EID_SHIFT 16
120 # define SIDL_EID_MASK 3
121 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
122 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
123 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
124 # define DLC_RTR_SHIFT 6
125 #define TXBCTRL_OFF 0
126 #define TXBSIDH_OFF 1
127 #define TXBSIDL_OFF 2
128 #define TXBEID8_OFF 3
129 #define TXBEID0_OFF 4
130 #define TXBDLC_OFF 5
131 #define TXBDAT_OFF 6
132 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
133 # define RXBCTRL_BUKT 0x04
134 # define RXBCTRL_RXM0 0x20
135 # define RXBCTRL_RXM1 0x40
136 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
137 # define RXBSIDH_SHIFT 3
138 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
139 # define RXBSIDL_IDE 0x08
140 # define RXBSIDL_SRR 0x10
141 # define RXBSIDL_EID 3
142 # define RXBSIDL_SHIFT 5
143 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
144 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
145 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
146 # define RXBDLC_LEN_MASK 0x0f
147 # define RXBDLC_RTR 0x40
148 #define RXBCTRL_OFF 0
149 #define RXBSIDH_OFF 1
150 #define RXBSIDL_OFF 2
151 #define RXBEID8_OFF 3
152 #define RXBEID0_OFF 4
153 #define RXBDLC_OFF 5
154 #define RXBDAT_OFF 6
155 #define RXFSID(n) ((n < 3) ? 0 : 4)
156 #define RXFSIDH(n) ((n) * 4 + RXFSID(n))
157 #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
158 #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
159 #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
160 #define RXMSIDH(n) ((n) * 4 + 0x20)
161 #define RXMSIDL(n) ((n) * 4 + 0x21)
162 #define RXMEID8(n) ((n) * 4 + 0x22)
163 #define RXMEID0(n) ((n) * 4 + 0x23)
164
165 #define GET_BYTE(val, byte) \
166 (((val) >> ((byte) * 8)) & 0xff)
167 #define SET_BYTE(val, byte) \
168 (((val) & 0xff) << ((byte) * 8))
169
170
171
172
173 #define CAN_FRAME_MAX_DATA_LEN 8
174 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
175 #define CAN_FRAME_MAX_BITS 128
176
177 #define TX_ECHO_SKB_MAX 1
178
179 #define MCP251X_OST_DELAY_MS (5)
180
181 #define DEVICE_NAME "mcp251x"
182
183 static const struct can_bittiming_const mcp251x_bittiming_const = {
184 .name = DEVICE_NAME,
185 .tseg1_min = 3,
186 .tseg1_max = 16,
187 .tseg2_min = 2,
188 .tseg2_max = 8,
189 .sjw_max = 4,
190 .brp_min = 1,
191 .brp_max = 64,
192 .brp_inc = 1,
193 };
194
195 enum mcp251x_model {
196 CAN_MCP251X_MCP2510 = 0x2510,
197 CAN_MCP251X_MCP2515 = 0x2515,
198 CAN_MCP251X_MCP25625 = 0x25625,
199 };
200
201 struct mcp251x_priv {
202 struct can_priv can;
203 struct net_device *net;
204 struct spi_device *spi;
205 enum mcp251x_model model;
206
207 struct mutex mcp_lock;
208
209 u8 *spi_tx_buf;
210 u8 *spi_rx_buf;
211
212 struct sk_buff *tx_skb;
213 int tx_len;
214
215 struct workqueue_struct *wq;
216 struct work_struct tx_work;
217 struct work_struct restart_work;
218
219 int force_quit;
220 int after_suspend;
221 #define AFTER_SUSPEND_UP 1
222 #define AFTER_SUSPEND_DOWN 2
223 #define AFTER_SUSPEND_POWER 4
224 #define AFTER_SUSPEND_RESTART 8
225 int restart_tx;
226 struct regulator *power;
227 struct regulator *transceiver;
228 struct clk *clk;
229 };
230
231 #define MCP251X_IS(_model) \
232 static inline int mcp251x_is_##_model(struct spi_device *spi) \
233 { \
234 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
235 return priv->model == CAN_MCP251X_MCP##_model; \
236 }
237
238 MCP251X_IS(2510);
239
240 static void mcp251x_clean(struct net_device *net)
241 {
242 struct mcp251x_priv *priv = netdev_priv(net);
243
244 if (priv->tx_skb || priv->tx_len)
245 net->stats.tx_errors++;
246 dev_kfree_skb(priv->tx_skb);
247 if (priv->tx_len)
248 can_free_echo_skb(priv->net, 0);
249 priv->tx_skb = NULL;
250 priv->tx_len = 0;
251 }
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263
264
265 static int mcp251x_spi_trans(struct spi_device *spi, int len)
266 {
267 struct mcp251x_priv *priv = spi_get_drvdata(spi);
268 struct spi_transfer t = {
269 .tx_buf = priv->spi_tx_buf,
270 .rx_buf = priv->spi_rx_buf,
271 .len = len,
272 .cs_change = 0,
273 };
274 struct spi_message m;
275 int ret;
276
277 spi_message_init(&m);
278 spi_message_add_tail(&t, &m);
279
280 ret = spi_sync(spi, &m);
281 if (ret)
282 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
283 return ret;
284 }
285
286 static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
287 {
288 struct mcp251x_priv *priv = spi_get_drvdata(spi);
289 u8 val = 0;
290
291 priv->spi_tx_buf[0] = INSTRUCTION_READ;
292 priv->spi_tx_buf[1] = reg;
293
294 mcp251x_spi_trans(spi, 3);
295 val = priv->spi_rx_buf[2];
296
297 return val;
298 }
299
300 static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
301 {
302 struct mcp251x_priv *priv = spi_get_drvdata(spi);
303
304 priv->spi_tx_buf[0] = INSTRUCTION_READ;
305 priv->spi_tx_buf[1] = reg;
306
307 mcp251x_spi_trans(spi, 4);
308
309 *v1 = priv->spi_rx_buf[2];
310 *v2 = priv->spi_rx_buf[3];
311 }
312
313 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
314 {
315 struct mcp251x_priv *priv = spi_get_drvdata(spi);
316
317 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
318 priv->spi_tx_buf[1] = reg;
319 priv->spi_tx_buf[2] = val;
320
321 mcp251x_spi_trans(spi, 3);
322 }
323
324 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
325 u8 mask, u8 val)
326 {
327 struct mcp251x_priv *priv = spi_get_drvdata(spi);
328
329 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
330 priv->spi_tx_buf[1] = reg;
331 priv->spi_tx_buf[2] = mask;
332 priv->spi_tx_buf[3] = val;
333
334 mcp251x_spi_trans(spi, 4);
335 }
336
337 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
338 int len, int tx_buf_idx)
339 {
340 struct mcp251x_priv *priv = spi_get_drvdata(spi);
341
342 if (mcp251x_is_2510(spi)) {
343 int i;
344
345 for (i = 1; i < TXBDAT_OFF + len; i++)
346 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
347 buf[i]);
348 } else {
349 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
350 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
351 }
352 }
353
354 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
355 int tx_buf_idx)
356 {
357 struct mcp251x_priv *priv = spi_get_drvdata(spi);
358 u32 sid, eid, exide, rtr;
359 u8 buf[SPI_TRANSFER_BUF_LEN];
360
361 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0;
362 if (exide)
363 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
364 else
365 sid = frame->can_id & CAN_SFF_MASK;
366 eid = frame->can_id & CAN_EFF_MASK;
367 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0;
368
369 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
370 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
371 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
372 (exide << SIDL_EXIDE_SHIFT) |
373 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
374 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
375 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
376 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
377 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
378 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
379
380
381 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
382 mcp251x_spi_trans(priv->spi, 1);
383 }
384
385 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
386 int buf_idx)
387 {
388 struct mcp251x_priv *priv = spi_get_drvdata(spi);
389
390 if (mcp251x_is_2510(spi)) {
391 int i, len;
392
393 for (i = 1; i < RXBDAT_OFF; i++)
394 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
395
396 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
397 for (; i < (RXBDAT_OFF + len); i++)
398 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
399 } else {
400 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
401 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
402 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
403 }
404 }
405
406 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
407 {
408 struct mcp251x_priv *priv = spi_get_drvdata(spi);
409 struct sk_buff *skb;
410 struct can_frame *frame;
411 u8 buf[SPI_TRANSFER_BUF_LEN];
412
413 skb = alloc_can_skb(priv->net, &frame);
414 if (!skb) {
415 dev_err(&spi->dev, "cannot allocate RX skb\n");
416 priv->net->stats.rx_dropped++;
417 return;
418 }
419
420 mcp251x_hw_rx_frame(spi, buf, buf_idx);
421 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
422
423 frame->can_id = CAN_EFF_FLAG;
424 frame->can_id |=
425
426 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
427 SET_BYTE(buf[RXBEID8_OFF], 1) |
428 SET_BYTE(buf[RXBEID0_OFF], 0) |
429
430 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
431 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
432
433 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
434 frame->can_id |= CAN_RTR_FLAG;
435 } else {
436
437 frame->can_id =
438 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
439 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
440 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
441 frame->can_id |= CAN_RTR_FLAG;
442 }
443
444 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
445 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
446
447 priv->net->stats.rx_packets++;
448 priv->net->stats.rx_bytes += frame->can_dlc;
449
450 can_led_event(priv->net, CAN_LED_EVENT_RX);
451
452 netif_rx_ni(skb);
453 }
454
455 static void mcp251x_hw_sleep(struct spi_device *spi)
456 {
457 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
458 }
459
460 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
461 struct net_device *net)
462 {
463 struct mcp251x_priv *priv = netdev_priv(net);
464 struct spi_device *spi = priv->spi;
465
466 if (priv->tx_skb || priv->tx_len) {
467 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
468 return NETDEV_TX_BUSY;
469 }
470
471 if (can_dropped_invalid_skb(net, skb))
472 return NETDEV_TX_OK;
473
474 netif_stop_queue(net);
475 priv->tx_skb = skb;
476 queue_work(priv->wq, &priv->tx_work);
477
478 return NETDEV_TX_OK;
479 }
480
481 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
482 {
483 struct mcp251x_priv *priv = netdev_priv(net);
484
485 switch (mode) {
486 case CAN_MODE_START:
487 mcp251x_clean(net);
488
489 priv->can.state = CAN_STATE_ERROR_ACTIVE;
490 priv->restart_tx = 1;
491 if (priv->can.restart_ms == 0)
492 priv->after_suspend = AFTER_SUSPEND_RESTART;
493 queue_work(priv->wq, &priv->restart_work);
494 break;
495 default:
496 return -EOPNOTSUPP;
497 }
498
499 return 0;
500 }
501
502 static int mcp251x_set_normal_mode(struct spi_device *spi)
503 {
504 struct mcp251x_priv *priv = spi_get_drvdata(spi);
505 unsigned long timeout;
506
507
508 mcp251x_write_reg(spi, CANINTE,
509 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
510 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
511
512 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
513
514 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
515 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
516
517 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
518 } else {
519
520 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
521
522
523 timeout = jiffies + HZ;
524 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
525 schedule();
526 if (time_after(jiffies, timeout)) {
527 dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
528 return -EBUSY;
529 }
530 }
531 }
532 priv->can.state = CAN_STATE_ERROR_ACTIVE;
533 return 0;
534 }
535
536 static int mcp251x_do_set_bittiming(struct net_device *net)
537 {
538 struct mcp251x_priv *priv = netdev_priv(net);
539 struct can_bittiming *bt = &priv->can.bittiming;
540 struct spi_device *spi = priv->spi;
541
542 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
543 (bt->brp - 1));
544 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
545 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
546 CNF2_SAM : 0) |
547 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
548 (bt->prop_seg - 1));
549 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
550 (bt->phase_seg2 - 1));
551 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
552 mcp251x_read_reg(spi, CNF1),
553 mcp251x_read_reg(spi, CNF2),
554 mcp251x_read_reg(spi, CNF3));
555
556 return 0;
557 }
558
559 static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
560 {
561 mcp251x_do_set_bittiming(net);
562
563 mcp251x_write_reg(spi, RXBCTRL(0),
564 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
565 mcp251x_write_reg(spi, RXBCTRL(1),
566 RXBCTRL_RXM0 | RXBCTRL_RXM1);
567 return 0;
568 }
569
570 static int mcp251x_hw_reset(struct spi_device *spi)
571 {
572 struct mcp251x_priv *priv = spi_get_drvdata(spi);
573 unsigned long timeout;
574 int ret;
575
576
577 mdelay(MCP251X_OST_DELAY_MS);
578
579 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
580 ret = mcp251x_spi_trans(spi, 1);
581 if (ret)
582 return ret;
583
584
585 mdelay(MCP251X_OST_DELAY_MS);
586
587
588 timeout = jiffies + HZ;
589 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) !=
590 CANCTRL_REQOP_CONF) {
591 usleep_range(MCP251X_OST_DELAY_MS * 1000,
592 MCP251X_OST_DELAY_MS * 1000 * 2);
593
594 if (time_after(jiffies, timeout)) {
595 dev_err(&spi->dev,
596 "MCP251x didn't enter in conf mode after reset\n");
597 return -EBUSY;
598 }
599 }
600 return 0;
601 }
602
603 static int mcp251x_hw_probe(struct spi_device *spi)
604 {
605 u8 ctrl;
606 int ret;
607
608 ret = mcp251x_hw_reset(spi);
609 if (ret)
610 return ret;
611
612 ctrl = mcp251x_read_reg(spi, CANCTRL);
613
614 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
615
616
617 if ((ctrl & 0x17) != 0x07)
618 return -ENODEV;
619
620 return 0;
621 }
622
623 static int mcp251x_power_enable(struct regulator *reg, int enable)
624 {
625 if (IS_ERR_OR_NULL(reg))
626 return 0;
627
628 if (enable)
629 return regulator_enable(reg);
630 else
631 return regulator_disable(reg);
632 }
633
634 static int mcp251x_stop(struct net_device *net)
635 {
636 struct mcp251x_priv *priv = netdev_priv(net);
637 struct spi_device *spi = priv->spi;
638
639 close_candev(net);
640
641 priv->force_quit = 1;
642 free_irq(spi->irq, priv);
643 destroy_workqueue(priv->wq);
644 priv->wq = NULL;
645
646 mutex_lock(&priv->mcp_lock);
647
648
649 mcp251x_write_reg(spi, CANINTE, 0x00);
650 mcp251x_write_reg(spi, CANINTF, 0x00);
651
652 mcp251x_write_reg(spi, TXBCTRL(0), 0);
653 mcp251x_clean(net);
654
655 mcp251x_hw_sleep(spi);
656
657 mcp251x_power_enable(priv->transceiver, 0);
658
659 priv->can.state = CAN_STATE_STOPPED;
660
661 mutex_unlock(&priv->mcp_lock);
662
663 can_led_event(net, CAN_LED_EVENT_STOP);
664
665 return 0;
666 }
667
668 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
669 {
670 struct sk_buff *skb;
671 struct can_frame *frame;
672
673 skb = alloc_can_err_skb(net, &frame);
674 if (skb) {
675 frame->can_id |= can_id;
676 frame->data[1] = data1;
677 netif_rx_ni(skb);
678 } else {
679 netdev_err(net, "cannot allocate error skb\n");
680 }
681 }
682
683 static void mcp251x_tx_work_handler(struct work_struct *ws)
684 {
685 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
686 tx_work);
687 struct spi_device *spi = priv->spi;
688 struct net_device *net = priv->net;
689 struct can_frame *frame;
690
691 mutex_lock(&priv->mcp_lock);
692 if (priv->tx_skb) {
693 if (priv->can.state == CAN_STATE_BUS_OFF) {
694 mcp251x_clean(net);
695 } else {
696 frame = (struct can_frame *)priv->tx_skb->data;
697
698 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
699 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
700 mcp251x_hw_tx(spi, frame, 0);
701 priv->tx_len = 1 + frame->can_dlc;
702 can_put_echo_skb(priv->tx_skb, net, 0);
703 priv->tx_skb = NULL;
704 }
705 }
706 mutex_unlock(&priv->mcp_lock);
707 }
708
709 static void mcp251x_restart_work_handler(struct work_struct *ws)
710 {
711 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
712 restart_work);
713 struct spi_device *spi = priv->spi;
714 struct net_device *net = priv->net;
715
716 mutex_lock(&priv->mcp_lock);
717 if (priv->after_suspend) {
718 mcp251x_hw_reset(spi);
719 mcp251x_setup(net, spi);
720 priv->force_quit = 0;
721 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
722 mcp251x_set_normal_mode(spi);
723 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
724 netif_device_attach(net);
725 mcp251x_clean(net);
726 mcp251x_set_normal_mode(spi);
727 netif_wake_queue(net);
728 } else {
729 mcp251x_hw_sleep(spi);
730 }
731 priv->after_suspend = 0;
732 }
733
734 if (priv->restart_tx) {
735 priv->restart_tx = 0;
736 mcp251x_write_reg(spi, TXBCTRL(0), 0);
737 mcp251x_clean(net);
738 netif_wake_queue(net);
739 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
740 }
741 mutex_unlock(&priv->mcp_lock);
742 }
743
744 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
745 {
746 struct mcp251x_priv *priv = dev_id;
747 struct spi_device *spi = priv->spi;
748 struct net_device *net = priv->net;
749
750 mutex_lock(&priv->mcp_lock);
751 while (!priv->force_quit) {
752 enum can_state new_state;
753 u8 intf, eflag;
754 u8 clear_intf = 0;
755 int can_id = 0, data1 = 0;
756
757 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
758
759
760 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
761
762
763 if (intf & CANINTF_RX0IF) {
764 mcp251x_hw_rx(spi, 0);
765
766
767
768 if (mcp251x_is_2510(spi))
769 mcp251x_write_bits(spi, CANINTF,
770 CANINTF_RX0IF, 0x00);
771 }
772
773
774 if (intf & CANINTF_RX1IF) {
775 mcp251x_hw_rx(spi, 1);
776
777 if (mcp251x_is_2510(spi))
778 clear_intf |= CANINTF_RX1IF;
779 }
780
781
782 if (intf & (CANINTF_ERR | CANINTF_TX))
783 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
784 if (clear_intf)
785 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
786
787 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
788 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
789
790
791 if (eflag & EFLG_TXBO) {
792 new_state = CAN_STATE_BUS_OFF;
793 can_id |= CAN_ERR_BUSOFF;
794 } else if (eflag & EFLG_TXEP) {
795 new_state = CAN_STATE_ERROR_PASSIVE;
796 can_id |= CAN_ERR_CRTL;
797 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
798 } else if (eflag & EFLG_RXEP) {
799 new_state = CAN_STATE_ERROR_PASSIVE;
800 can_id |= CAN_ERR_CRTL;
801 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
802 } else if (eflag & EFLG_TXWAR) {
803 new_state = CAN_STATE_ERROR_WARNING;
804 can_id |= CAN_ERR_CRTL;
805 data1 |= CAN_ERR_CRTL_TX_WARNING;
806 } else if (eflag & EFLG_RXWAR) {
807 new_state = CAN_STATE_ERROR_WARNING;
808 can_id |= CAN_ERR_CRTL;
809 data1 |= CAN_ERR_CRTL_RX_WARNING;
810 } else {
811 new_state = CAN_STATE_ERROR_ACTIVE;
812 }
813
814
815 switch (priv->can.state) {
816 case CAN_STATE_ERROR_ACTIVE:
817 if (new_state >= CAN_STATE_ERROR_WARNING &&
818 new_state <= CAN_STATE_BUS_OFF)
819 priv->can.can_stats.error_warning++;
820
821 case CAN_STATE_ERROR_WARNING:
822 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
823 new_state <= CAN_STATE_BUS_OFF)
824 priv->can.can_stats.error_passive++;
825 break;
826 default:
827 break;
828 }
829 priv->can.state = new_state;
830
831 if (intf & CANINTF_ERRIF) {
832
833 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
834 if (eflag & EFLG_RX0OVR) {
835 net->stats.rx_over_errors++;
836 net->stats.rx_errors++;
837 }
838 if (eflag & EFLG_RX1OVR) {
839 net->stats.rx_over_errors++;
840 net->stats.rx_errors++;
841 }
842 can_id |= CAN_ERR_CRTL;
843 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
844 }
845 mcp251x_error_skb(net, can_id, data1);
846 }
847
848 if (priv->can.state == CAN_STATE_BUS_OFF) {
849 if (priv->can.restart_ms == 0) {
850 priv->force_quit = 1;
851 priv->can.can_stats.bus_off++;
852 can_bus_off(net);
853 mcp251x_hw_sleep(spi);
854 break;
855 }
856 }
857
858 if (intf == 0)
859 break;
860
861 if (intf & CANINTF_TX) {
862 net->stats.tx_packets++;
863 net->stats.tx_bytes += priv->tx_len - 1;
864 can_led_event(net, CAN_LED_EVENT_TX);
865 if (priv->tx_len) {
866 can_get_echo_skb(net, 0);
867 priv->tx_len = 0;
868 }
869 netif_wake_queue(net);
870 }
871 }
872 mutex_unlock(&priv->mcp_lock);
873 return IRQ_HANDLED;
874 }
875
876 static int mcp251x_open(struct net_device *net)
877 {
878 struct mcp251x_priv *priv = netdev_priv(net);
879 struct spi_device *spi = priv->spi;
880 unsigned long flags = 0;
881 int ret;
882
883 ret = open_candev(net);
884 if (ret) {
885 dev_err(&spi->dev, "unable to set initial baudrate!\n");
886 return ret;
887 }
888
889 mutex_lock(&priv->mcp_lock);
890 mcp251x_power_enable(priv->transceiver, 1);
891
892 priv->force_quit = 0;
893 priv->tx_skb = NULL;
894 priv->tx_len = 0;
895
896 if (!dev_fwnode(&spi->dev))
897 flags = IRQF_TRIGGER_FALLING;
898
899 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
900 flags | IRQF_ONESHOT, dev_name(&spi->dev),
901 priv);
902 if (ret) {
903 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
904 goto out_close;
905 }
906
907 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
908 0);
909 if (!priv->wq) {
910 ret = -ENOMEM;
911 goto out_clean;
912 }
913 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
914 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
915
916 ret = mcp251x_hw_reset(spi);
917 if (ret)
918 goto out_free_wq;
919 ret = mcp251x_setup(net, spi);
920 if (ret)
921 goto out_free_wq;
922 ret = mcp251x_set_normal_mode(spi);
923 if (ret)
924 goto out_free_wq;
925
926 can_led_event(net, CAN_LED_EVENT_OPEN);
927
928 netif_wake_queue(net);
929 mutex_unlock(&priv->mcp_lock);
930
931 return 0;
932
933 out_free_wq:
934 destroy_workqueue(priv->wq);
935 out_clean:
936 free_irq(spi->irq, priv);
937 mcp251x_hw_sleep(spi);
938 out_close:
939 mcp251x_power_enable(priv->transceiver, 0);
940 close_candev(net);
941 mutex_unlock(&priv->mcp_lock);
942 return ret;
943 }
944
945 static const struct net_device_ops mcp251x_netdev_ops = {
946 .ndo_open = mcp251x_open,
947 .ndo_stop = mcp251x_stop,
948 .ndo_start_xmit = mcp251x_hard_start_xmit,
949 .ndo_change_mtu = can_change_mtu,
950 };
951
952 static const struct of_device_id mcp251x_of_match[] = {
953 {
954 .compatible = "microchip,mcp2510",
955 .data = (void *)CAN_MCP251X_MCP2510,
956 },
957 {
958 .compatible = "microchip,mcp2515",
959 .data = (void *)CAN_MCP251X_MCP2515,
960 },
961 {
962 .compatible = "microchip,mcp25625",
963 .data = (void *)CAN_MCP251X_MCP25625,
964 },
965 { }
966 };
967 MODULE_DEVICE_TABLE(of, mcp251x_of_match);
968
969 static const struct spi_device_id mcp251x_id_table[] = {
970 {
971 .name = "mcp2510",
972 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
973 },
974 {
975 .name = "mcp2515",
976 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
977 },
978 {
979 .name = "mcp25625",
980 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
981 },
982 { }
983 };
984 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
985
986 static int mcp251x_can_probe(struct spi_device *spi)
987 {
988 const void *match = device_get_match_data(&spi->dev);
989 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev);
990 struct net_device *net;
991 struct mcp251x_priv *priv;
992 struct clk *clk;
993 int freq, ret;
994
995 clk = devm_clk_get_optional(&spi->dev, NULL);
996 if (IS_ERR(clk))
997 return PTR_ERR(clk);
998
999 freq = clk_get_rate(clk);
1000 if (freq == 0 && pdata)
1001 freq = pdata->oscillator_frequency;
1002
1003
1004 if (freq < 1000000 || freq > 25000000)
1005 return -ERANGE;
1006
1007
1008 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1009 if (!net)
1010 return -ENOMEM;
1011
1012 ret = clk_prepare_enable(clk);
1013 if (ret)
1014 goto out_free;
1015
1016 net->netdev_ops = &mcp251x_netdev_ops;
1017 net->flags |= IFF_ECHO;
1018
1019 priv = netdev_priv(net);
1020 priv->can.bittiming_const = &mcp251x_bittiming_const;
1021 priv->can.do_set_mode = mcp251x_do_set_mode;
1022 priv->can.clock.freq = freq / 2;
1023 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1024 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1025 if (match)
1026 priv->model = (enum mcp251x_model)match;
1027 else
1028 priv->model = spi_get_device_id(spi)->driver_data;
1029 priv->net = net;
1030 priv->clk = clk;
1031
1032 spi_set_drvdata(spi, priv);
1033
1034
1035 spi->bits_per_word = 8;
1036 if (mcp251x_is_2510(spi))
1037 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1038 else
1039 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1040 ret = spi_setup(spi);
1041 if (ret)
1042 goto out_clk;
1043
1044 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1045 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1046 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1047 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1048 ret = -EPROBE_DEFER;
1049 goto out_clk;
1050 }
1051
1052 ret = mcp251x_power_enable(priv->power, 1);
1053 if (ret)
1054 goto out_clk;
1055
1056 priv->spi = spi;
1057 mutex_init(&priv->mcp_lock);
1058
1059 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1060 GFP_KERNEL);
1061 if (!priv->spi_tx_buf) {
1062 ret = -ENOMEM;
1063 goto error_probe;
1064 }
1065
1066 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1067 GFP_KERNEL);
1068 if (!priv->spi_rx_buf) {
1069 ret = -ENOMEM;
1070 goto error_probe;
1071 }
1072
1073 SET_NETDEV_DEV(net, &spi->dev);
1074
1075
1076 ret = mcp251x_hw_probe(spi);
1077 if (ret) {
1078 if (ret == -ENODEV)
1079 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
1080 priv->model);
1081 goto error_probe;
1082 }
1083
1084 mcp251x_hw_sleep(spi);
1085
1086 ret = register_candev(net);
1087 if (ret)
1088 goto error_probe;
1089
1090 devm_can_led_init(net);
1091
1092 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1093 return 0;
1094
1095 error_probe:
1096 mcp251x_power_enable(priv->power, 0);
1097
1098 out_clk:
1099 clk_disable_unprepare(clk);
1100
1101 out_free:
1102 free_candev(net);
1103
1104 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1105 return ret;
1106 }
1107
1108 static int mcp251x_can_remove(struct spi_device *spi)
1109 {
1110 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1111 struct net_device *net = priv->net;
1112
1113 unregister_candev(net);
1114
1115 mcp251x_power_enable(priv->power, 0);
1116
1117 clk_disable_unprepare(priv->clk);
1118
1119 free_candev(net);
1120
1121 return 0;
1122 }
1123
1124 static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1125 {
1126 struct spi_device *spi = to_spi_device(dev);
1127 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1128 struct net_device *net = priv->net;
1129
1130 priv->force_quit = 1;
1131 disable_irq(spi->irq);
1132
1133
1134
1135 if (netif_running(net)) {
1136 netif_device_detach(net);
1137
1138 mcp251x_hw_sleep(spi);
1139 mcp251x_power_enable(priv->transceiver, 0);
1140 priv->after_suspend = AFTER_SUSPEND_UP;
1141 } else {
1142 priv->after_suspend = AFTER_SUSPEND_DOWN;
1143 }
1144
1145 mcp251x_power_enable(priv->power, 0);
1146 priv->after_suspend |= AFTER_SUSPEND_POWER;
1147
1148 return 0;
1149 }
1150
1151 static int __maybe_unused mcp251x_can_resume(struct device *dev)
1152 {
1153 struct spi_device *spi = to_spi_device(dev);
1154 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1155
1156 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1157 mcp251x_power_enable(priv->power, 1);
1158
1159 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1160 mcp251x_power_enable(priv->transceiver, 1);
1161 queue_work(priv->wq, &priv->restart_work);
1162 } else {
1163 priv->after_suspend = 0;
1164 }
1165
1166 priv->force_quit = 0;
1167 enable_irq(spi->irq);
1168 return 0;
1169 }
1170
1171 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1172 mcp251x_can_resume);
1173
1174 static struct spi_driver mcp251x_can_driver = {
1175 .driver = {
1176 .name = DEVICE_NAME,
1177 .of_match_table = mcp251x_of_match,
1178 .pm = &mcp251x_can_pm_ops,
1179 },
1180 .id_table = mcp251x_id_table,
1181 .probe = mcp251x_can_probe,
1182 .remove = mcp251x_can_remove,
1183 };
1184 module_spi_driver(mcp251x_can_driver);
1185
1186 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1187 "Christian Pellegrin <chripell@evolware.org>");
1188 MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
1189 MODULE_LICENSE("GPL v2");