This source file includes following definitions.
- get_registers
- set_registers
- rtl_set_unplug
- generic_ocp_read
- generic_ocp_write
- pla_ocp_read
- pla_ocp_write
- usb_ocp_write
- ocp_read_dword
- ocp_write_dword
- ocp_read_word
- ocp_write_word
- ocp_read_byte
- ocp_write_byte
- ocp_reg_read
- ocp_reg_write
- r8152_mdio_write
- r8152_mdio_read
- sram_write
- sram_read
- read_mii_word
- write_mii_word
- rtl8152_set_mac_address
- vendor_mac_passthru_addr_read
- determine_ethernet_addr
- set_ethernet_addr
- read_bulk_callback
- write_bulk_callback
- intr_callback
- rx_agg_align
- tx_agg_align
- free_rx_agg
- alloc_rx_agg
- free_all_mem
- alloc_all_mem
- r8152_get_tx_agg
- r8152_csum_workaround
- msdn_giant_send_check
- rtl_tx_vlan_tag
- rtl_rx_vlan_tag
- r8152_tx_csum
- r8152_tx_agg_fill
- r8152_rx_csum
- rx_count_exceed
- agg_offset
- rtl_get_free_rx
- rx_bottom
- tx_bottom
- bottom_half
- r8152_poll
- r8152_submit_rx
- rtl_drop_queued_tx
- rtl8152_tx_timeout
- rtl8152_set_rx_mode
- _rtl8152_set_rx_mode
- rtl8152_features_check
- rtl8152_start_xmit
- r8152b_reset_packet_filter
- rtl8152_nic_reset
- set_tx_qlen
- rtl8152_get_speed
- rtl_set_eee_plus
- rxdy_gated_en
- rtl_start_rx
- rtl_stop_rx
- r8153b_rx_agg_chg_indicate
- rtl_enable
- rtl8152_enable
- r8153_set_rx_early_timeout
- r8153_set_rx_early_size
- rtl8153_enable
- rtl_disable
- r8152_power_cut_en
- rtl_rx_vlan_en
- rtl8152_set_features
- __rtl_get_wol
- __rtl_set_wol
- r8153_mac_clk_spd
- r8153_u1u2en
- r8153b_u1u2en
- r8153_u2p3en
- r8153b_ups_flags
- r8153b_green_en
- r8153_phy_status
- r8153b_ups_en
- r8153_power_cut_en
- r8153b_power_cut_en
- r8153_queue_wake
- rtl_can_wakeup
- rtl_runtime_suspend_enable
- rtl8153_runtime_enable
- rtl8153b_runtime_enable
- r8153_teredo_off
- rtl_reset_bmu
- r8152_aldps_en
- r8152_mmd_indirect
- r8152_mmd_read
- r8152_mmd_write
- r8152_eee_en
- r8153_eee_en
- rtl_eee_enable
- r8152b_enable_fc
- rtl8152_disable
- r8152b_hw_phy_cfg
- r8152b_exit_oob
- r8152b_enter_oob
- r8153_patch_request
- r8153_aldps_en
- r8153_hw_phy_cfg
- r8152_efuse_read
- r8153b_hw_phy_cfg
- r8153_first_init
- r8153_enter_oob
- rtl8153_disable
- rtl8152_set_speed
- rtl8152_up
- rtl8152_down
- rtl8153_up
- rtl8153_down
- rtl8153b_up
- rtl8153b_down
- rtl8152_in_nway
- rtl8153_in_nway
- set_carrier
- rtl_work_func_t
- rtl_hw_phy_work_func_t
- rtl_notifier
- rtl8152_open
- rtl8152_close
- rtl_tally_reset
- r8152b_init
- r8153_init
- r8153b_init
- rtl8152_pre_reset
- rtl8152_post_reset
- delay_autosuspend
- rtl8152_runtime_resume
- rtl8152_system_resume
- rtl8152_runtime_suspend
- rtl8152_system_suspend
- rtl8152_suspend
- rtl8152_resume
- rtl8152_reset_resume
- rtl8152_get_wol
- rtl8152_set_wol
- rtl8152_get_msglevel
- rtl8152_set_msglevel
- rtl8152_get_drvinfo
- rtl8152_get_link_ksettings
- rtl8152_set_link_ksettings
- rtl8152_get_sset_count
- rtl8152_get_ethtool_stats
- rtl8152_get_strings
- r8152_get_eee
- r8152_set_eee
- r8153_get_eee
- rtl_ethtool_get_eee
- rtl_ethtool_set_eee
- rtl8152_nway_reset
- rtl8152_get_coalesce
- rtl8152_set_coalesce
- rtl8152_get_tunable
- rtl8152_set_tunable
- rtl8152_get_ringparam
- rtl8152_set_ringparam
- rtl8152_ioctl
- rtl8152_change_mtu
- rtl8152_unload
- rtl8153_unload
- rtl8153b_unload
- rtl_ops_init
- rtl_get_version
- rtl8152_probe
- rtl8152_disconnect
1
2
3
4
5
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27
28
29 #define NETNEXT_VERSION "10"
30
31
32 #define NET_VERSION "11"
33
34 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
35 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
36 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
37 #define MODULENAME "r8152"
38
39 #define R8152_PHY_ID 32
40
41 #define PLA_IDR 0xc000
42 #define PLA_RCR 0xc010
43 #define PLA_RMS 0xc016
44 #define PLA_RXFIFO_CTRL0 0xc0a0
45 #define PLA_RXFIFO_CTRL1 0xc0a4
46 #define PLA_RXFIFO_CTRL2 0xc0a8
47 #define PLA_DMY_REG0 0xc0b0
48 #define PLA_FMC 0xc0b4
49 #define PLA_CFG_WOL 0xc0b6
50 #define PLA_TEREDO_CFG 0xc0bc
51 #define PLA_TEREDO_WAKE_BASE 0xc0c4
52 #define PLA_MAR 0xcd00
53 #define PLA_BACKUP 0xd000
54 #define PLA_BDC_CR 0xd1a0
55 #define PLA_TEREDO_TIMER 0xd2cc
56 #define PLA_REALWOW_TIMER 0xd2e8
57 #define PLA_SUSPEND_FLAG 0xd38a
58 #define PLA_INDICATE_FALG 0xd38c
59 #define PLA_EXTRA_STATUS 0xd398
60 #define PLA_EFUSE_DATA 0xdd00
61 #define PLA_EFUSE_CMD 0xdd02
62 #define PLA_LEDSEL 0xdd90
63 #define PLA_LED_FEATURE 0xdd92
64 #define PLA_PHYAR 0xde00
65 #define PLA_BOOT_CTRL 0xe004
66 #define PLA_LWAKE_CTRL_REG 0xe007
67 #define PLA_GPHY_INTR_IMR 0xe022
68 #define PLA_EEE_CR 0xe040
69 #define PLA_EEEP_CR 0xe080
70 #define PLA_MAC_PWR_CTRL 0xe0c0
71 #define PLA_MAC_PWR_CTRL2 0xe0ca
72 #define PLA_MAC_PWR_CTRL3 0xe0cc
73 #define PLA_MAC_PWR_CTRL4 0xe0ce
74 #define PLA_WDT6_CTRL 0xe428
75 #define PLA_TCR0 0xe610
76 #define PLA_TCR1 0xe612
77 #define PLA_MTPS 0xe615
78 #define PLA_TXFIFO_CTRL 0xe618
79 #define PLA_RSTTALLY 0xe800
80 #define PLA_CR 0xe813
81 #define PLA_CRWECR 0xe81c
82 #define PLA_CONFIG12 0xe81e
83 #define PLA_CONFIG34 0xe820
84 #define PLA_CONFIG5 0xe822
85 #define PLA_PHY_PWR 0xe84c
86 #define PLA_OOB_CTRL 0xe84f
87 #define PLA_CPCR 0xe854
88 #define PLA_MISC_0 0xe858
89 #define PLA_MISC_1 0xe85a
90 #define PLA_OCP_GPHY_BASE 0xe86c
91 #define PLA_TALLYCNT 0xe890
92 #define PLA_SFF_STS_7 0xe8de
93 #define PLA_PHYSTATUS 0xe908
94 #define PLA_CONFIG6 0xe90a
95 #define PLA_BP_BA 0xfc26
96 #define PLA_BP_0 0xfc28
97 #define PLA_BP_1 0xfc2a
98 #define PLA_BP_2 0xfc2c
99 #define PLA_BP_3 0xfc2e
100 #define PLA_BP_4 0xfc30
101 #define PLA_BP_5 0xfc32
102 #define PLA_BP_6 0xfc34
103 #define PLA_BP_7 0xfc36
104 #define PLA_BP_EN 0xfc38
105
106 #define USB_USB2PHY 0xb41e
107 #define USB_SSPHYLINK1 0xb426
108 #define USB_SSPHYLINK2 0xb428
109 #define USB_U2P3_CTRL 0xb460
110 #define USB_CSR_DUMMY1 0xb464
111 #define USB_CSR_DUMMY2 0xb466
112 #define USB_DEV_STAT 0xb808
113 #define USB_CONNECT_TIMER 0xcbf8
114 #define USB_MSC_TIMER 0xcbfc
115 #define USB_BURST_SIZE 0xcfc0
116 #define USB_LPM_CONFIG 0xcfd8
117 #define USB_USB_CTRL 0xd406
118 #define USB_PHY_CTRL 0xd408
119 #define USB_TX_AGG 0xd40a
120 #define USB_RX_BUF_TH 0xd40c
121 #define USB_USB_TIMER 0xd428
122 #define USB_RX_EARLY_TIMEOUT 0xd42c
123 #define USB_RX_EARLY_SIZE 0xd42e
124 #define USB_PM_CTRL_STATUS 0xd432
125 #define USB_RX_EXTRA_AGGR_TMR 0xd432
126 #define USB_TX_DMA 0xd434
127 #define USB_UPT_RXDMA_OWN 0xd437
128 #define USB_TOLERANCE 0xd490
129 #define USB_LPM_CTRL 0xd41a
130 #define USB_BMU_RESET 0xd4b0
131 #define USB_U1U2_TIMER 0xd4da
132 #define USB_UPS_CTRL 0xd800
133 #define USB_POWER_CUT 0xd80a
134 #define USB_MISC_0 0xd81a
135 #define USB_MISC_1 0xd81f
136 #define USB_AFE_CTRL2 0xd824
137 #define USB_UPS_CFG 0xd842
138 #define USB_UPS_FLAGS 0xd848
139 #define USB_WDT11_CTRL 0xe43c
140 #define USB_BP_BA 0xfc26
141 #define USB_BP_0 0xfc28
142 #define USB_BP_1 0xfc2a
143 #define USB_BP_2 0xfc2c
144 #define USB_BP_3 0xfc2e
145 #define USB_BP_4 0xfc30
146 #define USB_BP_5 0xfc32
147 #define USB_BP_6 0xfc34
148 #define USB_BP_7 0xfc36
149 #define USB_BP_EN 0xfc38
150 #define USB_BP_8 0xfc38
151 #define USB_BP_9 0xfc3a
152 #define USB_BP_10 0xfc3c
153 #define USB_BP_11 0xfc3e
154 #define USB_BP_12 0xfc40
155 #define USB_BP_13 0xfc42
156 #define USB_BP_14 0xfc44
157 #define USB_BP_15 0xfc46
158 #define USB_BP2_EN 0xfc48
159
160
161 #define OCP_ALDPS_CONFIG 0x2010
162 #define OCP_EEE_CONFIG1 0x2080
163 #define OCP_EEE_CONFIG2 0x2092
164 #define OCP_EEE_CONFIG3 0x2094
165 #define OCP_BASE_MII 0xa400
166 #define OCP_EEE_AR 0xa41a
167 #define OCP_EEE_DATA 0xa41c
168 #define OCP_PHY_STATUS 0xa420
169 #define OCP_NCTL_CFG 0xa42c
170 #define OCP_POWER_CFG 0xa430
171 #define OCP_EEE_CFG 0xa432
172 #define OCP_SRAM_ADDR 0xa436
173 #define OCP_SRAM_DATA 0xa438
174 #define OCP_DOWN_SPEED 0xa442
175 #define OCP_EEE_ABLE 0xa5c4
176 #define OCP_EEE_ADV 0xa5d0
177 #define OCP_EEE_LPABLE 0xa5d2
178 #define OCP_PHY_STATE 0xa708
179 #define OCP_PHY_PATCH_STAT 0xb800
180 #define OCP_PHY_PATCH_CMD 0xb820
181 #define OCP_ADC_IOFFSET 0xbcfc
182 #define OCP_ADC_CFG 0xbc06
183 #define OCP_SYSCLK_CFG 0xc416
184
185
186 #define SRAM_GREEN_CFG 0x8011
187 #define SRAM_LPF_CFG 0x8012
188 #define SRAM_10M_AMP1 0x8080
189 #define SRAM_10M_AMP2 0x8082
190 #define SRAM_IMPEDANCE 0x8084
191
192
193 #define RCR_AAP 0x00000001
194 #define RCR_APM 0x00000002
195 #define RCR_AM 0x00000004
196 #define RCR_AB 0x00000008
197 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
198
199
200 #define RXFIFO_THR1_NORMAL 0x00080002
201 #define RXFIFO_THR1_OOB 0x01800003
202
203
204 #define RXFIFO_THR2_FULL 0x00000060
205 #define RXFIFO_THR2_HIGH 0x00000038
206 #define RXFIFO_THR2_OOB 0x0000004a
207 #define RXFIFO_THR2_NORMAL 0x00a0
208
209
210 #define RXFIFO_THR3_FULL 0x00000078
211 #define RXFIFO_THR3_HIGH 0x00000048
212 #define RXFIFO_THR3_OOB 0x0000005a
213 #define RXFIFO_THR3_NORMAL 0x0110
214
215
216 #define TXFIFO_THR_NORMAL 0x00400008
217 #define TXFIFO_THR_NORMAL2 0x01000008
218
219
220 #define ECM_ALDPS 0x0002
221
222
223 #define FMC_FCR_MCU_EN 0x0001
224
225
226 #define EEEP_CR_EEEP_TX 0x0002
227
228
229 #define WDT6_SET_MODE 0x0010
230
231
232 #define TCR0_TX_EMPTY 0x0800
233 #define TCR0_AUTO_FIFO 0x0080
234
235
236 #define VERSION_MASK 0x7cf0
237
238
239 #define MTPS_JUMBO (12 * 1024 / 64)
240 #define MTPS_DEFAULT (6 * 1024 / 64)
241
242
243 #define TALLY_RESET 0x0001
244
245
246 #define CR_RST 0x10
247 #define CR_RE 0x08
248 #define CR_TE 0x04
249
250
251 #define CRWECR_NORAML 0x00
252 #define CRWECR_CONFIG 0xc0
253
254
255 #define NOW_IS_OOB 0x80
256 #define TXFIFO_EMPTY 0x20
257 #define RXFIFO_EMPTY 0x10
258 #define LINK_LIST_READY 0x02
259 #define DIS_MCU_CLROOB 0x01
260 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
261
262
263 #define RXDY_GATED_EN 0x0008
264
265
266 #define RE_INIT_LL 0x8000
267 #define MCU_BORW_EN 0x4000
268
269
270 #define CPCR_RX_VLAN 0x0040
271
272
273 #define MAGIC_EN 0x0001
274
275
276 #define TEREDO_SEL 0x8000
277 #define TEREDO_WAKE_MASK 0x7f00
278 #define TEREDO_RS_EVENT_MASK 0x00fe
279 #define OOB_TEREDO_EN 0x0001
280
281
282 #define ALDPS_PROXY_MODE 0x0001
283
284
285 #define EFUSE_READ_CMD BIT(15)
286 #define EFUSE_DATA_BIT16 BIT(7)
287
288
289 #define LINK_ON_WAKE_EN 0x0010
290 #define LINK_OFF_WAKE_EN 0x0008
291
292
293 #define LANWAKE_CLR_EN BIT(0)
294
295
296 #define BWF_EN 0x0040
297 #define MWF_EN 0x0020
298 #define UWF_EN 0x0010
299 #define LAN_WAKE_EN 0x0002
300
301
302 #define LED_MODE_MASK 0x0700
303
304
305 #define TX_10M_IDLE_EN 0x0080
306 #define PFM_PWM_SWITCH 0x0040
307 #define TEST_IO_OFF BIT(4)
308
309
310 #define D3_CLK_GATED_EN 0x00004000
311 #define MCU_CLK_RATIO 0x07010f07
312 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
313 #define ALDPS_SPDWN_RATIO 0x0f87
314
315
316 #define EEE_SPDWN_RATIO 0x8007
317 #define MAC_CLK_SPDWN_EN BIT(15)
318
319
320 #define PLA_MCU_SPDWN_EN BIT(14)
321 #define PKT_AVAIL_SPDWN_EN 0x0100
322 #define SUSPEND_SPDWN_EN 0x0004
323 #define U1U2_SPDWN_EN 0x0002
324 #define L1_SPDWN_EN 0x0001
325
326
327 #define PWRSAVE_SPDWN_EN 0x1000
328 #define RXDV_SPDWN_EN 0x0800
329 #define TX10MIDLE_EN 0x0100
330 #define TP100_SPDWN_EN 0x0020
331 #define TP500_SPDWN_EN 0x0010
332 #define TP1000_SPDWN_EN 0x0008
333 #define EEE_SPDWN_EN 0x0001
334
335
336 #define GPHY_STS_MSK 0x0001
337 #define SPEED_DOWN_MSK 0x0002
338 #define SPDWN_RXDV_MSK 0x0004
339 #define SPDWN_LINKCHG_MSK 0x0008
340
341
342 #define PHYAR_FLAG 0x80000000
343
344
345 #define EEE_RX_EN 0x0001
346 #define EEE_TX_EN 0x0002
347
348
349 #define AUTOLOAD_DONE 0x0002
350
351
352 #define LANWAKE_PIN BIT(7)
353
354
355 #define LINK_CHG_EVENT BIT(0)
356
357
358 #define UPCOMING_RUNTIME_D3 BIT(0)
359
360
361 #define LINK_CHANGE_FLAG BIT(8)
362
363
364 #define USB2PHY_SUSPEND 0x0001
365 #define USB2PHY_L1 0x0002
366
367
368 #define DELAY_PHY_PWR_CHG BIT(1)
369
370
371 #define pwd_dn_scale_mask 0x3ffe
372 #define pwd_dn_scale(x) ((x) << 1)
373
374
375 #define DYNAMIC_BURST 0x0001
376
377
378 #define EP4_FULL_FC 0x0001
379
380
381 #define STAT_SPEED_MASK 0x0006
382 #define STAT_SPEED_HIGH 0x0000
383 #define STAT_SPEED_FULL 0x0002
384
385
386 #define LPM_U1U2_EN BIT(0)
387
388
389 #define TX_AGG_MAX_THRESHOLD 0x03
390
391
392 #define RX_THR_SUPPER 0x0c350180
393 #define RX_THR_HIGH 0x7a120180
394 #define RX_THR_SLOW 0xffff0180
395 #define RX_THR_B 0x00010001
396
397
398 #define TEST_MODE_DISABLE 0x00000001
399 #define TX_SIZE_ADJUST1 0x00000100
400
401
402 #define BMU_RESET_EP_IN 0x01
403 #define BMU_RESET_EP_OUT 0x02
404
405
406 #define OWN_UPDATE BIT(0)
407 #define OWN_CLEAR BIT(1)
408
409
410 #define POWER_CUT 0x0100
411
412
413 #define RESUME_INDICATE 0x0001
414
415
416 #define RX_AGG_DISABLE 0x0010
417 #define RX_ZERO_EN 0x0080
418
419
420 #define U2P3_ENABLE 0x0001
421
422
423 #define PWR_EN 0x0001
424 #define PHASE2_EN 0x0008
425 #define UPS_EN BIT(4)
426 #define USP_PREWAKE BIT(5)
427
428
429 #define PCUT_STATUS 0x0001
430
431
432 #define COALESCE_SUPER 85000U
433 #define COALESCE_HIGH 250000U
434 #define COALESCE_SLOW 524280U
435
436
437 #define TIMER11_EN 0x0001
438
439
440
441 #define FIFO_EMPTY_1FB 0x30
442
443 #define LPM_TIMER_MASK 0x0c
444 #define LPM_TIMER_500MS 0x04
445 #define LPM_TIMER_500US 0x0c
446 #define ROK_EXIT_LPM 0x02
447
448
449 #define SEN_VAL_MASK 0xf800
450 #define SEN_VAL_NORMAL 0xa000
451 #define SEL_RXIDLE 0x0100
452
453
454 #define SAW_CNT_1MS_MASK 0x0fff
455
456
457 #define UPS_FLAGS_R_TUNE BIT(0)
458 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
459 #define UPS_FLAGS_250M_CKDIV BIT(2)
460 #define UPS_FLAGS_EN_ALDPS BIT(3)
461 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
462 #define ups_flags_speed(x) ((x) << 16)
463 #define UPS_FLAGS_EN_EEE BIT(20)
464 #define UPS_FLAGS_EN_500M_EEE BIT(21)
465 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
466 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
467 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
468 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
469 #define UPS_FLAGS_EN_GREEN BIT(26)
470 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
471
472 enum spd_duplex {
473 NWAY_10M_HALF,
474 NWAY_10M_FULL,
475 NWAY_100M_HALF,
476 NWAY_100M_FULL,
477 NWAY_1000M_FULL,
478 FORCE_10M_HALF,
479 FORCE_10M_FULL,
480 FORCE_100M_HALF,
481 FORCE_100M_FULL,
482 };
483
484
485 #define ENPWRSAVE 0x8000
486 #define ENPDNPS 0x0200
487 #define LINKENA 0x0100
488 #define DIS_SDSAVE 0x0010
489
490
491 #define PHY_STAT_MASK 0x0007
492 #define PHY_STAT_EXT_INIT 2
493 #define PHY_STAT_LAN_ON 3
494 #define PHY_STAT_PWRDN 5
495
496
497 #define PGA_RETURN_EN BIT(1)
498
499
500 #define EEE_CLKDIV_EN 0x8000
501 #define EN_ALDPS 0x0004
502 #define EN_10M_PLLOFF 0x0001
503
504
505 #define RG_TXLPI_MSK_HFDUP 0x8000
506 #define RG_MATCLR_EN 0x4000
507 #define EEE_10_CAP 0x2000
508 #define EEE_NWAY_EN 0x1000
509 #define TX_QUIET_EN 0x0200
510 #define RX_QUIET_EN 0x0100
511 #define sd_rise_time_mask 0x0070
512 #define sd_rise_time(x) (min(x, 7) << 4)
513 #define RG_RXLPI_MSK_HFDUP 0x0008
514 #define SDFALLTIME 0x0007
515
516
517 #define RG_LPIHYS_NUM 0x7000
518 #define RG_DACQUIET_EN 0x0400
519 #define RG_LDVQUIET_EN 0x0200
520 #define RG_CKRSEL 0x0020
521 #define RG_EEEPRG_EN 0x0010
522
523
524 #define fast_snr_mask 0xff80
525 #define fast_snr(x) (min(x, 0x1ff) << 7)
526 #define RG_LFS_SEL 0x0060
527 #define MSK_PH 0x0006
528
529
530
531 #define FUN_ADDR 0x0000
532 #define FUN_DATA 0x4000
533
534
535
536 #define CTAP_SHORT_EN 0x0040
537 #define EEE10_EN 0x0010
538
539
540 #define EN_EEE_CMODE BIT(14)
541 #define EN_EEE_1000 BIT(13)
542 #define EN_EEE_100 BIT(12)
543 #define EN_10M_CLKDIV BIT(11)
544 #define EN_10M_BGOFF 0x0080
545
546
547 #define TXDIS_STATE 0x01
548 #define ABD_STATE 0x02
549
550
551 #define PATCH_READY BIT(6)
552
553
554 #define PATCH_REQUEST BIT(4)
555
556
557 #define CKADSEL_L 0x0100
558 #define ADC_EN 0x0080
559 #define EN_EMI_L 0x0040
560
561
562 #define clk_div_expo(x) (min(x, 5) << 8)
563
564
565 #define GREEN_ETH_EN BIT(15)
566 #define R_TUNE_EN BIT(11)
567
568
569 #define LPF_AUTO_TUNE 0x8000
570
571
572 #define GDAC_IB_UPALL 0x0008
573
574
575 #define AMP_DN 0x0200
576
577
578 #define RX_DRIVING_MASK 0x6000
579
580
581 #define AD_MASK 0xfee0
582 #define BND_MASK 0x0004
583 #define BD_MASK 0x0001
584 #define EFUSE 0xcfdb
585 #define PASS_THRU_MASK 0x1
586
587 enum rtl_register_content {
588 _1000bps = 0x10,
589 _100bps = 0x08,
590 _10bps = 0x04,
591 LINK_STATUS = 0x02,
592 FULL_DUP = 0x01,
593 };
594
595 #define RTL8152_MAX_TX 4
596 #define RTL8152_MAX_RX 10
597 #define INTBUFSIZE 2
598 #define TX_ALIGN 4
599 #define RX_ALIGN 8
600
601 #define RTL8152_RX_MAX_PENDING 4096
602 #define RTL8152_RXFG_HEADSZ 256
603
604 #define INTR_LINK 0x0004
605
606 #define RTL8152_REQT_READ 0xc0
607 #define RTL8152_REQT_WRITE 0x40
608 #define RTL8152_REQ_GET_REGS 0x05
609 #define RTL8152_REQ_SET_REGS 0x05
610
611 #define BYTE_EN_DWORD 0xff
612 #define BYTE_EN_WORD 0x33
613 #define BYTE_EN_BYTE 0x11
614 #define BYTE_EN_SIX_BYTES 0x3f
615 #define BYTE_EN_START_MASK 0x0f
616 #define BYTE_EN_END_MASK 0xf0
617
618 #define RTL8153_MAX_PACKET 9216
619 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
620 ETH_FCS_LEN)
621 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
622 #define RTL8153_RMS RTL8153_MAX_PACKET
623 #define RTL8152_TX_TIMEOUT (5 * HZ)
624 #define RTL8152_NAPI_WEIGHT 64
625 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
626 sizeof(struct rx_desc) + RX_ALIGN)
627
628
629 enum rtl8152_flags {
630 RTL8152_UNPLUG = 0,
631 RTL8152_SET_RX_MODE,
632 WORK_ENABLE,
633 RTL8152_LINK_CHG,
634 SELECTIVE_SUSPEND,
635 PHY_RESET,
636 SCHEDULE_TASKLET,
637 GREEN_ETHERNET,
638 DELL_TB_RX_AGG_BUG,
639 };
640
641
642 #define VENDOR_ID_REALTEK 0x0bda
643 #define VENDOR_ID_MICROSOFT 0x045e
644 #define VENDOR_ID_SAMSUNG 0x04e8
645 #define VENDOR_ID_LENOVO 0x17ef
646 #define VENDOR_ID_LINKSYS 0x13b1
647 #define VENDOR_ID_NVIDIA 0x0955
648 #define VENDOR_ID_TPLINK 0x2357
649
650 #define MCU_TYPE_PLA 0x0100
651 #define MCU_TYPE_USB 0x0000
652
653 struct tally_counter {
654 __le64 tx_packets;
655 __le64 rx_packets;
656 __le64 tx_errors;
657 __le32 rx_errors;
658 __le16 rx_missed;
659 __le16 align_errors;
660 __le32 tx_one_collision;
661 __le32 tx_multi_collision;
662 __le64 rx_unicast;
663 __le64 rx_broadcast;
664 __le32 rx_multicast;
665 __le16 tx_aborted;
666 __le16 tx_underrun;
667 };
668
669 struct rx_desc {
670 __le32 opts1;
671 #define RX_LEN_MASK 0x7fff
672
673 __le32 opts2;
674 #define RD_UDP_CS BIT(23)
675 #define RD_TCP_CS BIT(22)
676 #define RD_IPV6_CS BIT(20)
677 #define RD_IPV4_CS BIT(19)
678
679 __le32 opts3;
680 #define IPF BIT(23)
681 #define UDPF BIT(22)
682 #define TCPF BIT(21)
683 #define RX_VLAN_TAG BIT(16)
684
685 __le32 opts4;
686 __le32 opts5;
687 __le32 opts6;
688 };
689
690 struct tx_desc {
691 __le32 opts1;
692 #define TX_FS BIT(31)
693 #define TX_LS BIT(30)
694 #define GTSENDV4 BIT(28)
695 #define GTSENDV6 BIT(27)
696 #define GTTCPHO_SHIFT 18
697 #define GTTCPHO_MAX 0x7fU
698 #define TX_LEN_MAX 0x3ffffU
699
700 __le32 opts2;
701 #define UDP_CS BIT(31)
702 #define TCP_CS BIT(30)
703 #define IPV4_CS BIT(29)
704 #define IPV6_CS BIT(28)
705 #define MSS_SHIFT 17
706 #define MSS_MAX 0x7ffU
707 #define TCPHO_SHIFT 17
708 #define TCPHO_MAX 0x7ffU
709 #define TX_VLAN_TAG BIT(16)
710 };
711
712 struct r8152;
713
714 struct rx_agg {
715 struct list_head list, info_list;
716 struct urb *urb;
717 struct r8152 *context;
718 struct page *page;
719 void *buffer;
720 };
721
722 struct tx_agg {
723 struct list_head list;
724 struct urb *urb;
725 struct r8152 *context;
726 void *buffer;
727 void *head;
728 u32 skb_num;
729 u32 skb_len;
730 };
731
732 struct r8152 {
733 unsigned long flags;
734 struct usb_device *udev;
735 struct napi_struct napi;
736 struct usb_interface *intf;
737 struct net_device *netdev;
738 struct urb *intr_urb;
739 struct tx_agg tx_info[RTL8152_MAX_TX];
740 struct list_head rx_info, rx_used;
741 struct list_head rx_done, tx_free;
742 struct sk_buff_head tx_queue, rx_queue;
743 spinlock_t rx_lock, tx_lock;
744 struct delayed_work schedule, hw_phy_work;
745 struct mii_if_info mii;
746 struct mutex control;
747 #ifdef CONFIG_PM_SLEEP
748 struct notifier_block pm_notifier;
749 #endif
750 struct tasklet_struct tx_tl;
751
752 struct rtl_ops {
753 void (*init)(struct r8152 *);
754 int (*enable)(struct r8152 *);
755 void (*disable)(struct r8152 *);
756 void (*up)(struct r8152 *);
757 void (*down)(struct r8152 *);
758 void (*unload)(struct r8152 *);
759 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
760 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
761 bool (*in_nway)(struct r8152 *);
762 void (*hw_phy_cfg)(struct r8152 *);
763 void (*autosuspend_en)(struct r8152 *tp, bool enable);
764 } rtl_ops;
765
766 struct ups_info {
767 u32 _10m_ckdiv:1;
768 u32 _250m_ckdiv:1;
769 u32 aldps:1;
770 u32 lite_mode:2;
771 u32 speed_duplex:4;
772 u32 eee:1;
773 u32 eee_lite:1;
774 u32 eee_ckdiv:1;
775 u32 eee_plloff_100:1;
776 u32 eee_plloff_giga:1;
777 u32 eee_cmod_lv:1;
778 u32 green:1;
779 u32 flow_control:1;
780 u32 ctap_short_off:1;
781 } ups_info;
782
783 atomic_t rx_count;
784
785 bool eee_en;
786 int intr_interval;
787 u32 saved_wolopts;
788 u32 msg_enable;
789 u32 tx_qlen;
790 u32 coalesce;
791 u32 advertising;
792 u32 rx_buf_sz;
793 u32 rx_copybreak;
794 u32 rx_pending;
795
796 u16 ocp_base;
797 u16 speed;
798 u16 eee_adv;
799 u8 *intr_buff;
800 u8 version;
801 u8 duplex;
802 u8 autoneg;
803 };
804
805 enum rtl_version {
806 RTL_VER_UNKNOWN = 0,
807 RTL_VER_01,
808 RTL_VER_02,
809 RTL_VER_03,
810 RTL_VER_04,
811 RTL_VER_05,
812 RTL_VER_06,
813 RTL_VER_07,
814 RTL_VER_08,
815 RTL_VER_09,
816 RTL_VER_MAX
817 };
818
819 enum tx_csum_stat {
820 TX_CSUM_SUCCESS = 0,
821 TX_CSUM_TSO,
822 TX_CSUM_NONE
823 };
824
825 #define RTL_ADVERTISED_10_HALF BIT(0)
826 #define RTL_ADVERTISED_10_FULL BIT(1)
827 #define RTL_ADVERTISED_100_HALF BIT(2)
828 #define RTL_ADVERTISED_100_FULL BIT(3)
829 #define RTL_ADVERTISED_1000_HALF BIT(4)
830 #define RTL_ADVERTISED_1000_FULL BIT(5)
831
832
833
834
835 static const int multicast_filter_limit = 32;
836 static unsigned int agg_buf_sz = 16384;
837
838 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
839 VLAN_ETH_HLEN - ETH_FCS_LEN)
840
841 static
842 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
843 {
844 int ret;
845 void *tmp;
846
847 tmp = kmalloc(size, GFP_KERNEL);
848 if (!tmp)
849 return -ENOMEM;
850
851 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
852 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
853 value, index, tmp, size, 500);
854 if (ret < 0)
855 memset(data, 0xff, size);
856 else
857 memcpy(data, tmp, size);
858
859 kfree(tmp);
860
861 return ret;
862 }
863
864 static
865 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
866 {
867 int ret;
868 void *tmp;
869
870 tmp = kmemdup(data, size, GFP_KERNEL);
871 if (!tmp)
872 return -ENOMEM;
873
874 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
875 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
876 value, index, tmp, size, 500);
877
878 kfree(tmp);
879
880 return ret;
881 }
882
883 static void rtl_set_unplug(struct r8152 *tp)
884 {
885 if (tp->udev->state == USB_STATE_NOTATTACHED) {
886 set_bit(RTL8152_UNPLUG, &tp->flags);
887 smp_mb__after_atomic();
888 }
889 }
890
891 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
892 void *data, u16 type)
893 {
894 u16 limit = 64;
895 int ret = 0;
896
897 if (test_bit(RTL8152_UNPLUG, &tp->flags))
898 return -ENODEV;
899
900
901 if ((size & 3) || !size || (index & 3) || !data)
902 return -EPERM;
903
904 if ((u32)index + (u32)size > 0xffff)
905 return -EPERM;
906
907 while (size) {
908 if (size > limit) {
909 ret = get_registers(tp, index, type, limit, data);
910 if (ret < 0)
911 break;
912
913 index += limit;
914 data += limit;
915 size -= limit;
916 } else {
917 ret = get_registers(tp, index, type, size, data);
918 if (ret < 0)
919 break;
920
921 index += size;
922 data += size;
923 size = 0;
924 break;
925 }
926 }
927
928 if (ret == -ENODEV)
929 rtl_set_unplug(tp);
930
931 return ret;
932 }
933
934 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
935 u16 size, void *data, u16 type)
936 {
937 int ret;
938 u16 byteen_start, byteen_end, byen;
939 u16 limit = 512;
940
941 if (test_bit(RTL8152_UNPLUG, &tp->flags))
942 return -ENODEV;
943
944
945 if ((size & 3) || !size || (index & 3) || !data)
946 return -EPERM;
947
948 if ((u32)index + (u32)size > 0xffff)
949 return -EPERM;
950
951 byteen_start = byteen & BYTE_EN_START_MASK;
952 byteen_end = byteen & BYTE_EN_END_MASK;
953
954 byen = byteen_start | (byteen_start << 4);
955 ret = set_registers(tp, index, type | byen, 4, data);
956 if (ret < 0)
957 goto error1;
958
959 index += 4;
960 data += 4;
961 size -= 4;
962
963 if (size) {
964 size -= 4;
965
966 while (size) {
967 if (size > limit) {
968 ret = set_registers(tp, index,
969 type | BYTE_EN_DWORD,
970 limit, data);
971 if (ret < 0)
972 goto error1;
973
974 index += limit;
975 data += limit;
976 size -= limit;
977 } else {
978 ret = set_registers(tp, index,
979 type | BYTE_EN_DWORD,
980 size, data);
981 if (ret < 0)
982 goto error1;
983
984 index += size;
985 data += size;
986 size = 0;
987 break;
988 }
989 }
990
991 byen = byteen_end | (byteen_end >> 4);
992 ret = set_registers(tp, index, type | byen, 4, data);
993 if (ret < 0)
994 goto error1;
995 }
996
997 error1:
998 if (ret == -ENODEV)
999 rtl_set_unplug(tp);
1000
1001 return ret;
1002 }
1003
1004 static inline
1005 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1006 {
1007 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1008 }
1009
1010 static inline
1011 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1012 {
1013 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1014 }
1015
1016 static inline
1017 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1018 {
1019 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1020 }
1021
1022 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1023 {
1024 __le32 data;
1025
1026 generic_ocp_read(tp, index, sizeof(data), &data, type);
1027
1028 return __le32_to_cpu(data);
1029 }
1030
1031 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1032 {
1033 __le32 tmp = __cpu_to_le32(data);
1034
1035 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1036 }
1037
1038 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1039 {
1040 u32 data;
1041 __le32 tmp;
1042 u16 byen = BYTE_EN_WORD;
1043 u8 shift = index & 2;
1044
1045 index &= ~3;
1046 byen <<= shift;
1047
1048 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1049
1050 data = __le32_to_cpu(tmp);
1051 data >>= (shift * 8);
1052 data &= 0xffff;
1053
1054 return (u16)data;
1055 }
1056
1057 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1058 {
1059 u32 mask = 0xffff;
1060 __le32 tmp;
1061 u16 byen = BYTE_EN_WORD;
1062 u8 shift = index & 2;
1063
1064 data &= mask;
1065
1066 if (index & 2) {
1067 byen <<= shift;
1068 mask <<= (shift * 8);
1069 data <<= (shift * 8);
1070 index &= ~3;
1071 }
1072
1073 tmp = __cpu_to_le32(data);
1074
1075 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1076 }
1077
1078 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1079 {
1080 u32 data;
1081 __le32 tmp;
1082 u8 shift = index & 3;
1083
1084 index &= ~3;
1085
1086 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1087
1088 data = __le32_to_cpu(tmp);
1089 data >>= (shift * 8);
1090 data &= 0xff;
1091
1092 return (u8)data;
1093 }
1094
1095 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1096 {
1097 u32 mask = 0xff;
1098 __le32 tmp;
1099 u16 byen = BYTE_EN_BYTE;
1100 u8 shift = index & 3;
1101
1102 data &= mask;
1103
1104 if (index & 3) {
1105 byen <<= shift;
1106 mask <<= (shift * 8);
1107 data <<= (shift * 8);
1108 index &= ~3;
1109 }
1110
1111 tmp = __cpu_to_le32(data);
1112
1113 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1114 }
1115
1116 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1117 {
1118 u16 ocp_base, ocp_index;
1119
1120 ocp_base = addr & 0xf000;
1121 if (ocp_base != tp->ocp_base) {
1122 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1123 tp->ocp_base = ocp_base;
1124 }
1125
1126 ocp_index = (addr & 0x0fff) | 0xb000;
1127 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1128 }
1129
1130 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1131 {
1132 u16 ocp_base, ocp_index;
1133
1134 ocp_base = addr & 0xf000;
1135 if (ocp_base != tp->ocp_base) {
1136 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1137 tp->ocp_base = ocp_base;
1138 }
1139
1140 ocp_index = (addr & 0x0fff) | 0xb000;
1141 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1142 }
1143
1144 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1145 {
1146 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1147 }
1148
1149 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1150 {
1151 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1152 }
1153
1154 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1155 {
1156 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1157 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1158 }
1159
1160 static u16 sram_read(struct r8152 *tp, u16 addr)
1161 {
1162 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1163 return ocp_reg_read(tp, OCP_SRAM_DATA);
1164 }
1165
1166 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1167 {
1168 struct r8152 *tp = netdev_priv(netdev);
1169 int ret;
1170
1171 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1172 return -ENODEV;
1173
1174 if (phy_id != R8152_PHY_ID)
1175 return -EINVAL;
1176
1177 ret = r8152_mdio_read(tp, reg);
1178
1179 return ret;
1180 }
1181
1182 static
1183 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1184 {
1185 struct r8152 *tp = netdev_priv(netdev);
1186
1187 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1188 return;
1189
1190 if (phy_id != R8152_PHY_ID)
1191 return;
1192
1193 r8152_mdio_write(tp, reg, val);
1194 }
1195
1196 static int
1197 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1198
1199 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1200 {
1201 struct r8152 *tp = netdev_priv(netdev);
1202 struct sockaddr *addr = p;
1203 int ret = -EADDRNOTAVAIL;
1204
1205 if (!is_valid_ether_addr(addr->sa_data))
1206 goto out1;
1207
1208 ret = usb_autopm_get_interface(tp->intf);
1209 if (ret < 0)
1210 goto out1;
1211
1212 mutex_lock(&tp->control);
1213
1214 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1215
1216 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1217 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1218 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1219
1220 mutex_unlock(&tp->control);
1221
1222 usb_autopm_put_interface(tp->intf);
1223 out1:
1224 return ret;
1225 }
1226
1227
1228
1229
1230
1231 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1232 {
1233 acpi_status status;
1234 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1235 union acpi_object *obj;
1236 int ret = -EINVAL;
1237 u32 ocp_data;
1238 unsigned char buf[6];
1239
1240
1241 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1242 if ((ocp_data & AD_MASK) == 0x1000) {
1243
1244 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1245 if ((ocp_data & PASS_THRU_MASK) != 1) {
1246 netif_dbg(tp, probe, tp->netdev,
1247 "No efuse for RTL8153-AD MAC pass through\n");
1248 return -ENODEV;
1249 }
1250 } else {
1251
1252 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1253 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1254 netif_dbg(tp, probe, tp->netdev,
1255 "Invalid variant for MAC pass through\n");
1256 return -ENODEV;
1257 }
1258 }
1259
1260
1261 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1262 obj = (union acpi_object *)buffer.pointer;
1263 if (!ACPI_SUCCESS(status))
1264 return -ENODEV;
1265 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1266 netif_warn(tp, probe, tp->netdev,
1267 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1268 obj->type, obj->string.length);
1269 goto amacout;
1270 }
1271 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1272 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1273 netif_warn(tp, probe, tp->netdev,
1274 "Invalid header when reading pass-thru MAC addr\n");
1275 goto amacout;
1276 }
1277 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1278 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1279 netif_warn(tp, probe, tp->netdev,
1280 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1281 ret, buf);
1282 ret = -EINVAL;
1283 goto amacout;
1284 }
1285 memcpy(sa->sa_data, buf, 6);
1286 netif_info(tp, probe, tp->netdev,
1287 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1288
1289 amacout:
1290 kfree(obj);
1291 return ret;
1292 }
1293
1294 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1295 {
1296 struct net_device *dev = tp->netdev;
1297 int ret;
1298
1299 sa->sa_family = dev->type;
1300
1301 if (tp->version == RTL_VER_01) {
1302 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1303 } else {
1304
1305
1306
1307 ret = vendor_mac_passthru_addr_read(tp, sa);
1308 if (ret < 0)
1309 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data);
1310 }
1311
1312 if (ret < 0) {
1313 netif_err(tp, probe, dev, "Get ether addr fail\n");
1314 } else if (!is_valid_ether_addr(sa->sa_data)) {
1315 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1316 sa->sa_data);
1317 eth_hw_addr_random(dev);
1318 ether_addr_copy(sa->sa_data, dev->dev_addr);
1319 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1320 sa->sa_data);
1321 return 0;
1322 }
1323
1324 return ret;
1325 }
1326
1327 static int set_ethernet_addr(struct r8152 *tp)
1328 {
1329 struct net_device *dev = tp->netdev;
1330 struct sockaddr sa;
1331 int ret;
1332
1333 ret = determine_ethernet_addr(tp, &sa);
1334 if (ret < 0)
1335 return ret;
1336
1337 if (tp->version == RTL_VER_01)
1338 ether_addr_copy(dev->dev_addr, sa.sa_data);
1339 else
1340 ret = rtl8152_set_mac_address(dev, &sa);
1341
1342 return ret;
1343 }
1344
1345 static void read_bulk_callback(struct urb *urb)
1346 {
1347 struct net_device *netdev;
1348 int status = urb->status;
1349 struct rx_agg *agg;
1350 struct r8152 *tp;
1351 unsigned long flags;
1352
1353 agg = urb->context;
1354 if (!agg)
1355 return;
1356
1357 tp = agg->context;
1358 if (!tp)
1359 return;
1360
1361 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1362 return;
1363
1364 if (!test_bit(WORK_ENABLE, &tp->flags))
1365 return;
1366
1367 netdev = tp->netdev;
1368
1369
1370
1371 if (!netif_carrier_ok(netdev))
1372 return;
1373
1374 usb_mark_last_busy(tp->udev);
1375
1376 switch (status) {
1377 case 0:
1378 if (urb->actual_length < ETH_ZLEN)
1379 break;
1380
1381 spin_lock_irqsave(&tp->rx_lock, flags);
1382 list_add_tail(&agg->list, &tp->rx_done);
1383 spin_unlock_irqrestore(&tp->rx_lock, flags);
1384 napi_schedule(&tp->napi);
1385 return;
1386 case -ESHUTDOWN:
1387 rtl_set_unplug(tp);
1388 netif_device_detach(tp->netdev);
1389 return;
1390 case -ENOENT:
1391 return;
1392 case -ETIME:
1393 if (net_ratelimit())
1394 netdev_warn(netdev, "maybe reset is needed?\n");
1395 break;
1396 default:
1397 if (net_ratelimit())
1398 netdev_warn(netdev, "Rx status %d\n", status);
1399 break;
1400 }
1401
1402 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1403 }
1404
1405 static void write_bulk_callback(struct urb *urb)
1406 {
1407 struct net_device_stats *stats;
1408 struct net_device *netdev;
1409 struct tx_agg *agg;
1410 struct r8152 *tp;
1411 unsigned long flags;
1412 int status = urb->status;
1413
1414 agg = urb->context;
1415 if (!agg)
1416 return;
1417
1418 tp = agg->context;
1419 if (!tp)
1420 return;
1421
1422 netdev = tp->netdev;
1423 stats = &netdev->stats;
1424 if (status) {
1425 if (net_ratelimit())
1426 netdev_warn(netdev, "Tx status %d\n", status);
1427 stats->tx_errors += agg->skb_num;
1428 } else {
1429 stats->tx_packets += agg->skb_num;
1430 stats->tx_bytes += agg->skb_len;
1431 }
1432
1433 spin_lock_irqsave(&tp->tx_lock, flags);
1434 list_add_tail(&agg->list, &tp->tx_free);
1435 spin_unlock_irqrestore(&tp->tx_lock, flags);
1436
1437 usb_autopm_put_interface_async(tp->intf);
1438
1439 if (!netif_carrier_ok(netdev))
1440 return;
1441
1442 if (!test_bit(WORK_ENABLE, &tp->flags))
1443 return;
1444
1445 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1446 return;
1447
1448 if (!skb_queue_empty(&tp->tx_queue))
1449 tasklet_schedule(&tp->tx_tl);
1450 }
1451
1452 static void intr_callback(struct urb *urb)
1453 {
1454 struct r8152 *tp;
1455 __le16 *d;
1456 int status = urb->status;
1457 int res;
1458
1459 tp = urb->context;
1460 if (!tp)
1461 return;
1462
1463 if (!test_bit(WORK_ENABLE, &tp->flags))
1464 return;
1465
1466 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1467 return;
1468
1469 switch (status) {
1470 case 0:
1471 break;
1472 case -ECONNRESET:
1473 case -ESHUTDOWN:
1474 netif_device_detach(tp->netdev);
1475
1476 case -ENOENT:
1477 case -EPROTO:
1478 netif_info(tp, intr, tp->netdev,
1479 "Stop submitting intr, status %d\n", status);
1480 return;
1481 case -EOVERFLOW:
1482 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1483 goto resubmit;
1484
1485 default:
1486 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1487 goto resubmit;
1488 }
1489
1490 d = urb->transfer_buffer;
1491 if (INTR_LINK & __le16_to_cpu(d[0])) {
1492 if (!netif_carrier_ok(tp->netdev)) {
1493 set_bit(RTL8152_LINK_CHG, &tp->flags);
1494 schedule_delayed_work(&tp->schedule, 0);
1495 }
1496 } else {
1497 if (netif_carrier_ok(tp->netdev)) {
1498 netif_stop_queue(tp->netdev);
1499 set_bit(RTL8152_LINK_CHG, &tp->flags);
1500 schedule_delayed_work(&tp->schedule, 0);
1501 }
1502 }
1503
1504 resubmit:
1505 res = usb_submit_urb(urb, GFP_ATOMIC);
1506 if (res == -ENODEV) {
1507 rtl_set_unplug(tp);
1508 netif_device_detach(tp->netdev);
1509 } else if (res) {
1510 netif_err(tp, intr, tp->netdev,
1511 "can't resubmit intr, status %d\n", res);
1512 }
1513 }
1514
1515 static inline void *rx_agg_align(void *data)
1516 {
1517 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1518 }
1519
1520 static inline void *tx_agg_align(void *data)
1521 {
1522 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1523 }
1524
1525 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1526 {
1527 list_del(&agg->info_list);
1528
1529 usb_free_urb(agg->urb);
1530 put_page(agg->page);
1531 kfree(agg);
1532
1533 atomic_dec(&tp->rx_count);
1534 }
1535
1536 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1537 {
1538 struct net_device *netdev = tp->netdev;
1539 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1540 unsigned int order = get_order(tp->rx_buf_sz);
1541 struct rx_agg *rx_agg;
1542 unsigned long flags;
1543
1544 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1545 if (!rx_agg)
1546 return NULL;
1547
1548 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1549 if (!rx_agg->page)
1550 goto free_rx;
1551
1552 rx_agg->buffer = page_address(rx_agg->page);
1553
1554 rx_agg->urb = usb_alloc_urb(0, mflags);
1555 if (!rx_agg->urb)
1556 goto free_buf;
1557
1558 rx_agg->context = tp;
1559
1560 INIT_LIST_HEAD(&rx_agg->list);
1561 INIT_LIST_HEAD(&rx_agg->info_list);
1562 spin_lock_irqsave(&tp->rx_lock, flags);
1563 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1564 spin_unlock_irqrestore(&tp->rx_lock, flags);
1565
1566 atomic_inc(&tp->rx_count);
1567
1568 return rx_agg;
1569
1570 free_buf:
1571 __free_pages(rx_agg->page, order);
1572 free_rx:
1573 kfree(rx_agg);
1574 return NULL;
1575 }
1576
1577 static void free_all_mem(struct r8152 *tp)
1578 {
1579 struct rx_agg *agg, *agg_next;
1580 unsigned long flags;
1581 int i;
1582
1583 spin_lock_irqsave(&tp->rx_lock, flags);
1584
1585 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1586 free_rx_agg(tp, agg);
1587
1588 spin_unlock_irqrestore(&tp->rx_lock, flags);
1589
1590 WARN_ON(atomic_read(&tp->rx_count));
1591
1592 for (i = 0; i < RTL8152_MAX_TX; i++) {
1593 usb_free_urb(tp->tx_info[i].urb);
1594 tp->tx_info[i].urb = NULL;
1595
1596 kfree(tp->tx_info[i].buffer);
1597 tp->tx_info[i].buffer = NULL;
1598 tp->tx_info[i].head = NULL;
1599 }
1600
1601 usb_free_urb(tp->intr_urb);
1602 tp->intr_urb = NULL;
1603
1604 kfree(tp->intr_buff);
1605 tp->intr_buff = NULL;
1606 }
1607
1608 static int alloc_all_mem(struct r8152 *tp)
1609 {
1610 struct net_device *netdev = tp->netdev;
1611 struct usb_interface *intf = tp->intf;
1612 struct usb_host_interface *alt = intf->cur_altsetting;
1613 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1614 int node, i;
1615
1616 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1617
1618 spin_lock_init(&tp->rx_lock);
1619 spin_lock_init(&tp->tx_lock);
1620 INIT_LIST_HEAD(&tp->rx_info);
1621 INIT_LIST_HEAD(&tp->tx_free);
1622 INIT_LIST_HEAD(&tp->rx_done);
1623 skb_queue_head_init(&tp->tx_queue);
1624 skb_queue_head_init(&tp->rx_queue);
1625 atomic_set(&tp->rx_count, 0);
1626
1627 for (i = 0; i < RTL8152_MAX_RX; i++) {
1628 if (!alloc_rx_agg(tp, GFP_KERNEL))
1629 goto err1;
1630 }
1631
1632 for (i = 0; i < RTL8152_MAX_TX; i++) {
1633 struct urb *urb;
1634 u8 *buf;
1635
1636 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1637 if (!buf)
1638 goto err1;
1639
1640 if (buf != tx_agg_align(buf)) {
1641 kfree(buf);
1642 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1643 node);
1644 if (!buf)
1645 goto err1;
1646 }
1647
1648 urb = usb_alloc_urb(0, GFP_KERNEL);
1649 if (!urb) {
1650 kfree(buf);
1651 goto err1;
1652 }
1653
1654 INIT_LIST_HEAD(&tp->tx_info[i].list);
1655 tp->tx_info[i].context = tp;
1656 tp->tx_info[i].urb = urb;
1657 tp->tx_info[i].buffer = buf;
1658 tp->tx_info[i].head = tx_agg_align(buf);
1659
1660 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1661 }
1662
1663 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1664 if (!tp->intr_urb)
1665 goto err1;
1666
1667 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1668 if (!tp->intr_buff)
1669 goto err1;
1670
1671 tp->intr_interval = (int)ep_intr->desc.bInterval;
1672 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1673 tp->intr_buff, INTBUFSIZE, intr_callback,
1674 tp, tp->intr_interval);
1675
1676 return 0;
1677
1678 err1:
1679 free_all_mem(tp);
1680 return -ENOMEM;
1681 }
1682
1683 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1684 {
1685 struct tx_agg *agg = NULL;
1686 unsigned long flags;
1687
1688 if (list_empty(&tp->tx_free))
1689 return NULL;
1690
1691 spin_lock_irqsave(&tp->tx_lock, flags);
1692 if (!list_empty(&tp->tx_free)) {
1693 struct list_head *cursor;
1694
1695 cursor = tp->tx_free.next;
1696 list_del_init(cursor);
1697 agg = list_entry(cursor, struct tx_agg, list);
1698 }
1699 spin_unlock_irqrestore(&tp->tx_lock, flags);
1700
1701 return agg;
1702 }
1703
1704
1705
1706
1707
1708 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1709 struct sk_buff_head *list)
1710 {
1711 if (skb_shinfo(skb)->gso_size) {
1712 netdev_features_t features = tp->netdev->features;
1713 struct sk_buff_head seg_list;
1714 struct sk_buff *segs, *nskb;
1715
1716 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1717 segs = skb_gso_segment(skb, features);
1718 if (IS_ERR(segs) || !segs)
1719 goto drop;
1720
1721 __skb_queue_head_init(&seg_list);
1722
1723 do {
1724 nskb = segs;
1725 segs = segs->next;
1726 nskb->next = NULL;
1727 __skb_queue_tail(&seg_list, nskb);
1728 } while (segs);
1729
1730 skb_queue_splice(&seg_list, list);
1731 dev_kfree_skb(skb);
1732 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1733 if (skb_checksum_help(skb) < 0)
1734 goto drop;
1735
1736 __skb_queue_head(list, skb);
1737 } else {
1738 struct net_device_stats *stats;
1739
1740 drop:
1741 stats = &tp->netdev->stats;
1742 stats->tx_dropped++;
1743 dev_kfree_skb(skb);
1744 }
1745 }
1746
1747
1748
1749
1750
1751 static int msdn_giant_send_check(struct sk_buff *skb)
1752 {
1753 const struct ipv6hdr *ipv6h;
1754 struct tcphdr *th;
1755 int ret;
1756
1757 ret = skb_cow_head(skb, 0);
1758 if (ret)
1759 return ret;
1760
1761 ipv6h = ipv6_hdr(skb);
1762 th = tcp_hdr(skb);
1763
1764 th->check = 0;
1765 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1766
1767 return ret;
1768 }
1769
1770 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1771 {
1772 if (skb_vlan_tag_present(skb)) {
1773 u32 opts2;
1774
1775 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1776 desc->opts2 |= cpu_to_le32(opts2);
1777 }
1778 }
1779
1780 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1781 {
1782 u32 opts2 = le32_to_cpu(desc->opts2);
1783
1784 if (opts2 & RX_VLAN_TAG)
1785 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1786 swab16(opts2 & 0xffff));
1787 }
1788
1789 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1790 struct sk_buff *skb, u32 len, u32 transport_offset)
1791 {
1792 u32 mss = skb_shinfo(skb)->gso_size;
1793 u32 opts1, opts2 = 0;
1794 int ret = TX_CSUM_SUCCESS;
1795
1796 WARN_ON_ONCE(len > TX_LEN_MAX);
1797
1798 opts1 = len | TX_FS | TX_LS;
1799
1800 if (mss) {
1801 if (transport_offset > GTTCPHO_MAX) {
1802 netif_warn(tp, tx_err, tp->netdev,
1803 "Invalid transport offset 0x%x for TSO\n",
1804 transport_offset);
1805 ret = TX_CSUM_TSO;
1806 goto unavailable;
1807 }
1808
1809 switch (vlan_get_protocol(skb)) {
1810 case htons(ETH_P_IP):
1811 opts1 |= GTSENDV4;
1812 break;
1813
1814 case htons(ETH_P_IPV6):
1815 if (msdn_giant_send_check(skb)) {
1816 ret = TX_CSUM_TSO;
1817 goto unavailable;
1818 }
1819 opts1 |= GTSENDV6;
1820 break;
1821
1822 default:
1823 WARN_ON_ONCE(1);
1824 break;
1825 }
1826
1827 opts1 |= transport_offset << GTTCPHO_SHIFT;
1828 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1829 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1830 u8 ip_protocol;
1831
1832 if (transport_offset > TCPHO_MAX) {
1833 netif_warn(tp, tx_err, tp->netdev,
1834 "Invalid transport offset 0x%x\n",
1835 transport_offset);
1836 ret = TX_CSUM_NONE;
1837 goto unavailable;
1838 }
1839
1840 switch (vlan_get_protocol(skb)) {
1841 case htons(ETH_P_IP):
1842 opts2 |= IPV4_CS;
1843 ip_protocol = ip_hdr(skb)->protocol;
1844 break;
1845
1846 case htons(ETH_P_IPV6):
1847 opts2 |= IPV6_CS;
1848 ip_protocol = ipv6_hdr(skb)->nexthdr;
1849 break;
1850
1851 default:
1852 ip_protocol = IPPROTO_RAW;
1853 break;
1854 }
1855
1856 if (ip_protocol == IPPROTO_TCP)
1857 opts2 |= TCP_CS;
1858 else if (ip_protocol == IPPROTO_UDP)
1859 opts2 |= UDP_CS;
1860 else
1861 WARN_ON_ONCE(1);
1862
1863 opts2 |= transport_offset << TCPHO_SHIFT;
1864 }
1865
1866 desc->opts2 = cpu_to_le32(opts2);
1867 desc->opts1 = cpu_to_le32(opts1);
1868
1869 unavailable:
1870 return ret;
1871 }
1872
1873 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1874 {
1875 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1876 int remain, ret;
1877 u8 *tx_data;
1878
1879 __skb_queue_head_init(&skb_head);
1880 spin_lock(&tx_queue->lock);
1881 skb_queue_splice_init(tx_queue, &skb_head);
1882 spin_unlock(&tx_queue->lock);
1883
1884 tx_data = agg->head;
1885 agg->skb_num = 0;
1886 agg->skb_len = 0;
1887 remain = agg_buf_sz;
1888
1889 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1890 struct tx_desc *tx_desc;
1891 struct sk_buff *skb;
1892 unsigned int len;
1893 u32 offset;
1894
1895 skb = __skb_dequeue(&skb_head);
1896 if (!skb)
1897 break;
1898
1899 len = skb->len + sizeof(*tx_desc);
1900
1901 if (len > remain) {
1902 __skb_queue_head(&skb_head, skb);
1903 break;
1904 }
1905
1906 tx_data = tx_agg_align(tx_data);
1907 tx_desc = (struct tx_desc *)tx_data;
1908
1909 offset = (u32)skb_transport_offset(skb);
1910
1911 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1912 r8152_csum_workaround(tp, skb, &skb_head);
1913 continue;
1914 }
1915
1916 rtl_tx_vlan_tag(tx_desc, skb);
1917
1918 tx_data += sizeof(*tx_desc);
1919
1920 len = skb->len;
1921 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1922 struct net_device_stats *stats = &tp->netdev->stats;
1923
1924 stats->tx_dropped++;
1925 dev_kfree_skb_any(skb);
1926 tx_data -= sizeof(*tx_desc);
1927 continue;
1928 }
1929
1930 tx_data += len;
1931 agg->skb_len += len;
1932 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1933
1934 dev_kfree_skb_any(skb);
1935
1936 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1937
1938 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
1939 break;
1940 }
1941
1942 if (!skb_queue_empty(&skb_head)) {
1943 spin_lock(&tx_queue->lock);
1944 skb_queue_splice(&skb_head, tx_queue);
1945 spin_unlock(&tx_queue->lock);
1946 }
1947
1948 netif_tx_lock(tp->netdev);
1949
1950 if (netif_queue_stopped(tp->netdev) &&
1951 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1952 netif_wake_queue(tp->netdev);
1953
1954 netif_tx_unlock(tp->netdev);
1955
1956 ret = usb_autopm_get_interface_async(tp->intf);
1957 if (ret < 0)
1958 goto out_tx_fill;
1959
1960 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1961 agg->head, (int)(tx_data - (u8 *)agg->head),
1962 (usb_complete_t)write_bulk_callback, agg);
1963
1964 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1965 if (ret < 0)
1966 usb_autopm_put_interface_async(tp->intf);
1967
1968 out_tx_fill:
1969 return ret;
1970 }
1971
1972 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1973 {
1974 u8 checksum = CHECKSUM_NONE;
1975 u32 opts2, opts3;
1976
1977 if (!(tp->netdev->features & NETIF_F_RXCSUM))
1978 goto return_result;
1979
1980 opts2 = le32_to_cpu(rx_desc->opts2);
1981 opts3 = le32_to_cpu(rx_desc->opts3);
1982
1983 if (opts2 & RD_IPV4_CS) {
1984 if (opts3 & IPF)
1985 checksum = CHECKSUM_NONE;
1986 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1987 checksum = CHECKSUM_UNNECESSARY;
1988 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1989 checksum = CHECKSUM_UNNECESSARY;
1990 } else if (opts2 & RD_IPV6_CS) {
1991 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1992 checksum = CHECKSUM_UNNECESSARY;
1993 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1994 checksum = CHECKSUM_UNNECESSARY;
1995 }
1996
1997 return_result:
1998 return checksum;
1999 }
2000
2001 static inline bool rx_count_exceed(struct r8152 *tp)
2002 {
2003 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2004 }
2005
2006 static inline int agg_offset(struct rx_agg *agg, void *addr)
2007 {
2008 return (int)(addr - agg->buffer);
2009 }
2010
2011 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2012 {
2013 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2014 unsigned long flags;
2015
2016 spin_lock_irqsave(&tp->rx_lock, flags);
2017
2018 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2019 if (page_count(agg->page) == 1) {
2020 if (!agg_free) {
2021 list_del_init(&agg->list);
2022 agg_free = agg;
2023 continue;
2024 }
2025 if (rx_count_exceed(tp)) {
2026 list_del_init(&agg->list);
2027 free_rx_agg(tp, agg);
2028 }
2029 break;
2030 }
2031 }
2032
2033 spin_unlock_irqrestore(&tp->rx_lock, flags);
2034
2035 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2036 agg_free = alloc_rx_agg(tp, mflags);
2037
2038 return agg_free;
2039 }
2040
2041 static int rx_bottom(struct r8152 *tp, int budget)
2042 {
2043 unsigned long flags;
2044 struct list_head *cursor, *next, rx_queue;
2045 int ret = 0, work_done = 0;
2046 struct napi_struct *napi = &tp->napi;
2047
2048 if (!skb_queue_empty(&tp->rx_queue)) {
2049 while (work_done < budget) {
2050 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2051 struct net_device *netdev = tp->netdev;
2052 struct net_device_stats *stats = &netdev->stats;
2053 unsigned int pkt_len;
2054
2055 if (!skb)
2056 break;
2057
2058 pkt_len = skb->len;
2059 napi_gro_receive(napi, skb);
2060 work_done++;
2061 stats->rx_packets++;
2062 stats->rx_bytes += pkt_len;
2063 }
2064 }
2065
2066 if (list_empty(&tp->rx_done))
2067 goto out1;
2068
2069 INIT_LIST_HEAD(&rx_queue);
2070 spin_lock_irqsave(&tp->rx_lock, flags);
2071 list_splice_init(&tp->rx_done, &rx_queue);
2072 spin_unlock_irqrestore(&tp->rx_lock, flags);
2073
2074 list_for_each_safe(cursor, next, &rx_queue) {
2075 struct rx_desc *rx_desc;
2076 struct rx_agg *agg, *agg_free;
2077 int len_used = 0;
2078 struct urb *urb;
2079 u8 *rx_data;
2080
2081 list_del_init(cursor);
2082
2083 agg = list_entry(cursor, struct rx_agg, list);
2084 urb = agg->urb;
2085 if (urb->actual_length < ETH_ZLEN)
2086 goto submit;
2087
2088 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2089
2090 rx_desc = agg->buffer;
2091 rx_data = agg->buffer;
2092 len_used += sizeof(struct rx_desc);
2093
2094 while (urb->actual_length > len_used) {
2095 struct net_device *netdev = tp->netdev;
2096 struct net_device_stats *stats = &netdev->stats;
2097 unsigned int pkt_len, rx_frag_head_sz;
2098 struct sk_buff *skb;
2099
2100
2101 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2102 break;
2103
2104 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2105 if (pkt_len < ETH_ZLEN)
2106 break;
2107
2108 len_used += pkt_len;
2109 if (urb->actual_length < len_used)
2110 break;
2111
2112 pkt_len -= ETH_FCS_LEN;
2113 rx_data += sizeof(struct rx_desc);
2114
2115 if (!agg_free || tp->rx_copybreak > pkt_len)
2116 rx_frag_head_sz = pkt_len;
2117 else
2118 rx_frag_head_sz = tp->rx_copybreak;
2119
2120 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2121 if (!skb) {
2122 stats->rx_dropped++;
2123 goto find_next_rx;
2124 }
2125
2126 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2127 memcpy(skb->data, rx_data, rx_frag_head_sz);
2128 skb_put(skb, rx_frag_head_sz);
2129 pkt_len -= rx_frag_head_sz;
2130 rx_data += rx_frag_head_sz;
2131 if (pkt_len) {
2132 skb_add_rx_frag(skb, 0, agg->page,
2133 agg_offset(agg, rx_data),
2134 pkt_len,
2135 SKB_DATA_ALIGN(pkt_len));
2136 get_page(agg->page);
2137 }
2138
2139 skb->protocol = eth_type_trans(skb, netdev);
2140 rtl_rx_vlan_tag(rx_desc, skb);
2141 if (work_done < budget) {
2142 work_done++;
2143 stats->rx_packets++;
2144 stats->rx_bytes += skb->len;
2145 napi_gro_receive(napi, skb);
2146 } else {
2147 __skb_queue_tail(&tp->rx_queue, skb);
2148 }
2149
2150 find_next_rx:
2151 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2152 rx_desc = (struct rx_desc *)rx_data;
2153 len_used = agg_offset(agg, rx_data);
2154 len_used += sizeof(struct rx_desc);
2155 }
2156
2157 WARN_ON(!agg_free && page_count(agg->page) > 1);
2158
2159 if (agg_free) {
2160 spin_lock_irqsave(&tp->rx_lock, flags);
2161 if (page_count(agg->page) == 1) {
2162 list_add(&agg_free->list, &tp->rx_used);
2163 } else {
2164 list_add_tail(&agg->list, &tp->rx_used);
2165 agg = agg_free;
2166 urb = agg->urb;
2167 }
2168 spin_unlock_irqrestore(&tp->rx_lock, flags);
2169 }
2170
2171 submit:
2172 if (!ret) {
2173 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2174 } else {
2175 urb->actual_length = 0;
2176 list_add_tail(&agg->list, next);
2177 }
2178 }
2179
2180 if (!list_empty(&rx_queue)) {
2181 spin_lock_irqsave(&tp->rx_lock, flags);
2182 list_splice_tail(&rx_queue, &tp->rx_done);
2183 spin_unlock_irqrestore(&tp->rx_lock, flags);
2184 }
2185
2186 out1:
2187 return work_done;
2188 }
2189
2190 static void tx_bottom(struct r8152 *tp)
2191 {
2192 int res;
2193
2194 do {
2195 struct tx_agg *agg;
2196
2197 if (skb_queue_empty(&tp->tx_queue))
2198 break;
2199
2200 agg = r8152_get_tx_agg(tp);
2201 if (!agg)
2202 break;
2203
2204 res = r8152_tx_agg_fill(tp, agg);
2205 if (res) {
2206 struct net_device *netdev = tp->netdev;
2207
2208 if (res == -ENODEV) {
2209 rtl_set_unplug(tp);
2210 netif_device_detach(netdev);
2211 } else {
2212 struct net_device_stats *stats = &netdev->stats;
2213 unsigned long flags;
2214
2215 netif_warn(tp, tx_err, netdev,
2216 "failed tx_urb %d\n", res);
2217 stats->tx_dropped += agg->skb_num;
2218
2219 spin_lock_irqsave(&tp->tx_lock, flags);
2220 list_add_tail(&agg->list, &tp->tx_free);
2221 spin_unlock_irqrestore(&tp->tx_lock, flags);
2222 }
2223 }
2224 } while (res == 0);
2225 }
2226
2227 static void bottom_half(unsigned long data)
2228 {
2229 struct r8152 *tp;
2230
2231 tp = (struct r8152 *)data;
2232
2233 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2234 return;
2235
2236 if (!test_bit(WORK_ENABLE, &tp->flags))
2237 return;
2238
2239
2240
2241 if (!netif_carrier_ok(tp->netdev))
2242 return;
2243
2244 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2245
2246 tx_bottom(tp);
2247 }
2248
2249 static int r8152_poll(struct napi_struct *napi, int budget)
2250 {
2251 struct r8152 *tp = container_of(napi, struct r8152, napi);
2252 int work_done;
2253
2254 work_done = rx_bottom(tp, budget);
2255
2256 if (work_done < budget) {
2257 if (!napi_complete_done(napi, work_done))
2258 goto out;
2259 if (!list_empty(&tp->rx_done))
2260 napi_schedule(napi);
2261 }
2262
2263 out:
2264 return work_done;
2265 }
2266
2267 static
2268 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2269 {
2270 int ret;
2271
2272
2273 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2274 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2275 return 0;
2276
2277 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2278 agg->buffer, tp->rx_buf_sz,
2279 (usb_complete_t)read_bulk_callback, agg);
2280
2281 ret = usb_submit_urb(agg->urb, mem_flags);
2282 if (ret == -ENODEV) {
2283 rtl_set_unplug(tp);
2284 netif_device_detach(tp->netdev);
2285 } else if (ret) {
2286 struct urb *urb = agg->urb;
2287 unsigned long flags;
2288
2289 urb->actual_length = 0;
2290 spin_lock_irqsave(&tp->rx_lock, flags);
2291 list_add_tail(&agg->list, &tp->rx_done);
2292 spin_unlock_irqrestore(&tp->rx_lock, flags);
2293
2294 netif_err(tp, rx_err, tp->netdev,
2295 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2296
2297 napi_schedule(&tp->napi);
2298 }
2299
2300 return ret;
2301 }
2302
2303 static void rtl_drop_queued_tx(struct r8152 *tp)
2304 {
2305 struct net_device_stats *stats = &tp->netdev->stats;
2306 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2307 struct sk_buff *skb;
2308
2309 if (skb_queue_empty(tx_queue))
2310 return;
2311
2312 __skb_queue_head_init(&skb_head);
2313 spin_lock_bh(&tx_queue->lock);
2314 skb_queue_splice_init(tx_queue, &skb_head);
2315 spin_unlock_bh(&tx_queue->lock);
2316
2317 while ((skb = __skb_dequeue(&skb_head))) {
2318 dev_kfree_skb(skb);
2319 stats->tx_dropped++;
2320 }
2321 }
2322
2323 static void rtl8152_tx_timeout(struct net_device *netdev)
2324 {
2325 struct r8152 *tp = netdev_priv(netdev);
2326
2327 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2328
2329 usb_queue_reset_device(tp->intf);
2330 }
2331
2332 static void rtl8152_set_rx_mode(struct net_device *netdev)
2333 {
2334 struct r8152 *tp = netdev_priv(netdev);
2335
2336 if (netif_carrier_ok(netdev)) {
2337 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2338 schedule_delayed_work(&tp->schedule, 0);
2339 }
2340 }
2341
2342 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2343 {
2344 struct r8152 *tp = netdev_priv(netdev);
2345 u32 mc_filter[2];
2346 __le32 tmp[2];
2347 u32 ocp_data;
2348
2349 netif_stop_queue(netdev);
2350 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2351 ocp_data &= ~RCR_ACPT_ALL;
2352 ocp_data |= RCR_AB | RCR_APM;
2353
2354 if (netdev->flags & IFF_PROMISC) {
2355
2356 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2357 ocp_data |= RCR_AM | RCR_AAP;
2358 mc_filter[1] = 0xffffffff;
2359 mc_filter[0] = 0xffffffff;
2360 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2361 (netdev->flags & IFF_ALLMULTI)) {
2362
2363 ocp_data |= RCR_AM;
2364 mc_filter[1] = 0xffffffff;
2365 mc_filter[0] = 0xffffffff;
2366 } else {
2367 struct netdev_hw_addr *ha;
2368
2369 mc_filter[1] = 0;
2370 mc_filter[0] = 0;
2371 netdev_for_each_mc_addr(ha, netdev) {
2372 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2373
2374 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2375 ocp_data |= RCR_AM;
2376 }
2377 }
2378
2379 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2380 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2381
2382 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2383 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2384 netif_wake_queue(netdev);
2385 }
2386
2387 static netdev_features_t
2388 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2389 netdev_features_t features)
2390 {
2391 u32 mss = skb_shinfo(skb)->gso_size;
2392 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2393 int offset = skb_transport_offset(skb);
2394
2395 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2396 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2397 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2398 features &= ~NETIF_F_GSO_MASK;
2399
2400 return features;
2401 }
2402
2403 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2404 struct net_device *netdev)
2405 {
2406 struct r8152 *tp = netdev_priv(netdev);
2407
2408 skb_tx_timestamp(skb);
2409
2410 skb_queue_tail(&tp->tx_queue, skb);
2411
2412 if (!list_empty(&tp->tx_free)) {
2413 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2414 set_bit(SCHEDULE_TASKLET, &tp->flags);
2415 schedule_delayed_work(&tp->schedule, 0);
2416 } else {
2417 usb_mark_last_busy(tp->udev);
2418 tasklet_schedule(&tp->tx_tl);
2419 }
2420 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2421 netif_stop_queue(netdev);
2422 }
2423
2424 return NETDEV_TX_OK;
2425 }
2426
2427 static void r8152b_reset_packet_filter(struct r8152 *tp)
2428 {
2429 u32 ocp_data;
2430
2431 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2432 ocp_data &= ~FMC_FCR_MCU_EN;
2433 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2434 ocp_data |= FMC_FCR_MCU_EN;
2435 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2436 }
2437
2438 static void rtl8152_nic_reset(struct r8152 *tp)
2439 {
2440 int i;
2441
2442 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2443
2444 for (i = 0; i < 1000; i++) {
2445 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2446 break;
2447 usleep_range(100, 400);
2448 }
2449 }
2450
2451 static void set_tx_qlen(struct r8152 *tp)
2452 {
2453 struct net_device *netdev = tp->netdev;
2454
2455 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2456 sizeof(struct tx_desc));
2457 }
2458
2459 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2460 {
2461 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2462 }
2463
2464 static void rtl_set_eee_plus(struct r8152 *tp)
2465 {
2466 u32 ocp_data;
2467 u8 speed;
2468
2469 speed = rtl8152_get_speed(tp);
2470 if (speed & _10bps) {
2471 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2472 ocp_data |= EEEP_CR_EEEP_TX;
2473 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2474 } else {
2475 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2476 ocp_data &= ~EEEP_CR_EEEP_TX;
2477 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2478 }
2479 }
2480
2481 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2482 {
2483 u32 ocp_data;
2484
2485 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2486 if (enable)
2487 ocp_data |= RXDY_GATED_EN;
2488 else
2489 ocp_data &= ~RXDY_GATED_EN;
2490 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2491 }
2492
2493 static int rtl_start_rx(struct r8152 *tp)
2494 {
2495 struct rx_agg *agg, *agg_next;
2496 struct list_head tmp_list;
2497 unsigned long flags;
2498 int ret = 0, i = 0;
2499
2500 INIT_LIST_HEAD(&tmp_list);
2501
2502 spin_lock_irqsave(&tp->rx_lock, flags);
2503
2504 INIT_LIST_HEAD(&tp->rx_done);
2505 INIT_LIST_HEAD(&tp->rx_used);
2506
2507 list_splice_init(&tp->rx_info, &tmp_list);
2508
2509 spin_unlock_irqrestore(&tp->rx_lock, flags);
2510
2511 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2512 INIT_LIST_HEAD(&agg->list);
2513
2514
2515 if (++i > RTL8152_MAX_RX) {
2516 spin_lock_irqsave(&tp->rx_lock, flags);
2517 list_add_tail(&agg->list, &tp->rx_used);
2518 spin_unlock_irqrestore(&tp->rx_lock, flags);
2519 } else if (unlikely(ret < 0)) {
2520 spin_lock_irqsave(&tp->rx_lock, flags);
2521 list_add_tail(&agg->list, &tp->rx_done);
2522 spin_unlock_irqrestore(&tp->rx_lock, flags);
2523 } else {
2524 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2525 }
2526 }
2527
2528 spin_lock_irqsave(&tp->rx_lock, flags);
2529 WARN_ON(!list_empty(&tp->rx_info));
2530 list_splice(&tmp_list, &tp->rx_info);
2531 spin_unlock_irqrestore(&tp->rx_lock, flags);
2532
2533 return ret;
2534 }
2535
2536 static int rtl_stop_rx(struct r8152 *tp)
2537 {
2538 struct rx_agg *agg, *agg_next;
2539 struct list_head tmp_list;
2540 unsigned long flags;
2541
2542 INIT_LIST_HEAD(&tmp_list);
2543
2544
2545
2546
2547
2548
2549
2550 spin_lock_irqsave(&tp->rx_lock, flags);
2551 list_splice_init(&tp->rx_info, &tmp_list);
2552 spin_unlock_irqrestore(&tp->rx_lock, flags);
2553
2554 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2555
2556
2557
2558 if (page_count(agg->page) > 1)
2559 free_rx_agg(tp, agg);
2560 else
2561 usb_kill_urb(agg->urb);
2562 }
2563
2564
2565 spin_lock_irqsave(&tp->rx_lock, flags);
2566 WARN_ON(!list_empty(&tp->rx_info));
2567 list_splice(&tmp_list, &tp->rx_info);
2568 spin_unlock_irqrestore(&tp->rx_lock, flags);
2569
2570 while (!skb_queue_empty(&tp->rx_queue))
2571 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2572
2573 return 0;
2574 }
2575
2576 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2577 {
2578 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2579 OWN_UPDATE | OWN_CLEAR);
2580 }
2581
2582 static int rtl_enable(struct r8152 *tp)
2583 {
2584 u32 ocp_data;
2585
2586 r8152b_reset_packet_filter(tp);
2587
2588 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2589 ocp_data |= CR_RE | CR_TE;
2590 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2591
2592 switch (tp->version) {
2593 case RTL_VER_08:
2594 case RTL_VER_09:
2595 r8153b_rx_agg_chg_indicate(tp);
2596 break;
2597 default:
2598 break;
2599 }
2600
2601 rxdy_gated_en(tp, false);
2602
2603 return 0;
2604 }
2605
2606 static int rtl8152_enable(struct r8152 *tp)
2607 {
2608 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2609 return -ENODEV;
2610
2611 set_tx_qlen(tp);
2612 rtl_set_eee_plus(tp);
2613
2614 return rtl_enable(tp);
2615 }
2616
2617 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2618 {
2619 u32 ocp_data = tp->coalesce / 8;
2620
2621 switch (tp->version) {
2622 case RTL_VER_03:
2623 case RTL_VER_04:
2624 case RTL_VER_05:
2625 case RTL_VER_06:
2626 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2627 ocp_data);
2628 break;
2629
2630 case RTL_VER_08:
2631 case RTL_VER_09:
2632
2633
2634
2635 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2636 128 / 8);
2637 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2638 ocp_data);
2639 break;
2640
2641 default:
2642 break;
2643 }
2644 }
2645
2646 static void r8153_set_rx_early_size(struct r8152 *tp)
2647 {
2648 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2649
2650 switch (tp->version) {
2651 case RTL_VER_03:
2652 case RTL_VER_04:
2653 case RTL_VER_05:
2654 case RTL_VER_06:
2655 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2656 ocp_data / 4);
2657 break;
2658 case RTL_VER_08:
2659 case RTL_VER_09:
2660 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2661 ocp_data / 8);
2662 break;
2663 default:
2664 WARN_ON_ONCE(1);
2665 break;
2666 }
2667 }
2668
2669 static int rtl8153_enable(struct r8152 *tp)
2670 {
2671 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2672 return -ENODEV;
2673
2674 set_tx_qlen(tp);
2675 rtl_set_eee_plus(tp);
2676 r8153_set_rx_early_timeout(tp);
2677 r8153_set_rx_early_size(tp);
2678
2679 return rtl_enable(tp);
2680 }
2681
2682 static void rtl_disable(struct r8152 *tp)
2683 {
2684 u32 ocp_data;
2685 int i;
2686
2687 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2688 rtl_drop_queued_tx(tp);
2689 return;
2690 }
2691
2692 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2693 ocp_data &= ~RCR_ACPT_ALL;
2694 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2695
2696 rtl_drop_queued_tx(tp);
2697
2698 for (i = 0; i < RTL8152_MAX_TX; i++)
2699 usb_kill_urb(tp->tx_info[i].urb);
2700
2701 rxdy_gated_en(tp, true);
2702
2703 for (i = 0; i < 1000; i++) {
2704 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2705 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2706 break;
2707 usleep_range(1000, 2000);
2708 }
2709
2710 for (i = 0; i < 1000; i++) {
2711 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2712 break;
2713 usleep_range(1000, 2000);
2714 }
2715
2716 rtl_stop_rx(tp);
2717
2718 rtl8152_nic_reset(tp);
2719 }
2720
2721 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2722 {
2723 u32 ocp_data;
2724
2725 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2726 if (enable)
2727 ocp_data |= POWER_CUT;
2728 else
2729 ocp_data &= ~POWER_CUT;
2730 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2731
2732 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2733 ocp_data &= ~RESUME_INDICATE;
2734 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2735 }
2736
2737 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2738 {
2739 u32 ocp_data;
2740
2741 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2742 if (enable)
2743 ocp_data |= CPCR_RX_VLAN;
2744 else
2745 ocp_data &= ~CPCR_RX_VLAN;
2746 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2747 }
2748
2749 static int rtl8152_set_features(struct net_device *dev,
2750 netdev_features_t features)
2751 {
2752 netdev_features_t changed = features ^ dev->features;
2753 struct r8152 *tp = netdev_priv(dev);
2754 int ret;
2755
2756 ret = usb_autopm_get_interface(tp->intf);
2757 if (ret < 0)
2758 goto out;
2759
2760 mutex_lock(&tp->control);
2761
2762 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2763 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2764 rtl_rx_vlan_en(tp, true);
2765 else
2766 rtl_rx_vlan_en(tp, false);
2767 }
2768
2769 mutex_unlock(&tp->control);
2770
2771 usb_autopm_put_interface(tp->intf);
2772
2773 out:
2774 return ret;
2775 }
2776
2777 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2778
2779 static u32 __rtl_get_wol(struct r8152 *tp)
2780 {
2781 u32 ocp_data;
2782 u32 wolopts = 0;
2783
2784 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2785 if (ocp_data & LINK_ON_WAKE_EN)
2786 wolopts |= WAKE_PHY;
2787
2788 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2789 if (ocp_data & UWF_EN)
2790 wolopts |= WAKE_UCAST;
2791 if (ocp_data & BWF_EN)
2792 wolopts |= WAKE_BCAST;
2793 if (ocp_data & MWF_EN)
2794 wolopts |= WAKE_MCAST;
2795
2796 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2797 if (ocp_data & MAGIC_EN)
2798 wolopts |= WAKE_MAGIC;
2799
2800 return wolopts;
2801 }
2802
2803 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2804 {
2805 u32 ocp_data;
2806
2807 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2808
2809 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2810 ocp_data &= ~LINK_ON_WAKE_EN;
2811 if (wolopts & WAKE_PHY)
2812 ocp_data |= LINK_ON_WAKE_EN;
2813 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2814
2815 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2816 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2817 if (wolopts & WAKE_UCAST)
2818 ocp_data |= UWF_EN;
2819 if (wolopts & WAKE_BCAST)
2820 ocp_data |= BWF_EN;
2821 if (wolopts & WAKE_MCAST)
2822 ocp_data |= MWF_EN;
2823 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2824
2825 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2826
2827 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2828 ocp_data &= ~MAGIC_EN;
2829 if (wolopts & WAKE_MAGIC)
2830 ocp_data |= MAGIC_EN;
2831 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2832
2833 if (wolopts & WAKE_ANY)
2834 device_set_wakeup_enable(&tp->udev->dev, true);
2835 else
2836 device_set_wakeup_enable(&tp->udev->dev, false);
2837 }
2838
2839 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2840 {
2841
2842 if (enable) {
2843 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2844 ALDPS_SPDWN_RATIO);
2845 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2846 EEE_SPDWN_RATIO);
2847 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2848 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2849 U1U2_SPDWN_EN | L1_SPDWN_EN);
2850 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2851 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2852 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2853 TP1000_SPDWN_EN);
2854 } else {
2855 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2856 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2857 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2858 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2859 }
2860 }
2861
2862 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2863 {
2864 u8 u1u2[8];
2865
2866 if (enable)
2867 memset(u1u2, 0xff, sizeof(u1u2));
2868 else
2869 memset(u1u2, 0x00, sizeof(u1u2));
2870
2871 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2872 }
2873
2874 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2875 {
2876 u32 ocp_data;
2877
2878 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2879 if (enable)
2880 ocp_data |= LPM_U1U2_EN;
2881 else
2882 ocp_data &= ~LPM_U1U2_EN;
2883
2884 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2885 }
2886
2887 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2888 {
2889 u32 ocp_data;
2890
2891 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2892 if (enable)
2893 ocp_data |= U2P3_ENABLE;
2894 else
2895 ocp_data &= ~U2P3_ENABLE;
2896 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2897 }
2898
2899 static void r8153b_ups_flags(struct r8152 *tp)
2900 {
2901 u32 ups_flags = 0;
2902
2903 if (tp->ups_info.green)
2904 ups_flags |= UPS_FLAGS_EN_GREEN;
2905
2906 if (tp->ups_info.aldps)
2907 ups_flags |= UPS_FLAGS_EN_ALDPS;
2908
2909 if (tp->ups_info.eee)
2910 ups_flags |= UPS_FLAGS_EN_EEE;
2911
2912 if (tp->ups_info.flow_control)
2913 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
2914
2915 if (tp->ups_info.eee_ckdiv)
2916 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
2917
2918 if (tp->ups_info.eee_cmod_lv)
2919 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
2920
2921 if (tp->ups_info._10m_ckdiv)
2922 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
2923
2924 if (tp->ups_info.eee_plloff_100)
2925 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
2926
2927 if (tp->ups_info.eee_plloff_giga)
2928 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
2929
2930 if (tp->ups_info._250m_ckdiv)
2931 ups_flags |= UPS_FLAGS_250M_CKDIV;
2932
2933 if (tp->ups_info.ctap_short_off)
2934 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
2935
2936 switch (tp->ups_info.speed_duplex) {
2937 case NWAY_10M_HALF:
2938 ups_flags |= ups_flags_speed(1);
2939 break;
2940 case NWAY_10M_FULL:
2941 ups_flags |= ups_flags_speed(2);
2942 break;
2943 case NWAY_100M_HALF:
2944 ups_flags |= ups_flags_speed(3);
2945 break;
2946 case NWAY_100M_FULL:
2947 ups_flags |= ups_flags_speed(4);
2948 break;
2949 case NWAY_1000M_FULL:
2950 ups_flags |= ups_flags_speed(5);
2951 break;
2952 case FORCE_10M_HALF:
2953 ups_flags |= ups_flags_speed(6);
2954 break;
2955 case FORCE_10M_FULL:
2956 ups_flags |= ups_flags_speed(7);
2957 break;
2958 case FORCE_100M_HALF:
2959 ups_flags |= ups_flags_speed(8);
2960 break;
2961 case FORCE_100M_FULL:
2962 ups_flags |= ups_flags_speed(9);
2963 break;
2964 default:
2965 break;
2966 }
2967
2968 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
2969 }
2970
2971 static void r8153b_green_en(struct r8152 *tp, bool enable)
2972 {
2973 u16 data;
2974
2975 if (enable) {
2976 sram_write(tp, 0x8045, 0);
2977 sram_write(tp, 0x804d, 0x1222);
2978 sram_write(tp, 0x805d, 0x0022);
2979 } else {
2980 sram_write(tp, 0x8045, 0x2444);
2981 sram_write(tp, 0x804d, 0x2444);
2982 sram_write(tp, 0x805d, 0x2444);
2983 }
2984
2985 data = sram_read(tp, SRAM_GREEN_CFG);
2986 data |= GREEN_ETH_EN;
2987 sram_write(tp, SRAM_GREEN_CFG, data);
2988
2989 tp->ups_info.green = enable;
2990 }
2991
2992 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2993 {
2994 u16 data;
2995 int i;
2996
2997 for (i = 0; i < 500; i++) {
2998 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2999 data &= PHY_STAT_MASK;
3000 if (desired) {
3001 if (data == desired)
3002 break;
3003 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3004 data == PHY_STAT_EXT_INIT) {
3005 break;
3006 }
3007
3008 msleep(20);
3009 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3010 break;
3011 }
3012
3013 return data;
3014 }
3015
3016 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3017 {
3018 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3019
3020 if (enable) {
3021 r8153b_ups_flags(tp);
3022
3023 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3024 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3025
3026 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3027 ocp_data |= BIT(0);
3028 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3029 } else {
3030 u16 data;
3031
3032 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3033 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3034
3035 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3036 ocp_data &= ~BIT(0);
3037 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3038
3039 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3040 ocp_data &= ~PCUT_STATUS;
3041 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3042
3043 data = r8153_phy_status(tp, 0);
3044
3045 switch (data) {
3046 case PHY_STAT_PWRDN:
3047 case PHY_STAT_EXT_INIT:
3048 r8153b_green_en(tp,
3049 test_bit(GREEN_ETHERNET, &tp->flags));
3050
3051 data = r8152_mdio_read(tp, MII_BMCR);
3052 data &= ~BMCR_PDOWN;
3053 data |= BMCR_RESET;
3054 r8152_mdio_write(tp, MII_BMCR, data);
3055
3056 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3057
3058
3059 default:
3060 if (data != PHY_STAT_LAN_ON)
3061 netif_warn(tp, link, tp->netdev,
3062 "PHY not ready");
3063 break;
3064 }
3065 }
3066 }
3067
3068 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3069 {
3070 u32 ocp_data;
3071
3072 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3073 if (enable)
3074 ocp_data |= PWR_EN | PHASE2_EN;
3075 else
3076 ocp_data &= ~(PWR_EN | PHASE2_EN);
3077 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3078
3079 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3080 ocp_data &= ~PCUT_STATUS;
3081 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3082 }
3083
3084 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3085 {
3086 u32 ocp_data;
3087
3088 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3089 if (enable)
3090 ocp_data |= PWR_EN | PHASE2_EN;
3091 else
3092 ocp_data &= ~PWR_EN;
3093 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3094
3095 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3096 ocp_data &= ~PCUT_STATUS;
3097 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3098 }
3099
3100 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3101 {
3102 u32 ocp_data;
3103
3104 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3105 if (enable)
3106 ocp_data |= UPCOMING_RUNTIME_D3;
3107 else
3108 ocp_data &= ~UPCOMING_RUNTIME_D3;
3109 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3110
3111 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3112 ocp_data &= ~LINK_CHG_EVENT;
3113 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3114
3115 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3116 ocp_data &= ~LINK_CHANGE_FLAG;
3117 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3118 }
3119
3120 static bool rtl_can_wakeup(struct r8152 *tp)
3121 {
3122 struct usb_device *udev = tp->udev;
3123
3124 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3125 }
3126
3127 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3128 {
3129 if (enable) {
3130 u32 ocp_data;
3131
3132 __rtl_set_wol(tp, WAKE_ANY);
3133
3134 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3135
3136 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3137 ocp_data |= LINK_OFF_WAKE_EN;
3138 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3139
3140 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3141 } else {
3142 u32 ocp_data;
3143
3144 __rtl_set_wol(tp, tp->saved_wolopts);
3145
3146 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3147
3148 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3149 ocp_data &= ~LINK_OFF_WAKE_EN;
3150 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3151
3152 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3153 }
3154 }
3155
3156 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3157 {
3158 if (enable) {
3159 r8153_u1u2en(tp, false);
3160 r8153_u2p3en(tp, false);
3161 r8153_mac_clk_spd(tp, true);
3162 rtl_runtime_suspend_enable(tp, true);
3163 } else {
3164 rtl_runtime_suspend_enable(tp, false);
3165 r8153_mac_clk_spd(tp, false);
3166
3167 switch (tp->version) {
3168 case RTL_VER_03:
3169 case RTL_VER_04:
3170 break;
3171 case RTL_VER_05:
3172 case RTL_VER_06:
3173 default:
3174 r8153_u2p3en(tp, true);
3175 break;
3176 }
3177
3178 r8153_u1u2en(tp, true);
3179 }
3180 }
3181
3182 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3183 {
3184 if (enable) {
3185 r8153_queue_wake(tp, true);
3186 r8153b_u1u2en(tp, false);
3187 r8153_u2p3en(tp, false);
3188 rtl_runtime_suspend_enable(tp, true);
3189 r8153b_ups_en(tp, true);
3190 } else {
3191 r8153b_ups_en(tp, false);
3192 r8153_queue_wake(tp, false);
3193 rtl_runtime_suspend_enable(tp, false);
3194 r8153b_u1u2en(tp, true);
3195 }
3196 }
3197
3198 static void r8153_teredo_off(struct r8152 *tp)
3199 {
3200 u32 ocp_data;
3201
3202 switch (tp->version) {
3203 case RTL_VER_01:
3204 case RTL_VER_02:
3205 case RTL_VER_03:
3206 case RTL_VER_04:
3207 case RTL_VER_05:
3208 case RTL_VER_06:
3209 case RTL_VER_07:
3210 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3211 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3212 OOB_TEREDO_EN);
3213 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3214 break;
3215
3216 case RTL_VER_08:
3217 case RTL_VER_09:
3218
3219
3220
3221 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3222 break;
3223
3224 default:
3225 break;
3226 }
3227
3228 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3229 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3230 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3231 }
3232
3233 static void rtl_reset_bmu(struct r8152 *tp)
3234 {
3235 u32 ocp_data;
3236
3237 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3238 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3239 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3240 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3241 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3242 }
3243
3244 static void r8152_aldps_en(struct r8152 *tp, bool enable)
3245 {
3246 if (enable) {
3247 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
3248 LINKENA | DIS_SDSAVE);
3249 } else {
3250 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
3251 DIS_SDSAVE);
3252 msleep(20);
3253 }
3254 }
3255
3256 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3257 {
3258 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3259 ocp_reg_write(tp, OCP_EEE_DATA, reg);
3260 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3261 }
3262
3263 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3264 {
3265 u16 data;
3266
3267 r8152_mmd_indirect(tp, dev, reg);
3268 data = ocp_reg_read(tp, OCP_EEE_DATA);
3269 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3270
3271 return data;
3272 }
3273
3274 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3275 {
3276 r8152_mmd_indirect(tp, dev, reg);
3277 ocp_reg_write(tp, OCP_EEE_DATA, data);
3278 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3279 }
3280
3281 static void r8152_eee_en(struct r8152 *tp, bool enable)
3282 {
3283 u16 config1, config2, config3;
3284 u32 ocp_data;
3285
3286 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3287 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3288 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3289 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3290
3291 if (enable) {
3292 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3293 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3294 config1 |= sd_rise_time(1);
3295 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3296 config3 |= fast_snr(42);
3297 } else {
3298 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3299 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3300 RX_QUIET_EN);
3301 config1 |= sd_rise_time(7);
3302 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3303 config3 |= fast_snr(511);
3304 }
3305
3306 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3307 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3308 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3309 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3310 }
3311
3312 static void r8153_eee_en(struct r8152 *tp, bool enable)
3313 {
3314 u32 ocp_data;
3315 u16 config;
3316
3317 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3318 config = ocp_reg_read(tp, OCP_EEE_CFG);
3319
3320 if (enable) {
3321 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3322 config |= EEE10_EN;
3323 } else {
3324 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3325 config &= ~EEE10_EN;
3326 }
3327
3328 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3329 ocp_reg_write(tp, OCP_EEE_CFG, config);
3330
3331 tp->ups_info.eee = enable;
3332 }
3333
3334 static void rtl_eee_enable(struct r8152 *tp, bool enable)
3335 {
3336 switch (tp->version) {
3337 case RTL_VER_01:
3338 case RTL_VER_02:
3339 case RTL_VER_07:
3340 if (enable) {
3341 r8152_eee_en(tp, true);
3342 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
3343 tp->eee_adv);
3344 } else {
3345 r8152_eee_en(tp, false);
3346 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
3347 }
3348 break;
3349 case RTL_VER_03:
3350 case RTL_VER_04:
3351 case RTL_VER_05:
3352 case RTL_VER_06:
3353 case RTL_VER_08:
3354 case RTL_VER_09:
3355 if (enable) {
3356 r8153_eee_en(tp, true);
3357 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
3358 } else {
3359 r8153_eee_en(tp, false);
3360 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3361 }
3362 break;
3363 default:
3364 break;
3365 }
3366 }
3367
3368 static void r8152b_enable_fc(struct r8152 *tp)
3369 {
3370 u16 anar;
3371
3372 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3373 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3374 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3375
3376 tp->ups_info.flow_control = true;
3377 }
3378
3379 static void rtl8152_disable(struct r8152 *tp)
3380 {
3381 r8152_aldps_en(tp, false);
3382 rtl_disable(tp);
3383 r8152_aldps_en(tp, true);
3384 }
3385
3386 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3387 {
3388 rtl_eee_enable(tp, tp->eee_en);
3389 r8152_aldps_en(tp, true);
3390 r8152b_enable_fc(tp);
3391
3392 set_bit(PHY_RESET, &tp->flags);
3393 }
3394
3395 static void r8152b_exit_oob(struct r8152 *tp)
3396 {
3397 u32 ocp_data;
3398 int i;
3399
3400 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3401 ocp_data &= ~RCR_ACPT_ALL;
3402 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3403
3404 rxdy_gated_en(tp, true);
3405 r8153_teredo_off(tp);
3406 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3407 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3408
3409 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3410 ocp_data &= ~NOW_IS_OOB;
3411 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3412
3413 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3414 ocp_data &= ~MCU_BORW_EN;
3415 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3416
3417 for (i = 0; i < 1000; i++) {
3418 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3419 if (ocp_data & LINK_LIST_READY)
3420 break;
3421 usleep_range(1000, 2000);
3422 }
3423
3424 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3425 ocp_data |= RE_INIT_LL;
3426 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3427
3428 for (i = 0; i < 1000; i++) {
3429 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3430 if (ocp_data & LINK_LIST_READY)
3431 break;
3432 usleep_range(1000, 2000);
3433 }
3434
3435 rtl8152_nic_reset(tp);
3436
3437
3438 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3439
3440 if (tp->udev->speed == USB_SPEED_FULL ||
3441 tp->udev->speed == USB_SPEED_LOW) {
3442
3443 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3444 RXFIFO_THR2_FULL);
3445 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3446 RXFIFO_THR3_FULL);
3447 } else {
3448
3449 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3450 RXFIFO_THR2_HIGH);
3451 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3452 RXFIFO_THR3_HIGH);
3453 }
3454
3455
3456 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3457
3458 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3459 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3460 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3461 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3462
3463 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3464
3465 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3466
3467 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3468 ocp_data |= TCR0_AUTO_FIFO;
3469 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3470 }
3471
3472 static void r8152b_enter_oob(struct r8152 *tp)
3473 {
3474 u32 ocp_data;
3475 int i;
3476
3477 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3478 ocp_data &= ~NOW_IS_OOB;
3479 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3480
3481 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3482 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3483 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3484
3485 rtl_disable(tp);
3486
3487 for (i = 0; i < 1000; i++) {
3488 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3489 if (ocp_data & LINK_LIST_READY)
3490 break;
3491 usleep_range(1000, 2000);
3492 }
3493
3494 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3495 ocp_data |= RE_INIT_LL;
3496 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3497
3498 for (i = 0; i < 1000; i++) {
3499 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3500 if (ocp_data & LINK_LIST_READY)
3501 break;
3502 usleep_range(1000, 2000);
3503 }
3504
3505 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3506
3507 rtl_rx_vlan_en(tp, true);
3508
3509 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
3510 ocp_data |= ALDPS_PROXY_MODE;
3511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
3512
3513 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3514 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3515 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3516
3517 rxdy_gated_en(tp, false);
3518
3519 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3520 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3521 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3522 }
3523
3524 static int r8153_patch_request(struct r8152 *tp, bool request)
3525 {
3526 u16 data;
3527 int i;
3528
3529 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3530 if (request)
3531 data |= PATCH_REQUEST;
3532 else
3533 data &= ~PATCH_REQUEST;
3534 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3535
3536 for (i = 0; request && i < 5000; i++) {
3537 usleep_range(1000, 2000);
3538 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3539 break;
3540 }
3541
3542 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3543 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3544 r8153_patch_request(tp, false);
3545 return -ETIME;
3546 } else {
3547 return 0;
3548 }
3549 }
3550
3551 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3552 {
3553 u16 data;
3554
3555 data = ocp_reg_read(tp, OCP_POWER_CFG);
3556 if (enable) {
3557 data |= EN_ALDPS;
3558 ocp_reg_write(tp, OCP_POWER_CFG, data);
3559 } else {
3560 int i;
3561
3562 data &= ~EN_ALDPS;
3563 ocp_reg_write(tp, OCP_POWER_CFG, data);
3564 for (i = 0; i < 20; i++) {
3565 usleep_range(1000, 2000);
3566 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3567 break;
3568 }
3569 }
3570
3571 tp->ups_info.aldps = enable;
3572 }
3573
3574 static void r8153_hw_phy_cfg(struct r8152 *tp)
3575 {
3576 u32 ocp_data;
3577 u16 data;
3578
3579
3580 r8153_aldps_en(tp, false);
3581
3582
3583 rtl_eee_enable(tp, false);
3584
3585 if (tp->version == RTL_VER_03) {
3586 data = ocp_reg_read(tp, OCP_EEE_CFG);
3587 data &= ~CTAP_SHORT_EN;
3588 ocp_reg_write(tp, OCP_EEE_CFG, data);
3589 }
3590
3591 data = ocp_reg_read(tp, OCP_POWER_CFG);
3592 data |= EEE_CLKDIV_EN;
3593 ocp_reg_write(tp, OCP_POWER_CFG, data);
3594
3595 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3596 data |= EN_10M_BGOFF;
3597 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3598 data = ocp_reg_read(tp, OCP_POWER_CFG);
3599 data |= EN_10M_PLLOFF;
3600 ocp_reg_write(tp, OCP_POWER_CFG, data);
3601 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3602
3603 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3604 ocp_data |= PFM_PWM_SWITCH;
3605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3606
3607
3608 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3609
3610
3611 sram_write(tp, SRAM_10M_AMP1, 0x00af);
3612 sram_write(tp, SRAM_10M_AMP2, 0x0208);
3613
3614 if (tp->eee_en)
3615 rtl_eee_enable(tp, true);
3616
3617 r8153_aldps_en(tp, true);
3618 r8152b_enable_fc(tp);
3619
3620 switch (tp->version) {
3621 case RTL_VER_03:
3622 case RTL_VER_04:
3623 break;
3624 case RTL_VER_05:
3625 case RTL_VER_06:
3626 default:
3627 r8153_u2p3en(tp, true);
3628 break;
3629 }
3630
3631 set_bit(PHY_RESET, &tp->flags);
3632 }
3633
3634 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3635 {
3636 u32 ocp_data;
3637
3638 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3639 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3640 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;
3641 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3642
3643 return ocp_data;
3644 }
3645
3646 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3647 {
3648 u32 ocp_data;
3649 u16 data;
3650
3651
3652 r8153_aldps_en(tp, false);
3653
3654
3655 rtl_eee_enable(tp, false);
3656
3657 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3658
3659 data = sram_read(tp, SRAM_GREEN_CFG);
3660 data |= R_TUNE_EN;
3661 sram_write(tp, SRAM_GREEN_CFG, data);
3662 data = ocp_reg_read(tp, OCP_NCTL_CFG);
3663 data |= PGA_RETURN_EN;
3664 ocp_reg_write(tp, OCP_NCTL_CFG, data);
3665
3666
3667
3668
3669
3670
3671 ocp_data = r8152_efuse_read(tp, 0x7d);
3672 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3673 if (data != 0xffff)
3674 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3675
3676
3677
3678
3679
3680 ocp_data = ocp_reg_read(tp, 0xc426);
3681 ocp_data &= 0x3fff;
3682 if (ocp_data) {
3683 u32 swr_cnt_1ms_ini;
3684
3685 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3686 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3687 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3688 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3689 }
3690
3691 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3692 ocp_data |= PFM_PWM_SWITCH;
3693 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3694
3695
3696 if (!r8153_patch_request(tp, true)) {
3697 data = ocp_reg_read(tp, OCP_POWER_CFG);
3698 data |= EEE_CLKDIV_EN;
3699 ocp_reg_write(tp, OCP_POWER_CFG, data);
3700 tp->ups_info.eee_ckdiv = true;
3701
3702 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3703 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3704 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3705 tp->ups_info.eee_cmod_lv = true;
3706 tp->ups_info._10m_ckdiv = true;
3707 tp->ups_info.eee_plloff_giga = true;
3708
3709 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3710 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3711 tp->ups_info._250m_ckdiv = true;
3712
3713 r8153_patch_request(tp, false);
3714 }
3715
3716 if (tp->eee_en)
3717 rtl_eee_enable(tp, true);
3718
3719 r8153_aldps_en(tp, true);
3720 r8152b_enable_fc(tp);
3721
3722 set_bit(PHY_RESET, &tp->flags);
3723 }
3724
3725 static void r8153_first_init(struct r8152 *tp)
3726 {
3727 u32 ocp_data;
3728 int i;
3729
3730 r8153_mac_clk_spd(tp, false);
3731 rxdy_gated_en(tp, true);
3732 r8153_teredo_off(tp);
3733
3734 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3735 ocp_data &= ~RCR_ACPT_ALL;
3736 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3737
3738 rtl8152_nic_reset(tp);
3739 rtl_reset_bmu(tp);
3740
3741 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3742 ocp_data &= ~NOW_IS_OOB;
3743 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3744
3745 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3746 ocp_data &= ~MCU_BORW_EN;
3747 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3748
3749 for (i = 0; i < 1000; i++) {
3750 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3751 if (ocp_data & LINK_LIST_READY)
3752 break;
3753 usleep_range(1000, 2000);
3754 }
3755
3756 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3757 ocp_data |= RE_INIT_LL;
3758 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3759
3760 for (i = 0; i < 1000; i++) {
3761 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3762 if (ocp_data & LINK_LIST_READY)
3763 break;
3764 usleep_range(1000, 2000);
3765 }
3766
3767 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3768
3769 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3770 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3771 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3772
3773 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3774 ocp_data |= TCR0_AUTO_FIFO;
3775 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3776
3777 rtl8152_nic_reset(tp);
3778
3779
3780 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3781 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3782 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3783
3784 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3785 }
3786
3787 static void r8153_enter_oob(struct r8152 *tp)
3788 {
3789 u32 ocp_data;
3790 int i;
3791
3792 r8153_mac_clk_spd(tp, true);
3793
3794 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3795 ocp_data &= ~NOW_IS_OOB;
3796 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3797
3798 rtl_disable(tp);
3799 rtl_reset_bmu(tp);
3800
3801 for (i = 0; i < 1000; i++) {
3802 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3803 if (ocp_data & LINK_LIST_READY)
3804 break;
3805 usleep_range(1000, 2000);
3806 }
3807
3808 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3809 ocp_data |= RE_INIT_LL;
3810 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3811
3812 for (i = 0; i < 1000; i++) {
3813 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3814 if (ocp_data & LINK_LIST_READY)
3815 break;
3816 usleep_range(1000, 2000);
3817 }
3818
3819 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3820 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3821
3822 switch (tp->version) {
3823 case RTL_VER_03:
3824 case RTL_VER_04:
3825 case RTL_VER_05:
3826 case RTL_VER_06:
3827 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3828 ocp_data &= ~TEREDO_WAKE_MASK;
3829 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3830 break;
3831
3832 case RTL_VER_08:
3833 case RTL_VER_09:
3834
3835
3836
3837
3838 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3839 break;
3840
3841 default:
3842 break;
3843 }
3844
3845 rtl_rx_vlan_en(tp, true);
3846
3847 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
3848 ocp_data |= ALDPS_PROXY_MODE;
3849 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
3850
3851 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3852 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3853 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3854
3855 rxdy_gated_en(tp, false);
3856
3857 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3858 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3859 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3860 }
3861
3862 static void rtl8153_disable(struct r8152 *tp)
3863 {
3864 r8153_aldps_en(tp, false);
3865 rtl_disable(tp);
3866 rtl_reset_bmu(tp);
3867 r8153_aldps_en(tp, true);
3868 }
3869
3870 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
3871 u32 advertising)
3872 {
3873 u16 bmcr;
3874 int ret = 0;
3875
3876 if (autoneg == AUTONEG_DISABLE) {
3877 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
3878 return -EINVAL;
3879
3880 switch (speed) {
3881 case SPEED_10:
3882 bmcr = BMCR_SPEED10;
3883 if (duplex == DUPLEX_FULL) {
3884 bmcr |= BMCR_FULLDPLX;
3885 tp->ups_info.speed_duplex = FORCE_10M_FULL;
3886 } else {
3887 tp->ups_info.speed_duplex = FORCE_10M_HALF;
3888 }
3889 break;
3890 case SPEED_100:
3891 bmcr = BMCR_SPEED100;
3892 if (duplex == DUPLEX_FULL) {
3893 bmcr |= BMCR_FULLDPLX;
3894 tp->ups_info.speed_duplex = FORCE_100M_FULL;
3895 } else {
3896 tp->ups_info.speed_duplex = FORCE_100M_HALF;
3897 }
3898 break;
3899 case SPEED_1000:
3900 if (tp->mii.supports_gmii) {
3901 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
3902 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
3903 break;
3904 }
3905
3906 default:
3907 ret = -EINVAL;
3908 goto out;
3909 }
3910
3911 if (duplex == DUPLEX_FULL)
3912 tp->mii.full_duplex = 1;
3913 else
3914 tp->mii.full_duplex = 0;
3915
3916 tp->mii.force_media = 1;
3917 } else {
3918 u16 anar, tmp1;
3919 u32 support;
3920
3921 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
3922 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
3923
3924 if (tp->mii.supports_gmii)
3925 support |= RTL_ADVERTISED_1000_FULL;
3926
3927 if (!(advertising & support))
3928 return -EINVAL;
3929
3930 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3931 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3932 ADVERTISE_100HALF | ADVERTISE_100FULL);
3933 if (advertising & RTL_ADVERTISED_10_HALF) {
3934 tmp1 |= ADVERTISE_10HALF;
3935 tp->ups_info.speed_duplex = NWAY_10M_HALF;
3936 }
3937 if (advertising & RTL_ADVERTISED_10_FULL) {
3938 tmp1 |= ADVERTISE_10FULL;
3939 tp->ups_info.speed_duplex = NWAY_10M_FULL;
3940 }
3941
3942 if (advertising & RTL_ADVERTISED_100_HALF) {
3943 tmp1 |= ADVERTISE_100HALF;
3944 tp->ups_info.speed_duplex = NWAY_100M_HALF;
3945 }
3946 if (advertising & RTL_ADVERTISED_100_FULL) {
3947 tmp1 |= ADVERTISE_100FULL;
3948 tp->ups_info.speed_duplex = NWAY_100M_FULL;
3949 }
3950
3951 if (anar != tmp1) {
3952 r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
3953 tp->mii.advertising = tmp1;
3954 }
3955
3956 if (tp->mii.supports_gmii) {
3957 u16 gbcr;
3958
3959 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3960 tmp1 = gbcr & ~(ADVERTISE_1000FULL |
3961 ADVERTISE_1000HALF);
3962
3963 if (advertising & RTL_ADVERTISED_1000_FULL) {
3964 tmp1 |= ADVERTISE_1000FULL;
3965 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
3966 }
3967
3968 if (gbcr != tmp1)
3969 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
3970 }
3971
3972 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3973
3974 tp->mii.force_media = 0;
3975 }
3976
3977 if (test_and_clear_bit(PHY_RESET, &tp->flags))
3978 bmcr |= BMCR_RESET;
3979
3980 r8152_mdio_write(tp, MII_BMCR, bmcr);
3981
3982 if (bmcr & BMCR_RESET) {
3983 int i;
3984
3985 for (i = 0; i < 50; i++) {
3986 msleep(20);
3987 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3988 break;
3989 }
3990 }
3991
3992 out:
3993 return ret;
3994 }
3995
3996 static void rtl8152_up(struct r8152 *tp)
3997 {
3998 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3999 return;
4000
4001 r8152_aldps_en(tp, false);
4002 r8152b_exit_oob(tp);
4003 r8152_aldps_en(tp, true);
4004 }
4005
4006 static void rtl8152_down(struct r8152 *tp)
4007 {
4008 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4009 rtl_drop_queued_tx(tp);
4010 return;
4011 }
4012
4013 r8152_power_cut_en(tp, false);
4014 r8152_aldps_en(tp, false);
4015 r8152b_enter_oob(tp);
4016 r8152_aldps_en(tp, true);
4017 }
4018
4019 static void rtl8153_up(struct r8152 *tp)
4020 {
4021 u32 ocp_data;
4022
4023 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4024 return;
4025
4026 r8153_u1u2en(tp, false);
4027 r8153_u2p3en(tp, false);
4028 r8153_aldps_en(tp, false);
4029 r8153_first_init(tp);
4030
4031 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4032 ocp_data |= LANWAKE_CLR_EN;
4033 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4034
4035 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
4036 ocp_data &= ~LANWAKE_PIN;
4037 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
4038
4039 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
4040 ocp_data &= ~DELAY_PHY_PWR_CHG;
4041 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
4042
4043 r8153_aldps_en(tp, true);
4044
4045 switch (tp->version) {
4046 case RTL_VER_03:
4047 case RTL_VER_04:
4048 break;
4049 case RTL_VER_05:
4050 case RTL_VER_06:
4051 default:
4052 r8153_u2p3en(tp, true);
4053 break;
4054 }
4055
4056 r8153_u1u2en(tp, true);
4057 }
4058
4059 static void rtl8153_down(struct r8152 *tp)
4060 {
4061 u32 ocp_data;
4062
4063 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4064 rtl_drop_queued_tx(tp);
4065 return;
4066 }
4067
4068 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4069 ocp_data &= ~LANWAKE_CLR_EN;
4070 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4071
4072 r8153_u1u2en(tp, false);
4073 r8153_u2p3en(tp, false);
4074 r8153_power_cut_en(tp, false);
4075 r8153_aldps_en(tp, false);
4076 r8153_enter_oob(tp);
4077 r8153_aldps_en(tp, true);
4078 }
4079
4080 static void rtl8153b_up(struct r8152 *tp)
4081 {
4082 u32 ocp_data;
4083
4084 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4085 return;
4086
4087 r8153b_u1u2en(tp, false);
4088 r8153_u2p3en(tp, false);
4089 r8153_aldps_en(tp, false);
4090
4091 r8153_first_init(tp);
4092 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
4093
4094 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
4095 ocp_data &= ~PLA_MCU_SPDWN_EN;
4096 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
4097
4098 r8153_aldps_en(tp, true);
4099 r8153b_u1u2en(tp, true);
4100 }
4101
4102 static void rtl8153b_down(struct r8152 *tp)
4103 {
4104 u32 ocp_data;
4105
4106 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4107 rtl_drop_queued_tx(tp);
4108 return;
4109 }
4110
4111 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
4112 ocp_data |= PLA_MCU_SPDWN_EN;
4113 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
4114
4115 r8153b_u1u2en(tp, false);
4116 r8153_u2p3en(tp, false);
4117 r8153b_power_cut_en(tp, false);
4118 r8153_aldps_en(tp, false);
4119 r8153_enter_oob(tp);
4120 r8153_aldps_en(tp, true);
4121 }
4122
4123 static bool rtl8152_in_nway(struct r8152 *tp)
4124 {
4125 u16 nway_state;
4126
4127 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
4128 tp->ocp_base = 0x2000;
4129 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);
4130 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
4131
4132
4133 if (nway_state & 0xc000)
4134 return false;
4135 else
4136 return true;
4137 }
4138
4139 static bool rtl8153_in_nway(struct r8152 *tp)
4140 {
4141 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
4142
4143 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
4144 return false;
4145 else
4146 return true;
4147 }
4148
4149 static void set_carrier(struct r8152 *tp)
4150 {
4151 struct net_device *netdev = tp->netdev;
4152 struct napi_struct *napi = &tp->napi;
4153 u8 speed;
4154
4155 speed = rtl8152_get_speed(tp);
4156
4157 if (speed & LINK_STATUS) {
4158 if (!netif_carrier_ok(netdev)) {
4159 tp->rtl_ops.enable(tp);
4160 netif_stop_queue(netdev);
4161 napi_disable(napi);
4162 netif_carrier_on(netdev);
4163 rtl_start_rx(tp);
4164 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
4165 _rtl8152_set_rx_mode(netdev);
4166 napi_enable(&tp->napi);
4167 netif_wake_queue(netdev);
4168 netif_info(tp, link, netdev, "carrier on\n");
4169 } else if (netif_queue_stopped(netdev) &&
4170 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
4171 netif_wake_queue(netdev);
4172 }
4173 } else {
4174 if (netif_carrier_ok(netdev)) {
4175 netif_carrier_off(netdev);
4176 tasklet_disable(&tp->tx_tl);
4177 napi_disable(napi);
4178 tp->rtl_ops.disable(tp);
4179 napi_enable(napi);
4180 tasklet_enable(&tp->tx_tl);
4181 netif_info(tp, link, netdev, "carrier off\n");
4182 }
4183 }
4184 }
4185
4186 static void rtl_work_func_t(struct work_struct *work)
4187 {
4188 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
4189
4190
4191
4192
4193 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
4194 return;
4195
4196 if (usb_autopm_get_interface(tp->intf) < 0)
4197 return;
4198
4199 if (!test_bit(WORK_ENABLE, &tp->flags))
4200 goto out1;
4201
4202 if (!mutex_trylock(&tp->control)) {
4203 schedule_delayed_work(&tp->schedule, 0);
4204 goto out1;
4205 }
4206
4207 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
4208 set_carrier(tp);
4209
4210 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
4211 _rtl8152_set_rx_mode(tp->netdev);
4212
4213
4214 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
4215 netif_carrier_ok(tp->netdev))
4216 tasklet_schedule(&tp->tx_tl);
4217
4218 mutex_unlock(&tp->control);
4219
4220 out1:
4221 usb_autopm_put_interface(tp->intf);
4222 }
4223
4224 static void rtl_hw_phy_work_func_t(struct work_struct *work)
4225 {
4226 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
4227
4228 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4229 return;
4230
4231 if (usb_autopm_get_interface(tp->intf) < 0)
4232 return;
4233
4234 mutex_lock(&tp->control);
4235
4236 tp->rtl_ops.hw_phy_cfg(tp);
4237
4238 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
4239 tp->advertising);
4240
4241 mutex_unlock(&tp->control);
4242
4243 usb_autopm_put_interface(tp->intf);
4244 }
4245
4246 #ifdef CONFIG_PM_SLEEP
4247 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
4248 void *data)
4249 {
4250 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
4251
4252 switch (action) {
4253 case PM_HIBERNATION_PREPARE:
4254 case PM_SUSPEND_PREPARE:
4255 usb_autopm_get_interface(tp->intf);
4256 break;
4257
4258 case PM_POST_HIBERNATION:
4259 case PM_POST_SUSPEND:
4260 usb_autopm_put_interface(tp->intf);
4261 break;
4262
4263 case PM_POST_RESTORE:
4264 case PM_RESTORE_PREPARE:
4265 default:
4266 break;
4267 }
4268
4269 return NOTIFY_DONE;
4270 }
4271 #endif
4272
4273 static int rtl8152_open(struct net_device *netdev)
4274 {
4275 struct r8152 *tp = netdev_priv(netdev);
4276 int res = 0;
4277
4278 res = alloc_all_mem(tp);
4279 if (res)
4280 goto out;
4281
4282 res = usb_autopm_get_interface(tp->intf);
4283 if (res < 0)
4284 goto out_free;
4285
4286 mutex_lock(&tp->control);
4287
4288 tp->rtl_ops.up(tp);
4289
4290 netif_carrier_off(netdev);
4291 netif_start_queue(netdev);
4292 set_bit(WORK_ENABLE, &tp->flags);
4293
4294 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4295 if (res) {
4296 if (res == -ENODEV)
4297 netif_device_detach(tp->netdev);
4298 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
4299 res);
4300 goto out_unlock;
4301 }
4302 napi_enable(&tp->napi);
4303 tasklet_enable(&tp->tx_tl);
4304
4305 mutex_unlock(&tp->control);
4306
4307 usb_autopm_put_interface(tp->intf);
4308 #ifdef CONFIG_PM_SLEEP
4309 tp->pm_notifier.notifier_call = rtl_notifier;
4310 register_pm_notifier(&tp->pm_notifier);
4311 #endif
4312 return 0;
4313
4314 out_unlock:
4315 mutex_unlock(&tp->control);
4316 usb_autopm_put_interface(tp->intf);
4317 out_free:
4318 free_all_mem(tp);
4319 out:
4320 return res;
4321 }
4322
4323 static int rtl8152_close(struct net_device *netdev)
4324 {
4325 struct r8152 *tp = netdev_priv(netdev);
4326 int res = 0;
4327
4328 #ifdef CONFIG_PM_SLEEP
4329 unregister_pm_notifier(&tp->pm_notifier);
4330 #endif
4331 tasklet_disable(&tp->tx_tl);
4332 clear_bit(WORK_ENABLE, &tp->flags);
4333 usb_kill_urb(tp->intr_urb);
4334 cancel_delayed_work_sync(&tp->schedule);
4335 napi_disable(&tp->napi);
4336 netif_stop_queue(netdev);
4337
4338 res = usb_autopm_get_interface(tp->intf);
4339 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
4340 rtl_drop_queued_tx(tp);
4341 rtl_stop_rx(tp);
4342 } else {
4343 mutex_lock(&tp->control);
4344
4345 tp->rtl_ops.down(tp);
4346
4347 mutex_unlock(&tp->control);
4348
4349 usb_autopm_put_interface(tp->intf);
4350 }
4351
4352 free_all_mem(tp);
4353
4354 return res;
4355 }
4356
4357 static void rtl_tally_reset(struct r8152 *tp)
4358 {
4359 u32 ocp_data;
4360
4361 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
4362 ocp_data |= TALLY_RESET;
4363 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
4364 }
4365
4366 static void r8152b_init(struct r8152 *tp)
4367 {
4368 u32 ocp_data;
4369 u16 data;
4370
4371 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4372 return;
4373
4374 data = r8152_mdio_read(tp, MII_BMCR);
4375 if (data & BMCR_PDOWN) {
4376 data &= ~BMCR_PDOWN;
4377 r8152_mdio_write(tp, MII_BMCR, data);
4378 }
4379
4380 r8152_aldps_en(tp, false);
4381
4382 if (tp->version == RTL_VER_01) {
4383 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4384 ocp_data &= ~LED_MODE_MASK;
4385 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4386 }
4387
4388 r8152_power_cut_en(tp, false);
4389
4390 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4391 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4392 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4393 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4394 ocp_data &= ~MCU_CLK_RATIO_MASK;
4395 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4396 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4397 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4398 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4399 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4400
4401 rtl_tally_reset(tp);
4402
4403
4404 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4405 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4406 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4407 }
4408
4409 static void r8153_init(struct r8152 *tp)
4410 {
4411 u32 ocp_data;
4412 u16 data;
4413 int i;
4414
4415 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4416 return;
4417
4418 r8153_u1u2en(tp, false);
4419
4420 for (i = 0; i < 500; i++) {
4421 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4422 AUTOLOAD_DONE)
4423 break;
4424
4425 msleep(20);
4426 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4427 break;
4428 }
4429
4430 data = r8153_phy_status(tp, 0);
4431
4432 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4433 tp->version == RTL_VER_05)
4434 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4435
4436 data = r8152_mdio_read(tp, MII_BMCR);
4437 if (data & BMCR_PDOWN) {
4438 data &= ~BMCR_PDOWN;
4439 r8152_mdio_write(tp, MII_BMCR, data);
4440 }
4441
4442 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4443
4444 r8153_u2p3en(tp, false);
4445
4446 if (tp->version == RTL_VER_04) {
4447 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4448 ocp_data &= ~pwd_dn_scale_mask;
4449 ocp_data |= pwd_dn_scale(96);
4450 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4451
4452 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4453 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4454 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4455 } else if (tp->version == RTL_VER_05) {
4456 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4457 ocp_data &= ~ECM_ALDPS;
4458 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4459
4460 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4461 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4462 ocp_data &= ~DYNAMIC_BURST;
4463 else
4464 ocp_data |= DYNAMIC_BURST;
4465 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4466 } else if (tp->version == RTL_VER_06) {
4467 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4468 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4469 ocp_data &= ~DYNAMIC_BURST;
4470 else
4471 ocp_data |= DYNAMIC_BURST;
4472 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4473 }
4474
4475 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4476 ocp_data |= EP4_FULL_FC;
4477 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4478
4479 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4480 ocp_data &= ~TIMER11_EN;
4481 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4482
4483 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4484 ocp_data &= ~LED_MODE_MASK;
4485 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4486
4487 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4488 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4489 ocp_data |= LPM_TIMER_500MS;
4490 else
4491 ocp_data |= LPM_TIMER_500US;
4492 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4493
4494 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4495 ocp_data &= ~SEN_VAL_MASK;
4496 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4497 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4498
4499 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4500
4501 r8153_power_cut_en(tp, false);
4502 r8153_u1u2en(tp, true);
4503 r8153_mac_clk_spd(tp, false);
4504 usb_enable_lpm(tp->udev);
4505
4506 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4507 ocp_data |= LANWAKE_CLR_EN;
4508 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4509
4510 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
4511 ocp_data &= ~LANWAKE_PIN;
4512 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
4513
4514
4515 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4516 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4517 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
4518 ocp_data |= RX_AGG_DISABLE;
4519
4520 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4521
4522 rtl_tally_reset(tp);
4523
4524 switch (tp->udev->speed) {
4525 case USB_SPEED_SUPER:
4526 case USB_SPEED_SUPER_PLUS:
4527 tp->coalesce = COALESCE_SUPER;
4528 break;
4529 case USB_SPEED_HIGH:
4530 tp->coalesce = COALESCE_HIGH;
4531 break;
4532 default:
4533 tp->coalesce = COALESCE_SLOW;
4534 break;
4535 }
4536 }
4537
4538 static void r8153b_init(struct r8152 *tp)
4539 {
4540 u32 ocp_data;
4541 u16 data;
4542 int i;
4543
4544 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4545 return;
4546
4547 r8153b_u1u2en(tp, false);
4548
4549 for (i = 0; i < 500; i++) {
4550 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4551 AUTOLOAD_DONE)
4552 break;
4553
4554 msleep(20);
4555 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4556 break;
4557 }
4558
4559 data = r8153_phy_status(tp, 0);
4560
4561 data = r8152_mdio_read(tp, MII_BMCR);
4562 if (data & BMCR_PDOWN) {
4563 data &= ~BMCR_PDOWN;
4564 r8152_mdio_write(tp, MII_BMCR, data);
4565 }
4566
4567 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4568
4569 r8153_u2p3en(tp, false);
4570
4571
4572 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4573
4574
4575 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4576
4577 r8153b_power_cut_en(tp, false);
4578 r8153b_ups_en(tp, false);
4579 r8153_queue_wake(tp, false);
4580 rtl_runtime_suspend_enable(tp, false);
4581 r8153b_u1u2en(tp, true);
4582 usb_enable_lpm(tp->udev);
4583
4584
4585 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4586 ocp_data |= MAC_CLK_SPDWN_EN;
4587 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4588
4589 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
4590 ocp_data &= ~PLA_MCU_SPDWN_EN;
4591 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
4592
4593 if (tp->version == RTL_VER_09) {
4594
4595 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
4596 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4597 ocp_data |= TEST_IO_OFF;
4598 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4599 }
4600 }
4601
4602 set_bit(GREEN_ETHERNET, &tp->flags);
4603
4604
4605 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4606 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4607 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4608
4609 rtl_tally_reset(tp);
4610
4611 tp->coalesce = 15000;
4612 }
4613
4614 static int rtl8152_pre_reset(struct usb_interface *intf)
4615 {
4616 struct r8152 *tp = usb_get_intfdata(intf);
4617 struct net_device *netdev;
4618
4619 if (!tp)
4620 return 0;
4621
4622 netdev = tp->netdev;
4623 if (!netif_running(netdev))
4624 return 0;
4625
4626 netif_stop_queue(netdev);
4627 tasklet_disable(&tp->tx_tl);
4628 clear_bit(WORK_ENABLE, &tp->flags);
4629 usb_kill_urb(tp->intr_urb);
4630 cancel_delayed_work_sync(&tp->schedule);
4631 napi_disable(&tp->napi);
4632 if (netif_carrier_ok(netdev)) {
4633 mutex_lock(&tp->control);
4634 tp->rtl_ops.disable(tp);
4635 mutex_unlock(&tp->control);
4636 }
4637
4638 return 0;
4639 }
4640
4641 static int rtl8152_post_reset(struct usb_interface *intf)
4642 {
4643 struct r8152 *tp = usb_get_intfdata(intf);
4644 struct net_device *netdev;
4645 struct sockaddr sa;
4646
4647 if (!tp)
4648 return 0;
4649
4650
4651 if (determine_ethernet_addr(tp, &sa) >= 0) {
4652 rtnl_lock();
4653 dev_set_mac_address (tp->netdev, &sa, NULL);
4654 rtnl_unlock();
4655 }
4656
4657 netdev = tp->netdev;
4658 if (!netif_running(netdev))
4659 return 0;
4660
4661 set_bit(WORK_ENABLE, &tp->flags);
4662 if (netif_carrier_ok(netdev)) {
4663 mutex_lock(&tp->control);
4664 tp->rtl_ops.enable(tp);
4665 rtl_start_rx(tp);
4666 _rtl8152_set_rx_mode(netdev);
4667 mutex_unlock(&tp->control);
4668 }
4669
4670 napi_enable(&tp->napi);
4671 tasklet_enable(&tp->tx_tl);
4672 netif_wake_queue(netdev);
4673 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4674
4675 if (!list_empty(&tp->rx_done))
4676 napi_schedule(&tp->napi);
4677
4678 return 0;
4679 }
4680
4681 static bool delay_autosuspend(struct r8152 *tp)
4682 {
4683 bool sw_linking = !!netif_carrier_ok(tp->netdev);
4684 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4685
4686
4687
4688
4689
4690 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4691 return true;
4692
4693
4694
4695
4696 if (!sw_linking && tp->rtl_ops.in_nway(tp))
4697 return true;
4698 else if (!skb_queue_empty(&tp->tx_queue))
4699 return true;
4700 else
4701 return false;
4702 }
4703
4704 static int rtl8152_runtime_resume(struct r8152 *tp)
4705 {
4706 struct net_device *netdev = tp->netdev;
4707
4708 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4709 struct napi_struct *napi = &tp->napi;
4710
4711 tp->rtl_ops.autosuspend_en(tp, false);
4712 napi_disable(napi);
4713 set_bit(WORK_ENABLE, &tp->flags);
4714
4715 if (netif_carrier_ok(netdev)) {
4716 if (rtl8152_get_speed(tp) & LINK_STATUS) {
4717 rtl_start_rx(tp);
4718 } else {
4719 netif_carrier_off(netdev);
4720 tp->rtl_ops.disable(tp);
4721 netif_info(tp, link, netdev, "linking down\n");
4722 }
4723 }
4724
4725 napi_enable(napi);
4726 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4727 smp_mb__after_atomic();
4728
4729 if (!list_empty(&tp->rx_done))
4730 napi_schedule(&tp->napi);
4731
4732 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4733 } else {
4734 if (netdev->flags & IFF_UP)
4735 tp->rtl_ops.autosuspend_en(tp, false);
4736
4737 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4738 }
4739
4740 return 0;
4741 }
4742
4743 static int rtl8152_system_resume(struct r8152 *tp)
4744 {
4745 struct net_device *netdev = tp->netdev;
4746
4747 netif_device_attach(netdev);
4748
4749 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
4750 tp->rtl_ops.up(tp);
4751 netif_carrier_off(netdev);
4752 set_bit(WORK_ENABLE, &tp->flags);
4753 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4754 }
4755
4756 return 0;
4757 }
4758
4759 static int rtl8152_runtime_suspend(struct r8152 *tp)
4760 {
4761 struct net_device *netdev = tp->netdev;
4762 int ret = 0;
4763
4764 set_bit(SELECTIVE_SUSPEND, &tp->flags);
4765 smp_mb__after_atomic();
4766
4767 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4768 u32 rcr = 0;
4769
4770 if (netif_carrier_ok(netdev)) {
4771 u32 ocp_data;
4772
4773 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4774 ocp_data = rcr & ~RCR_ACPT_ALL;
4775 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4776 rxdy_gated_en(tp, true);
4777 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4778 PLA_OOB_CTRL);
4779 if (!(ocp_data & RXFIFO_EMPTY)) {
4780 rxdy_gated_en(tp, false);
4781 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4782 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4783 smp_mb__after_atomic();
4784 ret = -EBUSY;
4785 goto out1;
4786 }
4787 }
4788
4789 clear_bit(WORK_ENABLE, &tp->flags);
4790 usb_kill_urb(tp->intr_urb);
4791
4792 tp->rtl_ops.autosuspend_en(tp, true);
4793
4794 if (netif_carrier_ok(netdev)) {
4795 struct napi_struct *napi = &tp->napi;
4796
4797 napi_disable(napi);
4798 rtl_stop_rx(tp);
4799 rxdy_gated_en(tp, false);
4800 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4801 napi_enable(napi);
4802 }
4803
4804 if (delay_autosuspend(tp)) {
4805 rtl8152_runtime_resume(tp);
4806 ret = -EBUSY;
4807 }
4808 }
4809
4810 out1:
4811 return ret;
4812 }
4813
4814 static int rtl8152_system_suspend(struct r8152 *tp)
4815 {
4816 struct net_device *netdev = tp->netdev;
4817
4818 netif_device_detach(netdev);
4819
4820 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4821 struct napi_struct *napi = &tp->napi;
4822
4823 clear_bit(WORK_ENABLE, &tp->flags);
4824 usb_kill_urb(tp->intr_urb);
4825 tasklet_disable(&tp->tx_tl);
4826 napi_disable(napi);
4827 cancel_delayed_work_sync(&tp->schedule);
4828 tp->rtl_ops.down(tp);
4829 napi_enable(napi);
4830 tasklet_enable(&tp->tx_tl);
4831 }
4832
4833 return 0;
4834 }
4835
4836 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4837 {
4838 struct r8152 *tp = usb_get_intfdata(intf);
4839 int ret;
4840
4841 mutex_lock(&tp->control);
4842
4843 if (PMSG_IS_AUTO(message))
4844 ret = rtl8152_runtime_suspend(tp);
4845 else
4846 ret = rtl8152_system_suspend(tp);
4847
4848 mutex_unlock(&tp->control);
4849
4850 return ret;
4851 }
4852
4853 static int rtl8152_resume(struct usb_interface *intf)
4854 {
4855 struct r8152 *tp = usb_get_intfdata(intf);
4856 int ret;
4857
4858 mutex_lock(&tp->control);
4859
4860 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4861 ret = rtl8152_runtime_resume(tp);
4862 else
4863 ret = rtl8152_system_resume(tp);
4864
4865 mutex_unlock(&tp->control);
4866
4867 return ret;
4868 }
4869
4870 static int rtl8152_reset_resume(struct usb_interface *intf)
4871 {
4872 struct r8152 *tp = usb_get_intfdata(intf);
4873
4874 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4875 tp->rtl_ops.init(tp);
4876 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4877 set_ethernet_addr(tp);
4878 return rtl8152_resume(intf);
4879 }
4880
4881 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4882 {
4883 struct r8152 *tp = netdev_priv(dev);
4884
4885 if (usb_autopm_get_interface(tp->intf) < 0)
4886 return;
4887
4888 if (!rtl_can_wakeup(tp)) {
4889 wol->supported = 0;
4890 wol->wolopts = 0;
4891 } else {
4892 mutex_lock(&tp->control);
4893 wol->supported = WAKE_ANY;
4894 wol->wolopts = __rtl_get_wol(tp);
4895 mutex_unlock(&tp->control);
4896 }
4897
4898 usb_autopm_put_interface(tp->intf);
4899 }
4900
4901 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4902 {
4903 struct r8152 *tp = netdev_priv(dev);
4904 int ret;
4905
4906 if (!rtl_can_wakeup(tp))
4907 return -EOPNOTSUPP;
4908
4909 if (wol->wolopts & ~WAKE_ANY)
4910 return -EINVAL;
4911
4912 ret = usb_autopm_get_interface(tp->intf);
4913 if (ret < 0)
4914 goto out_set_wol;
4915
4916 mutex_lock(&tp->control);
4917
4918 __rtl_set_wol(tp, wol->wolopts);
4919 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4920
4921 mutex_unlock(&tp->control);
4922
4923 usb_autopm_put_interface(tp->intf);
4924
4925 out_set_wol:
4926 return ret;
4927 }
4928
4929 static u32 rtl8152_get_msglevel(struct net_device *dev)
4930 {
4931 struct r8152 *tp = netdev_priv(dev);
4932
4933 return tp->msg_enable;
4934 }
4935
4936 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4937 {
4938 struct r8152 *tp = netdev_priv(dev);
4939
4940 tp->msg_enable = value;
4941 }
4942
4943 static void rtl8152_get_drvinfo(struct net_device *netdev,
4944 struct ethtool_drvinfo *info)
4945 {
4946 struct r8152 *tp = netdev_priv(netdev);
4947
4948 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4949 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4950 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4951 }
4952
4953 static
4954 int rtl8152_get_link_ksettings(struct net_device *netdev,
4955 struct ethtool_link_ksettings *cmd)
4956 {
4957 struct r8152 *tp = netdev_priv(netdev);
4958 int ret;
4959
4960 if (!tp->mii.mdio_read)
4961 return -EOPNOTSUPP;
4962
4963 ret = usb_autopm_get_interface(tp->intf);
4964 if (ret < 0)
4965 goto out;
4966
4967 mutex_lock(&tp->control);
4968
4969 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4970
4971 mutex_unlock(&tp->control);
4972
4973 usb_autopm_put_interface(tp->intf);
4974
4975 out:
4976 return ret;
4977 }
4978
4979 static int rtl8152_set_link_ksettings(struct net_device *dev,
4980 const struct ethtool_link_ksettings *cmd)
4981 {
4982 struct r8152 *tp = netdev_priv(dev);
4983 u32 advertising = 0;
4984 int ret;
4985
4986 ret = usb_autopm_get_interface(tp->intf);
4987 if (ret < 0)
4988 goto out;
4989
4990 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
4991 cmd->link_modes.advertising))
4992 advertising |= RTL_ADVERTISED_10_HALF;
4993
4994 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
4995 cmd->link_modes.advertising))
4996 advertising |= RTL_ADVERTISED_10_FULL;
4997
4998 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
4999 cmd->link_modes.advertising))
5000 advertising |= RTL_ADVERTISED_100_HALF;
5001
5002 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5003 cmd->link_modes.advertising))
5004 advertising |= RTL_ADVERTISED_100_FULL;
5005
5006 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5007 cmd->link_modes.advertising))
5008 advertising |= RTL_ADVERTISED_1000_HALF;
5009
5010 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
5011 cmd->link_modes.advertising))
5012 advertising |= RTL_ADVERTISED_1000_FULL;
5013
5014 mutex_lock(&tp->control);
5015
5016 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
5017 cmd->base.duplex, advertising);
5018 if (!ret) {
5019 tp->autoneg = cmd->base.autoneg;
5020 tp->speed = cmd->base.speed;
5021 tp->duplex = cmd->base.duplex;
5022 tp->advertising = advertising;
5023 }
5024
5025 mutex_unlock(&tp->control);
5026
5027 usb_autopm_put_interface(tp->intf);
5028
5029 out:
5030 return ret;
5031 }
5032
5033 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
5034 "tx_packets",
5035 "rx_packets",
5036 "tx_errors",
5037 "rx_errors",
5038 "rx_missed",
5039 "align_errors",
5040 "tx_single_collisions",
5041 "tx_multi_collisions",
5042 "rx_unicast",
5043 "rx_broadcast",
5044 "rx_multicast",
5045 "tx_aborted",
5046 "tx_underrun",
5047 };
5048
5049 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
5050 {
5051 switch (sset) {
5052 case ETH_SS_STATS:
5053 return ARRAY_SIZE(rtl8152_gstrings);
5054 default:
5055 return -EOPNOTSUPP;
5056 }
5057 }
5058
5059 static void rtl8152_get_ethtool_stats(struct net_device *dev,
5060 struct ethtool_stats *stats, u64 *data)
5061 {
5062 struct r8152 *tp = netdev_priv(dev);
5063 struct tally_counter tally;
5064
5065 if (usb_autopm_get_interface(tp->intf) < 0)
5066 return;
5067
5068 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
5069
5070 usb_autopm_put_interface(tp->intf);
5071
5072 data[0] = le64_to_cpu(tally.tx_packets);
5073 data[1] = le64_to_cpu(tally.rx_packets);
5074 data[2] = le64_to_cpu(tally.tx_errors);
5075 data[3] = le32_to_cpu(tally.rx_errors);
5076 data[4] = le16_to_cpu(tally.rx_missed);
5077 data[5] = le16_to_cpu(tally.align_errors);
5078 data[6] = le32_to_cpu(tally.tx_one_collision);
5079 data[7] = le32_to_cpu(tally.tx_multi_collision);
5080 data[8] = le64_to_cpu(tally.rx_unicast);
5081 data[9] = le64_to_cpu(tally.rx_broadcast);
5082 data[10] = le32_to_cpu(tally.rx_multicast);
5083 data[11] = le16_to_cpu(tally.tx_aborted);
5084 data[12] = le16_to_cpu(tally.tx_underrun);
5085 }
5086
5087 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5088 {
5089 switch (stringset) {
5090 case ETH_SS_STATS:
5091 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
5092 break;
5093 }
5094 }
5095
5096 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
5097 {
5098 u32 lp, adv, supported = 0;
5099 u16 val;
5100
5101 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
5102 supported = mmd_eee_cap_to_ethtool_sup_t(val);
5103
5104 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
5105 adv = mmd_eee_adv_to_ethtool_adv_t(val);
5106
5107 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
5108 lp = mmd_eee_adv_to_ethtool_adv_t(val);
5109
5110 eee->eee_enabled = tp->eee_en;
5111 eee->eee_active = !!(supported & adv & lp);
5112 eee->supported = supported;
5113 eee->advertised = tp->eee_adv;
5114 eee->lp_advertised = lp;
5115
5116 return 0;
5117 }
5118
5119 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
5120 {
5121 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
5122
5123 tp->eee_en = eee->eee_enabled;
5124 tp->eee_adv = val;
5125
5126 rtl_eee_enable(tp, tp->eee_en);
5127
5128 return 0;
5129 }
5130
5131 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
5132 {
5133 u32 lp, adv, supported = 0;
5134 u16 val;
5135
5136 val = ocp_reg_read(tp, OCP_EEE_ABLE);
5137 supported = mmd_eee_cap_to_ethtool_sup_t(val);
5138
5139 val = ocp_reg_read(tp, OCP_EEE_ADV);
5140 adv = mmd_eee_adv_to_ethtool_adv_t(val);
5141
5142 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
5143 lp = mmd_eee_adv_to_ethtool_adv_t(val);
5144
5145 eee->eee_enabled = tp->eee_en;
5146 eee->eee_active = !!(supported & adv & lp);
5147 eee->supported = supported;
5148 eee->advertised = tp->eee_adv;
5149 eee->lp_advertised = lp;
5150
5151 return 0;
5152 }
5153
5154 static int
5155 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
5156 {
5157 struct r8152 *tp = netdev_priv(net);
5158 int ret;
5159
5160 ret = usb_autopm_get_interface(tp->intf);
5161 if (ret < 0)
5162 goto out;
5163
5164 mutex_lock(&tp->control);
5165
5166 ret = tp->rtl_ops.eee_get(tp, edata);
5167
5168 mutex_unlock(&tp->control);
5169
5170 usb_autopm_put_interface(tp->intf);
5171
5172 out:
5173 return ret;
5174 }
5175
5176 static int
5177 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
5178 {
5179 struct r8152 *tp = netdev_priv(net);
5180 int ret;
5181
5182 ret = usb_autopm_get_interface(tp->intf);
5183 if (ret < 0)
5184 goto out;
5185
5186 mutex_lock(&tp->control);
5187
5188 ret = tp->rtl_ops.eee_set(tp, edata);
5189 if (!ret)
5190 ret = mii_nway_restart(&tp->mii);
5191
5192 mutex_unlock(&tp->control);
5193
5194 usb_autopm_put_interface(tp->intf);
5195
5196 out:
5197 return ret;
5198 }
5199
5200 static int rtl8152_nway_reset(struct net_device *dev)
5201 {
5202 struct r8152 *tp = netdev_priv(dev);
5203 int ret;
5204
5205 ret = usb_autopm_get_interface(tp->intf);
5206 if (ret < 0)
5207 goto out;
5208
5209 mutex_lock(&tp->control);
5210
5211 ret = mii_nway_restart(&tp->mii);
5212
5213 mutex_unlock(&tp->control);
5214
5215 usb_autopm_put_interface(tp->intf);
5216
5217 out:
5218 return ret;
5219 }
5220
5221 static int rtl8152_get_coalesce(struct net_device *netdev,
5222 struct ethtool_coalesce *coalesce)
5223 {
5224 struct r8152 *tp = netdev_priv(netdev);
5225
5226 switch (tp->version) {
5227 case RTL_VER_01:
5228 case RTL_VER_02:
5229 case RTL_VER_07:
5230 return -EOPNOTSUPP;
5231 default:
5232 break;
5233 }
5234
5235 coalesce->rx_coalesce_usecs = tp->coalesce;
5236
5237 return 0;
5238 }
5239
5240 static int rtl8152_set_coalesce(struct net_device *netdev,
5241 struct ethtool_coalesce *coalesce)
5242 {
5243 struct r8152 *tp = netdev_priv(netdev);
5244 int ret;
5245
5246 switch (tp->version) {
5247 case RTL_VER_01:
5248 case RTL_VER_02:
5249 case RTL_VER_07:
5250 return -EOPNOTSUPP;
5251 default:
5252 break;
5253 }
5254
5255 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
5256 return -EINVAL;
5257
5258 ret = usb_autopm_get_interface(tp->intf);
5259 if (ret < 0)
5260 return ret;
5261
5262 mutex_lock(&tp->control);
5263
5264 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
5265 tp->coalesce = coalesce->rx_coalesce_usecs;
5266
5267 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
5268 netif_stop_queue(netdev);
5269 napi_disable(&tp->napi);
5270 tp->rtl_ops.disable(tp);
5271 tp->rtl_ops.enable(tp);
5272 rtl_start_rx(tp);
5273 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5274 _rtl8152_set_rx_mode(netdev);
5275 napi_enable(&tp->napi);
5276 netif_wake_queue(netdev);
5277 }
5278 }
5279
5280 mutex_unlock(&tp->control);
5281
5282 usb_autopm_put_interface(tp->intf);
5283
5284 return ret;
5285 }
5286
5287 static int rtl8152_get_tunable(struct net_device *netdev,
5288 const struct ethtool_tunable *tunable, void *d)
5289 {
5290 struct r8152 *tp = netdev_priv(netdev);
5291
5292 switch (tunable->id) {
5293 case ETHTOOL_RX_COPYBREAK:
5294 *(u32 *)d = tp->rx_copybreak;
5295 break;
5296 default:
5297 return -EOPNOTSUPP;
5298 }
5299
5300 return 0;
5301 }
5302
5303 static int rtl8152_set_tunable(struct net_device *netdev,
5304 const struct ethtool_tunable *tunable,
5305 const void *d)
5306 {
5307 struct r8152 *tp = netdev_priv(netdev);
5308 u32 val;
5309
5310 switch (tunable->id) {
5311 case ETHTOOL_RX_COPYBREAK:
5312 val = *(u32 *)d;
5313 if (val < ETH_ZLEN) {
5314 netif_err(tp, rx_err, netdev,
5315 "Invalid rx copy break value\n");
5316 return -EINVAL;
5317 }
5318
5319 if (tp->rx_copybreak != val) {
5320 if (netdev->flags & IFF_UP) {
5321 mutex_lock(&tp->control);
5322 napi_disable(&tp->napi);
5323 tp->rx_copybreak = val;
5324 napi_enable(&tp->napi);
5325 mutex_unlock(&tp->control);
5326 } else {
5327 tp->rx_copybreak = val;
5328 }
5329 }
5330 break;
5331 default:
5332 return -EOPNOTSUPP;
5333 }
5334
5335 return 0;
5336 }
5337
5338 static void rtl8152_get_ringparam(struct net_device *netdev,
5339 struct ethtool_ringparam *ring)
5340 {
5341 struct r8152 *tp = netdev_priv(netdev);
5342
5343 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
5344 ring->rx_pending = tp->rx_pending;
5345 }
5346
5347 static int rtl8152_set_ringparam(struct net_device *netdev,
5348 struct ethtool_ringparam *ring)
5349 {
5350 struct r8152 *tp = netdev_priv(netdev);
5351
5352 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
5353 return -EINVAL;
5354
5355 if (tp->rx_pending != ring->rx_pending) {
5356 if (netdev->flags & IFF_UP) {
5357 mutex_lock(&tp->control);
5358 napi_disable(&tp->napi);
5359 tp->rx_pending = ring->rx_pending;
5360 napi_enable(&tp->napi);
5361 mutex_unlock(&tp->control);
5362 } else {
5363 tp->rx_pending = ring->rx_pending;
5364 }
5365 }
5366
5367 return 0;
5368 }
5369
5370 static const struct ethtool_ops ops = {
5371 .get_drvinfo = rtl8152_get_drvinfo,
5372 .get_link = ethtool_op_get_link,
5373 .nway_reset = rtl8152_nway_reset,
5374 .get_msglevel = rtl8152_get_msglevel,
5375 .set_msglevel = rtl8152_set_msglevel,
5376 .get_wol = rtl8152_get_wol,
5377 .set_wol = rtl8152_set_wol,
5378 .get_strings = rtl8152_get_strings,
5379 .get_sset_count = rtl8152_get_sset_count,
5380 .get_ethtool_stats = rtl8152_get_ethtool_stats,
5381 .get_coalesce = rtl8152_get_coalesce,
5382 .set_coalesce = rtl8152_set_coalesce,
5383 .get_eee = rtl_ethtool_get_eee,
5384 .set_eee = rtl_ethtool_set_eee,
5385 .get_link_ksettings = rtl8152_get_link_ksettings,
5386 .set_link_ksettings = rtl8152_set_link_ksettings,
5387 .get_tunable = rtl8152_get_tunable,
5388 .set_tunable = rtl8152_set_tunable,
5389 .get_ringparam = rtl8152_get_ringparam,
5390 .set_ringparam = rtl8152_set_ringparam,
5391 };
5392
5393 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
5394 {
5395 struct r8152 *tp = netdev_priv(netdev);
5396 struct mii_ioctl_data *data = if_mii(rq);
5397 int res;
5398
5399 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5400 return -ENODEV;
5401
5402 res = usb_autopm_get_interface(tp->intf);
5403 if (res < 0)
5404 goto out;
5405
5406 switch (cmd) {
5407 case SIOCGMIIPHY:
5408 data->phy_id = R8152_PHY_ID;
5409 break;
5410
5411 case SIOCGMIIREG:
5412 mutex_lock(&tp->control);
5413 data->val_out = r8152_mdio_read(tp, data->reg_num);
5414 mutex_unlock(&tp->control);
5415 break;
5416
5417 case SIOCSMIIREG:
5418 if (!capable(CAP_NET_ADMIN)) {
5419 res = -EPERM;
5420 break;
5421 }
5422 mutex_lock(&tp->control);
5423 r8152_mdio_write(tp, data->reg_num, data->val_in);
5424 mutex_unlock(&tp->control);
5425 break;
5426
5427 default:
5428 res = -EOPNOTSUPP;
5429 }
5430
5431 usb_autopm_put_interface(tp->intf);
5432
5433 out:
5434 return res;
5435 }
5436
5437 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
5438 {
5439 struct r8152 *tp = netdev_priv(dev);
5440 int ret;
5441
5442 switch (tp->version) {
5443 case RTL_VER_01:
5444 case RTL_VER_02:
5445 case RTL_VER_07:
5446 dev->mtu = new_mtu;
5447 return 0;
5448 default:
5449 break;
5450 }
5451
5452 ret = usb_autopm_get_interface(tp->intf);
5453 if (ret < 0)
5454 return ret;
5455
5456 mutex_lock(&tp->control);
5457
5458 dev->mtu = new_mtu;
5459
5460 if (netif_running(dev)) {
5461 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
5462
5463 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
5464
5465 if (netif_carrier_ok(dev))
5466 r8153_set_rx_early_size(tp);
5467 }
5468
5469 mutex_unlock(&tp->control);
5470
5471 usb_autopm_put_interface(tp->intf);
5472
5473 return ret;
5474 }
5475
5476 static const struct net_device_ops rtl8152_netdev_ops = {
5477 .ndo_open = rtl8152_open,
5478 .ndo_stop = rtl8152_close,
5479 .ndo_do_ioctl = rtl8152_ioctl,
5480 .ndo_start_xmit = rtl8152_start_xmit,
5481 .ndo_tx_timeout = rtl8152_tx_timeout,
5482 .ndo_set_features = rtl8152_set_features,
5483 .ndo_set_rx_mode = rtl8152_set_rx_mode,
5484 .ndo_set_mac_address = rtl8152_set_mac_address,
5485 .ndo_change_mtu = rtl8152_change_mtu,
5486 .ndo_validate_addr = eth_validate_addr,
5487 .ndo_features_check = rtl8152_features_check,
5488 };
5489
5490 static void rtl8152_unload(struct r8152 *tp)
5491 {
5492 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5493 return;
5494
5495 if (tp->version != RTL_VER_01)
5496 r8152_power_cut_en(tp, true);
5497 }
5498
5499 static void rtl8153_unload(struct r8152 *tp)
5500 {
5501 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5502 return;
5503
5504 r8153_power_cut_en(tp, false);
5505 }
5506
5507 static void rtl8153b_unload(struct r8152 *tp)
5508 {
5509 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5510 return;
5511
5512 r8153b_power_cut_en(tp, false);
5513 }
5514
5515 static int rtl_ops_init(struct r8152 *tp)
5516 {
5517 struct rtl_ops *ops = &tp->rtl_ops;
5518 int ret = 0;
5519
5520 switch (tp->version) {
5521 case RTL_VER_01:
5522 case RTL_VER_02:
5523 case RTL_VER_07:
5524 ops->init = r8152b_init;
5525 ops->enable = rtl8152_enable;
5526 ops->disable = rtl8152_disable;
5527 ops->up = rtl8152_up;
5528 ops->down = rtl8152_down;
5529 ops->unload = rtl8152_unload;
5530 ops->eee_get = r8152_get_eee;
5531 ops->eee_set = r8152_set_eee;
5532 ops->in_nway = rtl8152_in_nway;
5533 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
5534 ops->autosuspend_en = rtl_runtime_suspend_enable;
5535 tp->rx_buf_sz = 16 * 1024;
5536 tp->eee_en = true;
5537 tp->eee_adv = MDIO_EEE_100TX;
5538 break;
5539
5540 case RTL_VER_03:
5541 case RTL_VER_04:
5542 case RTL_VER_05:
5543 case RTL_VER_06:
5544 ops->init = r8153_init;
5545 ops->enable = rtl8153_enable;
5546 ops->disable = rtl8153_disable;
5547 ops->up = rtl8153_up;
5548 ops->down = rtl8153_down;
5549 ops->unload = rtl8153_unload;
5550 ops->eee_get = r8153_get_eee;
5551 ops->eee_set = r8152_set_eee;
5552 ops->in_nway = rtl8153_in_nway;
5553 ops->hw_phy_cfg = r8153_hw_phy_cfg;
5554 ops->autosuspend_en = rtl8153_runtime_enable;
5555 tp->rx_buf_sz = 32 * 1024;
5556 tp->eee_en = true;
5557 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
5558 break;
5559
5560 case RTL_VER_08:
5561 case RTL_VER_09:
5562 ops->init = r8153b_init;
5563 ops->enable = rtl8153_enable;
5564 ops->disable = rtl8153_disable;
5565 ops->up = rtl8153b_up;
5566 ops->down = rtl8153b_down;
5567 ops->unload = rtl8153b_unload;
5568 ops->eee_get = r8153_get_eee;
5569 ops->eee_set = r8152_set_eee;
5570 ops->in_nway = rtl8153_in_nway;
5571 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
5572 ops->autosuspend_en = rtl8153b_runtime_enable;
5573 tp->rx_buf_sz = 32 * 1024;
5574 tp->eee_en = true;
5575 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
5576 break;
5577
5578 default:
5579 ret = -ENODEV;
5580 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5581 break;
5582 }
5583
5584 return ret;
5585 }
5586
5587 static u8 rtl_get_version(struct usb_interface *intf)
5588 {
5589 struct usb_device *udev = interface_to_usbdev(intf);
5590 u32 ocp_data = 0;
5591 __le32 *tmp;
5592 u8 version;
5593 int ret;
5594
5595 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5596 if (!tmp)
5597 return 0;
5598
5599 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5600 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5601 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5602 if (ret > 0)
5603 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5604
5605 kfree(tmp);
5606
5607 switch (ocp_data) {
5608 case 0x4c00:
5609 version = RTL_VER_01;
5610 break;
5611 case 0x4c10:
5612 version = RTL_VER_02;
5613 break;
5614 case 0x5c00:
5615 version = RTL_VER_03;
5616 break;
5617 case 0x5c10:
5618 version = RTL_VER_04;
5619 break;
5620 case 0x5c20:
5621 version = RTL_VER_05;
5622 break;
5623 case 0x5c30:
5624 version = RTL_VER_06;
5625 break;
5626 case 0x4800:
5627 version = RTL_VER_07;
5628 break;
5629 case 0x6000:
5630 version = RTL_VER_08;
5631 break;
5632 case 0x6010:
5633 version = RTL_VER_09;
5634 break;
5635 default:
5636 version = RTL_VER_UNKNOWN;
5637 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5638 break;
5639 }
5640
5641 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5642
5643 return version;
5644 }
5645
5646 static int rtl8152_probe(struct usb_interface *intf,
5647 const struct usb_device_id *id)
5648 {
5649 struct usb_device *udev = interface_to_usbdev(intf);
5650 u8 version = rtl_get_version(intf);
5651 struct r8152 *tp;
5652 struct net_device *netdev;
5653 int ret;
5654
5655 if (version == RTL_VER_UNKNOWN)
5656 return -ENODEV;
5657
5658 if (udev->actconfig->desc.bConfigurationValue != 1) {
5659 usb_driver_set_configuration(udev, 1);
5660 return -ENODEV;
5661 }
5662
5663 if (intf->cur_altsetting->desc.bNumEndpoints < 3)
5664 return -ENODEV;
5665
5666 usb_reset_device(udev);
5667 netdev = alloc_etherdev(sizeof(struct r8152));
5668 if (!netdev) {
5669 dev_err(&intf->dev, "Out of memory\n");
5670 return -ENOMEM;
5671 }
5672
5673 SET_NETDEV_DEV(netdev, &intf->dev);
5674 tp = netdev_priv(netdev);
5675 tp->msg_enable = 0x7FFF;
5676
5677 tp->udev = udev;
5678 tp->netdev = netdev;
5679 tp->intf = intf;
5680 tp->version = version;
5681
5682 switch (version) {
5683 case RTL_VER_01:
5684 case RTL_VER_02:
5685 case RTL_VER_07:
5686 tp->mii.supports_gmii = 0;
5687 break;
5688 default:
5689 tp->mii.supports_gmii = 1;
5690 break;
5691 }
5692
5693 ret = rtl_ops_init(tp);
5694 if (ret)
5695 goto out;
5696
5697 mutex_init(&tp->control);
5698 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5699 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5700 tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
5701 tasklet_disable(&tp->tx_tl);
5702
5703 netdev->netdev_ops = &rtl8152_netdev_ops;
5704 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5705
5706 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5707 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5708 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5709 NETIF_F_HW_VLAN_CTAG_TX;
5710 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5711 NETIF_F_TSO | NETIF_F_FRAGLIST |
5712 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5713 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5714 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5715 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5716 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5717
5718 if (tp->version == RTL_VER_01) {
5719 netdev->features &= ~NETIF_F_RXCSUM;
5720 netdev->hw_features &= ~NETIF_F_RXCSUM;
5721 }
5722
5723 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
5724 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) {
5725 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
5726 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
5727 }
5728
5729 netdev->ethtool_ops = &ops;
5730 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5731
5732
5733 netdev->min_mtu = ETH_MIN_MTU;
5734 switch (tp->version) {
5735 case RTL_VER_01:
5736 case RTL_VER_02:
5737 netdev->max_mtu = ETH_DATA_LEN;
5738 break;
5739 default:
5740 netdev->max_mtu = RTL8153_MAX_MTU;
5741 break;
5742 }
5743
5744 tp->mii.dev = netdev;
5745 tp->mii.mdio_read = read_mii_word;
5746 tp->mii.mdio_write = write_mii_word;
5747 tp->mii.phy_id_mask = 0x3f;
5748 tp->mii.reg_num_mask = 0x1f;
5749 tp->mii.phy_id = R8152_PHY_ID;
5750
5751 tp->autoneg = AUTONEG_ENABLE;
5752 tp->speed = SPEED_100;
5753 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
5754 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
5755 if (tp->mii.supports_gmii) {
5756 tp->speed = SPEED_1000;
5757 tp->advertising |= RTL_ADVERTISED_1000_FULL;
5758 }
5759 tp->duplex = DUPLEX_FULL;
5760
5761 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
5762 tp->rx_pending = 10 * RTL8152_MAX_RX;
5763
5764 intf->needs_remote_wakeup = 1;
5765
5766 if (!rtl_can_wakeup(tp))
5767 __rtl_set_wol(tp, 0);
5768 else
5769 tp->saved_wolopts = __rtl_get_wol(tp);
5770
5771 tp->rtl_ops.init(tp);
5772 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5773 set_ethernet_addr(tp);
5774
5775 usb_set_intfdata(intf, tp);
5776 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5777
5778 ret = register_netdev(netdev);
5779 if (ret != 0) {
5780 netif_err(tp, probe, netdev, "couldn't register the device\n");
5781 goto out1;
5782 }
5783
5784 if (tp->saved_wolopts)
5785 device_set_wakeup_enable(&udev->dev, true);
5786 else
5787 device_set_wakeup_enable(&udev->dev, false);
5788
5789 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5790
5791 return 0;
5792
5793 out1:
5794 tasklet_kill(&tp->tx_tl);
5795 usb_set_intfdata(intf, NULL);
5796 out:
5797 free_netdev(netdev);
5798 return ret;
5799 }
5800
5801 static void rtl8152_disconnect(struct usb_interface *intf)
5802 {
5803 struct r8152 *tp = usb_get_intfdata(intf);
5804
5805 usb_set_intfdata(intf, NULL);
5806 if (tp) {
5807 rtl_set_unplug(tp);
5808
5809 unregister_netdev(tp->netdev);
5810 tasklet_kill(&tp->tx_tl);
5811 cancel_delayed_work_sync(&tp->hw_phy_work);
5812 tp->rtl_ops.unload(tp);
5813 free_netdev(tp->netdev);
5814 }
5815 }
5816
5817 #define REALTEK_USB_DEVICE(vend, prod) \
5818 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5819 USB_DEVICE_ID_MATCH_INT_CLASS, \
5820 .idVendor = (vend), \
5821 .idProduct = (prod), \
5822 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5823 }, \
5824 { \
5825 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5826 USB_DEVICE_ID_MATCH_DEVICE, \
5827 .idVendor = (vend), \
5828 .idProduct = (prod), \
5829 .bInterfaceClass = USB_CLASS_COMM, \
5830 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5831 .bInterfaceProtocol = USB_CDC_PROTO_NONE
5832
5833
5834 static const struct usb_device_id rtl8152_table[] = {
5835 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5836 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5837 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5838 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5839 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5840 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
5841 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5842 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
5843 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
5844 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
5845 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
5846 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
5847 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
5848 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
5849 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5850 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
5851 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
5852 {}
5853 };
5854
5855 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5856
5857 static struct usb_driver rtl8152_driver = {
5858 .name = MODULENAME,
5859 .id_table = rtl8152_table,
5860 .probe = rtl8152_probe,
5861 .disconnect = rtl8152_disconnect,
5862 .suspend = rtl8152_suspend,
5863 .resume = rtl8152_resume,
5864 .reset_resume = rtl8152_reset_resume,
5865 .pre_reset = rtl8152_pre_reset,
5866 .post_reset = rtl8152_post_reset,
5867 .supports_autosuspend = 1,
5868 .disable_hub_initiated_lpm = 1,
5869 };
5870
5871 module_usb_driver(rtl8152_driver);
5872
5873 MODULE_AUTHOR(DRIVER_AUTHOR);
5874 MODULE_DESCRIPTION(DRIVER_DESC);
5875 MODULE_LICENSE("GPL");
5876 MODULE_VERSION(DRIVER_VERSION);