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7 #ifndef _MCR20A_H
8 #define _MCR20A_H
9
10
11 #define DAR_IRQ_STS1 0x00
12 #define DAR_IRQ_STS2 0x01
13 #define DAR_IRQ_STS3 0x02
14 #define DAR_PHY_CTRL1 0x03
15 #define DAR_PHY_CTRL2 0x04
16 #define DAR_PHY_CTRL3 0x05
17 #define DAR_RX_FRM_LEN 0x06
18 #define DAR_PHY_CTRL4 0x07
19 #define DAR_SRC_CTRL 0x08
20 #define DAR_SRC_ADDRS_SUM_LSB 0x09
21 #define DAR_SRC_ADDRS_SUM_MSB 0x0A
22 #define DAR_CCA1_ED_FNL 0x0B
23 #define DAR_EVENT_TMR_LSB 0x0C
24 #define DAR_EVENT_TMR_MSB 0x0D
25 #define DAR_EVENT_TMR_USB 0x0E
26 #define DAR_TIMESTAMP_LSB 0x0F
27 #define DAR_TIMESTAMP_MSB 0x10
28 #define DAR_TIMESTAMP_USB 0x11
29 #define DAR_T3CMP_LSB 0x12
30 #define DAR_T3CMP_MSB 0x13
31 #define DAR_T3CMP_USB 0x14
32 #define DAR_T2PRIMECMP_LSB 0x15
33 #define DAR_T2PRIMECMP_MSB 0x16
34 #define DAR_T1CMP_LSB 0x17
35 #define DAR_T1CMP_MSB 0x18
36 #define DAR_T1CMP_USB 0x19
37 #define DAR_T2CMP_LSB 0x1A
38 #define DAR_T2CMP_MSB 0x1B
39 #define DAR_T2CMP_USB 0x1C
40 #define DAR_T4CMP_LSB 0x1D
41 #define DAR_T4CMP_MSB 0x1E
42 #define DAR_T4CMP_USB 0x1F
43 #define DAR_PLL_INT0 0x20
44 #define DAR_PLL_FRAC0_LSB 0x21
45 #define DAR_PLL_FRAC0_MSB 0x22
46 #define DAR_PA_PWR 0x23
47 #define DAR_SEQ_STATE 0x24
48 #define DAR_LQI_VALUE 0x25
49 #define DAR_RSSI_CCA_CONT 0x26
50
51 #define DAR_ASM_CTRL1 0x28
52 #define DAR_ASM_CTRL2 0x29
53 #define DAR_ASM_DATA_0 0x2A
54 #define DAR_ASM_DATA_1 0x2B
55 #define DAR_ASM_DATA_2 0x2C
56 #define DAR_ASM_DATA_3 0x2D
57 #define DAR_ASM_DATA_4 0x2E
58 #define DAR_ASM_DATA_5 0x2F
59 #define DAR_ASM_DATA_6 0x30
60 #define DAR_ASM_DATA_7 0x31
61 #define DAR_ASM_DATA_8 0x32
62 #define DAR_ASM_DATA_9 0x33
63 #define DAR_ASM_DATA_A 0x34
64 #define DAR_ASM_DATA_B 0x35
65 #define DAR_ASM_DATA_C 0x36
66 #define DAR_ASM_DATA_D 0x37
67 #define DAR_ASM_DATA_E 0x38
68 #define DAR_ASM_DATA_F 0x39
69
70 #define DAR_OVERWRITE_VER 0x3B
71 #define DAR_CLK_OUT_CTRL 0x3C
72 #define DAR_PWR_MODES 0x3D
73 #define IAR_INDEX 0x3E
74 #define IAR_DATA 0x3F
75
76
77 #define IAR_PART_ID 0x00
78 #define IAR_XTAL_TRIM 0x01
79 #define IAR_PMC_LP_TRIM 0x02
80 #define IAR_MACPANID0_LSB 0x03
81 #define IAR_MACPANID0_MSB 0x04
82 #define IAR_MACSHORTADDRS0_LSB 0x05
83 #define IAR_MACSHORTADDRS0_MSB 0x06
84 #define IAR_MACLONGADDRS0_0 0x07
85 #define IAR_MACLONGADDRS0_8 0x08
86 #define IAR_MACLONGADDRS0_16 0x09
87 #define IAR_MACLONGADDRS0_24 0x0A
88 #define IAR_MACLONGADDRS0_32 0x0B
89 #define IAR_MACLONGADDRS0_40 0x0C
90 #define IAR_MACLONGADDRS0_48 0x0D
91 #define IAR_MACLONGADDRS0_56 0x0E
92 #define IAR_RX_FRAME_FILTER 0x0F
93 #define IAR_PLL_INT1 0x10
94 #define IAR_PLL_FRAC1_LSB 0x11
95 #define IAR_PLL_FRAC1_MSB 0x12
96 #define IAR_MACPANID1_LSB 0x13
97 #define IAR_MACPANID1_MSB 0x14
98 #define IAR_MACSHORTADDRS1_LSB 0x15
99 #define IAR_MACSHORTADDRS1_MSB 0x16
100 #define IAR_MACLONGADDRS1_0 0x17
101 #define IAR_MACLONGADDRS1_8 0x18
102 #define IAR_MACLONGADDRS1_16 0x19
103 #define IAR_MACLONGADDRS1_24 0x1A
104 #define IAR_MACLONGADDRS1_32 0x1B
105 #define IAR_MACLONGADDRS1_40 0x1C
106 #define IAR_MACLONGADDRS1_48 0x1D
107 #define IAR_MACLONGADDRS1_56 0x1E
108 #define IAR_DUAL_PAN_CTRL 0x1F
109 #define IAR_DUAL_PAN_DWELL 0x20
110 #define IAR_DUAL_PAN_STS 0x21
111 #define IAR_CCA1_THRESH 0x22
112 #define IAR_CCA1_ED_OFFSET_COMP 0x23
113 #define IAR_LQI_OFFSET_COMP 0x24
114 #define IAR_CCA_CTRL 0x25
115 #define IAR_CCA2_CORR_PEAKS 0x26
116 #define IAR_CCA2_CORR_THRESH 0x27
117 #define IAR_TMR_PRESCALE 0x28
118
119 #define IAR_GPIO_DATA 0x2A
120 #define IAR_GPIO_DIR 0x2B
121 #define IAR_GPIO_PUL_EN 0x2C
122 #define IAR_GPIO_PUL_SEL 0x2D
123 #define IAR_GPIO_DS 0x2E
124
125 #define IAR_ANT_PAD_CTRL 0x30
126 #define IAR_MISC_PAD_CTRL 0x31
127 #define IAR_BSM_CTRL 0x32
128
129 #define IAR_RNG 0x34
130 #define IAR_RX_BYTE_COUNT 0x35
131 #define IAR_RX_WTR_MARK 0x36
132 #define IAR_SOFT_RESET 0x37
133 #define IAR_TXDELAY 0x38
134 #define IAR_ACKDELAY 0x39
135 #define IAR_SEQ_MGR_CTRL 0x3A
136 #define IAR_SEQ_MGR_STS 0x3B
137 #define IAR_SEQ_T_STS 0x3C
138 #define IAR_ABORT_STS 0x3D
139 #define IAR_CCCA_BUSY_CNT 0x3E
140 #define IAR_SRC_ADDR_CHECKSUM1 0x3F
141 #define IAR_SRC_ADDR_CHECKSUM2 0x40
142 #define IAR_SRC_TBL_VALID1 0x41
143 #define IAR_SRC_TBL_VALID2 0x42
144 #define IAR_FILTERFAIL_CODE1 0x43
145 #define IAR_FILTERFAIL_CODE2 0x44
146 #define IAR_SLOT_PRELOAD 0x45
147
148 #define IAR_CORR_VT 0x47
149 #define IAR_SYNC_CTRL 0x48
150 #define IAR_PN_LSB_0 0x49
151 #define IAR_PN_LSB_1 0x4A
152 #define IAR_PN_MSB_0 0x4B
153 #define IAR_PN_MSB_1 0x4C
154 #define IAR_CORR_NVAL 0x4D
155 #define IAR_TX_MODE_CTRL 0x4E
156 #define IAR_SNF_THR 0x4F
157 #define IAR_FAD_THR 0x50
158 #define IAR_ANT_AGC_CTRL 0x51
159 #define IAR_AGC_THR1 0x52
160 #define IAR_AGC_THR2 0x53
161 #define IAR_AGC_HYS 0x54
162 #define IAR_AFC 0x55
163
164
165 #define IAR_PHY_STS 0x58
166 #define IAR_RX_MAX_CORR 0x59
167 #define IAR_RX_MAX_PREAMBLE 0x5A
168 #define IAR_RSSI 0x5B
169
170
171 #define IAR_PLL_DIG_CTRL 0x5E
172 #define IAR_VCO_CAL 0x5F
173 #define IAR_VCO_BEST_DIFF 0x60
174 #define IAR_VCO_BIAS 0x61
175 #define IAR_KMOD_CTRL 0x62
176 #define IAR_KMOD_CAL 0x63
177 #define IAR_PA_CAL 0x64
178 #define IAR_PA_PWRCAL 0x65
179 #define IAR_ATT_RSSI1 0x66
180 #define IAR_ATT_RSSI2 0x67
181 #define IAR_RSSI_OFFSET 0x68
182 #define IAR_RSSI_SLOPE 0x69
183 #define IAR_RSSI_CAL1 0x6A
184 #define IAR_RSSI_CAL2 0x6B
185
186
187 #define IAR_XTAL_CTRL 0x6E
188 #define IAR_XTAL_COMP_MIN 0x6F
189 #define IAR_XTAL_COMP_MAX 0x70
190 #define IAR_XTAL_GM 0x71
191
192
193 #define IAR_LNA_TUNE 0x74
194 #define IAR_LNA_AGCGAIN 0x75
195
196
197 #define IAR_CHF_PMA_GAIN 0x78
198 #define IAR_CHF_IBUF 0x79
199 #define IAR_CHF_QBUF 0x7A
200 #define IAR_CHF_IRIN 0x7B
201 #define IAR_CHF_QRIN 0x7C
202 #define IAR_CHF_IL 0x7D
203 #define IAR_CHF_QL 0x7E
204 #define IAR_CHF_CC1 0x7F
205 #define IAR_CHF_CCL 0x80
206 #define IAR_CHF_CC2 0x81
207 #define IAR_CHF_IROUT 0x82
208 #define IAR_CHF_QROUT 0x83
209
210
211 #define IAR_RSSI_CTRL 0x86
212
213
214 #define IAR_PA_BIAS 0x89
215 #define IAR_PA_TUNING 0x8A
216
217
218 #define IAR_PMC_HP_TRIM 0x8D
219 #define IAR_VREGA_TRIM 0x8E
220
221
222 #define IAR_VCO_CTRL1 0x91
223 #define IAR_VCO_CTRL2 0x92
224
225
226 #define IAR_ANA_SPARE_OUT1 0x95
227 #define IAR_ANA_SPARE_OUT2 0x96
228 #define IAR_ANA_SPARE_IN 0x97
229 #define IAR_MISCELLANEOUS 0x98
230
231 #define IAR_SEQ_MGR_OVRD0 0x9A
232 #define IAR_SEQ_MGR_OVRD1 0x9B
233 #define IAR_SEQ_MGR_OVRD2 0x9C
234 #define IAR_SEQ_MGR_OVRD3 0x9D
235 #define IAR_SEQ_MGR_OVRD4 0x9E
236 #define IAR_SEQ_MGR_OVRD5 0x9F
237 #define IAR_SEQ_MGR_OVRD6 0xA0
238 #define IAR_SEQ_MGR_OVRD7 0xA1
239
240 #define IAR_TESTMODE_CTRL 0xA3
241 #define IAR_DTM_CTRL1 0xA4
242 #define IAR_DTM_CTRL2 0xA5
243 #define IAR_ATM_CTRL1 0xA6
244 #define IAR_ATM_CTRL2 0xA7
245 #define IAR_ATM_CTRL3 0xA8
246
247 #define IAR_LIM_FE_TEST_CTRL 0xAA
248 #define IAR_CHF_TEST_CTRL 0xAB
249 #define IAR_VCO_TEST_CTRL 0xAC
250 #define IAR_PLL_TEST_CTRL 0xAD
251 #define IAR_PA_TEST_CTRL 0xAE
252 #define IAR_PMC_TEST_CTRL 0xAF
253 #define IAR_SCAN_DTM_PROTECT_1 0xFE
254 #define IAR_SCAN_DTM_PROTECT_0 0xFF
255
256
257 #define DAR_IRQSTS1_RX_FRM_PEND BIT(7)
258 #define DAR_IRQSTS1_PLL_UNLOCK_IRQ BIT(6)
259 #define DAR_IRQSTS1_FILTERFAIL_IRQ BIT(5)
260 #define DAR_IRQSTS1_RXWTRMRKIRQ BIT(4)
261 #define DAR_IRQSTS1_CCAIRQ BIT(3)
262 #define DAR_IRQSTS1_RXIRQ BIT(2)
263 #define DAR_IRQSTS1_TXIRQ BIT(1)
264 #define DAR_IRQSTS1_SEQIRQ BIT(0)
265
266
267 #define DAR_IRQSTS2_CRCVALID BIT(7)
268 #define DAR_IRQSTS2_CCA BIT(6)
269 #define DAR_IRQSTS2_SRCADDR BIT(5)
270 #define DAR_IRQSTS2_PI BIT(4)
271 #define DAR_IRQSTS2_TMRSTATUS BIT(3)
272 #define DAR_IRQSTS2_ASM_IRQ BIT(2)
273 #define DAR_IRQSTS2_PB_ERR_IRQ BIT(1)
274 #define DAR_IRQSTS2_WAKE_IRQ BIT(0)
275
276
277 #define DAR_IRQSTS3_TMR4MSK BIT(7)
278 #define DAR_IRQSTS3_TMR3MSK BIT(6)
279 #define DAR_IRQSTS3_TMR2MSK BIT(5)
280 #define DAR_IRQSTS3_TMR1MSK BIT(4)
281 #define DAR_IRQSTS3_TMR4IRQ BIT(3)
282 #define DAR_IRQSTS3_TMR3IRQ BIT(2)
283 #define DAR_IRQSTS3_TMR2IRQ BIT(1)
284 #define DAR_IRQSTS3_TMR1IRQ BIT(0)
285
286
287 #define DAR_PHY_CTRL1_TMRTRIGEN BIT(7)
288 #define DAR_PHY_CTRL1_SLOTTED BIT(6)
289 #define DAR_PHY_CTRL1_CCABFRTX BIT(5)
290 #define DAR_PHY_CTRL1_CCABFRTX_SHIFT 5
291 #define DAR_PHY_CTRL1_RXACKRQD BIT(4)
292 #define DAR_PHY_CTRL1_AUTOACK BIT(3)
293 #define DAR_PHY_CTRL1_XCVSEQ_MASK 0x07
294
295
296 #define DAR_PHY_CTRL2_CRC_MSK BIT(7)
297 #define DAR_PHY_CTRL2_PLL_UNLOCK_MSK BIT(6)
298 #define DAR_PHY_CTRL2_FILTERFAIL_MSK BIT(5)
299 #define DAR_PHY_CTRL2_RX_WMRK_MSK BIT(4)
300 #define DAR_PHY_CTRL2_CCAMSK BIT(3)
301 #define DAR_PHY_CTRL2_RXMSK BIT(2)
302 #define DAR_PHY_CTRL2_TXMSK BIT(1)
303 #define DAR_PHY_CTRL2_SEQMSK BIT(0)
304
305
306 #define DAR_PHY_CTRL3_TMR4CMP_EN BIT(7)
307 #define DAR_PHY_CTRL3_TMR3CMP_EN BIT(6)
308 #define DAR_PHY_CTRL3_TMR2CMP_EN BIT(5)
309 #define DAR_PHY_CTRL3_TMR1CMP_EN BIT(4)
310 #define DAR_PHY_CTRL3_ASM_MSK BIT(2)
311 #define DAR_PHY_CTRL3_PB_ERR_MSK BIT(1)
312 #define DAR_PHY_CTRL3_WAKE_MSK BIT(0)
313
314
315 #define DAR_RX_FRAME_LENGTH_MASK (0x7F)
316
317
318 #define DAR_PHY_CTRL4_TRCV_MSK BIT(7)
319 #define DAR_PHY_CTRL4_TC3TMOUT BIT(6)
320 #define DAR_PHY_CTRL4_PANCORDNTR0 BIT(5)
321 #define DAR_PHY_CTRL4_CCATYPE (3)
322 #define DAR_PHY_CTRL4_CCATYPE_SHIFT (3)
323 #define DAR_PHY_CTRL4_CCATYPE_MASK (0x18)
324 #define DAR_PHY_CTRL4_TMRLOAD BIT(2)
325 #define DAR_PHY_CTRL4_PROMISCUOUS BIT(1)
326 #define DAR_PHY_CTRL4_TC2PRIME_EN BIT(0)
327
328
329 #define DAR_SRC_CTRL_INDEX (0x0F)
330 #define DAR_SRC_CTRL_INDEX_SHIFT (4)
331 #define DAR_SRC_CTRL_ACK_FRM_PND BIT(3)
332 #define DAR_SRC_CTRL_SRCADDR_EN BIT(2)
333 #define DAR_SRC_CTRL_INDEX_EN BIT(1)
334 #define DAR_SRC_CTRL_INDEX_DISABLE BIT(0)
335
336
337 #define DAR_ASM_CTRL1_CLEAR BIT(7)
338 #define DAR_ASM_CTRL1_START BIT(6)
339 #define DAR_ASM_CTRL1_SELFTST BIT(5)
340 #define DAR_ASM_CTRL1_CTR BIT(4)
341 #define DAR_ASM_CTRL1_CBC BIT(3)
342 #define DAR_ASM_CTRL1_AES BIT(2)
343 #define DAR_ASM_CTRL1_LOAD_MAC BIT(1)
344
345
346 #define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL (7)
347 #define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL_SHIFT (5)
348 #define DAR_ASM_CTRL2_TSTPAS BIT(1)
349
350
351 #define DAR_CLK_OUT_CTRL_EXTEND BIT(7)
352 #define DAR_CLK_OUT_CTRL_HIZ BIT(6)
353 #define DAR_CLK_OUT_CTRL_SR BIT(5)
354 #define DAR_CLK_OUT_CTRL_DS BIT(4)
355 #define DAR_CLK_OUT_CTRL_EN BIT(3)
356 #define DAR_CLK_OUT_CTRL_DIV (7)
357
358
359 #define DAR_PWR_MODES_XTAL_READY BIT(5)
360 #define DAR_PWR_MODES_XTALEN BIT(4)
361 #define DAR_PWR_MODES_ASM_CLK_EN BIT(3)
362 #define DAR_PWR_MODES_AUTODOZE BIT(1)
363 #define DAR_PWR_MODES_PMC_MODE BIT(0)
364
365
366 #define IAR_RX_FRAME_FLT_FRM_VER (0xC0)
367 #define IAR_RX_FRAME_FLT_FRM_VER_SHIFT (6)
368 #define IAR_RX_FRAME_FLT_ACTIVE_PROMISCUOUS BIT(5)
369 #define IAR_RX_FRAME_FLT_NS_FT BIT(4)
370 #define IAR_RX_FRAME_FLT_CMD_FT BIT(3)
371 #define IAR_RX_FRAME_FLT_ACK_FT BIT(2)
372 #define IAR_RX_FRAME_FLT_DATA_FT BIT(1)
373 #define IAR_RX_FRAME_FLT_BEACON_FT BIT(0)
374
375
376 #define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
377 #define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT (4)
378 #define IAR_DUAL_PAN_CTRL_CURRENT_NETWORK BIT(3)
379 #define IAR_DUAL_PAN_CTRL_PANCORDNTR1 BIT(2)
380 #define IAR_DUAL_PAN_CTRL_DUAL_PAN_AUTO BIT(1)
381 #define IAR_DUAL_PAN_CTRL_ACTIVE_NETWORK BIT(0)
382
383
384 #define IAR_DUAL_PAN_STS_RECD_ON_PAN1 BIT(7)
385 #define IAR_DUAL_PAN_STS_RECD_ON_PAN0 BIT(6)
386 #define IAR_DUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
387
388
389 #define IAR_CCA_CTRL_AGC_FRZ_EN BIT(6)
390 #define IAR_CCA_CTRL_CONT_RSSI_EN BIT(5)
391 #define IAR_CCA_CTRL_LQI_RSSI_NOT_CORR BIT(4)
392 #define IAR_CCA_CTRL_CCA3_AND_NOT_OR BIT(3)
393 #define IAR_CCA_CTRL_POWER_COMP_EN_LQI BIT(2)
394 #define IAR_CCA_CTRL_POWER_COMP_EN_ED BIT(1)
395 #define IAR_CCA_CTRL_POWER_COMP_EN_CCA1 BIT(0)
396
397
398 #define IAR_ANT_PAD_CTRL_ANTX_POL (0x0F)
399 #define IAR_ANT_PAD_CTRL_ANTX_POL_SHIFT (4)
400 #define IAR_ANT_PAD_CTRL_ANTX_CTRLMODE BIT(3)
401 #define IAR_ANT_PAD_CTRL_ANTX_HZ BIT(2)
402 #define IAR_ANT_PAD_CTRL_ANTX_EN (3)
403
404
405 #define IAR_MISC_PAD_CTRL_MISO_HIZ_EN BIT(3)
406 #define IAR_MISC_PAD_CTRL_IRQ_B_OD BIT(2)
407 #define IAR_MISC_PAD_CTRL_NON_GPIO_DS BIT(1)
408 #define IAR_MISC_PAD_CTRL_ANTX_CURR (1)
409
410
411 #define IAR_ANT_AGC_CTRL_FAD_EN_SHIFT (0)
412 #define IAR_ANT_AGC_CTRL_FAD_EN_MASK (1)
413 #define IAR_ANT_AGC_CTRL_ANTX_SHIFT (1)
414 #define IAR_ANT_AGC_CTRL_ANTX_MASK BIT(AR_ANT_AGC_CTRL_ANTX_SHIFT)
415
416
417 #define BSM_CTRL_BSM_EN (1)
418
419
420 #define IAR_SOFT_RESET_SOG_RST BIT(7)
421 #define IAR_SOFT_RESET_REGS_RST BIT(4)
422 #define IAR_SOFT_RESET_PLL_RST BIT(3)
423 #define IAR_SOFT_RESET_TX_RST BIT(2)
424 #define IAR_SOFT_RESET_RX_RST BIT(1)
425 #define IAR_SOFT_RESET_SEQ_MGR_RST BIT(0)
426
427
428 #define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
429 #define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT (6)
430 #define IAR_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5)
431 #define IAR_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4)
432 #define IAR_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH BIT(3)
433 #define IAR_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT BIT(2)
434 #define IAR_SEQ_MGR_CTRL_PSM_LOCK_DIS BIT(1)
435 #define IAR_SEQ_MGR_CTRL_PLL_ABORT_OVRD BIT(0)
436
437
438 #define IAR_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED BIT(7)
439 #define IAR_SEQ_MGR_STS_RX_MODE BIT(6)
440 #define IAR_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5)
441 #define IAR_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4)
442 #define IAR_SEQ_MGR_STS_SEQ_IDLE BIT(3)
443 #define IAR_SEQ_MGR_STS_XCVSEQ_ACTUAL (7)
444
445
446 #define IAR_ABORT_STS_PLL_ABORTED BIT(2)
447 #define IAR_ABORT_STS_TC3_ABORTED BIT(1)
448 #define IAR_ABORT_STS_SW_ABORTED BIT(0)
449
450
451 #define IAR_FILTERFAIL_CODE2_PAN_SEL BIT(7)
452 #define IAR_FILTERFAIL_CODE2_9_8 (3)
453
454
455 #define IAR_PHY_STS_PLL_UNLOCK BIT(7)
456 #define IAR_PHY_STS_PLL_LOCK_ERR BIT(6)
457 #define IAR_PHY_STS_PLL_LOCK BIT(5)
458 #define IAR_PHY_STS_CRCVALID BIT(3)
459 #define IAR_PHY_STS_FILTERFAIL_FLAG_SEL BIT(2)
460 #define IAR_PHY_STS_SFD_DET BIT(1)
461 #define IAR_PHY_STS_PREAMBLE_DET BIT(0)
462
463
464 #define IAR_TEST_MODE_CTRL_HOT_ANT BIT(4)
465 #define IAR_TEST_MODE_CTRL_IDEAL_RSSI_EN BIT(3)
466 #define IAR_TEST_MODE_CTRL_IDEAL_PFC_EN BIT(2)
467 #define IAR_TEST_MODE_CTRL_CONTINUOUS_EN BIT(1)
468 #define IAR_TEST_MODE_CTRL_FPGA_EN BIT(0)
469
470
471 #define IAR_DTM_CTRL1_ATM_LOCKED BIT(7)
472 #define IAR_DTM_CTRL1_DTM_EN BIT(6)
473 #define IAR_DTM_CTRL1_PAGE5 BIT(5)
474 #define IAR_DTM_CTRL1_PAGE4 BIT(4)
475 #define IAR_DTM_CTRL1_PAGE3 BIT(3)
476 #define IAR_DTM_CTRL1_PAGE2 BIT(2)
477 #define IAR_DTM_CTRL1_PAGE1 BIT(1)
478 #define IAR_DTM_CTRL1_PAGE0 BIT(0)
479
480
481 #define IAR_TX_MODE_CTRL_TX_INV BIT(4)
482 #define IAR_TX_MODE_CTRL_BT_EN BIT(3)
483 #define IAR_TX_MODE_CTRL_DTS2 BIT(2)
484 #define IAR_TX_MODE_CTRL_DTS1 BIT(1)
485 #define IAR_TX_MODE_CTRL_DTS0 BIT(0)
486
487 #define TX_MODE_CTRL_DTS_MASK (7)
488
489 #endif