drivers/net/wireless/st/cw1200/hwio.h

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
cw1200_reg_read_16
cw1200_reg_write_16
cw1200_reg_read_32
cw1200_reg_write_32
cw1200_apb_read
cw1200_ahb_read
cw1200_apb_read_32
cw1200_apb_write_32
cw1200_ahb_read_32
   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Low-level API for mac80211 ST-Ericsson CW1200 drivers
   4  *
   5  * Copyright (c) 2010, ST-Ericsson
   6  * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
   7  *
   8  * Based on:
   9  * ST-Ericsson UMAC CW1200 driver which is
  10  * Copyright (c) 2010, ST-Ericsson
  11  * Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
  12  */
  13 
  14 #ifndef CW1200_HWIO_H_INCLUDED
  15 #define CW1200_HWIO_H_INCLUDED
  16 
  17 /* extern */ struct cw1200_common;
  18 
  19 #define CW1200_CUT_11_ID_STR            (0x302E3830)
  20 #define CW1200_CUT_22_ID_STR1           (0x302e3132)
  21 #define CW1200_CUT_22_ID_STR2           (0x32302e30)
  22 #define CW1200_CUT_22_ID_STR3           (0x3335)
  23 #define CW1200_CUT_ID_ADDR              (0xFFF17F90)
  24 #define CW1200_CUT2_ID_ADDR             (0xFFF1FF90)
  25 
  26 /* Download control area */
  27 /* boot loader start address in SRAM */
  28 #define DOWNLOAD_BOOT_LOADER_OFFSET     (0x00000000)
  29 /* 32K, 0x4000 to 0xDFFF */
  30 #define DOWNLOAD_FIFO_OFFSET            (0x00004000)
  31 /* 32K */
  32 #define DOWNLOAD_FIFO_SIZE              (0x00008000)
  33 /* 128 bytes, 0xFF80 to 0xFFFF */
  34 #define DOWNLOAD_CTRL_OFFSET            (0x0000FF80)
  35 #define DOWNLOAD_CTRL_DATA_DWORDS       (32-6)
  36 
  37 struct download_cntl_t {
  38         /* size of whole firmware file (including Cheksum), host init */
  39         u32 image_size;
  40         /* downloading flags */
  41         u32 flags;
  42         /* No. of bytes put into the download, init & updated by host */
  43         u32 put;
  44         /* last traced program counter, last ARM reg_pc */
  45         u32 trace_pc;
  46         /* No. of bytes read from the download, host init, device updates */
  47         u32 get;
  48         /* r0, boot losader status, host init to pending, device updates */
  49         u32 status;
  50         /* Extra debug info, r1 to r14 if status=r0=DOWNLOAD_EXCEPTION */
  51         u32 debug_data[DOWNLOAD_CTRL_DATA_DWORDS];
  52 };
  53 
  54 #define DOWNLOAD_IMAGE_SIZE_REG         \
  55         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, image_size))
  56 #define DOWNLOAD_FLAGS_REG              \
  57         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, flags))
  58 #define DOWNLOAD_PUT_REG                \
  59         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, put))
  60 #define DOWNLOAD_TRACE_PC_REG           \
  61         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, trace_pc))
  62 #define DOWNLOAD_GET_REG                \
  63         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, get))
  64 #define DOWNLOAD_STATUS_REG             \
  65         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, status))
  66 #define DOWNLOAD_DEBUG_DATA_REG         \
  67         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, debug_data))
  68 #define DOWNLOAD_DEBUG_DATA_LEN         (108)
  69 
  70 #define DOWNLOAD_BLOCK_SIZE             (1024)
  71 
  72 /* For boot loader detection */
  73 #define DOWNLOAD_ARE_YOU_HERE           (0x87654321)
  74 #define DOWNLOAD_I_AM_HERE              (0x12345678)
  75 
  76 /* Download error code */
  77 #define DOWNLOAD_PENDING                (0xFFFFFFFF)
  78 #define DOWNLOAD_SUCCESS                (0)
  79 #define DOWNLOAD_EXCEPTION              (1)
  80 #define DOWNLOAD_ERR_MEM_1              (2)
  81 #define DOWNLOAD_ERR_MEM_2              (3)
  82 #define DOWNLOAD_ERR_SOFTWARE           (4)
  83 #define DOWNLOAD_ERR_FILE_SIZE          (5)
  84 #define DOWNLOAD_ERR_CHECKSUM           (6)
  85 #define DOWNLOAD_ERR_OVERFLOW           (7)
  86 #define DOWNLOAD_ERR_IMAGE              (8)
  87 #define DOWNLOAD_ERR_HOST               (9)
  88 #define DOWNLOAD_ERR_ABORT              (10)
  89 
  90 
  91 #define SYS_BASE_ADDR_SILICON           (0)
  92 #define PAC_BASE_ADDRESS_SILICON        (SYS_BASE_ADDR_SILICON + 0x09000000)
  93 #define PAC_SHARED_MEMORY_SILICON       (PAC_BASE_ADDRESS_SILICON)
  94 
  95 #define CW1200_APB(addr)                (PAC_SHARED_MEMORY_SILICON + (addr))
  96 
  97 /* Device register definitions */
  98 
  99 /* WBF - SPI Register Addresses */
 100 #define ST90TDS_ADDR_ID_BASE            (0x0000)
 101 /* 16/32 bits */
 102 #define ST90TDS_CONFIG_REG_ID           (0x0000)
 103 /* 16/32 bits */
 104 #define ST90TDS_CONTROL_REG_ID          (0x0001)
 105 /* 16 bits, Q mode W/R */
 106 #define ST90TDS_IN_OUT_QUEUE_REG_ID     (0x0002)
 107 /* 32 bits, AHB bus R/W */
 108 #define ST90TDS_AHB_DPORT_REG_ID        (0x0003)
 109 /* 16/32 bits */
 110 #define ST90TDS_SRAM_BASE_ADDR_REG_ID   (0x0004)
 111 /* 32 bits, APB bus R/W */
 112 #define ST90TDS_SRAM_DPORT_REG_ID       (0x0005)
 113 /* 32 bits, t_settle/general */
 114 #define ST90TDS_TSET_GEN_R_W_REG_ID     (0x0006)
 115 /* 16 bits, Q mode read, no length */
 116 #define ST90TDS_FRAME_OUT_REG_ID        (0x0007)
 117 #define ST90TDS_ADDR_ID_MAX             (ST90TDS_FRAME_OUT_REG_ID)
 118 
 119 /* WBF - Control register bit set */
 120 /* next o/p length, bit 11 to 0 */
 121 #define ST90TDS_CONT_NEXT_LEN_MASK      (0x0FFF)
 122 #define ST90TDS_CONT_WUP_BIT            (BIT(12))
 123 #define ST90TDS_CONT_RDY_BIT            (BIT(13))
 124 #define ST90TDS_CONT_IRQ_ENABLE         (BIT(14))
 125 #define ST90TDS_CONT_RDY_ENABLE         (BIT(15))
 126 #define ST90TDS_CONT_IRQ_RDY_ENABLE     (BIT(14)|BIT(15))
 127 
 128 /* SPI Config register bit set */
 129 #define ST90TDS_CONFIG_FRAME_BIT        (BIT(2))
 130 #define ST90TDS_CONFIG_WORD_MODE_BITS   (BIT(3)|BIT(4))
 131 #define ST90TDS_CONFIG_WORD_MODE_1      (BIT(3))
 132 #define ST90TDS_CONFIG_WORD_MODE_2      (BIT(4))
 133 #define ST90TDS_CONFIG_ERROR_0_BIT      (BIT(5))
 134 #define ST90TDS_CONFIG_ERROR_1_BIT      (BIT(6))
 135 #define ST90TDS_CONFIG_ERROR_2_BIT      (BIT(7))
 136 /* TBD: Sure??? */
 137 #define ST90TDS_CONFIG_CSN_FRAME_BIT    (BIT(7))
 138 #define ST90TDS_CONFIG_ERROR_3_BIT      (BIT(8))
 139 #define ST90TDS_CONFIG_ERROR_4_BIT      (BIT(9))
 140 /* QueueM */
 141 #define ST90TDS_CONFIG_ACCESS_MODE_BIT  (BIT(10))
 142 /* AHB bus */
 143 #define ST90TDS_CONFIG_AHB_PRFETCH_BIT  (BIT(11))
 144 #define ST90TDS_CONFIG_CPU_CLK_DIS_BIT  (BIT(12))
 145 /* APB bus */
 146 #define ST90TDS_CONFIG_PRFETCH_BIT      (BIT(13))
 147 /* cpu reset */
 148 #define ST90TDS_CONFIG_CPU_RESET_BIT    (BIT(14))
 149 #define ST90TDS_CONFIG_CLEAR_INT_BIT    (BIT(15))
 150 
 151 /* For CW1200 the IRQ Enable and Ready Bits are in CONFIG register */
 152 #define ST90TDS_CONF_IRQ_ENABLE         (BIT(16))
 153 #define ST90TDS_CONF_RDY_ENABLE         (BIT(17))
 154 #define ST90TDS_CONF_IRQ_RDY_ENABLE     (BIT(16)|BIT(17))
 155 
 156 int cw1200_data_read(struct cw1200_common *priv,
 157                      void *buf, size_t buf_len);
 158 int cw1200_data_write(struct cw1200_common *priv,
 159                       const void *buf, size_t buf_len);
 160 
 161 int cw1200_reg_read(struct cw1200_common *priv, u16 addr,
 162                     void *buf, size_t buf_len);
 163 int cw1200_reg_write(struct cw1200_common *priv, u16 addr,
 164                      const void *buf, size_t buf_len);
 165 
 166 static inline int cw1200_reg_read_16(struct cw1200_common *priv,
 167                                      u16 addr, u16 *val)
 168 {
 169         __le32 tmp;
 170         int i;
 171         i = cw1200_reg_read(priv, addr, &tmp, sizeof(tmp));
 172         *val = le32_to_cpu(tmp) & 0xfffff;
 173         return i;
 174 }
 175 
 176 static inline int cw1200_reg_write_16(struct cw1200_common *priv,
 177                                       u16 addr, u16 val)
 178 {
 179         __le32 tmp = cpu_to_le32((u32)val);
 180         return cw1200_reg_write(priv, addr, &tmp, sizeof(tmp));
 181 }
 182 
 183 static inline int cw1200_reg_read_32(struct cw1200_common *priv,
 184                                      u16 addr, u32 *val)
 185 {
 186         __le32 tmp;
 187         int i = cw1200_reg_read(priv, addr, &tmp, sizeof(tmp));
 188         *val = le32_to_cpu(tmp);
 189         return i;
 190 }
 191 
 192 static inline int cw1200_reg_write_32(struct cw1200_common *priv,
 193                                       u16 addr, u32 val)
 194 {
 195         __le32 tmp = cpu_to_le32(val);
 196         return cw1200_reg_write(priv, addr, &tmp, sizeof(val));
 197 }
 198 
 199 int cw1200_indirect_read(struct cw1200_common *priv, u32 addr, void *buf,
 200                          size_t buf_len, u32 prefetch, u16 port_addr);
 201 int cw1200_apb_write(struct cw1200_common *priv, u32 addr, const void *buf,
 202                      size_t buf_len);
 203 
 204 static inline int cw1200_apb_read(struct cw1200_common *priv, u32 addr,
 205                                   void *buf, size_t buf_len)
 206 {
 207         return cw1200_indirect_read(priv, addr, buf, buf_len,
 208                                     ST90TDS_CONFIG_PRFETCH_BIT,
 209                                     ST90TDS_SRAM_DPORT_REG_ID);
 210 }
 211 
 212 static inline int cw1200_ahb_read(struct cw1200_common *priv, u32 addr,
 213                                   void *buf, size_t buf_len)
 214 {
 215         return cw1200_indirect_read(priv, addr, buf, buf_len,
 216                                     ST90TDS_CONFIG_AHB_PRFETCH_BIT,
 217                                     ST90TDS_AHB_DPORT_REG_ID);
 218 }
 219 
 220 static inline int cw1200_apb_read_32(struct cw1200_common *priv,
 221                                      u32 addr, u32 *val)
 222 {
 223         __le32 tmp;
 224         int i = cw1200_apb_read(priv, addr, &tmp, sizeof(tmp));
 225         *val = le32_to_cpu(tmp);
 226         return i;
 227 }
 228 
 229 static inline int cw1200_apb_write_32(struct cw1200_common *priv,
 230                                       u32 addr, u32 val)
 231 {
 232         __le32 tmp = cpu_to_le32(val);
 233         return cw1200_apb_write(priv, addr, &tmp, sizeof(val));
 234 }
 235 static inline int cw1200_ahb_read_32(struct cw1200_common *priv,
 236                                      u32 addr, u32 *val)
 237 {
 238         __le32 tmp;
 239         int i = cw1200_ahb_read(priv, addr, &tmp, sizeof(tmp));
 240         *val = le32_to_cpu(tmp);
 241         return i;
 242 }
 243 
 244 #endif /* CW1200_HWIO_H_INCLUDED */
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/wireless/st/cw1200/hwio.h

INCLUDED FROM

DEFINITIONS
