drivers/net/wireless/ralink/rt2x00/rt2800lib.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
rt2800_is_305x_soc
rt2800_bbp_write
rt2800_bbp_read
rt2800_rfcsr_write
rt2800_rfcsr_write_bank
rt2800_rfcsr_write_chanreg
rt2800_rfcsr_write_dccal
rt2800_rfcsr_read
rt2800_rfcsr_read_bank
rt2800_rf_write
rt2800_eeprom_word_index
rt2800_eeprom_addr
rt2800_eeprom_read
rt2800_eeprom_write
rt2800_eeprom_read_from_array
rt2800_enable_wlan_rt3290
rt2800_mcu_request
rt2800_wait_csr_ready
rt2800_wait_wpdma_ready
rt2800_disable_wpdma
rt2800_get_txwi_rxwi_size
rt2800_check_firmware_crc
rt2800_check_firmware
rt2800_load_firmware
rt2800_write_tx_data
rt2800_agc_to_rssi
rt2800_process_rxwi
rt2800_rate_from_status
rt2800_txdone_entry_check
rt2800_txdone_entry
rt2800_txdone
rt2800_entry_txstatus_timeout
rt2800_txstatus_timeout
rt2800_txstatus_pending
rt2800_txdone_nostatus
rt2800_check_hung
rt2800_watchdog
rt2800_hw_beacon_base
rt2800_get_beacon_offset
rt2800_update_beacons_setup
rt2800_write_beacon
rt2800_clear_beacon_register
rt2800_clear_beacon
rt2800_rfkill_poll
rt2800_brightness_set
rt2800_init_led
rt2800_config_wcid
rt2800_delete_wcid_attr
rt2800_config_wcid_attr_bssidx
rt2800_config_wcid_attr_cipher
rt2800_config_shared_key
rt2800_config_pairwise_key
rt2800_set_max_psdu_len
rt2800_sta_add
rt2800_sta_remove
rt2800_pre_reset_hw
rt2800_config_filter
rt2800_config_intf
rt2800_config_ht_opmode
rt2800_config_erp
rt2800_config_3572bt_ant
rt2800_set_ant_diversity
rt2800_config_ant
rt2800_config_lna_gain
rt2800_clk_is_20mhz
rt2800_freq_cal_mode1
rt2800_config_channel_rf2xxx
rt2800_config_channel_rf3xxx
rt2800_config_channel_rf3052
rt2800_config_channel_rf3053
rt2800_config_channel_rf3853
rt2800_config_channel_rf3290
rt2800_config_channel_rf3322
rt2800_config_channel_rf53xx
rt2800_config_channel_rf55xx
rt2800_config_channel_rf7620
rt2800_config_alc
rt2800_bbp_write_with_rx_chain
rt2800_iq_calibrate
rt2800_txpower_to_dev
rt3883_bbp_adjust
rt2800_config_channel
rt2800_get_gain_calibration_delta
rt2800_get_txpower_bw_comp
rt2800_get_txpower_reg_delta
rt2800_compensate_txpower
rt2800_config_txpower_rt3593
rt2800_config_txpower_rt6352
rt2800_config_txpower_rt28xx
rt2800_config_txpower
rt2800_gain_calibration
rt2800_vco_calibration
rt2800_config_retry_limit
rt2800_config_ps
rt2800_config
rt2800_link_stats
rt2800_get_default_vgc
rt2800_set_vgc
rt2800_reset_tuner
rt2800_link_tuner
rt2800_init_registers
rt2800_wait_bbp_rf_ready
rt2800_wait_bbp_ready
rt2800_bbp4_mac_if_ctrl
rt2800_init_freq_calibration
rt2800_init_bbp_5592_glrt
rt2800_init_bbp_early
rt2800_disable_unused_dac_adc
rt2800_init_bbp_305x_soc
rt2800_init_bbp_28xx
rt2800_init_bbp_30xx
rt2800_init_bbp_3290
rt2800_init_bbp_3352
rt2800_init_bbp_3390
rt2800_init_bbp_3572
rt2800_init_bbp_3593
rt2800_init_bbp_3883
rt2800_init_bbp_53xx
rt2800_init_bbp_5592
rt2800_bbp_glrt_write
rt2800_bbp_dcoc_write
rt2800_bbp_dcoc_read
rt2800_init_bbp_6352
rt2800_init_bbp
rt2800_led_open_drain_enable
rt2800_init_rx_filter
rt2800_rf_init_calibration
rt2800_rx_filter_calibration
rt2800_normal_mode_setup_3xxx
rt2800_normal_mode_setup_3593
rt2800_normal_mode_setup_5xxx
rt2800_init_rfcsr_305x_soc
rt2800_init_rfcsr_30xx
rt2800_init_rfcsr_3290
rt2800_init_rfcsr_3352
rt2800_init_rfcsr_3390
rt2800_init_rfcsr_3572
rt3593_post_bbp_init
rt2800_init_rfcsr_3593
rt2800_init_rfcsr_5350
rt2800_init_rfcsr_3883
rt2800_init_rfcsr_5390
rt2800_init_rfcsr_5392
rt2800_init_rfcsr_5592
rt2800_bbp_core_soft_reset
rt2800_rf_lp_config
rt2800_lp_tx_filter_bw_cal
rt2800_bw_filter_calibration
rt2800_init_rfcsr_6352
rt2800_init_rfcsr
rt2800_enable_radio
rt2800_disable_radio
rt2800_efuse_detect
rt2800_efuse_read
rt2800_read_eeprom_efuse
rt2800_get_txmixer_gain_24g
rt2800_get_txmixer_gain_5g
rt2800_validate_eeprom
rt2800_init_eeprom
rt2800_probe_hw_mode
rt2800_probe_rt
rt2800_probe_hw
rt2800_get_key_seq
rt2800_set_rts_threshold
rt2800_conf_tx
rt2800_get_tsf
rt2800_ampdu_action
rt2800_get_survey
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   4         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   5         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   6         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   7 
   8         Based on the original rt2800pci.c and rt2800usb.c.
   9           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
  10           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  11           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  12           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  13           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  14           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  15           <http://rt2x00.serialmonkey.com>
  16 
  17  */
  18 
  19 /*
  20         Module: rt2800lib
  21         Abstract: rt2800 generic device routines.
  22  */
  23 
  24 #include <linux/crc-ccitt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28 
  29 #include "rt2x00.h"
  30 #include "rt2800lib.h"
  31 #include "rt2800.h"
  32 
  33 static bool modparam_watchdog;
  34 module_param_named(watchdog, modparam_watchdog, bool, S_IRUGO);
  35 MODULE_PARM_DESC(watchdog, "Enable watchdog to detect tx/rx hangs and reset hardware if detected");
  36 
  37 /*
  38  * Register access.
  39  * All access to the CSR registers will go through the methods
  40  * rt2800_register_read and rt2800_register_write.
  41  * BBP and RF register require indirect register access,
  42  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  43  * These indirect registers work with busy bits,
  44  * and we will try maximal REGISTER_BUSY_COUNT times to access
  45  * the register while taking a REGISTER_BUSY_DELAY us delay
  46  * between each attampt. When the busy bit is still set at that time,
  47  * the access attempt is considered to have failed,
  48  * and we will print an error.
  49  * The _lock versions must be used if you already hold the csr_mutex
  50  */
  51 #define WAIT_FOR_BBP(__dev, __reg) \
  52         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  53 #define WAIT_FOR_RFCSR(__dev, __reg) \
  54         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  55 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
  56         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
  57                             (__reg))
  58 #define WAIT_FOR_RF(__dev, __reg) \
  59         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  60 #define WAIT_FOR_MCU(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  62                             H2M_MAILBOX_CSR_OWNER, (__reg))
  63 
  64 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  65 {
  66         /* check for rt2872 on SoC */
  67         if (!rt2x00_is_soc(rt2x00dev) ||
  68             !rt2x00_rt(rt2x00dev, RT2872))
  69                 return false;
  70 
  71         /* we know for sure that these rf chipsets are used on rt305x boards */
  72         if (rt2x00_rf(rt2x00dev, RF3020) ||
  73             rt2x00_rf(rt2x00dev, RF3021) ||
  74             rt2x00_rf(rt2x00dev, RF3022))
  75                 return true;
  76 
  77         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  78         return false;
  79 }
  80 
  81 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  82                              const unsigned int word, const u8 value)
  83 {
  84         u32 reg;
  85 
  86         mutex_lock(&rt2x00dev->csr_mutex);
  87 
  88         /*
  89          * Wait until the BBP becomes available, afterwards we
  90          * can safely write the new data into the register.
  91          */
  92         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  93                 reg = 0;
  94                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  95                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  96                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  97                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  98                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  99 
 100                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 101         }
 102 
 103         mutex_unlock(&rt2x00dev->csr_mutex);
 104 }
 105 
 106 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
 107 {
 108         u32 reg;
 109         u8 value;
 110 
 111         mutex_lock(&rt2x00dev->csr_mutex);
 112 
 113         /*
 114          * Wait until the BBP becomes available, afterwards we
 115          * can safely write the read request into the register.
 116          * After the data has been written, we wait until hardware
 117          * returns the correct value, if at any time the register
 118          * doesn't become available in time, reg will be 0xffffffff
 119          * which means we return 0xff to the caller.
 120          */
 121         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 122                 reg = 0;
 123                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 124                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 125                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 126                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 127 
 128                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 129 
 130                 WAIT_FOR_BBP(rt2x00dev, &reg);
 131         }
 132 
 133         value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 134 
 135         mutex_unlock(&rt2x00dev->csr_mutex);
 136 
 137         return value;
 138 }
 139 
 140 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 141                                const unsigned int word, const u8 value)
 142 {
 143         u32 reg;
 144 
 145         mutex_lock(&rt2x00dev->csr_mutex);
 146 
 147         /*
 148          * Wait until the RFCSR becomes available, afterwards we
 149          * can safely write the new data into the register.
 150          */
 151         switch (rt2x00dev->chip.rt) {
 152         case RT6352:
 153                 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 154                         reg = 0;
 155                         rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
 156                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 157                                            word);
 158                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
 159                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 160 
 161                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 162                 }
 163                 break;
 164 
 165         default:
 166                 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 167                         reg = 0;
 168                         rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 169                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 170                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 171                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 172 
 173                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 174                 }
 175                 break;
 176         }
 177 
 178         mutex_unlock(&rt2x00dev->csr_mutex);
 179 }
 180 
 181 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 182                                     const unsigned int reg, const u8 value)
 183 {
 184         rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
 185 }
 186 
 187 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
 188                                        const unsigned int reg, const u8 value)
 189 {
 190         rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
 191         rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
 192 }
 193 
 194 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
 195                                      const unsigned int reg, const u8 value)
 196 {
 197         rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
 198         rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
 199 }
 200 
 201 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 202                             const unsigned int word)
 203 {
 204         u32 reg;
 205         u8 value;
 206 
 207         mutex_lock(&rt2x00dev->csr_mutex);
 208 
 209         /*
 210          * Wait until the RFCSR becomes available, afterwards we
 211          * can safely write the read request into the register.
 212          * After the data has been written, we wait until hardware
 213          * returns the correct value, if at any time the register
 214          * doesn't become available in time, reg will be 0xffffffff
 215          * which means we return 0xff to the caller.
 216          */
 217         switch (rt2x00dev->chip.rt) {
 218         case RT6352:
 219                 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 220                         reg = 0;
 221                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 222                                            word);
 223                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
 224                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 225 
 226                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 227 
 228                         WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
 229                 }
 230 
 231                 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
 232                 break;
 233 
 234         default:
 235                 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 236                         reg = 0;
 237                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 238                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 239                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 240 
 241                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 242 
 243                         WAIT_FOR_RFCSR(rt2x00dev, &reg);
 244                 }
 245 
 246                 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 247                 break;
 248         }
 249 
 250         mutex_unlock(&rt2x00dev->csr_mutex);
 251 
 252         return value;
 253 }
 254 
 255 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 256                                  const unsigned int reg)
 257 {
 258         return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
 259 }
 260 
 261 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 262                             const unsigned int word, const u32 value)
 263 {
 264         u32 reg;
 265 
 266         mutex_lock(&rt2x00dev->csr_mutex);
 267 
 268         /*
 269          * Wait until the RF becomes available, afterwards we
 270          * can safely write the new data into the register.
 271          */
 272         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 273                 reg = 0;
 274                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 275                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 276                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 277                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 278 
 279                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 280                 rt2x00_rf_write(rt2x00dev, word, value);
 281         }
 282 
 283         mutex_unlock(&rt2x00dev->csr_mutex);
 284 }
 285 
 286 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 287         [EEPROM_CHIP_ID]                = 0x0000,
 288         [EEPROM_VERSION]                = 0x0001,
 289         [EEPROM_MAC_ADDR_0]             = 0x0002,
 290         [EEPROM_MAC_ADDR_1]             = 0x0003,
 291         [EEPROM_MAC_ADDR_2]             = 0x0004,
 292         [EEPROM_NIC_CONF0]              = 0x001a,
 293         [EEPROM_NIC_CONF1]              = 0x001b,
 294         [EEPROM_FREQ]                   = 0x001d,
 295         [EEPROM_LED_AG_CONF]            = 0x001e,
 296         [EEPROM_LED_ACT_CONF]           = 0x001f,
 297         [EEPROM_LED_POLARITY]           = 0x0020,
 298         [EEPROM_NIC_CONF2]              = 0x0021,
 299         [EEPROM_LNA]                    = 0x0022,
 300         [EEPROM_RSSI_BG]                = 0x0023,
 301         [EEPROM_RSSI_BG2]               = 0x0024,
 302         [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 303         [EEPROM_RSSI_A]                 = 0x0025,
 304         [EEPROM_RSSI_A2]                = 0x0026,
 305         [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 306         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 307         [EEPROM_TXPOWER_DELTA]          = 0x0028,
 308         [EEPROM_TXPOWER_BG1]            = 0x0029,
 309         [EEPROM_TXPOWER_BG2]            = 0x0030,
 310         [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 311         [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 312         [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 313         [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 314         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 315         [EEPROM_TXPOWER_A1]             = 0x003c,
 316         [EEPROM_TXPOWER_A2]             = 0x0053,
 317         [EEPROM_TXPOWER_INIT]           = 0x0068,
 318         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 319         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 320         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 321         [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 322         [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 323         [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 324         [EEPROM_BBP_START]              = 0x0078,
 325 };
 326 
 327 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 328         [EEPROM_CHIP_ID]                = 0x0000,
 329         [EEPROM_VERSION]                = 0x0001,
 330         [EEPROM_MAC_ADDR_0]             = 0x0002,
 331         [EEPROM_MAC_ADDR_1]             = 0x0003,
 332         [EEPROM_MAC_ADDR_2]             = 0x0004,
 333         [EEPROM_NIC_CONF0]              = 0x001a,
 334         [EEPROM_NIC_CONF1]              = 0x001b,
 335         [EEPROM_NIC_CONF2]              = 0x001c,
 336         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 337         [EEPROM_FREQ]                   = 0x0022,
 338         [EEPROM_LED_AG_CONF]            = 0x0023,
 339         [EEPROM_LED_ACT_CONF]           = 0x0024,
 340         [EEPROM_LED_POLARITY]           = 0x0025,
 341         [EEPROM_LNA]                    = 0x0026,
 342         [EEPROM_EXT_LNA2]               = 0x0027,
 343         [EEPROM_RSSI_BG]                = 0x0028,
 344         [EEPROM_RSSI_BG2]               = 0x0029,
 345         [EEPROM_RSSI_A]                 = 0x002a,
 346         [EEPROM_RSSI_A2]                = 0x002b,
 347         [EEPROM_TXPOWER_BG1]            = 0x0030,
 348         [EEPROM_TXPOWER_BG2]            = 0x0037,
 349         [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 350         [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 351         [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 352         [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 353         [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 354         [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 355         [EEPROM_TXPOWER_A1]             = 0x004b,
 356         [EEPROM_TXPOWER_A2]             = 0x0065,
 357         [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 358         [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 359         [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 360         [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 361         [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 362         [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 363         [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 364 };
 365 
 366 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 367                                              const enum rt2800_eeprom_word word)
 368 {
 369         const unsigned int *map;
 370         unsigned int index;
 371 
 372         if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 373                       "%s: invalid EEPROM word %d\n",
 374                       wiphy_name(rt2x00dev->hw->wiphy), word))
 375                 return 0;
 376 
 377         if (rt2x00_rt(rt2x00dev, RT3593) ||
 378             rt2x00_rt(rt2x00dev, RT3883))
 379                 map = rt2800_eeprom_map_ext;
 380         else
 381                 map = rt2800_eeprom_map;
 382 
 383         index = map[word];
 384 
 385         /* Index 0 is valid only for EEPROM_CHIP_ID.
 386          * Otherwise it means that the offset of the
 387          * given word is not initialized in the map,
 388          * or that the field is not usable on the
 389          * actual chipset.
 390          */
 391         WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
 392                   "%s: invalid access of EEPROM word %d\n",
 393                   wiphy_name(rt2x00dev->hw->wiphy), word);
 394 
 395         return index;
 396 }
 397 
 398 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
 399                                 const enum rt2800_eeprom_word word)
 400 {
 401         unsigned int index;
 402 
 403         index = rt2800_eeprom_word_index(rt2x00dev, word);
 404         return rt2x00_eeprom_addr(rt2x00dev, index);
 405 }
 406 
 407 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
 408                               const enum rt2800_eeprom_word word)
 409 {
 410         unsigned int index;
 411 
 412         index = rt2800_eeprom_word_index(rt2x00dev, word);
 413         return rt2x00_eeprom_read(rt2x00dev, index);
 414 }
 415 
 416 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
 417                                 const enum rt2800_eeprom_word word, u16 data)
 418 {
 419         unsigned int index;
 420 
 421         index = rt2800_eeprom_word_index(rt2x00dev, word);
 422         rt2x00_eeprom_write(rt2x00dev, index, data);
 423 }
 424 
 425 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
 426                                          const enum rt2800_eeprom_word array,
 427                                          unsigned int offset)
 428 {
 429         unsigned int index;
 430 
 431         index = rt2800_eeprom_word_index(rt2x00dev, array);
 432         return rt2x00_eeprom_read(rt2x00dev, index + offset);
 433 }
 434 
 435 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 436 {
 437         u32 reg;
 438         int i, count;
 439 
 440         reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
 441         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 442         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 443         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 444         rt2x00_set_field32(&reg, WLAN_EN, 1);
 445         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 446 
 447         udelay(REGISTER_BUSY_DELAY);
 448 
 449         count = 0;
 450         do {
 451                 /*
 452                  * Check PLL_LD & XTAL_RDY.
 453                  */
 454                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 455                         reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
 456                         if (rt2x00_get_field32(reg, PLL_LD) &&
 457                             rt2x00_get_field32(reg, XTAL_RDY))
 458                                 break;
 459                         udelay(REGISTER_BUSY_DELAY);
 460                 }
 461 
 462                 if (i >= REGISTER_BUSY_COUNT) {
 463 
 464                         if (count >= 10)
 465                                 return -EIO;
 466 
 467                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 468                         udelay(REGISTER_BUSY_DELAY);
 469                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 470                         udelay(REGISTER_BUSY_DELAY);
 471                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 472                         udelay(REGISTER_BUSY_DELAY);
 473                         count++;
 474                 } else {
 475                         count = 0;
 476                 }
 477 
 478                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
 479                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 480                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 481                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 482                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 483                 udelay(10);
 484                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 485                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 486                 udelay(10);
 487                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 488         } while (count != 0);
 489 
 490         return 0;
 491 }
 492 
 493 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 494                         const u8 command, const u8 token,
 495                         const u8 arg0, const u8 arg1)
 496 {
 497         u32 reg;
 498 
 499         /*
 500          * SOC devices don't support MCU requests.
 501          */
 502         if (rt2x00_is_soc(rt2x00dev))
 503                 return;
 504 
 505         mutex_lock(&rt2x00dev->csr_mutex);
 506 
 507         /*
 508          * Wait until the MCU becomes available, afterwards we
 509          * can safely write the new data into the register.
 510          */
 511         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 512                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 513                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 514                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 515                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 516                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 517 
 518                 reg = 0;
 519                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 520                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 521         }
 522 
 523         mutex_unlock(&rt2x00dev->csr_mutex);
 524 }
 525 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 526 
 527 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 528 {
 529         unsigned int i = 0;
 530         u32 reg;
 531 
 532         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 533                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
 534                 if (reg && reg != ~0)
 535                         return 0;
 536                 msleep(1);
 537         }
 538 
 539         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 540         return -EBUSY;
 541 }
 542 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 543 
 544 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 545 {
 546         unsigned int i;
 547         u32 reg;
 548 
 549         /*
 550          * Some devices are really slow to respond here. Wait a whole second
 551          * before timing out.
 552          */
 553         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 554                 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
 555                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 556                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 557                         return 0;
 558 
 559                 msleep(10);
 560         }
 561 
 562         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 563         return -EACCES;
 564 }
 565 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 566 
 567 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 568 {
 569         u32 reg;
 570 
 571         reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
 572         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 573         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 574         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 575         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 576         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 577         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 578 }
 579 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 580 
 581 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
 582                                unsigned short *txwi_size,
 583                                unsigned short *rxwi_size)
 584 {
 585         switch (rt2x00dev->chip.rt) {
 586         case RT3593:
 587         case RT3883:
 588                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 589                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 590                 break;
 591 
 592         case RT5592:
 593         case RT6352:
 594                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 595                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 596                 break;
 597 
 598         default:
 599                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 600                 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 601                 break;
 602         }
 603 }
 604 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
 605 
 606 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 607 {
 608         u16 fw_crc;
 609         u16 crc;
 610 
 611         /*
 612          * The last 2 bytes in the firmware array are the crc checksum itself,
 613          * this means that we should never pass those 2 bytes to the crc
 614          * algorithm.
 615          */
 616         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 617 
 618         /*
 619          * Use the crc ccitt algorithm.
 620          * This will return the same value as the legacy driver which
 621          * used bit ordering reversion on the both the firmware bytes
 622          * before input input as well as on the final output.
 623          * Obviously using crc ccitt directly is much more efficient.
 624          */
 625         crc = crc_ccitt(~0, data, len - 2);
 626 
 627         /*
 628          * There is a small difference between the crc-itu-t + bitrev and
 629          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 630          * will be swapped, use swab16 to convert the crc to the correct
 631          * value.
 632          */
 633         crc = swab16(crc);
 634 
 635         return fw_crc == crc;
 636 }
 637 
 638 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 639                           const u8 *data, const size_t len)
 640 {
 641         size_t offset = 0;
 642         size_t fw_len;
 643         bool multiple;
 644 
 645         /*
 646          * PCI(e) & SOC devices require firmware with a length
 647          * of 8kb. USB devices require firmware files with a length
 648          * of 4kb. Certain USB chipsets however require different firmware,
 649          * which Ralink only provides attached to the original firmware
 650          * file. Thus for USB devices, firmware files have a length
 651          * which is a multiple of 4kb. The firmware for rt3290 chip also
 652          * have a length which is a multiple of 4kb.
 653          */
 654         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 655                 fw_len = 4096;
 656         else
 657                 fw_len = 8192;
 658 
 659         multiple = true;
 660         /*
 661          * Validate the firmware length
 662          */
 663         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 664                 return FW_BAD_LENGTH;
 665 
 666         /*
 667          * Check if the chipset requires one of the upper parts
 668          * of the firmware.
 669          */
 670         if (rt2x00_is_usb(rt2x00dev) &&
 671             !rt2x00_rt(rt2x00dev, RT2860) &&
 672             !rt2x00_rt(rt2x00dev, RT2872) &&
 673             !rt2x00_rt(rt2x00dev, RT3070) &&
 674             ((len / fw_len) == 1))
 675                 return FW_BAD_VERSION;
 676 
 677         /*
 678          * 8kb firmware files must be checked as if it were
 679          * 2 separate firmware files.
 680          */
 681         while (offset < len) {
 682                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 683                         return FW_BAD_CRC;
 684 
 685                 offset += fw_len;
 686         }
 687 
 688         return FW_OK;
 689 }
 690 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 691 
 692 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 693                          const u8 *data, const size_t len)
 694 {
 695         unsigned int i;
 696         u32 reg;
 697         int retval;
 698 
 699         if (rt2x00_rt(rt2x00dev, RT3290)) {
 700                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 701                 if (retval)
 702                         return -EBUSY;
 703         }
 704 
 705         /*
 706          * If driver doesn't wake up firmware here,
 707          * rt2800_load_firmware will hang forever when interface is up again.
 708          */
 709         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 710 
 711         /*
 712          * Wait for stable hardware.
 713          */
 714         if (rt2800_wait_csr_ready(rt2x00dev))
 715                 return -EBUSY;
 716 
 717         if (rt2x00_is_pci(rt2x00dev)) {
 718                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 719                     rt2x00_rt(rt2x00dev, RT3572) ||
 720                     rt2x00_rt(rt2x00dev, RT5390) ||
 721                     rt2x00_rt(rt2x00dev, RT5392)) {
 722                         reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
 723                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 724                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 725                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 726                 }
 727                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 728         }
 729 
 730         rt2800_disable_wpdma(rt2x00dev);
 731 
 732         /*
 733          * Write firmware to the device.
 734          */
 735         rt2800_drv_write_firmware(rt2x00dev, data, len);
 736 
 737         /*
 738          * Wait for device to stabilize.
 739          */
 740         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 741                 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
 742                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 743                         break;
 744                 msleep(1);
 745         }
 746 
 747         if (i == REGISTER_BUSY_COUNT) {
 748                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 749                 return -EBUSY;
 750         }
 751 
 752         /*
 753          * Disable DMA, will be reenabled later when enabling
 754          * the radio.
 755          */
 756         rt2800_disable_wpdma(rt2x00dev);
 757 
 758         /*
 759          * Initialize firmware.
 760          */
 761         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 762         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 763         if (rt2x00_is_usb(rt2x00dev)) {
 764                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 765                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 766         }
 767         msleep(1);
 768 
 769         return 0;
 770 }
 771 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 772 
 773 void rt2800_write_tx_data(struct queue_entry *entry,
 774                           struct txentry_desc *txdesc)
 775 {
 776         __le32 *txwi = rt2800_drv_get_txwi(entry);
 777         u32 word;
 778         int i;
 779 
 780         /*
 781          * Initialize TX Info descriptor
 782          */
 783         word = rt2x00_desc_read(txwi, 0);
 784         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 785                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 786         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 787                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 788         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 789         rt2x00_set_field32(&word, TXWI_W0_TS,
 790                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 791         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 792                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 793         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 794                            txdesc->u.ht.mpdu_density);
 795         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 796         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 797         rt2x00_set_field32(&word, TXWI_W0_BW,
 798                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 799         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 800                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 801         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 802         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 803         rt2x00_desc_write(txwi, 0, word);
 804 
 805         word = rt2x00_desc_read(txwi, 1);
 806         rt2x00_set_field32(&word, TXWI_W1_ACK,
 807                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 808         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 809                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 810         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 811         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 812                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 813                            txdesc->key_idx : txdesc->u.ht.wcid);
 814         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 815                            txdesc->length);
 816         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 817         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 818         rt2x00_desc_write(txwi, 1, word);
 819 
 820         /*
 821          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 822          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 823          * When TXD_W3_WIV is set to 1 it will use the IV data
 824          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 825          * crypto entry in the registers should be used to encrypt the frame.
 826          *
 827          * Nulify all remaining words as well, we don't know how to program them.
 828          */
 829         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 830                 _rt2x00_desc_write(txwi, i, 0);
 831 }
 832 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 833 
 834 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 835 {
 836         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 837         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 838         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 839         u16 eeprom;
 840         u8 offset0;
 841         u8 offset1;
 842         u8 offset2;
 843 
 844         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
 845                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
 846                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 847                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 848                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
 849                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 850         } else {
 851                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
 852                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 853                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 854                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
 855                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 856         }
 857 
 858         /*
 859          * Convert the value from the descriptor into the RSSI value
 860          * If the value in the descriptor is 0, it is considered invalid
 861          * and the default (extremely low) rssi value is assumed
 862          */
 863         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 864         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 865         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 866 
 867         /*
 868          * mac80211 only accepts a single RSSI value. Calculating the
 869          * average doesn't deliver a fair answer either since -60:-60 would
 870          * be considered equally good as -50:-70 while the second is the one
 871          * which gives less energy...
 872          */
 873         rssi0 = max(rssi0, rssi1);
 874         return (int)max(rssi0, rssi2);
 875 }
 876 
 877 void rt2800_process_rxwi(struct queue_entry *entry,
 878                          struct rxdone_entry_desc *rxdesc)
 879 {
 880         __le32 *rxwi = (__le32 *) entry->skb->data;
 881         u32 word;
 882 
 883         word = rt2x00_desc_read(rxwi, 0);
 884 
 885         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 886         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 887 
 888         word = rt2x00_desc_read(rxwi, 1);
 889 
 890         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 891                 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
 892 
 893         if (rt2x00_get_field32(word, RXWI_W1_BW))
 894                 rxdesc->bw = RATE_INFO_BW_40;
 895 
 896         /*
 897          * Detect RX rate, always use MCS as signal type.
 898          */
 899         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 900         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 901         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 902 
 903         /*
 904          * Mask of 0x8 bit to remove the short preamble flag.
 905          */
 906         if (rxdesc->rate_mode == RATE_MODE_CCK)
 907                 rxdesc->signal &= ~0x8;
 908 
 909         word = rt2x00_desc_read(rxwi, 2);
 910 
 911         /*
 912          * Convert descriptor AGC value to RSSI value.
 913          */
 914         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 915         /*
 916          * Remove RXWI descriptor from start of the buffer.
 917          */
 918         skb_pull(entry->skb, entry->queue->winfo_size);
 919 }
 920 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 921 
 922 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
 923                                     u32 status, enum nl80211_band band)
 924 {
 925         u8 flags = 0;
 926         u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 927 
 928         switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
 929         case RATE_MODE_HT_GREENFIELD:
 930                 flags |= IEEE80211_TX_RC_GREEN_FIELD;
 931                 /* fall through */
 932         case RATE_MODE_HT_MIX:
 933                 flags |= IEEE80211_TX_RC_MCS;
 934                 break;
 935         case RATE_MODE_OFDM:
 936                 if (band == NL80211_BAND_2GHZ)
 937                         idx += 4;
 938                 break;
 939         case RATE_MODE_CCK:
 940                 if (idx >= 8)
 941                         idx -= 8;
 942                 break;
 943         }
 944 
 945         if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
 946                 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
 947 
 948         if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
 949                 flags |= IEEE80211_TX_RC_SHORT_GI;
 950 
 951         skbdesc->tx_rate_idx = idx;
 952         skbdesc->tx_rate_flags = flags;
 953 }
 954 
 955 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
 956 {
 957         __le32 *txwi;
 958         u32 word;
 959         int wcid, ack, pid;
 960         int tx_wcid, tx_ack, tx_pid, is_agg;
 961 
 962         /*
 963          * This frames has returned with an IO error,
 964          * so the status report is not intended for this
 965          * frame.
 966          */
 967         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
 968                 return false;
 969 
 970         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 971         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 972         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 973         is_agg  = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE);
 974 
 975         /*
 976          * Validate if this TX status report is intended for
 977          * this entry by comparing the WCID/ACK/PID fields.
 978          */
 979         txwi = rt2800_drv_get_txwi(entry);
 980 
 981         word = rt2x00_desc_read(txwi, 1);
 982         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 983         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 984         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 985 
 986         if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) {
 987                 rt2x00_dbg(entry->queue->rt2x00dev,
 988                            "TX status report missed for queue %d entry %d\n",
 989                            entry->queue->qid, entry->entry_idx);
 990                 return false;
 991         }
 992 
 993         return true;
 994 }
 995 
 996 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
 997                          bool match)
 998 {
 999         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1000         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1001         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1002         struct txdone_entry_desc txdesc;
1003         u32 word;
1004         u16 mcs, real_mcs;
1005         int aggr, ampdu, wcid, ack_req;
1006 
1007         /*
1008          * Obtain the status about this packet.
1009          */
1010         txdesc.flags = 0;
1011         word = rt2x00_desc_read(txwi, 0);
1012 
1013         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1014         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
1015 
1016         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
1017         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
1018         wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
1019         ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
1020 
1021         /*
1022          * If a frame was meant to be sent as a single non-aggregated MPDU
1023          * but ended up in an aggregate the used tx rate doesn't correlate
1024          * with the one specified in the TXWI as the whole aggregate is sent
1025          * with the same rate.
1026          *
1027          * For example: two frames are sent to rt2x00, the first one sets
1028          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
1029          * and requests MCS15. If the hw aggregates both frames into one
1030          * AMDPU the tx status for both frames will contain MCS7 although
1031          * the frame was sent successfully.
1032          *
1033          * Hence, replace the requested rate with the real tx rate to not
1034          * confuse the rate control algortihm by providing clearly wrong
1035          * data.
1036          *
1037          * FIXME: if we do not find matching entry, we tell that frame was
1038          * posted without any retries. We need to find a way to fix that
1039          * and provide retry count.
1040          */
1041         if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
1042                 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1043                 mcs = real_mcs;
1044         }
1045 
1046         if (aggr == 1 || ampdu == 1)
1047                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
1048 
1049         if (!ack_req)
1050                 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1051 
1052         /*
1053          * Ralink has a retry mechanism using a global fallback
1054          * table. We setup this fallback table to try the immediate
1055          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1056          * always contains the MCS used for the last transmission, be
1057          * it successful or not.
1058          */
1059         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1060                 /*
1061                  * Transmission succeeded. The number of retries is
1062                  * mcs - real_mcs
1063                  */
1064                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1065                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1066         } else {
1067                 /*
1068                  * Transmission failed. The number of retries is
1069                  * always 7 in this case (for a total number of 8
1070                  * frames sent).
1071                  */
1072                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1073                 txdesc.retry = rt2x00dev->long_retry;
1074         }
1075 
1076         /*
1077          * the frame was retried at least once
1078          * -> hw used fallback rates
1079          */
1080         if (txdesc.retry)
1081                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1082 
1083         if (!match) {
1084                 /* RCU assures non-null sta will not be freed by mac80211. */
1085                 rcu_read_lock();
1086                 if (likely(wcid >= WCID_START && wcid <= WCID_END))
1087                         skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1088                 else
1089                         skbdesc->sta = NULL;
1090                 rt2x00lib_txdone_nomatch(entry, &txdesc);
1091                 rcu_read_unlock();
1092         } else {
1093                 rt2x00lib_txdone(entry, &txdesc);
1094         }
1095 }
1096 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1097 
1098 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)
1099 {
1100         struct data_queue *queue;
1101         struct queue_entry *entry;
1102         u32 reg;
1103         u8 qid;
1104         bool match;
1105 
1106         while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
1107                 /*
1108                  * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is
1109                  * guaranteed to be one of the TX QIDs .
1110                  */
1111                 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
1112                 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
1113 
1114                 if (unlikely(rt2x00queue_empty(queue))) {
1115                         rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
1116                                    qid);
1117                         break;
1118                 }
1119 
1120                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1121 
1122                 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1123                              !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) {
1124                         rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
1125                                     entry->entry_idx, qid);
1126                         break;
1127                 }
1128 
1129                 match = rt2800_txdone_entry_check(entry, reg);
1130                 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match);
1131         }
1132 }
1133 EXPORT_SYMBOL_GPL(rt2800_txdone);
1134 
1135 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
1136                                                  struct queue_entry *entry)
1137 {
1138         bool ret;
1139         unsigned long tout;
1140 
1141         if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1142                 return false;
1143 
1144         if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1145                 tout = msecs_to_jiffies(50);
1146         else
1147                 tout = msecs_to_jiffies(2000);
1148 
1149         ret = time_after(jiffies, entry->last_action + tout);
1150         if (unlikely(ret))
1151                 rt2x00_dbg(entry->queue->rt2x00dev,
1152                            "TX status timeout for entry %d in queue %d\n",
1153                            entry->entry_idx, entry->queue->qid);
1154         return ret;
1155 }
1156 
1157 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
1158 {
1159         struct data_queue *queue;
1160         struct queue_entry *entry;
1161 
1162         tx_queue_for_each(rt2x00dev, queue) {
1163                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1164                 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1165                         return true;
1166         }
1167 
1168         return false;
1169 }
1170 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout);
1171 
1172 /*
1173  * test if there is an entry in any TX queue for which DMA is done
1174  * but the TX status has not been returned yet
1175  */
1176 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)
1177 {
1178         struct data_queue *queue;
1179 
1180         tx_queue_for_each(rt2x00dev, queue) {
1181                 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) !=
1182                     rt2x00queue_get_entry(queue, Q_INDEX_DONE))
1183                         return true;
1184         }
1185         return false;
1186 }
1187 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending);
1188 
1189 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
1190 {
1191         struct data_queue *queue;
1192         struct queue_entry *entry;
1193 
1194         /*
1195          * Process any trailing TX status reports for IO failures,
1196          * we loop until we find the first non-IO error entry. This
1197          * can either be a frame which is free, is being uploaded,
1198          * or has completed the upload but didn't have an entry
1199          * in the TX_STAT_FIFO register yet.
1200          */
1201         tx_queue_for_each(rt2x00dev, queue) {
1202                 while (!rt2x00queue_empty(queue)) {
1203                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1204 
1205                         if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1206                             !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1207                                 break;
1208 
1209                         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) ||
1210                             rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1211                                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
1212                         else
1213                                 break;
1214                 }
1215         }
1216 }
1217 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus);
1218 
1219 static int rt2800_check_hung(struct data_queue *queue)
1220 {
1221         unsigned int cur_idx = rt2800_drv_get_dma_done(queue);
1222 
1223         if (queue->wd_idx != cur_idx)
1224                 queue->wd_count = 0;
1225         else
1226                 queue->wd_count++;
1227 
1228         return queue->wd_count > 16;
1229 }
1230 
1231 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev)
1232 {
1233         struct data_queue *queue;
1234         bool hung_tx = false;
1235         bool hung_rx = false;
1236 
1237         if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
1238                 return;
1239 
1240         queue_for_each(rt2x00dev, queue) {
1241                 switch (queue->qid) {
1242                 case QID_AC_VO:
1243                 case QID_AC_VI:
1244                 case QID_AC_BE:
1245                 case QID_AC_BK:
1246                 case QID_MGMT:
1247                         if (rt2x00queue_empty(queue))
1248                                 continue;
1249                         hung_tx = rt2800_check_hung(queue);
1250                         break;
1251                 case QID_RX:
1252                         /* For station mode we should reactive at least
1253                          * beacons. TODO: need to find good way detect
1254                          * RX hung for AP mode.
1255                          */
1256                         if (rt2x00dev->intf_sta_count == 0)
1257                                 continue;
1258                         hung_rx = rt2800_check_hung(queue);
1259                         break;
1260                 default:
1261                         break;
1262                 }
1263         }
1264 
1265         if (hung_tx)
1266                 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n");
1267 
1268         if (hung_rx)
1269                 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n");
1270 
1271         if (hung_tx || hung_rx)
1272                 ieee80211_restart_hw(rt2x00dev->hw);
1273 }
1274 EXPORT_SYMBOL_GPL(rt2800_watchdog);
1275 
1276 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1277                                           unsigned int index)
1278 {
1279         return HW_BEACON_BASE(index);
1280 }
1281 
1282 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1283                                           unsigned int index)
1284 {
1285         return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1286 }
1287 
1288 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1289 {
1290         struct data_queue *queue = rt2x00dev->bcn;
1291         struct queue_entry *entry;
1292         int i, bcn_num = 0;
1293         u64 off, reg = 0;
1294         u32 bssid_dw1;
1295 
1296         /*
1297          * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1298          */
1299         for (i = 0; i < queue->limit; i++) {
1300                 entry = &queue->entries[i];
1301                 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1302                         continue;
1303                 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1304                 reg |= off << (8 * bcn_num);
1305                 bcn_num++;
1306         }
1307 
1308         rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1309         rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1310 
1311         /*
1312          * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1313          */
1314         bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1315         rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1316                            bcn_num > 0 ? bcn_num - 1 : 0);
1317         rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1318 }
1319 
1320 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1321 {
1322         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1323         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1324         unsigned int beacon_base;
1325         unsigned int padding_len;
1326         u32 orig_reg, reg;
1327         const int txwi_desc_size = entry->queue->winfo_size;
1328 
1329         /*
1330          * Disable beaconing while we are reloading the beacon data,
1331          * otherwise we might be sending out invalid data.
1332          */
1333         reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1334         orig_reg = reg;
1335         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1336         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1337 
1338         /*
1339          * Add space for the TXWI in front of the skb.
1340          */
1341         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1342 
1343         /*
1344          * Register descriptor details in skb frame descriptor.
1345          */
1346         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1347         skbdesc->desc = entry->skb->data;
1348         skbdesc->desc_len = txwi_desc_size;
1349 
1350         /*
1351          * Add the TXWI for the beacon to the skb.
1352          */
1353         rt2800_write_tx_data(entry, txdesc);
1354 
1355         /*
1356          * Dump beacon to userspace through debugfs.
1357          */
1358         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1359 
1360         /*
1361          * Write entire beacon with TXWI and padding to register.
1362          */
1363         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1364         if (padding_len && skb_pad(entry->skb, padding_len)) {
1365                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1366                 /* skb freed by skb_pad() on failure */
1367                 entry->skb = NULL;
1368                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1369                 return;
1370         }
1371 
1372         beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1373 
1374         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1375                                    entry->skb->len + padding_len);
1376         __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1377 
1378         /*
1379          * Change global beacons settings.
1380          */
1381         rt2800_update_beacons_setup(rt2x00dev);
1382 
1383         /*
1384          * Restore beaconing state.
1385          */
1386         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1387 
1388         /*
1389          * Clean up beacon skb.
1390          */
1391         dev_kfree_skb_any(entry->skb);
1392         entry->skb = NULL;
1393 }
1394 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1395 
1396 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1397                                                 unsigned int index)
1398 {
1399         int i;
1400         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1401         unsigned int beacon_base;
1402 
1403         beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1404 
1405         /*
1406          * For the Beacon base registers we only need to clear
1407          * the whole TXWI which (when set to 0) will invalidate
1408          * the entire beacon.
1409          */
1410         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1411                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1412 }
1413 
1414 void rt2800_clear_beacon(struct queue_entry *entry)
1415 {
1416         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1417         u32 orig_reg, reg;
1418 
1419         /*
1420          * Disable beaconing while we are reloading the beacon data,
1421          * otherwise we might be sending out invalid data.
1422          */
1423         orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1424         reg = orig_reg;
1425         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1426         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1427 
1428         /*
1429          * Clear beacon.
1430          */
1431         rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1432         __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1433 
1434         /*
1435          * Change global beacons settings.
1436          */
1437         rt2800_update_beacons_setup(rt2x00dev);
1438         /*
1439          * Restore beaconing state.
1440          */
1441         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1442 }
1443 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1444 
1445 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1446 const struct rt2x00debug rt2800_rt2x00debug = {
1447         .owner  = THIS_MODULE,
1448         .csr    = {
1449                 .read           = rt2800_register_read,
1450                 .write          = rt2800_register_write,
1451                 .flags          = RT2X00DEBUGFS_OFFSET,
1452                 .word_base      = CSR_REG_BASE,
1453                 .word_size      = sizeof(u32),
1454                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1455         },
1456         .eeprom = {
1457                 /* NOTE: The local EEPROM access functions can't
1458                  * be used here, use the generic versions instead.
1459                  */
1460                 .read           = rt2x00_eeprom_read,
1461                 .write          = rt2x00_eeprom_write,
1462                 .word_base      = EEPROM_BASE,
1463                 .word_size      = sizeof(u16),
1464                 .word_count     = EEPROM_SIZE / sizeof(u16),
1465         },
1466         .bbp    = {
1467                 .read           = rt2800_bbp_read,
1468                 .write          = rt2800_bbp_write,
1469                 .word_base      = BBP_BASE,
1470                 .word_size      = sizeof(u8),
1471                 .word_count     = BBP_SIZE / sizeof(u8),
1472         },
1473         .rf     = {
1474                 .read           = rt2x00_rf_read,
1475                 .write          = rt2800_rf_write,
1476                 .word_base      = RF_BASE,
1477                 .word_size      = sizeof(u32),
1478                 .word_count     = RF_SIZE / sizeof(u32),
1479         },
1480         .rfcsr  = {
1481                 .read           = rt2800_rfcsr_read,
1482                 .write          = rt2800_rfcsr_write,
1483                 .word_base      = RFCSR_BASE,
1484                 .word_size      = sizeof(u8),
1485                 .word_count     = RFCSR_SIZE / sizeof(u8),
1486         },
1487 };
1488 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1489 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1490 
1491 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1492 {
1493         u32 reg;
1494 
1495         if (rt2x00_rt(rt2x00dev, RT3290)) {
1496                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1497                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1498         } else {
1499                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1500                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1501         }
1502 }
1503 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1504 
1505 #ifdef CONFIG_RT2X00_LIB_LEDS
1506 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1507                                   enum led_brightness brightness)
1508 {
1509         struct rt2x00_led *led =
1510             container_of(led_cdev, struct rt2x00_led, led_dev);
1511         unsigned int enabled = brightness != LED_OFF;
1512         unsigned int bg_mode =
1513             (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1514         unsigned int polarity =
1515                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1516                                    EEPROM_FREQ_LED_POLARITY);
1517         unsigned int ledmode =
1518                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1519                                    EEPROM_FREQ_LED_MODE);
1520         u32 reg;
1521 
1522         /* Check for SoC (SOC devices don't support MCU requests) */
1523         if (rt2x00_is_soc(led->rt2x00dev)) {
1524                 reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1525 
1526                 /* Set LED Polarity */
1527                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1528 
1529                 /* Set LED Mode */
1530                 if (led->type == LED_TYPE_RADIO) {
1531                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1532                                            enabled ? 3 : 0);
1533                 } else if (led->type == LED_TYPE_ASSOC) {
1534                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1535                                            enabled ? 3 : 0);
1536                 } else if (led->type == LED_TYPE_QUALITY) {
1537                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1538                                            enabled ? 3 : 0);
1539                 }
1540 
1541                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1542 
1543         } else {
1544                 if (led->type == LED_TYPE_RADIO) {
1545                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1546                                               enabled ? 0x20 : 0);
1547                 } else if (led->type == LED_TYPE_ASSOC) {
1548                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1549                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1550                 } else if (led->type == LED_TYPE_QUALITY) {
1551                         /*
1552                          * The brightness is divided into 6 levels (0 - 5),
1553                          * The specs tell us the following levels:
1554                          *      0, 1 ,3, 7, 15, 31
1555                          * to determine the level in a simple way we can simply
1556                          * work with bitshifting:
1557                          *      (1 << level) - 1
1558                          */
1559                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1560                                               (1 << brightness / (LED_FULL / 6)) - 1,
1561                                               polarity);
1562                 }
1563         }
1564 }
1565 
1566 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1567                      struct rt2x00_led *led, enum led_type type)
1568 {
1569         led->rt2x00dev = rt2x00dev;
1570         led->type = type;
1571         led->led_dev.brightness_set = rt2800_brightness_set;
1572         led->flags = LED_INITIALIZED;
1573 }
1574 #endif /* CONFIG_RT2X00_LIB_LEDS */
1575 
1576 /*
1577  * Configuration handlers.
1578  */
1579 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1580                                const u8 *address,
1581                                int wcid)
1582 {
1583         struct mac_wcid_entry wcid_entry;
1584         u32 offset;
1585 
1586         offset = MAC_WCID_ENTRY(wcid);
1587 
1588         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1589         if (address)
1590                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1591 
1592         rt2800_register_multiwrite(rt2x00dev, offset,
1593                                       &wcid_entry, sizeof(wcid_entry));
1594 }
1595 
1596 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1597 {
1598         u32 offset;
1599         offset = MAC_WCID_ATTR_ENTRY(wcid);
1600         rt2800_register_write(rt2x00dev, offset, 0);
1601 }
1602 
1603 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1604                                            int wcid, u32 bssidx)
1605 {
1606         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1607         u32 reg;
1608 
1609         /*
1610          * The BSS Idx numbers is split in a main value of 3 bits,
1611          * and a extended field for adding one additional bit to the value.
1612          */
1613         reg = rt2800_register_read(rt2x00dev, offset);
1614         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1615         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1616                            (bssidx & 0x8) >> 3);
1617         rt2800_register_write(rt2x00dev, offset, reg);
1618 }
1619 
1620 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1621                                            struct rt2x00lib_crypto *crypto,
1622                                            struct ieee80211_key_conf *key)
1623 {
1624         struct mac_iveiv_entry iveiv_entry;
1625         u32 offset;
1626         u32 reg;
1627 
1628         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1629 
1630         if (crypto->cmd == SET_KEY) {
1631                 reg = rt2800_register_read(rt2x00dev, offset);
1632                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1633                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1634                 /*
1635                  * Both the cipher as the BSS Idx numbers are split in a main
1636                  * value of 3 bits, and a extended field for adding one additional
1637                  * bit to the value.
1638                  */
1639                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1640                                    (crypto->cipher & 0x7));
1641                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1642                                    (crypto->cipher & 0x8) >> 3);
1643                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1644                 rt2800_register_write(rt2x00dev, offset, reg);
1645         } else {
1646                 /* Delete the cipher without touching the bssidx */
1647                 reg = rt2800_register_read(rt2x00dev, offset);
1648                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1649                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1650                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1651                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1652                 rt2800_register_write(rt2x00dev, offset, reg);
1653         }
1654 
1655         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1656 
1657         if (crypto->cmd == SET_KEY) {
1658                 rt2800_register_multiread(rt2x00dev, offset,
1659                                           &iveiv_entry, sizeof(iveiv_entry));
1660                 if ((crypto->cipher == CIPHER_TKIP) ||
1661                     (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1662                     (crypto->cipher == CIPHER_AES))
1663                         iveiv_entry.iv[3] |= 0x20;
1664                 iveiv_entry.iv[3] |= key->keyidx << 6;
1665         } else {
1666                 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1667         }
1668 
1669         rt2800_register_multiwrite(rt2x00dev, offset,
1670                                    &iveiv_entry, sizeof(iveiv_entry));
1671 }
1672 
1673 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1674                              struct rt2x00lib_crypto *crypto,
1675                              struct ieee80211_key_conf *key)
1676 {
1677         struct hw_key_entry key_entry;
1678         struct rt2x00_field32 field;
1679         u32 offset;
1680         u32 reg;
1681 
1682         if (crypto->cmd == SET_KEY) {
1683                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1684 
1685                 memcpy(key_entry.key, crypto->key,
1686                        sizeof(key_entry.key));
1687                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1688                        sizeof(key_entry.tx_mic));
1689                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1690                        sizeof(key_entry.rx_mic));
1691 
1692                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1693                 rt2800_register_multiwrite(rt2x00dev, offset,
1694                                               &key_entry, sizeof(key_entry));
1695         }
1696 
1697         /*
1698          * The cipher types are stored over multiple registers
1699          * starting with SHARED_KEY_MODE_BASE each word will have
1700          * 32 bits and contains the cipher types for 2 bssidx each.
1701          * Using the correct defines correctly will cause overhead,
1702          * so just calculate the correct offset.
1703          */
1704         field.bit_offset = 4 * (key->hw_key_idx % 8);
1705         field.bit_mask = 0x7 << field.bit_offset;
1706 
1707         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1708 
1709         reg = rt2800_register_read(rt2x00dev, offset);
1710         rt2x00_set_field32(&reg, field,
1711                            (crypto->cmd == SET_KEY) * crypto->cipher);
1712         rt2800_register_write(rt2x00dev, offset, reg);
1713 
1714         /*
1715          * Update WCID information
1716          */
1717         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1718         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1719                                        crypto->bssidx);
1720         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1721 
1722         return 0;
1723 }
1724 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1725 
1726 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1727                                struct rt2x00lib_crypto *crypto,
1728                                struct ieee80211_key_conf *key)
1729 {
1730         struct hw_key_entry key_entry;
1731         u32 offset;
1732 
1733         if (crypto->cmd == SET_KEY) {
1734                 /*
1735                  * Allow key configuration only for STAs that are
1736                  * known by the hw.
1737                  */
1738                 if (crypto->wcid > WCID_END)
1739                         return -ENOSPC;
1740                 key->hw_key_idx = crypto->wcid;
1741 
1742                 memcpy(key_entry.key, crypto->key,
1743                        sizeof(key_entry.key));
1744                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1745                        sizeof(key_entry.tx_mic));
1746                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1747                        sizeof(key_entry.rx_mic));
1748 
1749                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1750                 rt2800_register_multiwrite(rt2x00dev, offset,
1751                                               &key_entry, sizeof(key_entry));
1752         }
1753 
1754         /*
1755          * Update WCID information
1756          */
1757         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1758 
1759         return 0;
1760 }
1761 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1762 
1763 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1764 {
1765         u8 i, max_psdu;
1766         u32 reg;
1767         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1768 
1769         for (i = 0; i < 3; i++)
1770                 if (drv_data->ampdu_factor_cnt[i] > 0)
1771                         break;
1772 
1773         max_psdu = min(drv_data->max_psdu, i);
1774 
1775         reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1776         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1777         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1778 }
1779 
1780 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1781                    struct ieee80211_sta *sta)
1782 {
1783         struct rt2x00_dev *rt2x00dev = hw->priv;
1784         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1785         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1786         int wcid;
1787 
1788         /*
1789          * Limit global maximum TX AMPDU length to smallest value of all
1790          * connected stations. In AP mode this can be suboptimal, but we
1791          * do not have a choice if some connected STA is not capable to
1792          * receive the same amount of data like the others.
1793          */
1794         if (sta->ht_cap.ht_supported) {
1795                 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++;
1796                 rt2800_set_max_psdu_len(rt2x00dev);
1797         }
1798 
1799         /*
1800          * Search for the first free WCID entry and return the corresponding
1801          * index.
1802          */
1803         wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1804 
1805         /*
1806          * Store selected wcid even if it is invalid so that we can
1807          * later decide if the STA is uploaded into the hw.
1808          */
1809         sta_priv->wcid = wcid;
1810 
1811         /*
1812          * No space left in the device, however, we can still communicate
1813          * with the STA -> No error.
1814          */
1815         if (wcid > WCID_END)
1816                 return 0;
1817 
1818         __set_bit(wcid - WCID_START, drv_data->sta_ids);
1819         drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1820 
1821         /*
1822          * Clean up WCID attributes and write STA address to the device.
1823          */
1824         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1825         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1826         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1827                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1828         return 0;
1829 }
1830 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1831 
1832 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1833                       struct ieee80211_sta *sta)
1834 {
1835         struct rt2x00_dev *rt2x00dev = hw->priv;
1836         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1837         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1838         int wcid = sta_priv->wcid;
1839 
1840         if (sta->ht_cap.ht_supported) {
1841                 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--;
1842                 rt2800_set_max_psdu_len(rt2x00dev);
1843         }
1844 
1845         if (wcid > WCID_END)
1846                 return 0;
1847         /*
1848          * Remove WCID entry, no need to clean the attributes as they will
1849          * get renewed when the WCID is reused.
1850          */
1851         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1852         drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1853         __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1854 
1855         return 0;
1856 }
1857 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1858 
1859 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev)
1860 {
1861         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1862         struct data_queue *queue = rt2x00dev->bcn;
1863         struct queue_entry *entry;
1864         int i, wcid;
1865 
1866         for (wcid = WCID_START; wcid < WCID_END; wcid++) {
1867                 drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1868                 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1869         }
1870 
1871         for (i = 0; i < queue->limit; i++) {
1872                 entry = &queue->entries[i];
1873                 clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags);
1874         }
1875 }
1876 EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw);
1877 
1878 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1879                           const unsigned int filter_flags)
1880 {
1881         u32 reg;
1882 
1883         /*
1884          * Start configuration steps.
1885          * Note that the version error will always be dropped
1886          * and broadcast frames will always be accepted since
1887          * there is no filter for it at this time.
1888          */
1889         reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1890         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1891                            !(filter_flags & FIF_FCSFAIL));
1892         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1893                            !(filter_flags & FIF_PLCPFAIL));
1894         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1895                            !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1896         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1897         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1898         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1899                            !(filter_flags & FIF_ALLMULTI));
1900         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1901         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1902         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1903                            !(filter_flags & FIF_CONTROL));
1904         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1905                            !(filter_flags & FIF_CONTROL));
1906         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1907                            !(filter_flags & FIF_CONTROL));
1908         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1909                            !(filter_flags & FIF_CONTROL));
1910         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1911                            !(filter_flags & FIF_CONTROL));
1912         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1913                            !(filter_flags & FIF_PSPOLL));
1914         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1915         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1916                            !(filter_flags & FIF_CONTROL));
1917         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1918                            !(filter_flags & FIF_CONTROL));
1919         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1920 }
1921 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1922 
1923 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1924                         struct rt2x00intf_conf *conf, const unsigned int flags)
1925 {
1926         u32 reg;
1927         bool update_bssid = false;
1928 
1929         if (flags & CONFIG_UPDATE_TYPE) {
1930                 /*
1931                  * Enable synchronisation.
1932                  */
1933                 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1934                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1935                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1936 
1937                 if (conf->sync == TSF_SYNC_AP_NONE) {
1938                         /*
1939                          * Tune beacon queue transmit parameters for AP mode
1940                          */
1941                         reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1942                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1943                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1944                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1945                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1946                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1947                 } else {
1948                         reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1949                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1950                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1951                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1952                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1953                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1954                 }
1955         }
1956 
1957         if (flags & CONFIG_UPDATE_MAC) {
1958                 if (flags & CONFIG_UPDATE_TYPE &&
1959                     conf->sync == TSF_SYNC_AP_NONE) {
1960                         /*
1961                          * The BSSID register has to be set to our own mac
1962                          * address in AP mode.
1963                          */
1964                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1965                         update_bssid = true;
1966                 }
1967 
1968                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1969                         reg = le32_to_cpu(conf->mac[1]);
1970                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1971                         conf->mac[1] = cpu_to_le32(reg);
1972                 }
1973 
1974                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1975                                               conf->mac, sizeof(conf->mac));
1976         }
1977 
1978         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1979                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1980                         reg = le32_to_cpu(conf->bssid[1]);
1981                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1982                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
1983                         conf->bssid[1] = cpu_to_le32(reg);
1984                 }
1985 
1986                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1987                                               conf->bssid, sizeof(conf->bssid));
1988         }
1989 }
1990 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1991 
1992 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1993                                     struct rt2x00lib_erp *erp)
1994 {
1995         bool any_sta_nongf = !!(erp->ht_opmode &
1996                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1997         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1998         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1999         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
2000         u32 reg;
2001 
2002         /* default protection rate for HT20: OFDM 24M */
2003         mm20_rate = gf20_rate = 0x4004;
2004 
2005         /* default protection rate for HT40: duplicate OFDM 24M */
2006         mm40_rate = gf40_rate = 0x4084;
2007 
2008         switch (protection) {
2009         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
2010                 /*
2011                  * All STAs in this BSS are HT20/40 but there might be
2012                  * STAs not supporting greenfield mode.
2013                  * => Disable protection for HT transmissions.
2014                  */
2015                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
2016 
2017                 break;
2018         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2019                 /*
2020                  * All STAs in this BSS are HT20 or HT20/40 but there
2021                  * might be STAs not supporting greenfield mode.
2022                  * => Protect all HT40 transmissions.
2023                  */
2024                 mm20_mode = gf20_mode = 0;
2025                 mm40_mode = gf40_mode = 1;
2026 
2027                 break;
2028         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
2029                 /*
2030                  * Nonmember protection:
2031                  * According to 802.11n we _should_ protect all
2032                  * HT transmissions (but we don't have to).
2033                  *
2034                  * But if cts_protection is enabled we _shall_ protect
2035                  * all HT transmissions using a CCK rate.
2036                  *
2037                  * And if any station is non GF we _shall_ protect
2038                  * GF transmissions.
2039                  *
2040                  * We decide to protect everything
2041                  * -> fall through to mixed mode.
2042                  */
2043         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2044                 /*
2045                  * Legacy STAs are present
2046                  * => Protect all HT transmissions.
2047                  */
2048                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
2049 
2050                 /*
2051                  * If erp protection is needed we have to protect HT
2052                  * transmissions with CCK 11M long preamble.
2053                  */
2054                 if (erp->cts_protection) {
2055                         /* don't duplicate RTS/CTS in CCK mode */
2056                         mm20_rate = mm40_rate = 0x0003;
2057                         gf20_rate = gf40_rate = 0x0003;
2058                 }
2059                 break;
2060         }
2061 
2062         /* check for STAs not supporting greenfield mode */
2063         if (any_sta_nongf)
2064                 gf20_mode = gf40_mode = 1;
2065 
2066         /* Update HT protection config */
2067         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
2068         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
2069         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
2070         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2071 
2072         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
2073         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
2074         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
2075         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2076 
2077         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
2078         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
2079         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
2080         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2081 
2082         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
2083         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
2084         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
2085         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2086 }
2087 
2088 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
2089                        u32 changed)
2090 {
2091         u32 reg;
2092 
2093         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2094                 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
2095                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
2096                                    !!erp->short_preamble);
2097                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2098         }
2099 
2100         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2101                 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
2102                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
2103                                    erp->cts_protection ? 2 : 0);
2104                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2105         }
2106 
2107         if (changed & BSS_CHANGED_BASIC_RATES) {
2108                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
2109                                       0xff0 | erp->basic_rates);
2110                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2111         }
2112 
2113         if (changed & BSS_CHANGED_ERP_SLOT) {
2114                 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
2115                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
2116                                    erp->slot_time);
2117                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2118 
2119                 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
2120                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
2121                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2122         }
2123 
2124         if (changed & BSS_CHANGED_BEACON_INT) {
2125                 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2126                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
2127                                    erp->beacon_int * 16);
2128                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2129         }
2130 
2131         if (changed & BSS_CHANGED_HT)
2132                 rt2800_config_ht_opmode(rt2x00dev, erp);
2133 }
2134 EXPORT_SYMBOL_GPL(rt2800_config_erp);
2135 
2136 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
2137 {
2138         u32 reg;
2139         u16 eeprom;
2140         u8 led_ctrl, led_g_mode, led_r_mode;
2141 
2142         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
2143         if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2144                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
2145                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
2146         } else {
2147                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
2148                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
2149         }
2150         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2151 
2152         reg = rt2800_register_read(rt2x00dev, LED_CFG);
2153         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
2154         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
2155         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
2156             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
2157                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
2158                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
2159                 if (led_ctrl == 0 || led_ctrl > 0x40) {
2160                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
2161                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
2162                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2163                 } else {
2164                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
2165                                            (led_g_mode << 2) | led_r_mode, 1);
2166                 }
2167         }
2168 }
2169 
2170 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
2171                                      enum antenna ant)
2172 {
2173         u32 reg;
2174         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
2175         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
2176 
2177         if (rt2x00_is_pci(rt2x00dev)) {
2178                 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
2179                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
2180                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
2181         } else if (rt2x00_is_usb(rt2x00dev))
2182                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
2183                                    eesk_pin, 0);
2184 
2185         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2186         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
2187         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
2188         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2189 }
2190 
2191 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
2192 {
2193         u8 r1;
2194         u8 r3;
2195         u16 eeprom;
2196 
2197         r1 = rt2800_bbp_read(rt2x00dev, 1);
2198         r3 = rt2800_bbp_read(rt2x00dev, 3);
2199 
2200         if (rt2x00_rt(rt2x00dev, RT3572) &&
2201             rt2x00_has_cap_bt_coexist(rt2x00dev))
2202                 rt2800_config_3572bt_ant(rt2x00dev);
2203 
2204         /*
2205          * Configure the TX antenna.
2206          */
2207         switch (ant->tx_chain_num) {
2208         case 1:
2209                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
2210                 break;
2211         case 2:
2212                 if (rt2x00_rt(rt2x00dev, RT3572) &&
2213                     rt2x00_has_cap_bt_coexist(rt2x00dev))
2214                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
2215                 else
2216                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2217                 break;
2218         case 3:
2219                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2220                 break;
2221         }
2222 
2223         /*
2224          * Configure the RX antenna.
2225          */
2226         switch (ant->rx_chain_num) {
2227         case 1:
2228                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2229                     rt2x00_rt(rt2x00dev, RT3090) ||
2230                     rt2x00_rt(rt2x00dev, RT3352) ||
2231                     rt2x00_rt(rt2x00dev, RT3390)) {
2232                         eeprom = rt2800_eeprom_read(rt2x00dev,
2233                                                     EEPROM_NIC_CONF1);
2234                         if (rt2x00_get_field16(eeprom,
2235                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
2236                                 rt2800_set_ant_diversity(rt2x00dev,
2237                                                 rt2x00dev->default_ant.rx);
2238                 }
2239                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
2240                 break;
2241         case 2:
2242                 if (rt2x00_rt(rt2x00dev, RT3572) &&
2243                     rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2244                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2245                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
2246                                 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2247                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2248                 } else {
2249                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2250                 }
2251                 break;
2252         case 3:
2253                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2254                 break;
2255         }
2256 
2257         rt2800_bbp_write(rt2x00dev, 3, r3);
2258         rt2800_bbp_write(rt2x00dev, 1, r1);
2259 
2260         if (rt2x00_rt(rt2x00dev, RT3593) ||
2261             rt2x00_rt(rt2x00dev, RT3883)) {
2262                 if (ant->rx_chain_num == 1)
2263                         rt2800_bbp_write(rt2x00dev, 86, 0x00);
2264                 else
2265                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
2266         }
2267 }
2268 EXPORT_SYMBOL_GPL(rt2800_config_ant);
2269 
2270 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2271                                    struct rt2x00lib_conf *libconf)
2272 {
2273         u16 eeprom;
2274         short lna_gain;
2275 
2276         if (libconf->rf.channel <= 14) {
2277                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2278                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2279         } else if (libconf->rf.channel <= 64) {
2280                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2281                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2282         } else if (libconf->rf.channel <= 128) {
2283                 if (rt2x00_rt(rt2x00dev, RT3593) ||
2284                     rt2x00_rt(rt2x00dev, RT3883)) {
2285                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2286                         lna_gain = rt2x00_get_field16(eeprom,
2287                                                       EEPROM_EXT_LNA2_A1);
2288                 } else {
2289                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2290                         lna_gain = rt2x00_get_field16(eeprom,
2291                                                       EEPROM_RSSI_BG2_LNA_A1);
2292                 }
2293         } else {
2294                 if (rt2x00_rt(rt2x00dev, RT3593) ||
2295                     rt2x00_rt(rt2x00dev, RT3883)) {
2296                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2297                         lna_gain = rt2x00_get_field16(eeprom,
2298                                                       EEPROM_EXT_LNA2_A2);
2299                 } else {
2300                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2301                         lna_gain = rt2x00_get_field16(eeprom,
2302                                                       EEPROM_RSSI_A2_LNA_A2);
2303                 }
2304         }
2305 
2306         rt2x00dev->lna_gain = lna_gain;
2307 }
2308 
2309 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2310 {
2311         return clk_get_rate(rt2x00dev->clk) == 20000000;
2312 }
2313 
2314 #define FREQ_OFFSET_BOUND       0x5f
2315 
2316 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2317 {
2318         u8 freq_offset, prev_freq_offset;
2319         u8 rfcsr, prev_rfcsr;
2320 
2321         freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2322         freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2323 
2324         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2325         prev_rfcsr = rfcsr;
2326 
2327         rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2328         if (rfcsr == prev_rfcsr)
2329                 return;
2330 
2331         if (rt2x00_is_usb(rt2x00dev)) {
2332                 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2333                                    freq_offset, prev_rfcsr);
2334                 return;
2335         }
2336 
2337         prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2338         while (prev_freq_offset != freq_offset) {
2339                 if (prev_freq_offset < freq_offset)
2340                         prev_freq_offset++;
2341                 else
2342                         prev_freq_offset--;
2343 
2344                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2345                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2346 
2347                 usleep_range(1000, 1500);
2348         }
2349 }
2350 
2351 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2352                                          struct ieee80211_conf *conf,
2353                                          struct rf_channel *rf,
2354                                          struct channel_info *info)
2355 {
2356         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2357 
2358         if (rt2x00dev->default_ant.tx_chain_num == 1)
2359                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2360 
2361         if (rt2x00dev->default_ant.rx_chain_num == 1) {
2362                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2363                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2364         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
2365                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2366 
2367         if (rf->channel > 14) {
2368                 /*
2369                  * When TX power is below 0, we should increase it by 7 to
2370                  * make it a positive value (Minimum value is -7).
2371                  * However this means that values between 0 and 7 have
2372                  * double meaning, and we should set a 7DBm boost flag.
2373                  */
2374                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2375                                    (info->default_power1 >= 0));
2376 
2377                 if (info->default_power1 < 0)
2378                         info->default_power1 += 7;
2379 
2380                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2381 
2382                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2383                                    (info->default_power2 >= 0));
2384 
2385                 if (info->default_power2 < 0)
2386                         info->default_power2 += 7;
2387 
2388                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2389         } else {
2390                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2391                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2392         }
2393 
2394         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2395 
2396         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2397         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2398         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2399         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2400 
2401         udelay(200);
2402 
2403         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2404         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2405         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2406         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2407 
2408         udelay(200);
2409 
2410         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2411         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2412         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2413         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2414 }
2415 
2416 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2417                                          struct ieee80211_conf *conf,
2418                                          struct rf_channel *rf,
2419                                          struct channel_info *info)
2420 {
2421         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2422         u8 rfcsr, calib_tx, calib_rx;
2423 
2424         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2425 
2426         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2427         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2428         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2429 
2430         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2431         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2432         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2433 
2434         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2435         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2436         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2437 
2438         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2439         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2440         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2441 
2442         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2443         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2444         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2445                           rt2x00dev->default_ant.rx_chain_num <= 1);
2446         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2447                           rt2x00dev->default_ant.rx_chain_num <= 2);
2448         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2449         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2450                           rt2x00dev->default_ant.tx_chain_num <= 1);
2451         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2452                           rt2x00dev->default_ant.tx_chain_num <= 2);
2453         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2454 
2455         rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2456         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2457         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2458 
2459         if (rt2x00_rt(rt2x00dev, RT3390)) {
2460                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2461                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2462         } else {
2463                 if (conf_is_ht40(conf)) {
2464                         calib_tx = drv_data->calibration_bw40;
2465                         calib_rx = drv_data->calibration_bw40;
2466                 } else {
2467                         calib_tx = drv_data->calibration_bw20;
2468                         calib_rx = drv_data->calibration_bw20;
2469                 }
2470         }
2471 
2472         rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2473         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2474         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2475 
2476         rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2477         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2478         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2479 
2480         rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2481         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2482         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2483 
2484         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2485         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2486         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2487 
2488         usleep_range(1000, 1500);
2489 
2490         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2491         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2492 }
2493 
2494 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2495                                          struct ieee80211_conf *conf,
2496                                          struct rf_channel *rf,
2497                                          struct channel_info *info)
2498 {
2499         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2500         u8 rfcsr;
2501         u32 reg;
2502 
2503         if (rf->channel <= 14) {
2504                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2505                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2506         } else {
2507                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2508                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2509         }
2510 
2511         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2512         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2513 
2514         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2515         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2516         if (rf->channel <= 14)
2517                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2518         else
2519                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2520         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2521 
2522         rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2523         if (rf->channel <= 14)
2524                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2525         else
2526                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2527         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2528 
2529         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2530         if (rf->channel <= 14) {
2531                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2532                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2533                                   info->default_power1);
2534         } else {
2535                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2536                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2537                                 (info->default_power1 & 0x3) |
2538                                 ((info->default_power1 & 0xC) << 1));
2539         }
2540         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2541 
2542         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2543         if (rf->channel <= 14) {
2544                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2545                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2546                                   info->default_power2);
2547         } else {
2548                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2549                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2550                                 (info->default_power2 & 0x3) |
2551                                 ((info->default_power2 & 0xC) << 1));
2552         }
2553         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2554 
2555         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2556         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2557         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2558         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2559         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2560         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2561         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2562         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2563                 if (rf->channel <= 14) {
2564                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2565                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2566                 }
2567                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2568                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2569         } else {
2570                 switch (rt2x00dev->default_ant.tx_chain_num) {
2571                 case 1:
2572                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2573                         /* fall through */
2574                 case 2:
2575                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2576                         break;
2577                 }
2578 
2579                 switch (rt2x00dev->default_ant.rx_chain_num) {
2580                 case 1:
2581                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2582                         /* fall through */
2583                 case 2:
2584                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2585                         break;
2586                 }
2587         }
2588         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2589 
2590         rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2591         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2592         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2593 
2594         if (conf_is_ht40(conf)) {
2595                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2596                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2597         } else {
2598                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2599                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2600         }
2601 
2602         if (rf->channel <= 14) {
2603                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2604                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2605                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2606                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2607                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2608                 rfcsr = 0x4c;
2609                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2610                                   drv_data->txmixer_gain_24g);
2611                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2612                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2613                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2614                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2615                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2616                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2617                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2618                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2619         } else {
2620                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2621                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2622                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2623                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2624                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2625                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2626                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2627                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2628                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2629                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2630                 rfcsr = 0x7a;
2631                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2632                                   drv_data->txmixer_gain_5g);
2633                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2634                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2635                 if (rf->channel <= 64) {
2636                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2637                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2638                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2639                 } else if (rf->channel <= 128) {
2640                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2641                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2642                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2643                 } else {
2644                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2645                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2646                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2647                 }
2648                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2649                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2650                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2651         }
2652 
2653         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2654         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2655         if (rf->channel <= 14)
2656                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2657         else
2658                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2659         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2660 
2661         rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2662         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2663         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2664 }
2665 
2666 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2667                                          struct ieee80211_conf *conf,
2668                                          struct rf_channel *rf,
2669                                          struct channel_info *info)
2670 {
2671         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2672         u8 txrx_agc_fc;
2673         u8 txrx_h20m;
2674         u8 rfcsr;
2675         u8 bbp;
2676         const bool txbf_enabled = false; /* TODO */
2677 
2678         /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2679         bbp = rt2800_bbp_read(rt2x00dev, 109);
2680         rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2681         rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2682         rt2800_bbp_write(rt2x00dev, 109, bbp);
2683 
2684         bbp = rt2800_bbp_read(rt2x00dev, 110);
2685         rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2686         rt2800_bbp_write(rt2x00dev, 110, bbp);
2687 
2688         if (rf->channel <= 14) {
2689                 /* Restore BBP 25 & 26 for 2.4 GHz */
2690                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2691                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2692         } else {
2693                 /* Hard code BBP 25 & 26 for 5GHz */
2694 
2695                 /* Enable IQ Phase correction */
2696                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2697                 /* Setup IQ Phase correction value */
2698                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2699         }
2700 
2701         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2702         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2703 
2704         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2705         rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2706         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2707 
2708         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2709         rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2710         if (rf->channel <= 14)
2711                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2712         else
2713                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2714         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2715 
2716         rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2717         if (rf->channel <= 14) {
2718                 rfcsr = 0;
2719                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2720                                   info->default_power1 & 0x1f);
2721         } else {
2722                 if (rt2x00_is_usb(rt2x00dev))
2723                         rfcsr = 0x40;
2724 
2725                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2726                                   ((info->default_power1 & 0x18) << 1) |
2727                                   (info->default_power1 & 7));
2728         }
2729         rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2730 
2731         rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2732         if (rf->channel <= 14) {
2733                 rfcsr = 0;
2734                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2735                                   info->default_power2 & 0x1f);
2736         } else {
2737                 if (rt2x00_is_usb(rt2x00dev))
2738                         rfcsr = 0x40;
2739 
2740                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2741                                   ((info->default_power2 & 0x18) << 1) |
2742                                   (info->default_power2 & 7));
2743         }
2744         rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2745 
2746         rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2747         if (rf->channel <= 14) {
2748                 rfcsr = 0;
2749                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2750                                   info->default_power3 & 0x1f);
2751         } else {
2752                 if (rt2x00_is_usb(rt2x00dev))
2753                         rfcsr = 0x40;
2754 
2755                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2756                                   ((info->default_power3 & 0x18) << 1) |
2757                                   (info->default_power3 & 7));
2758         }
2759         rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2760 
2761         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2762         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2763         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2764         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2765         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2766         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2767         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2768         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2769         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2770 
2771         switch (rt2x00dev->default_ant.tx_chain_num) {
2772         case 3:
2773                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2774                 /* fallthrough */
2775         case 2:
2776                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2777                 /* fallthrough */
2778         case 1:
2779                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2780                 break;
2781         }
2782 
2783         switch (rt2x00dev->default_ant.rx_chain_num) {
2784         case 3:
2785                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2786                 /* fallthrough */
2787         case 2:
2788                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2789                 /* fallthrough */
2790         case 1:
2791                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2792                 break;
2793         }
2794         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2795 
2796         rt2800_freq_cal_mode1(rt2x00dev);
2797 
2798         if (conf_is_ht40(conf)) {
2799                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2800                                                 RFCSR24_TX_AGC_FC);
2801                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2802                                               RFCSR24_TX_H20M);
2803         } else {
2804                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2805                                                 RFCSR24_TX_AGC_FC);
2806                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2807                                               RFCSR24_TX_H20M);
2808         }
2809 
2810         /* NOTE: the reference driver does not writes the new value
2811          * back to RFCSR 32
2812          */
2813         rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2814         rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2815 
2816         if (rf->channel <= 14)
2817                 rfcsr = 0xa0;
2818         else
2819                 rfcsr = 0x80;
2820         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2821 
2822         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2823         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2824         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2825         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2826 
2827         /* Band selection */
2828         rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2829         if (rf->channel <= 14)
2830                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2831         else
2832                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2833         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2834 
2835         rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2836         if (rf->channel <= 14)
2837                 rfcsr = 0x3c;
2838         else
2839                 rfcsr = 0x20;
2840         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2841 
2842         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2843         if (rf->channel <= 14)
2844                 rfcsr = 0x1a;
2845         else
2846                 rfcsr = 0x12;
2847         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2848 
2849         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2850         if (rf->channel >= 1 && rf->channel <= 14)
2851                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2852         else if (rf->channel >= 36 && rf->channel <= 64)
2853                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2854         else if (rf->channel >= 100 && rf->channel <= 128)
2855                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2856         else
2857                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2858         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2859 
2860         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2861         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2862         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2863 
2864         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2865 
2866         if (rf->channel <= 14) {
2867                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2868                 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2869         } else {
2870                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2871                 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2872         }
2873 
2874         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2875         rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2876         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2877 
2878         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2879         if (rf->channel <= 14) {
2880                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2881                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2882         } else {
2883                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2884                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2885         }
2886         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2887 
2888         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2889         if (rf->channel <= 14)
2890                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2891         else
2892                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2893 
2894         if (txbf_enabled)
2895                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2896 
2897         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2898 
2899         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2900         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2901         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2902 
2903         rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2904         if (rf->channel <= 14)
2905                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2906         else
2907                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2908         rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2909 
2910         if (rf->channel <= 14) {
2911                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2912                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2913         } else {
2914                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2915                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2916         }
2917 
2918         /* Initiate VCO calibration */
2919         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2920         if (rf->channel <= 14) {
2921                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2922         } else {
2923                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2924                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2925                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2926                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2927                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2928                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2929         }
2930         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2931 
2932         if (rf->channel >= 1 && rf->channel <= 14) {
2933                 rfcsr = 0x23;
2934                 if (txbf_enabled)
2935                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2936                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2937 
2938                 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2939         } else if (rf->channel >= 36 && rf->channel <= 64) {
2940                 rfcsr = 0x36;
2941                 if (txbf_enabled)
2942                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2943                 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2944 
2945                 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2946         } else if (rf->channel >= 100 && rf->channel <= 128) {
2947                 rfcsr = 0x32;
2948                 if (txbf_enabled)
2949                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2950                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2951 
2952                 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2953         } else {
2954                 rfcsr = 0x30;
2955                 if (txbf_enabled)
2956                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2957                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2958 
2959                 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2960         }
2961 }
2962 
2963 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
2964                                          struct ieee80211_conf *conf,
2965                                          struct rf_channel *rf,
2966                                          struct channel_info *info)
2967 {
2968         u8 rfcsr;
2969         u8 bbp;
2970         u8 pwr1, pwr2, pwr3;
2971 
2972         const bool txbf_enabled = false; /* TODO */
2973 
2974         /* TODO: add band selection */
2975 
2976         if (rf->channel <= 14)
2977                 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2978         else if (rf->channel < 132)
2979                 rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
2980         else
2981                 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2982 
2983         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2984         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2985 
2986         if (rf->channel <= 14)
2987                 rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
2988         else
2989                 rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
2990 
2991         if (rf->channel <= 14)
2992                 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
2993         else
2994                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2995 
2996         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2997 
2998         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2999         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3000         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3001         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3002         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3003         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3004         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3005         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3006         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3007 
3008         switch (rt2x00dev->default_ant.tx_chain_num) {
3009         case 3:
3010                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
3011                 /* fallthrough */
3012         case 2:
3013                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3014                 /* fallthrough */
3015         case 1:
3016                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3017                 break;
3018         }
3019 
3020         switch (rt2x00dev->default_ant.rx_chain_num) {
3021         case 3:
3022                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
3023                 /* fallthrough */
3024         case 2:
3025                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3026                 /* fallthrough */
3027         case 1:
3028                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3029                 break;
3030         }
3031         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3032 
3033         rt2800_freq_cal_mode1(rt2x00dev);
3034 
3035         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3036         if (!conf_is_ht40(conf))
3037                 rfcsr &= ~(0x06);
3038         else
3039                 rfcsr |= 0x06;
3040         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3041 
3042         if (rf->channel <= 14)
3043                 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
3044         else
3045                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3046 
3047         if (conf_is_ht40(conf))
3048                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3049         else
3050                 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
3051 
3052         if (rf->channel <= 14)
3053                 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
3054         else
3055                 rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
3056 
3057         /* loopback RF_BS */
3058         rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
3059         if (rf->channel <= 14)
3060                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
3061         else
3062                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
3063         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
3064 
3065         if (rf->channel <= 14)
3066                 rfcsr = 0x23;
3067         else if (rf->channel < 100)
3068                 rfcsr = 0x36;
3069         else if (rf->channel < 132)
3070                 rfcsr = 0x32;
3071         else
3072                 rfcsr = 0x30;
3073 
3074         if (txbf_enabled)
3075                 rfcsr |= 0x40;
3076 
3077         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3078 
3079         if (rf->channel <= 14)
3080                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3081         else
3082                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3083 
3084         if (rf->channel <= 14)
3085                 rfcsr = 0xbb;
3086         else if (rf->channel < 100)
3087                 rfcsr = 0xeb;
3088         else if (rf->channel < 132)
3089                 rfcsr = 0xb3;
3090         else
3091                 rfcsr = 0x9b;
3092         rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
3093 
3094         if (rf->channel <= 14)
3095                 rfcsr = 0x8e;
3096         else
3097                 rfcsr = 0x8a;
3098 
3099         if (txbf_enabled)
3100                 rfcsr |= 0x20;
3101 
3102         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3103 
3104         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
3105 
3106         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3107         if (rf->channel <= 14)
3108                 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
3109         else
3110                 rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
3111 
3112         rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
3113         if (rf->channel <= 14)
3114                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3115         else
3116                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3117 
3118         if (rf->channel <= 14) {
3119                 pwr1 = info->default_power1 & 0x1f;
3120                 pwr2 = info->default_power2 & 0x1f;
3121                 pwr3 = info->default_power3 & 0x1f;
3122         } else {
3123                 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
3124                         (info->default_power1 & 0x7);
3125                 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
3126                         (info->default_power2 & 0x7);
3127                 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
3128                         (info->default_power3 & 0x7);
3129         }
3130 
3131         rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
3132         rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
3133         rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
3134 
3135         rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
3136                    rf->channel, pwr1, pwr2, pwr3);
3137 
3138         bbp = (info->default_power1 >> 5) |
3139               ((info->default_power2 & 0xe0) >> 1);
3140         rt2800_bbp_write(rt2x00dev, 109, bbp);
3141 
3142         bbp = rt2800_bbp_read(rt2x00dev, 110);
3143         bbp &= 0x0f;
3144         bbp |= (info->default_power3 & 0xe0) >> 1;
3145         rt2800_bbp_write(rt2x00dev, 110, bbp);
3146 
3147         rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3148         if (rf->channel <= 14)
3149                 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
3150         else
3151                 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
3152 
3153         /* Enable RF tuning */
3154         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3155         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3156         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3157 
3158         udelay(2000);
3159 
3160         bbp = rt2800_bbp_read(rt2x00dev, 49);
3161         /* clear update flag */
3162         rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
3163         rt2800_bbp_write(rt2x00dev, 49, bbp);
3164 
3165         /* TODO: add calibration for TxBF */
3166 }
3167 
3168 #define POWER_BOUND             0x27
3169 #define POWER_BOUND_5G          0x2b
3170 
3171 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
3172                                          struct ieee80211_conf *conf,
3173                                          struct rf_channel *rf,
3174                                          struct channel_info *info)
3175 {
3176         u8 rfcsr;
3177 
3178         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3179         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3180         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3181         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3182         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3183 
3184         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3185         if (info->default_power1 > POWER_BOUND)
3186                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3187         else
3188                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3189         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3190 
3191         rt2800_freq_cal_mode1(rt2x00dev);
3192 
3193         if (rf->channel <= 14) {
3194                 if (rf->channel == 6)
3195                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
3196                 else
3197                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3198 
3199                 if (rf->channel >= 1 && rf->channel <= 6)
3200                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
3201                 else if (rf->channel >= 7 && rf->channel <= 11)
3202                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
3203                 else if (rf->channel >= 12 && rf->channel <= 14)
3204                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
3205         }
3206 }
3207 
3208 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
3209                                          struct ieee80211_conf *conf,
3210                                          struct rf_channel *rf,
3211                                          struct channel_info *info)
3212 {
3213         u8 rfcsr;
3214 
3215         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3216         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3217 
3218         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
3219         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
3220         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
3221 
3222         if (info->default_power1 > POWER_BOUND)
3223                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
3224         else
3225                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
3226 
3227         if (info->default_power2 > POWER_BOUND)
3228                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
3229         else
3230                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
3231 
3232         rt2800_freq_cal_mode1(rt2x00dev);
3233 
3234         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3235         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3236         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3237 
3238         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
3239                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3240         else
3241                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3242 
3243         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
3244                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3245         else
3246                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3247 
3248         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3249         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3250 
3251         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3252 
3253         rt2800_rfcsr_write(rt2x00dev, 31, 80);
3254 }
3255 
3256 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
3257                                          struct ieee80211_conf *conf,
3258                                          struct rf_channel *rf,
3259                                          struct channel_info *info)
3260 {
3261         u8 rfcsr;
3262         int idx = rf->channel-1;
3263 
3264         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3265         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3266         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3267         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3268         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3269 
3270         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3271         if (info->default_power1 > POWER_BOUND)
3272                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3273         else
3274                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3275         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3276 
3277         if (rt2x00_rt(rt2x00dev, RT5392)) {
3278                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3279                 if (info->default_power2 > POWER_BOUND)
3280                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
3281                 else
3282                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
3283                                           info->default_power2);
3284                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3285         }
3286 
3287         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3288         if (rt2x00_rt(rt2x00dev, RT5392)) {
3289                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3290                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3291         }
3292         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3293         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3294         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3295         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3296         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3297 
3298         rt2800_freq_cal_mode1(rt2x00dev);
3299 
3300         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3301                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3302                         /* r55/r59 value array of channel 1~14 */
3303                         static const char r55_bt_rev[] = {0x83, 0x83,
3304                                 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
3305                                 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
3306                         static const char r59_bt_rev[] = {0x0e, 0x0e,
3307                                 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
3308                                 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
3309 
3310                         rt2800_rfcsr_write(rt2x00dev, 55,
3311                                            r55_bt_rev[idx]);
3312                         rt2800_rfcsr_write(rt2x00dev, 59,
3313                                            r59_bt_rev[idx]);
3314                 } else {
3315                         static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
3316                                 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
3317                                 0x88, 0x88, 0x86, 0x85, 0x84};
3318 
3319                         rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
3320                 }
3321         } else {
3322                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3323                         static const char r55_nonbt_rev[] = {0x23, 0x23,
3324                                 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
3325                                 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
3326                         static const char r59_nonbt_rev[] = {0x07, 0x07,
3327                                 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
3328                                 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
3329 
3330                         rt2800_rfcsr_write(rt2x00dev, 55,
3331                                            r55_nonbt_rev[idx]);
3332                         rt2800_rfcsr_write(rt2x00dev, 59,
3333                                            r59_nonbt_rev[idx]);
3334                 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3335                            rt2x00_rt(rt2x00dev, RT5392) ||
3336                            rt2x00_rt(rt2x00dev, RT6352)) {
3337                         static const char r59_non_bt[] = {0x8f, 0x8f,
3338                                 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
3339                                 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
3340 
3341                         rt2800_rfcsr_write(rt2x00dev, 59,
3342                                            r59_non_bt[idx]);
3343                 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
3344                         static const char r59_non_bt[] = {0x0b, 0x0b,
3345                                 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
3346                                 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
3347 
3348                         rt2800_rfcsr_write(rt2x00dev, 59,
3349                                            r59_non_bt[idx]);
3350                 }
3351         }
3352 }
3353 
3354 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
3355                                          struct ieee80211_conf *conf,
3356                                          struct rf_channel *rf,
3357                                          struct channel_info *info)
3358 {
3359         u8 rfcsr, ep_reg;
3360         u32 reg;
3361         int power_bound;
3362 
3363         /* TODO */
3364         const bool is_11b = false;
3365         const bool is_type_ep = false;
3366 
3367         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
3368         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
3369                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
3370         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3371 
3372         /* Order of values on rf_channel entry: N, K, mod, R */
3373         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3374 
3375         rfcsr = rt2800_rfcsr_read(rt2x00dev,  9);
3376         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
3377         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
3378         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
3379         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3380 
3381         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3382         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
3383         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
3384         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3385 
3386         if (rf->channel <= 14) {
3387                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
3388                 /* FIXME: RF11 owerwrite ? */
3389                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
3390                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3391                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3392                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3393                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
3394                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3395                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3396                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
3397                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3398                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3399                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
3400                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
3401                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
3402                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
3403                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
3404                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
3405                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
3406                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
3407                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3408                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
3409                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3410                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3411                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
3412                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3413                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3414                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3415                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3416                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3417 
3418                 /* TODO RF27 <- tssi */
3419 
3420                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
3421                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3422                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3423 
3424                 if (is_11b) {
3425                         /* CCK */
3426                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
3427                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
3428                         if (is_type_ep)
3429                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3430                         else
3431                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
3432                 } else {
3433                         /* OFDM */
3434                         if (is_type_ep)
3435                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
3436                         else
3437                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3438                 }
3439 
3440                 power_bound = POWER_BOUND;
3441                 ep_reg = 0x2;
3442         } else {
3443                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3444                 /* FIMXE: RF11 overwrite */
3445                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3446                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3447                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3448                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3449                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3450                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3451                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3452                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3453                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3454                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3455                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3456                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3457                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3458                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3459 
3460                 /* TODO RF27 <- tssi */
3461 
3462                 if (rf->channel >= 36 && rf->channel <= 64) {
3463 
3464                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3465                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3466                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3467                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3468                         if (rf->channel <= 50)
3469                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3470                         else if (rf->channel >= 52)
3471                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3472                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3473                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3474                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3475                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3476                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3477                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3478                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3479                         if (rf->channel <= 50) {
3480                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3481                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3482                         } else if (rf->channel >= 52) {
3483                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3484                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3485                         }
3486 
3487                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3488                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3489                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3490 
3491                 } else if (rf->channel >= 100 && rf->channel <= 165) {
3492 
3493                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3494                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3495                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3496                         if (rf->channel <= 153) {
3497                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3498                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3499                         } else if (rf->channel >= 155) {
3500                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3501                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3502                         }
3503                         if (rf->channel <= 138) {
3504                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3505                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3506                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3507                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3508                         } else if (rf->channel >= 140) {
3509                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3510                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3511                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3512                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3513                         }
3514                         if (rf->channel <= 124)
3515                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3516                         else if (rf->channel >= 126)
3517                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3518                         if (rf->channel <= 138)
3519                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3520                         else if (rf->channel >= 140)
3521                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3522                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3523                         if (rf->channel <= 138)
3524                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3525                         else if (rf->channel >= 140)
3526                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3527                         if (rf->channel <= 128)
3528                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3529                         else if (rf->channel >= 130)
3530                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3531                         if (rf->channel <= 116)
3532                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3533                         else if (rf->channel >= 118)
3534                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3535                         if (rf->channel <= 138)
3536                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3537                         else if (rf->channel >= 140)
3538                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3539                         if (rf->channel <= 116)
3540                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3541                         else if (rf->channel >= 118)
3542                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3543                 }
3544 
3545                 power_bound = POWER_BOUND_5G;
3546                 ep_reg = 0x3;
3547         }
3548 
3549         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3550         if (info->default_power1 > power_bound)
3551                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3552         else
3553                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3554         if (is_type_ep)
3555                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3556         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3557 
3558         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3559         if (info->default_power2 > power_bound)
3560                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3561         else
3562                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3563         if (is_type_ep)
3564                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3565         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3566 
3567         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3568         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3569         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3570 
3571         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3572                           rt2x00dev->default_ant.tx_chain_num >= 1);
3573         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3574                           rt2x00dev->default_ant.tx_chain_num == 2);
3575         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3576 
3577         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3578                           rt2x00dev->default_ant.rx_chain_num >= 1);
3579         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3580                           rt2x00dev->default_ant.rx_chain_num == 2);
3581         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3582 
3583         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3584         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3585 
3586         if (conf_is_ht40(conf))
3587                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3588         else
3589                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3590 
3591         if (!is_11b) {
3592                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3593                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3594         }
3595 
3596         /* TODO proper frequency adjustment */
3597         rt2800_freq_cal_mode1(rt2x00dev);
3598 
3599         /* TODO merge with others */
3600         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3601         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3602         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3603 
3604         /* BBP settings */
3605         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3606         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3607         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3608 
3609         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3610         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3611         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3612         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3613 
3614         /* GLRT band configuration */
3615         rt2800_bbp_write(rt2x00dev, 195, 128);
3616         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3617         rt2800_bbp_write(rt2x00dev, 195, 129);
3618         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3619         rt2800_bbp_write(rt2x00dev, 195, 130);
3620         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3621         rt2800_bbp_write(rt2x00dev, 195, 131);
3622         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3623         rt2800_bbp_write(rt2x00dev, 195, 133);
3624         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3625         rt2800_bbp_write(rt2x00dev, 195, 124);
3626         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3627 }
3628 
3629 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3630                                          struct ieee80211_conf *conf,
3631                                          struct rf_channel *rf,
3632                                          struct channel_info *info)
3633 {
3634         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3635         u8 rx_agc_fc, tx_agc_fc;
3636         u8 rfcsr;
3637 
3638         /* Frequeny plan setting */
3639         /* Rdiv setting (set 0x03 if Xtal==20)
3640          * R13[1:0]
3641          */
3642         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3643         rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3644                           rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3645         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3646 
3647         /* N setting
3648          * R20[7:0] in rf->rf1
3649          * R21[0] always 0
3650          */
3651         rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3652         rfcsr = (rf->rf1 & 0x00ff);
3653         rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3654 
3655         rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3656         rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3657         rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3658 
3659         /* K setting (always 0)
3660          * R16[3:0] (RF PLL freq selection)
3661          */
3662         rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3663         rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3664         rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3665 
3666         /* D setting (always 0)
3667          * R22[2:0] (D=15, R22[2:0]=<111>)
3668          */
3669         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3670         rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3671         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3672 
3673         /* Ksd setting
3674          * Ksd: R17<7:0> in rf->rf2
3675          *      R18<7:0> in rf->rf3
3676          *      R19<1:0> in rf->rf4
3677          */
3678         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3679         rfcsr = rf->rf2;
3680         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3681 
3682         rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3683         rfcsr = rf->rf3;
3684         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3685 
3686         rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3687         rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3688         rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3689 
3690         /* Default: XO=20MHz , SDM mode */
3691         rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3692         rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3693         rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3694 
3695         rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3696         rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3697         rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3698 
3699         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3700         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3701                           rt2x00dev->default_ant.tx_chain_num != 1);
3702         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3703 
3704         rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3705         rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3706                           rt2x00dev->default_ant.tx_chain_num != 1);
3707         rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3708                           rt2x00dev->default_ant.rx_chain_num != 1);
3709         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3710 
3711         rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3712         rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3713                           rt2x00dev->default_ant.tx_chain_num != 1);
3714         rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3715 
3716         /* RF for DC Cal BW */
3717         if (conf_is_ht40(conf)) {
3718                 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3719                 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3720                 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3721                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3722                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3723         } else {
3724                 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3725                 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3726                 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3727                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3728                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3729         }
3730 
3731         if (conf_is_ht40(conf)) {
3732                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3733                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3734         } else {
3735                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3736                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3737         }
3738 
3739         rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3740         rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3741                           conf_is_ht40(conf) && (rf->channel == 11));
3742         rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3743 
3744         if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3745                 if (conf_is_ht40(conf)) {
3746                         rx_agc_fc = drv_data->rx_calibration_bw40;
3747                         tx_agc_fc = drv_data->tx_calibration_bw40;
3748                 } else {
3749                         rx_agc_fc = drv_data->rx_calibration_bw20;
3750                         tx_agc_fc = drv_data->tx_calibration_bw20;
3751                 }
3752                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3753                 rfcsr &= (~0x3F);
3754                 rfcsr |= rx_agc_fc;
3755                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3756                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3757                 rfcsr &= (~0x3F);
3758                 rfcsr |= rx_agc_fc;
3759                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3760                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3761                 rfcsr &= (~0x3F);
3762                 rfcsr |= rx_agc_fc;
3763                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3764                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3765                 rfcsr &= (~0x3F);
3766                 rfcsr |= rx_agc_fc;
3767                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3768 
3769                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3770                 rfcsr &= (~0x3F);
3771                 rfcsr |= tx_agc_fc;
3772                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3773                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3774                 rfcsr &= (~0x3F);
3775                 rfcsr |= tx_agc_fc;
3776                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3777                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3778                 rfcsr &= (~0x3F);
3779                 rfcsr |= tx_agc_fc;
3780                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3781                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3782                 rfcsr &= (~0x3F);
3783                 rfcsr |= tx_agc_fc;
3784                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3785         }
3786 }
3787 
3788 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3789                               struct ieee80211_channel *chan,
3790                               int power_level) {
3791         u16 eeprom, target_power, max_power;
3792         u32 mac_sys_ctrl, mac_status;
3793         u32 reg;
3794         u8 bbp;
3795         int i;
3796 
3797         /* hardware unit is 0.5dBm, limited to 23.5dBm */
3798         power_level *= 2;
3799         if (power_level > 0x2f)
3800                 power_level = 0x2f;
3801 
3802         max_power = chan->max_power * 2;
3803         if (max_power > 0x2f)
3804                 max_power = 0x2f;
3805 
3806         reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3807         rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
3808         rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
3809         rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
3810         rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
3811 
3812         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3813         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3814                 /* init base power by eeprom target power */
3815                 target_power = rt2800_eeprom_read(rt2x00dev,
3816                                                   EEPROM_TXPOWER_INIT);
3817                 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
3818                 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
3819         }
3820         rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3821 
3822         reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3823         rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3824         rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3825 
3826         /* Save MAC SYS CTRL registers */
3827         mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3828         /* Disable Tx/Rx */
3829         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3830         /* Check MAC Tx/Rx idle */
3831         for (i = 0; i < 10000; i++) {
3832                 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
3833                 if (mac_status & 0x3)
3834                         usleep_range(50, 200);
3835                 else
3836                         break;
3837         }
3838 
3839         if (i == 10000)
3840                 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3841 
3842         if (chan->center_freq > 2457) {
3843                 bbp = rt2800_bbp_read(rt2x00dev, 30);
3844                 bbp = 0x40;
3845                 rt2800_bbp_write(rt2x00dev, 30, bbp);
3846                 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3847                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3848                         rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3849                 else
3850                         rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3851         } else {
3852                 bbp = rt2800_bbp_read(rt2x00dev, 30);
3853                 bbp = 0x1f;
3854                 rt2800_bbp_write(rt2x00dev, 30, bbp);
3855                 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3856                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3857                         rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3858                 else
3859                         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3860         }
3861         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3862 
3863         rt2800_vco_calibration(rt2x00dev);
3864 }
3865 
3866 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3867                                            const unsigned int word,
3868                                            const u8 value)
3869 {
3870         u8 chain, reg;
3871 
3872         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3873                 reg = rt2800_bbp_read(rt2x00dev, 27);
3874                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3875                 rt2800_bbp_write(rt2x00dev, 27, reg);
3876 
3877                 rt2800_bbp_write(rt2x00dev, word, value);
3878         }
3879 }
3880 
3881 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3882 {
3883         u8 cal;
3884 
3885         /* TX0 IQ Gain */
3886         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3887         if (channel <= 14)
3888                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3889         else if (channel >= 36 && channel <= 64)
3890                 cal = rt2x00_eeprom_byte(rt2x00dev,
3891                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3892         else if (channel >= 100 && channel <= 138)
3893                 cal = rt2x00_eeprom_byte(rt2x00dev,
3894                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3895         else if (channel >= 140 && channel <= 165)
3896                 cal = rt2x00_eeprom_byte(rt2x00dev,
3897                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3898         else
3899                 cal = 0;
3900         rt2800_bbp_write(rt2x00dev, 159, cal);
3901 
3902         /* TX0 IQ Phase */
3903         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3904         if (channel <= 14)
3905                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3906         else if (channel >= 36 && channel <= 64)
3907                 cal = rt2x00_eeprom_byte(rt2x00dev,
3908                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3909         else if (channel >= 100 && channel <= 138)
3910                 cal = rt2x00_eeprom_byte(rt2x00dev,
3911                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3912         else if (channel >= 140 && channel <= 165)
3913                 cal = rt2x00_eeprom_byte(rt2x00dev,
3914                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3915         else
3916                 cal = 0;
3917         rt2800_bbp_write(rt2x00dev, 159, cal);
3918 
3919         /* TX1 IQ Gain */
3920         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3921         if (channel <= 14)
3922                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3923         else if (channel >= 36 && channel <= 64)
3924                 cal = rt2x00_eeprom_byte(rt2x00dev,
3925                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3926         else if (channel >= 100 && channel <= 138)
3927                 cal = rt2x00_eeprom_byte(rt2x00dev,
3928                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3929         else if (channel >= 140 && channel <= 165)
3930                 cal = rt2x00_eeprom_byte(rt2x00dev,
3931                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3932         else
3933                 cal = 0;
3934         rt2800_bbp_write(rt2x00dev, 159, cal);
3935 
3936         /* TX1 IQ Phase */
3937         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3938         if (channel <= 14)
3939                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3940         else if (channel >= 36 && channel <= 64)
3941                 cal = rt2x00_eeprom_byte(rt2x00dev,
3942                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3943         else if (channel >= 100 && channel <= 138)
3944                 cal = rt2x00_eeprom_byte(rt2x00dev,
3945                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3946         else if (channel >= 140 && channel <= 165)
3947                 cal = rt2x00_eeprom_byte(rt2x00dev,
3948                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3949         else
3950                 cal = 0;
3951         rt2800_bbp_write(rt2x00dev, 159, cal);
3952 
3953         /* FIXME: possible RX0, RX1 callibration ? */
3954 
3955         /* RF IQ compensation control */
3956         rt2800_bbp_write(rt2x00dev, 158, 0x04);
3957         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3958         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3959 
3960         /* RF IQ imbalance compensation control */
3961         rt2800_bbp_write(rt2x00dev, 158, 0x03);
3962         cal = rt2x00_eeprom_byte(rt2x00dev,
3963                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3964         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3965 }
3966 
3967 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3968                                   unsigned int channel,
3969                                   char txpower)
3970 {
3971         if (rt2x00_rt(rt2x00dev, RT3593) ||
3972             rt2x00_rt(rt2x00dev, RT3883))
3973                 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3974 
3975         if (channel <= 14)
3976                 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3977 
3978         if (rt2x00_rt(rt2x00dev, RT3593) ||
3979             rt2x00_rt(rt2x00dev, RT3883))
3980                 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3981                                MAX_A_TXPOWER_3593);
3982         else
3983                 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3984 }
3985 
3986 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
3987                               struct rf_channel *rf)
3988 {
3989         u8 bbp;
3990 
3991         bbp = (rf->channel > 14) ? 0x48 : 0x38;
3992         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
3993 
3994         rt2800_bbp_write(rt2x00dev, 69, 0x12);
3995 
3996         if (rf->channel <= 14) {
3997                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3998         } else {
3999                 /* Disable CCK packet detection */
4000                 rt2800_bbp_write(rt2x00dev, 70, 0x00);
4001         }
4002 
4003         rt2800_bbp_write(rt2x00dev, 73, 0x10);
4004 
4005         if (rf->channel > 14) {
4006                 rt2800_bbp_write(rt2x00dev, 62, 0x1d);
4007                 rt2800_bbp_write(rt2x00dev, 63, 0x1d);
4008                 rt2800_bbp_write(rt2x00dev, 64, 0x1d);
4009         } else {
4010                 rt2800_bbp_write(rt2x00dev, 62, 0x2d);
4011                 rt2800_bbp_write(rt2x00dev, 63, 0x2d);
4012                 rt2800_bbp_write(rt2x00dev, 64, 0x2d);
4013         }
4014 }
4015 
4016 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
4017                                   struct ieee80211_conf *conf,
4018                                   struct rf_channel *rf,
4019                                   struct channel_info *info)
4020 {
4021         u32 reg;
4022         u32 tx_pin;
4023         u8 bbp, rfcsr;
4024 
4025         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4026                                                      info->default_power1);
4027         info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4028                                                      info->default_power2);
4029         if (rt2x00dev->default_ant.tx_chain_num > 2)
4030                 info->default_power3 =
4031                         rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4032                                               info->default_power3);
4033 
4034         switch (rt2x00dev->chip.rt) {
4035         case RT3883:
4036                 rt3883_bbp_adjust(rt2x00dev, rf);
4037                 break;
4038         }
4039 
4040         switch (rt2x00dev->chip.rf) {
4041         case RF2020:
4042         case RF3020:
4043         case RF3021:
4044         case RF3022:
4045         case RF3320:
4046                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
4047                 break;
4048         case RF3052:
4049                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
4050                 break;
4051         case RF3053:
4052                 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
4053                 break;
4054         case RF3290:
4055                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
4056                 break;
4057         case RF3322:
4058                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
4059                 break;
4060         case RF3853:
4061                 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
4062                 break;
4063         case RF3070:
4064         case RF5350:
4065         case RF5360:
4066         case RF5362:
4067         case RF5370:
4068         case RF5372:
4069         case RF5390:
4070         case RF5392:
4071                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
4072                 break;
4073         case RF5592:
4074                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
4075                 break;
4076         case RF7620:
4077                 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
4078                 break;
4079         default:
4080                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
4081         }
4082 
4083         if (rt2x00_rf(rt2x00dev, RF3070) ||
4084             rt2x00_rf(rt2x00dev, RF3290) ||
4085             rt2x00_rf(rt2x00dev, RF3322) ||
4086             rt2x00_rf(rt2x00dev, RF5350) ||
4087             rt2x00_rf(rt2x00dev, RF5360) ||
4088             rt2x00_rf(rt2x00dev, RF5362) ||
4089             rt2x00_rf(rt2x00dev, RF5370) ||
4090             rt2x00_rf(rt2x00dev, RF5372) ||
4091             rt2x00_rf(rt2x00dev, RF5390) ||
4092             rt2x00_rf(rt2x00dev, RF5392)) {
4093                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
4094                 if (rt2x00_rf(rt2x00dev, RF3322)) {
4095                         rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
4096                                           conf_is_ht40(conf));
4097                         rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
4098                                           conf_is_ht40(conf));
4099                 } else {
4100                         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
4101                                           conf_is_ht40(conf));
4102                         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
4103                                           conf_is_ht40(conf));
4104                 }
4105                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4106 
4107                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4108                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4109                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4110         }
4111 
4112         /*
4113          * Change BBP settings
4114          */
4115 
4116         if (rt2x00_rt(rt2x00dev, RT3352)) {
4117                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4118                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4119                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4120 
4121                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
4122                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4123                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
4124                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4125                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4126                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4127         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4128                 if (rf->channel > 14) {
4129                         /* Disable CCK Packet detection on 5GHz */
4130                         rt2800_bbp_write(rt2x00dev, 70, 0x00);
4131                 } else {
4132                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4133                 }
4134 
4135                 if (conf_is_ht40(conf))
4136                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
4137                 else
4138                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
4139 
4140                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4141                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4142                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4143                 rt2800_bbp_write(rt2x00dev, 77, 0x98);
4144         } else if (rt2x00_rt(rt2x00dev, RT3883)) {
4145                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4146                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4147                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4148 
4149                 if (rt2x00dev->default_ant.rx_chain_num > 1)
4150                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
4151                 else
4152                         rt2800_bbp_write(rt2x00dev, 86, 0);
4153         } else {
4154                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4155                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4156                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4157                 rt2800_bbp_write(rt2x00dev, 86, 0);
4158         }
4159 
4160         if (rf->channel <= 14) {
4161                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4162                     !rt2x00_rt(rt2x00dev, RT5392) &&
4163                     !rt2x00_rt(rt2x00dev, RT6352)) {
4164                         if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4165                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4166                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4167                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4168                         } else {
4169                                 if (rt2x00_rt(rt2x00dev, RT3593))
4170                                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4171                                 else
4172                                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
4173                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
4174                         }
4175                         if (rt2x00_rt(rt2x00dev, RT3593) ||
4176                             rt2x00_rt(rt2x00dev, RT3883))
4177                                 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
4178                 }
4179 
4180         } else {
4181                 if (rt2x00_rt(rt2x00dev, RT3572))
4182                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
4183                 else if (rt2x00_rt(rt2x00dev, RT3593) ||
4184                          rt2x00_rt(rt2x00dev, RT3883))
4185                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
4186                 else if (!rt2x00_rt(rt2x00dev, RT6352))
4187                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
4188 
4189                 if (rt2x00_rt(rt2x00dev, RT3593) ||
4190                     rt2x00_rt(rt2x00dev, RT3883))
4191                         rt2800_bbp_write(rt2x00dev, 83, 0x9a);
4192 
4193                 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
4194                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
4195                 else
4196                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
4197         }
4198 
4199         reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
4200         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
4201         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
4202         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
4203         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
4204 
4205         if (rt2x00_rt(rt2x00dev, RT3572))
4206                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
4207 
4208         if (rt2x00_rt(rt2x00dev, RT6352)) {
4209                 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4210                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1);
4211         } else {
4212                 tx_pin = 0;
4213         }
4214 
4215         switch (rt2x00dev->default_ant.tx_chain_num) {
4216         case 3:
4217                 /* Turn on tertiary PAs */
4218                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
4219                                    rf->channel > 14);
4220                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
4221                                    rf->channel <= 14);
4222                 /* fall-through */
4223         case 2:
4224                 /* Turn on secondary PAs */
4225                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
4226                                    rf->channel > 14);
4227                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
4228                                    rf->channel <= 14);
4229                 /* fall-through */
4230         case 1:
4231                 /* Turn on primary PAs */
4232                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
4233                                    rf->channel > 14);
4234                 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
4235                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4236                 else
4237                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
4238                                            rf->channel <= 14);
4239                 break;
4240         }
4241 
4242         switch (rt2x00dev->default_ant.rx_chain_num) {
4243         case 3:
4244                 /* Turn on tertiary LNAs */
4245                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
4246                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
4247                 /* fall-through */
4248         case 2:
4249                 /* Turn on secondary LNAs */
4250                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
4251                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
4252                 /* fall-through */
4253         case 1:
4254                 /* Turn on primary LNAs */
4255                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
4256                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
4257                 break;
4258         }
4259 
4260         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
4261         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
4262 
4263         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4264 
4265         if (rt2x00_rt(rt2x00dev, RT3572)) {
4266                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
4267 
4268                 /* AGC init */
4269                 if (rf->channel <= 14)
4270                         reg = 0x1c + (2 * rt2x00dev->lna_gain);
4271                 else
4272                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4273 
4274                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4275         }
4276 
4277         if (rt2x00_rt(rt2x00dev, RT3593)) {
4278                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
4279 
4280                 /* Band selection */
4281                 if (rt2x00_is_usb(rt2x00dev) ||
4282                     rt2x00_is_pcie(rt2x00dev)) {
4283                         /* GPIO #8 controls all paths */
4284                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
4285                         if (rf->channel <= 14)
4286                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
4287                         else
4288                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
4289                 }
4290 
4291                 /* LNA PE control. */
4292                 if (rt2x00_is_usb(rt2x00dev)) {
4293                         /* GPIO #4 controls PE0 and PE1,
4294                          * GPIO #7 controls PE2
4295                          */
4296                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4297                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
4298 
4299                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4300                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
4301                 } else if (rt2x00_is_pcie(rt2x00dev)) {
4302                         /* GPIO #4 controls PE0, PE1 and PE2 */
4303                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4304                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4305                 }
4306 
4307                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4308 
4309                 /* AGC init */
4310                 if (rf->channel <= 14)
4311                         reg = 0x1c + 2 * rt2x00dev->lna_gain;
4312                 else
4313                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4314 
4315                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4316 
4317                 usleep_range(1000, 1500);
4318         }
4319 
4320         if (rt2x00_rt(rt2x00dev, RT3883)) {
4321                 if (!conf_is_ht40(conf))
4322                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
4323                 else
4324                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
4325 
4326                 /* AGC init */
4327                 if (rf->channel <= 14)
4328                         reg = 0x2e + rt2x00dev->lna_gain;
4329                 else
4330                         reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
4331 
4332                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4333 
4334                 usleep_range(1000, 1500);
4335         }
4336 
4337         if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
4338                 reg = 0x10;
4339                 if (!conf_is_ht40(conf)) {
4340                         if (rt2x00_rt(rt2x00dev, RT6352) &&
4341                             rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4342                                 reg |= 0x5;
4343                         } else {
4344                                 reg |= 0xa;
4345                         }
4346                 }
4347                 rt2800_bbp_write(rt2x00dev, 195, 141);
4348                 rt2800_bbp_write(rt2x00dev, 196, reg);
4349 
4350                 /* AGC init.
4351                  * Despite the vendor driver using different values here for
4352                  * RT6352 chip, we use 0x1c for now. This may have to be changed
4353                  * once TSSI got implemented.
4354                  */
4355                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
4356                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4357 
4358                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
4359         }
4360 
4361         bbp = rt2800_bbp_read(rt2x00dev, 4);
4362         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
4363         rt2800_bbp_write(rt2x00dev, 4, bbp);
4364 
4365         bbp = rt2800_bbp_read(rt2x00dev, 3);
4366         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
4367         rt2800_bbp_write(rt2x00dev, 3, bbp);
4368 
4369         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4370                 if (conf_is_ht40(conf)) {
4371                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
4372                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4373                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
4374                 } else {
4375                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
4376                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
4377                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
4378                 }
4379         }
4380 
4381         usleep_range(1000, 1500);
4382 
4383         /*
4384          * Clear channel statistic counters
4385          */
4386         reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
4387         reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
4388         reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
4389 
4390         /*
4391          * Clear update flag
4392          */
4393         if (rt2x00_rt(rt2x00dev, RT3352) ||
4394             rt2x00_rt(rt2x00dev, RT5350)) {
4395                 bbp = rt2800_bbp_read(rt2x00dev, 49);
4396                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
4397                 rt2800_bbp_write(rt2x00dev, 49, bbp);
4398         }
4399 }
4400 
4401 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
4402 {
4403         u8 tssi_bounds[9];
4404         u8 current_tssi;
4405         u16 eeprom;
4406         u8 step;
4407         int i;
4408 
4409         /*
4410          * First check if temperature compensation is supported.
4411          */
4412         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
4413         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
4414                 return 0;
4415 
4416         /*
4417          * Read TSSI boundaries for temperature compensation from
4418          * the EEPROM.
4419          *
4420          * Array idx               0    1    2    3    4    5    6    7    8
4421          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
4422          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
4423          */
4424         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4425                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
4426                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
4427                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
4428                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
4429                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
4430 
4431                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
4432                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
4433                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
4434                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
4435                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
4436 
4437                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
4438                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
4439                                         EEPROM_TSSI_BOUND_BG3_REF);
4440                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
4441                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
4442 
4443                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
4444                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
4445                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
4446                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
4447                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
4448 
4449                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
4450                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
4451                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
4452 
4453                 step = rt2x00_get_field16(eeprom,
4454                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
4455         } else {
4456                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
4457                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
4458                                         EEPROM_TSSI_BOUND_A1_MINUS4);
4459                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
4460                                         EEPROM_TSSI_BOUND_A1_MINUS3);
4461 
4462                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
4463                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
4464                                         EEPROM_TSSI_BOUND_A2_MINUS2);
4465                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
4466                                         EEPROM_TSSI_BOUND_A2_MINUS1);
4467 
4468                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
4469                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
4470                                         EEPROM_TSSI_BOUND_A3_REF);
4471                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
4472                                         EEPROM_TSSI_BOUND_A3_PLUS1);
4473 
4474                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
4475                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
4476                                         EEPROM_TSSI_BOUND_A4_PLUS2);
4477                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
4478                                         EEPROM_TSSI_BOUND_A4_PLUS3);
4479 
4480                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
4481                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
4482                                         EEPROM_TSSI_BOUND_A5_PLUS4);
4483 
4484                 step = rt2x00_get_field16(eeprom,
4485                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
4486         }
4487 
4488         /*
4489          * Check if temperature compensation is supported.
4490          */
4491         if (tssi_bounds[4] == 0xff || step == 0xff)
4492                 return 0;
4493 
4494         /*
4495          * Read current TSSI (BBP 49).
4496          */
4497         current_tssi = rt2800_bbp_read(rt2x00dev, 49);
4498 
4499         /*
4500          * Compare TSSI value (BBP49) with the compensation boundaries
4501          * from the EEPROM and increase or decrease tx power.
4502          */
4503         for (i = 0; i <= 3; i++) {
4504                 if (current_tssi > tssi_bounds[i])
4505                         break;
4506         }
4507 
4508         if (i == 4) {
4509                 for (i = 8; i >= 5; i--) {
4510                         if (current_tssi < tssi_bounds[i])
4511                                 break;
4512                 }
4513         }
4514 
4515         return (i - 4) * step;
4516 }
4517 
4518 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4519                                       enum nl80211_band band)
4520 {
4521         u16 eeprom;
4522         u8 comp_en;
4523         u8 comp_type;
4524         int comp_value = 0;
4525 
4526         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4527 
4528         /*
4529          * HT40 compensation not required.
4530          */
4531         if (eeprom == 0xffff ||
4532             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4533                 return 0;
4534 
4535         if (band == NL80211_BAND_2GHZ) {
4536                 comp_en = rt2x00_get_field16(eeprom,
4537                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
4538                 if (comp_en) {
4539                         comp_type = rt2x00_get_field16(eeprom,
4540                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
4541                         comp_value = rt2x00_get_field16(eeprom,
4542                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
4543                         if (!comp_type)
4544                                 comp_value = -comp_value;
4545                 }
4546         } else {
4547                 comp_en = rt2x00_get_field16(eeprom,
4548                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
4549                 if (comp_en) {
4550                         comp_type = rt2x00_get_field16(eeprom,
4551                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
4552                         comp_value = rt2x00_get_field16(eeprom,
4553                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
4554                         if (!comp_type)
4555                                 comp_value = -comp_value;
4556                 }
4557         }
4558 
4559         return comp_value;
4560 }
4561 
4562 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4563                                         int power_level, int max_power)
4564 {
4565         int delta;
4566 
4567         if (rt2x00_has_cap_power_limit(rt2x00dev))
4568                 return 0;
4569 
4570         /*
4571          * XXX: We don't know the maximum transmit power of our hardware since
4572          * the EEPROM doesn't expose it. We only know that we are calibrated
4573          * to 100% tx power.
4574          *
4575          * Hence, we assume the regulatory limit that cfg80211 calulated for
4576          * the current channel is our maximum and if we are requested to lower
4577          * the value we just reduce our tx power accordingly.
4578          */
4579         delta = power_level - max_power;
4580         return min(delta, 0);
4581 }
4582 
4583 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4584                                    enum nl80211_band band, int power_level,
4585                                    u8 txpower, int delta)
4586 {
4587         u16 eeprom;
4588         u8 criterion;
4589         u8 eirp_txpower;
4590         u8 eirp_txpower_criterion;
4591         u8 reg_limit;
4592 
4593         if (rt2x00_rt(rt2x00dev, RT3593))
4594                 return min_t(u8, txpower, 0xc);
4595 
4596         if (rt2x00_rt(rt2x00dev, RT3883))
4597                 return min_t(u8, txpower, 0xf);
4598 
4599         if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4600                 /*
4601                  * Check if eirp txpower exceed txpower_limit.
4602                  * We use OFDM 6M as criterion and its eirp txpower
4603                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
4604                  * .11b data rate need add additional 4dbm
4605                  * when calculating eirp txpower.
4606                  */
4607                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4608                                                        EEPROM_TXPOWER_BYRATE,
4609                                                        1);
4610                 criterion = rt2x00_get_field16(eeprom,
4611                                                EEPROM_TXPOWER_BYRATE_RATE0);
4612 
4613                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4614 
4615                 if (band == NL80211_BAND_2GHZ)
4616                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4617                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4618                 else
4619                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4620                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4621 
4622                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4623                                (is_rate_b ? 4 : 0) + delta;
4624 
4625                 reg_limit = (eirp_txpower > power_level) ?
4626                                         (eirp_txpower - power_level) : 0;
4627         } else
4628                 reg_limit = 0;
4629 
4630         txpower = max(0, txpower + delta - reg_limit);
4631         return min_t(u8, txpower, 0xc);
4632 }
4633 
4634 
4635 enum {
4636         TX_PWR_CFG_0_IDX,
4637         TX_PWR_CFG_1_IDX,
4638         TX_PWR_CFG_2_IDX,
4639         TX_PWR_CFG_3_IDX,
4640         TX_PWR_CFG_4_IDX,
4641         TX_PWR_CFG_5_IDX,
4642         TX_PWR_CFG_6_IDX,
4643         TX_PWR_CFG_7_IDX,
4644         TX_PWR_CFG_8_IDX,
4645         TX_PWR_CFG_9_IDX,
4646         TX_PWR_CFG_0_EXT_IDX,
4647         TX_PWR_CFG_1_EXT_IDX,
4648         TX_PWR_CFG_2_EXT_IDX,
4649         TX_PWR_CFG_3_EXT_IDX,
4650         TX_PWR_CFG_4_EXT_IDX,
4651         TX_PWR_CFG_IDX_COUNT,
4652 };
4653 
4654 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4655                                          struct ieee80211_channel *chan,
4656                                          int power_level)
4657 {
4658         u8 txpower;
4659         u16 eeprom;
4660         u32 regs[TX_PWR_CFG_IDX_COUNT];
4661         unsigned int offset;
4662         enum nl80211_band band = chan->band;
4663         int delta;
4664         int i;
4665 
4666         memset(regs, '\0', sizeof(regs));
4667 
4668         /* TODO: adapt TX power reduction from the rt28xx code */
4669 
4670         /* calculate temperature compensation delta */
4671         delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4672 
4673         if (band == NL80211_BAND_5GHZ)
4674                 offset = 16;
4675         else
4676                 offset = 0;
4677 
4678         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4679                 offset += 8;
4680 
4681         /* read the next four txpower values */
4682         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4683                                                offset);
4684 
4685         /* CCK 1MBS,2MBS */
4686         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4687         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4688                                             txpower, delta);
4689         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4690                            TX_PWR_CFG_0_CCK1_CH0, txpower);
4691         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4692                            TX_PWR_CFG_0_CCK1_CH1, txpower);
4693         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4694                            TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4695 
4696         /* CCK 5.5MBS,11MBS */
4697         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4698         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4699                                             txpower, delta);
4700         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4701                            TX_PWR_CFG_0_CCK5_CH0, txpower);
4702         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4703                            TX_PWR_CFG_0_CCK5_CH1, txpower);
4704         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4705                            TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4706 
4707         /* OFDM 6MBS,9MBS */
4708         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4709         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4710                                             txpower, delta);
4711         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4712                            TX_PWR_CFG_0_OFDM6_CH0, txpower);
4713         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4714                            TX_PWR_CFG_0_OFDM6_CH1, txpower);
4715         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4716                            TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4717 
4718         /* OFDM 12MBS,18MBS */
4719         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4720         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4721                                             txpower, delta);
4722         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4723                            TX_PWR_CFG_0_OFDM12_CH0, txpower);
4724         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4725                            TX_PWR_CFG_0_OFDM12_CH1, txpower);
4726         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4727                            TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4728 
4729         /* read the next four txpower values */
4730         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4731                                                offset + 1);
4732 
4733         /* OFDM 24MBS,36MBS */
4734         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4735         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4736                                             txpower, delta);
4737         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4738                            TX_PWR_CFG_1_OFDM24_CH0, txpower);
4739         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4740                            TX_PWR_CFG_1_OFDM24_CH1, txpower);
4741         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4742                            TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4743 
4744         /* OFDM 48MBS */
4745         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4746         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4747                                             txpower, delta);
4748         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4749                            TX_PWR_CFG_1_OFDM48_CH0, txpower);
4750         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4751                            TX_PWR_CFG_1_OFDM48_CH1, txpower);
4752         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4753                            TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4754 
4755         /* OFDM 54MBS */
4756         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4757         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4758                                             txpower, delta);
4759         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4760                            TX_PWR_CFG_7_OFDM54_CH0, txpower);
4761         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4762                            TX_PWR_CFG_7_OFDM54_CH1, txpower);
4763         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4764                            TX_PWR_CFG_7_OFDM54_CH2, txpower);
4765 
4766         /* read the next four txpower values */
4767         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4768                                                offset + 2);
4769 
4770         /* MCS 0,1 */
4771         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4772         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4773                                             txpower, delta);
4774         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4775                            TX_PWR_CFG_1_MCS0_CH0, txpower);
4776         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4777                            TX_PWR_CFG_1_MCS0_CH1, txpower);
4778         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4779                            TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4780 
4781         /* MCS 2,3 */
4782         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4783         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4784                                             txpower, delta);
4785         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4786                            TX_PWR_CFG_1_MCS2_CH0, txpower);
4787         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4788                            TX_PWR_CFG_1_MCS2_CH1, txpower);
4789         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4790                            TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4791 
4792         /* MCS 4,5 */
4793         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4794         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4795                                             txpower, delta);
4796         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4797                            TX_PWR_CFG_2_MCS4_CH0, txpower);
4798         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4799                            TX_PWR_CFG_2_MCS4_CH1, txpower);
4800         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4801                            TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4802 
4803         /* MCS 6 */
4804         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4805         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4806                                             txpower, delta);
4807         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4808                            TX_PWR_CFG_2_MCS6_CH0, txpower);
4809         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4810                            TX_PWR_CFG_2_MCS6_CH1, txpower);
4811         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4812                            TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4813 
4814         /* read the next four txpower values */
4815         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4816                                                offset + 3);
4817 
4818         /* MCS 7 */
4819         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4820         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4821                                             txpower, delta);
4822         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4823                            TX_PWR_CFG_7_MCS7_CH0, txpower);
4824         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4825                            TX_PWR_CFG_7_MCS7_CH1, txpower);
4826         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4827                            TX_PWR_CFG_7_MCS7_CH2, txpower);
4828 
4829         /* MCS 8,9 */
4830         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4831         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4832                                             txpower, delta);
4833         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4834                            TX_PWR_CFG_2_MCS8_CH0, txpower);
4835         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4836                            TX_PWR_CFG_2_MCS8_CH1, txpower);
4837         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4838                            TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4839 
4840         /* MCS 10,11 */
4841         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4842         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4843                                             txpower, delta);
4844         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4845                            TX_PWR_CFG_2_MCS10_CH0, txpower);
4846         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4847                            TX_PWR_CFG_2_MCS10_CH1, txpower);
4848         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4849                            TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4850 
4851         /* MCS 12,13 */
4852         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4853         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4854                                             txpower, delta);
4855         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4856                            TX_PWR_CFG_3_MCS12_CH0, txpower);
4857         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4858                            TX_PWR_CFG_3_MCS12_CH1, txpower);
4859         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4860                            TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4861 
4862         /* read the next four txpower values */
4863         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4864                                                offset + 4);
4865 
4866         /* MCS 14 */
4867         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4868         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4869                                             txpower, delta);
4870         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4871                            TX_PWR_CFG_3_MCS14_CH0, txpower);
4872         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4873                            TX_PWR_CFG_3_MCS14_CH1, txpower);
4874         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4875                            TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4876 
4877         /* MCS 15 */
4878         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4879         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4880                                             txpower, delta);
4881         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4882                            TX_PWR_CFG_8_MCS15_CH0, txpower);
4883         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4884                            TX_PWR_CFG_8_MCS15_CH1, txpower);
4885         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4886                            TX_PWR_CFG_8_MCS15_CH2, txpower);
4887 
4888         /* MCS 16,17 */
4889         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4890         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4891                                             txpower, delta);
4892         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4893                            TX_PWR_CFG_5_MCS16_CH0, txpower);
4894         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4895                            TX_PWR_CFG_5_MCS16_CH1, txpower);
4896         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4897                            TX_PWR_CFG_5_MCS16_CH2, txpower);
4898 
4899         /* MCS 18,19 */
4900         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4901         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4902                                             txpower, delta);
4903         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4904                            TX_PWR_CFG_5_MCS18_CH0, txpower);
4905         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4906                            TX_PWR_CFG_5_MCS18_CH1, txpower);
4907         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4908                            TX_PWR_CFG_5_MCS18_CH2, txpower);
4909 
4910         /* read the next four txpower values */
4911         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4912                                                offset + 5);
4913 
4914         /* MCS 20,21 */
4915         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4916         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4917                                             txpower, delta);
4918         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4919                            TX_PWR_CFG_6_MCS20_CH0, txpower);
4920         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4921                            TX_PWR_CFG_6_MCS20_CH1, txpower);
4922         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4923                            TX_PWR_CFG_6_MCS20_CH2, txpower);
4924 
4925         /* MCS 22 */
4926         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4927         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4928                                             txpower, delta);
4929         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4930                            TX_PWR_CFG_6_MCS22_CH0, txpower);
4931         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4932                            TX_PWR_CFG_6_MCS22_CH1, txpower);
4933         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4934                            TX_PWR_CFG_6_MCS22_CH2, txpower);
4935 
4936         /* MCS 23 */
4937         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4938         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4939                                             txpower, delta);
4940         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4941                            TX_PWR_CFG_8_MCS23_CH0, txpower);
4942         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4943                            TX_PWR_CFG_8_MCS23_CH1, txpower);
4944         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4945                            TX_PWR_CFG_8_MCS23_CH2, txpower);
4946 
4947         /* read the next four txpower values */
4948         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4949                                                offset + 6);
4950 
4951         /* STBC, MCS 0,1 */
4952         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4953         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4954                                             txpower, delta);
4955         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4956                            TX_PWR_CFG_3_STBC0_CH0, txpower);
4957         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4958                            TX_PWR_CFG_3_STBC0_CH1, txpower);
4959         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4960                            TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4961 
4962         /* STBC, MCS 2,3 */
4963         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4964         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4965                                             txpower, delta);
4966         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4967                            TX_PWR_CFG_3_STBC2_CH0, txpower);
4968         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4969                            TX_PWR_CFG_3_STBC2_CH1, txpower);
4970         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4971                            TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4972 
4973         /* STBC, MCS 4,5 */
4974         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4975         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4976                                             txpower, delta);
4977         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4978         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4979         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4980                            txpower);
4981 
4982         /* STBC, MCS 6 */
4983         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4984         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4985                                             txpower, delta);
4986         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4987         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4988         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4989                            txpower);
4990 
4991         /* read the next four txpower values */
4992         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4993                                                offset + 7);
4994 
4995         /* STBC, MCS 7 */
4996         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4997         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4998                                             txpower, delta);
4999         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5000                            TX_PWR_CFG_9_STBC7_CH0, txpower);
5001         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5002                            TX_PWR_CFG_9_STBC7_CH1, txpower);
5003         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5004                            TX_PWR_CFG_9_STBC7_CH2, txpower);
5005 
5006         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
5007         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
5008         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
5009         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
5010         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
5011         rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
5012         rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
5013         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
5014         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
5015         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
5016 
5017         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
5018                               regs[TX_PWR_CFG_0_EXT_IDX]);
5019         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
5020                               regs[TX_PWR_CFG_1_EXT_IDX]);
5021         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
5022                               regs[TX_PWR_CFG_2_EXT_IDX]);
5023         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
5024                               regs[TX_PWR_CFG_3_EXT_IDX]);
5025         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
5026                               regs[TX_PWR_CFG_4_EXT_IDX]);
5027 
5028         for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
5029                 rt2x00_dbg(rt2x00dev,
5030                            "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
5031                            (band == NL80211_BAND_5GHZ) ? '5' : '2',
5032                            (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
5033                                                                 '4' : '2',
5034                            (i > TX_PWR_CFG_9_IDX) ?
5035                                         (i - TX_PWR_CFG_9_IDX - 1) : i,
5036                            (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
5037                            (unsigned long) regs[i]);
5038 }
5039 
5040 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
5041                                          struct ieee80211_channel *chan,
5042                                          int power_level)
5043 {
5044         u32 reg, pwreg;
5045         u16 eeprom;
5046         u32 data, gdata;
5047         u8 t, i;
5048         enum nl80211_band band = chan->band;
5049         int delta;
5050 
5051         /* Warn user if bw_comp is set in EEPROM */
5052         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5053 
5054         if (delta)
5055                 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
5056                             delta);
5057 
5058         /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
5059          * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
5060          * driver does as well, though it looks kinda wrong.
5061          * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
5062          * the hardware has a problem handling 0x20, and as the code initially
5063          * used a fixed offset between HT20 and HT40 rates they had to work-
5064          * around that issue and most likely just forgot about it later on.
5065          * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
5066          * however, the corresponding EEPROM value is not respected by the
5067          * vendor driver, so maybe this is rather being taken care of the
5068          * TXALC and the driver doesn't need to handle it...?
5069          * Though this is all very awkward, just do as they did, as that's what
5070          * board vendors expected when they populated the EEPROM...
5071          */
5072         for (i = 0; i < 5; i++) {
5073                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5074                                                        EEPROM_TXPOWER_BYRATE,
5075                                                        i * 2);
5076 
5077                 data = eeprom;
5078 
5079                 t = eeprom & 0x3f;
5080                 if (t == 32)
5081                         t++;
5082 
5083                 gdata = t;
5084 
5085                 t = (eeprom & 0x3f00) >> 8;
5086                 if (t == 32)
5087                         t++;
5088 
5089                 gdata |= (t << 8);
5090 
5091                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5092                                                        EEPROM_TXPOWER_BYRATE,
5093                                                        (i * 2) + 1);
5094 
5095                 t = eeprom & 0x3f;
5096                 if (t == 32)
5097                         t++;
5098 
5099                 gdata |= (t << 16);
5100 
5101                 t = (eeprom & 0x3f00) >> 8;
5102                 if (t == 32)
5103                         t++;
5104 
5105                 gdata |= (t << 24);
5106                 data |= (eeprom << 16);
5107 
5108                 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
5109                         /* HT20 */
5110                         if (data != 0xffffffff)
5111                                 rt2800_register_write(rt2x00dev,
5112                                                       TX_PWR_CFG_0 + (i * 4),
5113                                                       data);
5114                 } else {
5115                         /* HT40 */
5116                         if (gdata != 0xffffffff)
5117                                 rt2800_register_write(rt2x00dev,
5118                                                       TX_PWR_CFG_0 + (i * 4),
5119                                                       gdata);
5120                 }
5121         }
5122 
5123         /* Aparently Ralink ran out of space in the BYRATE calibration section
5124          * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
5125          * registers. As recent 2T chips use 8-bit instead of 4-bit values for
5126          * power-offsets more space would be needed. Ralink decided to keep the
5127          * EEPROM layout untouched and rather have some shared values covering
5128          * multiple bitrates.
5129          * Populate the registers not covered by the EEPROM in the same way the
5130          * vendor driver does.
5131          */
5132 
5133         /* For OFDM 54MBS use value from OFDM 48MBS */
5134         pwreg = 0;
5135         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
5136         t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
5137         rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
5138 
5139         /* For MCS 7 use value from MCS 6 */
5140         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
5141         t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
5142         rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
5143         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
5144 
5145         /* For MCS 15 use value from MCS 14 */
5146         pwreg = 0;
5147         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
5148         t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
5149         rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
5150         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
5151 
5152         /* For STBC MCS 7 use value from STBC MCS 6 */
5153         pwreg = 0;
5154         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
5155         t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
5156         rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
5157         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
5158 
5159         rt2800_config_alc(rt2x00dev, chan, power_level);
5160 
5161         /* TODO: temperature compensation code! */
5162 }
5163 
5164 /*
5165  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
5166  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
5167  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
5168  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
5169  * Reference per rate transmit power values are located in the EEPROM at
5170  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
5171  * current conditions (i.e. band, bandwidth, temperature, user settings).
5172  */
5173 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
5174                                          struct ieee80211_channel *chan,
5175                                          int power_level)
5176 {
5177         u8 txpower, r1;
5178         u16 eeprom;
5179         u32 reg, offset;
5180         int i, is_rate_b, delta, power_ctrl;
5181         enum nl80211_band band = chan->band;
5182 
5183         /*
5184          * Calculate HT40 compensation. For 40MHz we need to add or subtract
5185          * value read from EEPROM (different for 2GHz and for 5GHz).
5186          */
5187         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5188 
5189         /*
5190          * Calculate temperature compensation. Depends on measurement of current
5191          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
5192          * to temperature or maybe other factors) is smaller or bigger than
5193          * expected. We adjust it, based on TSSI reference and boundaries values
5194          * provided in EEPROM.
5195          */
5196         switch (rt2x00dev->chip.rt) {
5197         case RT2860:
5198         case RT2872:
5199         case RT2883:
5200         case RT3070:
5201         case RT3071:
5202         case RT3090:
5203         case RT3572:
5204                 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
5205                 break;
5206         default:
5207                 /* TODO: temperature compensation code for other chips. */
5208                 break;
5209         }
5210 
5211         /*
5212          * Decrease power according to user settings, on devices with unknown
5213          * maximum tx power. For other devices we take user power_level into
5214          * consideration on rt2800_compensate_txpower().
5215          */
5216         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
5217                                               chan->max_power);
5218 
5219         /*
5220          * BBP_R1 controls TX power for all rates, it allow to set the following
5221          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
5222          *
5223          * TODO: we do not use +6 dBm option to do not increase power beyond
5224          * regulatory limit, however this could be utilized for devices with
5225          * CAPABILITY_POWER_LIMIT.
5226          */
5227         if (delta <= -12) {
5228                 power_ctrl = 2;
5229                 delta += 12;
5230         } else if (delta <= -6) {
5231                 power_ctrl = 1;
5232                 delta += 6;
5233         } else {
5234                 power_ctrl = 0;
5235         }
5236         r1 = rt2800_bbp_read(rt2x00dev, 1);
5237         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
5238         rt2800_bbp_write(rt2x00dev, 1, r1);
5239 
5240         offset = TX_PWR_CFG_0;
5241 
5242         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
5243                 /* just to be safe */
5244                 if (offset > TX_PWR_CFG_4)
5245                         break;
5246 
5247                 reg = rt2800_register_read(rt2x00dev, offset);
5248 
5249                 /* read the next four txpower values */
5250                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5251                                                        EEPROM_TXPOWER_BYRATE,
5252                                                        i);
5253 
5254                 is_rate_b = i ? 0 : 1;
5255                 /*
5256                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5257                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
5258                  * TX_PWR_CFG_4: unknown
5259                  */
5260                 txpower = rt2x00_get_field16(eeprom,
5261                                              EEPROM_TXPOWER_BYRATE_RATE0);
5262                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5263                                              power_level, txpower, delta);
5264                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5265 
5266                 /*
5267                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5268                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
5269                  * TX_PWR_CFG_4: unknown
5270                  */
5271                 txpower = rt2x00_get_field16(eeprom,
5272                                              EEPROM_TXPOWER_BYRATE_RATE1);
5273                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5274                                              power_level, txpower, delta);
5275                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5276 
5277                 /*
5278                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5279                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
5280                  * TX_PWR_CFG_4: unknown
5281                  */
5282                 txpower = rt2x00_get_field16(eeprom,
5283                                              EEPROM_TXPOWER_BYRATE_RATE2);
5284                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5285                                              power_level, txpower, delta);
5286                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5287 
5288                 /*
5289                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5290                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
5291                  * TX_PWR_CFG_4: unknown
5292                  */
5293                 txpower = rt2x00_get_field16(eeprom,
5294                                              EEPROM_TXPOWER_BYRATE_RATE3);
5295                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5296                                              power_level, txpower, delta);
5297                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5298 
5299                 /* read the next four txpower values */
5300                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5301                                                        EEPROM_TXPOWER_BYRATE,
5302                                                        i + 1);
5303 
5304                 is_rate_b = 0;
5305                 /*
5306                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5307                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
5308                  * TX_PWR_CFG_4: unknown
5309                  */
5310                 txpower = rt2x00_get_field16(eeprom,
5311                                              EEPROM_TXPOWER_BYRATE_RATE0);
5312                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5313                                              power_level, txpower, delta);
5314                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5315 
5316                 /*
5317                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5318                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
5319                  * TX_PWR_CFG_4: unknown
5320                  */
5321                 txpower = rt2x00_get_field16(eeprom,
5322                                              EEPROM_TXPOWER_BYRATE_RATE1);
5323                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5324                                              power_level, txpower, delta);
5325                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5326 
5327                 /*
5328                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5329                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
5330                  * TX_PWR_CFG_4: unknown
5331                  */
5332                 txpower = rt2x00_get_field16(eeprom,
5333                                              EEPROM_TXPOWER_BYRATE_RATE2);
5334                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5335                                              power_level, txpower, delta);
5336                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5337 
5338                 /*
5339                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5340                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
5341                  * TX_PWR_CFG_4: unknown
5342                  */
5343                 txpower = rt2x00_get_field16(eeprom,
5344                                              EEPROM_TXPOWER_BYRATE_RATE3);
5345                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5346                                              power_level, txpower, delta);
5347                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5348 
5349                 rt2800_register_write(rt2x00dev, offset, reg);
5350 
5351                 /* next TX_PWR_CFG register */
5352                 offset += 4;
5353         }
5354 }
5355 
5356 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5357                                   struct ieee80211_channel *chan,
5358                                   int power_level)
5359 {
5360         if (rt2x00_rt(rt2x00dev, RT3593) ||
5361             rt2x00_rt(rt2x00dev, RT3883))
5362                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
5363         else if (rt2x00_rt(rt2x00dev, RT6352))
5364                 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
5365         else
5366                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
5367 }
5368 
5369 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
5370 {
5371         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5372                               rt2x00dev->tx_power);
5373 }
5374 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
5375 
5376 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
5377 {
5378         u32     tx_pin;
5379         u8      rfcsr;
5380         unsigned long min_sleep = 0;
5381 
5382         /*
5383          * A voltage-controlled oscillator(VCO) is an electronic oscillator
5384          * designed to be controlled in oscillation frequency by a voltage
5385          * input. Maybe the temperature will affect the frequency of
5386          * oscillation to be shifted. The VCO calibration will be called
5387          * periodically to adjust the frequency to be precision.
5388         */
5389 
5390         tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5391         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
5392         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5393 
5394         switch (rt2x00dev->chip.rf) {
5395         case RF2020:
5396         case RF3020:
5397         case RF3021:
5398         case RF3022:
5399         case RF3320:
5400         case RF3052:
5401                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5402                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
5403                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5404                 break;
5405         case RF3053:
5406         case RF3070:
5407         case RF3290:
5408         case RF3853:
5409         case RF5350:
5410         case RF5360:
5411         case RF5362:
5412         case RF5370:
5413         case RF5372:
5414         case RF5390:
5415         case RF5392:
5416         case RF5592:
5417                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5418                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
5419                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5420                 min_sleep = 1000;
5421                 break;
5422         case RF7620:
5423                 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
5424                 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
5425                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5426                 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
5427                 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
5428                 min_sleep = 2000;
5429                 break;
5430         default:
5431                 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration",
5432                           rt2x00dev->chip.rf);
5433                 return;
5434         }
5435 
5436         if (min_sleep > 0)
5437                 usleep_range(min_sleep, min_sleep * 2);
5438 
5439         tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5440         if (rt2x00dev->rf_channel <= 14) {
5441                 switch (rt2x00dev->default_ant.tx_chain_num) {
5442                 case 3:
5443                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
5444                         /* fall through */
5445                 case 2:
5446                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
5447                         /* fall through */
5448                 case 1:
5449                 default:
5450                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
5451                         break;
5452                 }
5453         } else {
5454                 switch (rt2x00dev->default_ant.tx_chain_num) {
5455                 case 3:
5456                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
5457                         /* fall through */
5458                 case 2:
5459                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
5460                         /* fall through */
5461                 case 1:
5462                 default:
5463                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
5464                         break;
5465                 }
5466         }
5467         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5468 
5469         if (rt2x00_rt(rt2x00dev, RT6352)) {
5470                 if (rt2x00dev->default_ant.rx_chain_num == 1) {
5471                         rt2800_bbp_write(rt2x00dev, 91, 0x07);
5472                         rt2800_bbp_write(rt2x00dev, 95, 0x1A);
5473                         rt2800_bbp_write(rt2x00dev, 195, 128);
5474                         rt2800_bbp_write(rt2x00dev, 196, 0xA0);
5475                         rt2800_bbp_write(rt2x00dev, 195, 170);
5476                         rt2800_bbp_write(rt2x00dev, 196, 0x12);
5477                         rt2800_bbp_write(rt2x00dev, 195, 171);
5478                         rt2800_bbp_write(rt2x00dev, 196, 0x10);
5479                 } else {
5480                         rt2800_bbp_write(rt2x00dev, 91, 0x06);
5481                         rt2800_bbp_write(rt2x00dev, 95, 0x9A);
5482                         rt2800_bbp_write(rt2x00dev, 195, 128);
5483                         rt2800_bbp_write(rt2x00dev, 196, 0xE0);
5484                         rt2800_bbp_write(rt2x00dev, 195, 170);
5485                         rt2800_bbp_write(rt2x00dev, 196, 0x30);
5486                         rt2800_bbp_write(rt2x00dev, 195, 171);
5487                         rt2800_bbp_write(rt2x00dev, 196, 0x30);
5488                 }
5489 
5490                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
5491                         rt2800_bbp_write(rt2x00dev, 75, 0x68);
5492                         rt2800_bbp_write(rt2x00dev, 76, 0x4C);
5493                         rt2800_bbp_write(rt2x00dev, 79, 0x1C);
5494                         rt2800_bbp_write(rt2x00dev, 80, 0x0C);
5495                         rt2800_bbp_write(rt2x00dev, 82, 0xB6);
5496                 }
5497 
5498                 /* On 11A, We should delay and wait RF/BBP to be stable
5499                  * and the appropriate time should be 1000 micro seconds
5500                  * 2005/06/05 - On 11G, we also need this delay time.
5501                  * Otherwise it's difficult to pass the WHQL.
5502                  */
5503                 usleep_range(1000, 1500);
5504         }
5505 }
5506 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
5507 
5508 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5509                                       struct rt2x00lib_conf *libconf)
5510 {
5511         u32 reg;
5512 
5513         reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5514         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
5515                            libconf->conf->short_frame_max_tx_count);
5516         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
5517                            libconf->conf->long_frame_max_tx_count);
5518         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5519 }
5520 
5521 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5522                              struct rt2x00lib_conf *libconf)
5523 {
5524         enum dev_state state =
5525             (libconf->conf->flags & IEEE80211_CONF_PS) ?
5526                 STATE_SLEEP : STATE_AWAKE;
5527         u32 reg;
5528 
5529         if (state == STATE_SLEEP) {
5530                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5531 
5532                 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5533                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5534                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5535                                    libconf->conf->listen_interval - 1);
5536                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5537                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5538 
5539                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5540         } else {
5541                 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5542                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5543                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5544                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5545                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5546 
5547                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5548         }
5549 }
5550 
5551 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5552                    struct rt2x00lib_conf *libconf,
5553                    const unsigned int flags)
5554 {
5555         /* Always recalculate LNA gain before changing configuration */
5556         rt2800_config_lna_gain(rt2x00dev, libconf);
5557 
5558         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
5559                 rt2800_config_channel(rt2x00dev, libconf->conf,
5560                                       &libconf->rf, &libconf->channel);
5561                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5562                                       libconf->conf->power_level);
5563         }
5564         if (flags & IEEE80211_CONF_CHANGE_POWER)
5565                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5566                                       libconf->conf->power_level);
5567         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5568                 rt2800_config_retry_limit(rt2x00dev, libconf);
5569         if (flags & IEEE80211_CONF_CHANGE_PS)
5570                 rt2800_config_ps(rt2x00dev, libconf);
5571 }
5572 EXPORT_SYMBOL_GPL(rt2800_config);
5573 
5574 /*
5575  * Link tuning
5576  */
5577 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5578 {
5579         u32 reg;
5580 
5581         /*
5582          * Update FCS error count from register.
5583          */
5584         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5585         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5586 }
5587 EXPORT_SYMBOL_GPL(rt2800_link_stats);
5588 
5589 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5590 {
5591         u8 vgc;
5592 
5593         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5594                 if (rt2x00_rt(rt2x00dev, RT3070) ||
5595                     rt2x00_rt(rt2x00dev, RT3071) ||
5596                     rt2x00_rt(rt2x00dev, RT3090) ||
5597                     rt2x00_rt(rt2x00dev, RT3290) ||
5598                     rt2x00_rt(rt2x00dev, RT3390) ||
5599                     rt2x00_rt(rt2x00dev, RT3572) ||
5600                     rt2x00_rt(rt2x00dev, RT3593) ||
5601                     rt2x00_rt(rt2x00dev, RT5390) ||
5602                     rt2x00_rt(rt2x00dev, RT5392) ||
5603                     rt2x00_rt(rt2x00dev, RT5592) ||
5604                     rt2x00_rt(rt2x00dev, RT6352))
5605                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5606                 else
5607                         vgc = 0x2e + rt2x00dev->lna_gain;
5608         } else { /* 5GHZ band */
5609                 if (rt2x00_rt(rt2x00dev, RT3593) ||
5610                     rt2x00_rt(rt2x00dev, RT3883))
5611                         vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5612                 else if (rt2x00_rt(rt2x00dev, RT5592))
5613                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5614                 else {
5615                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5616                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5617                         else
5618                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5619                 }
5620         }
5621 
5622         return vgc;
5623 }
5624 
5625 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5626                                   struct link_qual *qual, u8 vgc_level)
5627 {
5628         if (qual->vgc_level != vgc_level) {
5629                 if (rt2x00_rt(rt2x00dev, RT3572) ||
5630                     rt2x00_rt(rt2x00dev, RT3593) ||
5631                     rt2x00_rt(rt2x00dev, RT3883)) {
5632                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5633                                                        vgc_level);
5634                 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5635                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5636                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5637                 } else {
5638                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5639                 }
5640 
5641                 qual->vgc_level = vgc_level;
5642                 qual->vgc_level_reg = vgc_level;
5643         }
5644 }
5645 
5646 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5647 {
5648         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5649 }
5650 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5651 
5652 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5653                        const u32 count)
5654 {
5655         u8 vgc;
5656 
5657         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5658                 return;
5659 
5660         /* When RSSI is better than a certain threshold, increase VGC
5661          * with a chip specific value in order to improve the balance
5662          * between sensibility and noise isolation.
5663          */
5664 
5665         vgc = rt2800_get_default_vgc(rt2x00dev);
5666 
5667         switch (rt2x00dev->chip.rt) {
5668         case RT3572:
5669         case RT3593:
5670                 if (qual->rssi > -65) {
5671                         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5672                                 vgc += 0x20;
5673                         else
5674                                 vgc += 0x10;
5675                 }
5676                 break;
5677 
5678         case RT3883:
5679                 if (qual->rssi > -65)
5680                         vgc += 0x10;
5681                 break;
5682 
5683         case RT5592:
5684                 if (qual->rssi > -65)
5685                         vgc += 0x20;
5686                 break;
5687 
5688         default:
5689                 if (qual->rssi > -80)
5690                         vgc += 0x10;
5691                 break;
5692         }
5693 
5694         rt2800_set_vgc(rt2x00dev, qual, vgc);
5695 }
5696 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
5697 
5698 /*
5699  * Initialization functions.
5700  */
5701 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5702 {
5703         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5704         u32 reg;
5705         u16 eeprom;
5706         unsigned int i;
5707         int ret;
5708 
5709         rt2800_disable_wpdma(rt2x00dev);
5710 
5711         ret = rt2800_drv_init_registers(rt2x00dev);
5712         if (ret)
5713                 return ret;
5714 
5715         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5716         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5717 
5718         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5719 
5720         reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5721         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
5722         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5723         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5724         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5725         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5726         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5727         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5728 
5729         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5730 
5731         reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5732         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5733         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5734         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5735 
5736         if (rt2x00_rt(rt2x00dev, RT3290)) {
5737                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5738                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5739                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
5740                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5741                 }
5742 
5743                 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5744                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5745                         rt2x00_set_field32(&reg, LDO0_EN, 1);
5746                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
5747                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5748                 }
5749 
5750                 reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5751                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
5752                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
5753                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
5754                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5755 
5756                 reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5757                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
5758                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5759 
5760                 reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5761                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
5762                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
5763                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
5764                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
5765                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5766 
5767                 reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5768                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
5769                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5770         }
5771 
5772         if (rt2x00_rt(rt2x00dev, RT3071) ||
5773             rt2x00_rt(rt2x00dev, RT3090) ||
5774             rt2x00_rt(rt2x00dev, RT3290) ||
5775             rt2x00_rt(rt2x00dev, RT3390)) {
5776 
5777                 if (rt2x00_rt(rt2x00dev, RT3290))
5778                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5779                                               0x00000404);
5780                 else
5781                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5782                                               0x00000400);
5783 
5784                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5785                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5786                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5787                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5788                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5789                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5790                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5791                                                       0x0000002c);
5792                         else
5793                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5794                                                       0x0000000f);
5795                 } else {
5796                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5797                 }
5798         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
5799                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5800 
5801                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5802                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5803                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5804                 } else {
5805                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5806                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5807                 }
5808         } else if (rt2800_is_305x_soc(rt2x00dev)) {
5809                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5810                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5811                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5812         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5813                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5814                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5815                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5816         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5817                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5818                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5819         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5820                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5821                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5822                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5823                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5824                         if (rt2x00_get_field16(eeprom,
5825                                                EEPROM_NIC_CONF1_DAC_TEST))
5826                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5827                                                       0x0000001f);
5828                         else
5829                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5830                                                       0x0000000f);
5831                 } else {
5832                         rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5833                                               0x00000000);
5834                 }
5835         } else if (rt2x00_rt(rt2x00dev, RT3883)) {
5836                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5837                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5838                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
5839                 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
5840                 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
5841         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
5842                    rt2x00_rt(rt2x00dev, RT5392)) {
5843                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5844                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5845                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5846         } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5847                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5848                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5849                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5850         } else if (rt2x00_rt(rt2x00dev, RT5350)) {
5851                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5852         } else if (rt2x00_rt(rt2x00dev, RT6352)) {
5853                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5854                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
5855                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5856                 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
5857                 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5858                 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5859                 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5860                 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5861                 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5862                                       0x3630363A);
5863                 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5864                                       0x3630363A);
5865                 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
5866                 rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5867                 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
5868         } else {
5869                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5870                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5871         }
5872 
5873         reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
5874         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5875         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5876         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5877         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5878         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5879         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5880         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
5881         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
5882         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5883 
5884         reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
5885         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
5886         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
5887         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5888         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5889 
5890         reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
5891         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5892         if (rt2x00_is_usb(rt2x00dev)) {
5893                 drv_data->max_psdu = 3;
5894         } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5895                    rt2x00_rt(rt2x00dev, RT2883) ||
5896                    rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
5897                 drv_data->max_psdu = 2;
5898         } else {
5899                 drv_data->max_psdu = 1;
5900         }
5901         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
5902         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
5903         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
5904         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5905 
5906         reg = rt2800_register_read(rt2x00dev, LED_CFG);
5907         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
5908         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
5909         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
5910         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
5911         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
5912         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
5913         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
5914         rt2800_register_write(rt2x00dev, LED_CFG, reg);
5915 
5916         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5917 
5918         reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5919         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
5920         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
5921         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5922         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5923         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
5924         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5925         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5926 
5927         reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
5928         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
5929         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
5930         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
5931         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
5932         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
5933         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5934         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5935         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5936 
5937         reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
5938         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
5939         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
5940         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
5941         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5942         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5943         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5944         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5945         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5946         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5947         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
5948         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5949 
5950         reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
5951         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
5952         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
5953         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
5954         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5955         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5956         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5957         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5958         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5959         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5960         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
5961         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5962 
5963         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
5964         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
5965         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
5966         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5967         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5968         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5969         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5970         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5971         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5972         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5973         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
5974         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5975 
5976         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
5977         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
5978         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
5979         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5980         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5981         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5982         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5983         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5984         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5985         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5986         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
5987         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5988 
5989         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
5990         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
5991         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
5992         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5993         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5994         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5995         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5996         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5997         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5998         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5999         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
6000         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6001 
6002         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
6003         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
6004         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
6005         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
6006         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6007         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6008         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6009         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
6010         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6011         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
6012         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
6013         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6014 
6015         if (rt2x00_is_usb(rt2x00dev)) {
6016                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
6017 
6018                 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
6019                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
6020                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
6021                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
6022                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
6023                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
6024                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
6025                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
6026                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
6027                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
6028                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6029         }
6030 
6031         /*
6032          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
6033          * although it is reserved.
6034          */
6035         reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
6036         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
6037         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
6038         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
6039         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
6040         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
6041         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
6042         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
6043         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
6044         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
6045         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
6046         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
6047 
6048         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
6049         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
6050 
6051         if (rt2x00_rt(rt2x00dev, RT3883)) {
6052                 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
6053                 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
6054         }
6055 
6056         reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
6057         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
6058         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
6059                            IEEE80211_MAX_RTS_THRESHOLD);
6060         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
6061         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6062 
6063         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
6064 
6065         /*
6066          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
6067          * time should be set to 16. However, the original Ralink driver uses
6068          * 16 for both and indeed using a value of 10 for CCK SIFS results in
6069          * connection problems with 11g + CTS protection. Hence, use the same
6070          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
6071          */
6072         reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
6073         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
6074         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
6075         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
6076         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
6077         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
6078         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
6079 
6080         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
6081 
6082         /*
6083          * ASIC will keep garbage value after boot, clear encryption keys.
6084          */
6085         for (i = 0; i < 4; i++)
6086                 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0);
6087 
6088         for (i = 0; i < 256; i++) {
6089                 rt2800_config_wcid(rt2x00dev, NULL, i);
6090                 rt2800_delete_wcid_attr(rt2x00dev, i);
6091         }
6092 
6093         /*
6094          * Clear encryption initialization vectors on start, but keep them
6095          * for watchdog reset. Otherwise we will have wrong IVs and not be
6096          * able to keep connections after reset.
6097          */
6098         if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
6099                 for (i = 0; i < 256; i++)
6100                         rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
6101 
6102         /*
6103          * Clear all beacons
6104          */
6105         for (i = 0; i < 8; i++)
6106                 rt2800_clear_beacon_register(rt2x00dev, i);
6107 
6108         if (rt2x00_is_usb(rt2x00dev)) {
6109                 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6110                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
6111                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6112         } else if (rt2x00_is_pcie(rt2x00dev)) {
6113                 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6114                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
6115                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6116         }
6117 
6118         reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
6119         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
6120         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
6121         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
6122         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
6123         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
6124         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
6125         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
6126         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
6127         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
6128 
6129         reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
6130         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
6131         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
6132         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
6133         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
6134         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
6135         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
6136         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
6137         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
6138         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
6139 
6140         reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
6141         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
6142         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
6143         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
6144         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
6145         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
6146         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
6147         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
6148         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
6149         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
6150 
6151         reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
6152         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
6153         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
6154         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
6155         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
6156         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
6157 
6158         /*
6159          * Do not force the BA window size, we use the TXWI to set it
6160          */
6161         reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
6162         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
6163         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
6164         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
6165 
6166         /*
6167          * We must clear the error counters.
6168          * These registers are cleared on read,
6169          * so we may pass a useless variable to store the value.
6170          */
6171         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
6172         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
6173         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
6174         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
6175         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
6176         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
6177 
6178         /*
6179          * Setup leadtime for pre tbtt interrupt to 6ms
6180          */
6181         reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
6182         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
6183         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
6184 
6185         /*
6186          * Set up channel statistics timer
6187          */
6188         reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
6189         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
6190         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
6191         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
6192         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
6193         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
6194         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
6195 
6196         return 0;
6197 }
6198 
6199 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
6200 {
6201         unsigned int i;
6202         u32 reg;
6203 
6204         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6205                 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
6206                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
6207                         return 0;
6208 
6209                 udelay(REGISTER_BUSY_DELAY);
6210         }
6211 
6212         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
6213         return -EACCES;
6214 }
6215 
6216 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
6217 {
6218         unsigned int i;
6219         u8 value;
6220 
6221         /*
6222          * BBP was enabled after firmware was loaded,
6223          * but we need to reactivate it now.
6224          */
6225         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6226         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6227         msleep(1);
6228 
6229         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6230                 value = rt2800_bbp_read(rt2x00dev, 0);
6231                 if ((value != 0xff) && (value != 0x00))
6232                         return 0;
6233                 udelay(REGISTER_BUSY_DELAY);
6234         }
6235 
6236         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
6237         return -EACCES;
6238 }
6239 
6240 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
6241 {
6242         u8 value;
6243 
6244         value = rt2800_bbp_read(rt2x00dev, 4);
6245         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
6246         rt2800_bbp_write(rt2x00dev, 4, value);
6247 }
6248 
6249 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
6250 {
6251         rt2800_bbp_write(rt2x00dev, 142, 1);
6252         rt2800_bbp_write(rt2x00dev, 143, 57);
6253 }
6254 
6255 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
6256 {
6257         static const u8 glrt_table[] = {
6258                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
6259                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
6260                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
6261                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
6262                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
6263                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
6264                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
6265                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
6266                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
6267         };
6268         int i;
6269 
6270         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
6271                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
6272                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
6273         }
6274 };
6275 
6276 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
6277 {
6278         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6279         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6280         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
6281         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6282         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6283         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6284         rt2800_bbp_write(rt2x00dev, 81, 0x37);
6285         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6286         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
6287         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6288         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6289         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6290         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6291         rt2800_bbp_write(rt2x00dev, 103, 0x00);
6292         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6293         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6294 }
6295 
6296 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
6297 {
6298         u16 eeprom;
6299         u8 value;
6300 
6301         value = rt2800_bbp_read(rt2x00dev, 138);
6302         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6303         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6304                 value |= 0x20;
6305         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6306                 value &= ~0x02;
6307         rt2800_bbp_write(rt2x00dev, 138, value);
6308 }
6309 
6310 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
6311 {
6312         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6313 
6314         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6315         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6316 
6317         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6318         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6319 
6320         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6321 
6322         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6323         rt2800_bbp_write(rt2x00dev, 80, 0x08);
6324 
6325         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6326 
6327         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6328 
6329         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6330 
6331         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6332 
6333         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6334 
6335         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6336 
6337         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6338 
6339         rt2800_bbp_write(rt2x00dev, 105, 0x01);
6340 
6341         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6342 }
6343 
6344 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
6345 {
6346         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6347         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6348 
6349         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
6350                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
6351                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
6352         } else {
6353                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6354                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6355         }
6356 
6357         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6358 
6359         rt2800_bbp_write(rt2x00dev, 81, 0x37);
6360 
6361         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6362 
6363         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6364 
6365         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
6366                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6367         else
6368                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6369 
6370         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6371 
6372         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6373 
6374         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6375 
6376         rt2800_bbp_write(rt2x00dev, 103, 0x00);
6377 
6378         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6379 
6380         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6381 }
6382 
6383 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
6384 {
6385         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6386         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6387 
6388         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6389         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6390 
6391         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6392 
6393         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6394         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6395         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6396 
6397         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6398 
6399         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6400 
6401         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6402 
6403         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6404 
6405         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6406 
6407         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6408 
6409         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
6410             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
6411             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
6412                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6413         else
6414                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6415 
6416         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6417 
6418         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6419 
6420         if (rt2x00_rt(rt2x00dev, RT3071) ||
6421             rt2x00_rt(rt2x00dev, RT3090))
6422                 rt2800_disable_unused_dac_adc(rt2x00dev);
6423 }
6424 
6425 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
6426 {
6427         u8 value;
6428 
6429         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6430 
6431         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6432 
6433         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6434         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6435 
6436         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6437 
6438         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6439         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6440         rt2800_bbp_write(rt2x00dev, 75, 0x46);
6441         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6442 
6443         rt2800_bbp_write(rt2x00dev, 77, 0x58);
6444 
6445         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6446 
6447         rt2800_bbp_write(rt2x00dev, 74, 0x0b);
6448         rt2800_bbp_write(rt2x00dev, 79, 0x18);
6449         rt2800_bbp_write(rt2x00dev, 80, 0x09);
6450         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6451 
6452         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6453 
6454         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6455 
6456         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6457 
6458         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6459 
6460         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6461 
6462         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6463 
6464         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6465 
6466         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6467 
6468         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
6469 
6470         rt2800_bbp_write(rt2x00dev, 106, 0x03);
6471 
6472         rt2800_bbp_write(rt2x00dev, 128, 0x12);
6473 
6474         rt2800_bbp_write(rt2x00dev, 67, 0x24);
6475         rt2800_bbp_write(rt2x00dev, 143, 0x04);
6476         rt2800_bbp_write(rt2x00dev, 142, 0x99);
6477         rt2800_bbp_write(rt2x00dev, 150, 0x30);
6478         rt2800_bbp_write(rt2x00dev, 151, 0x2e);
6479         rt2800_bbp_write(rt2x00dev, 152, 0x20);
6480         rt2800_bbp_write(rt2x00dev, 153, 0x34);
6481         rt2800_bbp_write(rt2x00dev, 154, 0x40);
6482         rt2800_bbp_write(rt2x00dev, 155, 0x3b);
6483         rt2800_bbp_write(rt2x00dev, 253, 0x04);
6484 
6485         value = rt2800_bbp_read(rt2x00dev, 47);
6486         rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
6487         rt2800_bbp_write(rt2x00dev, 47, value);
6488 
6489         /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
6490         value = rt2800_bbp_read(rt2x00dev, 3);
6491         rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
6492         rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
6493         rt2800_bbp_write(rt2x00dev, 3, value);
6494 }
6495 
6496 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
6497 {
6498         rt2800_bbp_write(rt2x00dev, 3, 0x00);
6499         rt2800_bbp_write(rt2x00dev, 4, 0x50);
6500 
6501         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6502 
6503         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6504 
6505         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6506         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6507 
6508         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6509 
6510         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6511         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6512         rt2800_bbp_write(rt2x00dev, 75, 0x46);
6513         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6514 
6515         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6516 
6517         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6518 
6519         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6520         rt2800_bbp_write(rt2x00dev, 80, 0x08);
6521         rt2800_bbp_write(rt2x00dev, 81, 0x37);
6522 
6523         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6524 
6525         if (rt2x00_rt(rt2x00dev, RT5350)) {
6526                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6527                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6528         } else {
6529                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6530                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6531         }
6532 
6533         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6534 
6535         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6536 
6537         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6538 
6539         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6540 
6541         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6542 
6543         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6544 
6545         if (rt2x00_rt(rt2x00dev, RT5350)) {
6546                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6547                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6548         } else {
6549                 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6550                 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6551         }
6552 
6553         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6554 
6555         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6556 
6557         rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6558         /* Set ITxBF timeout to 0x9c40=1000msec */
6559         rt2800_bbp_write(rt2x00dev, 179, 0x02);
6560         rt2800_bbp_write(rt2x00dev, 180, 0x00);
6561         rt2800_bbp_write(rt2x00dev, 182, 0x40);
6562         rt2800_bbp_write(rt2x00dev, 180, 0x01);
6563         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6564         rt2800_bbp_write(rt2x00dev, 179, 0x00);
6565         /* Reprogram the inband interface to put right values in RXWI */
6566         rt2800_bbp_write(rt2x00dev, 142, 0x04);
6567         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6568         rt2800_bbp_write(rt2x00dev, 142, 0x06);
6569         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6570         rt2800_bbp_write(rt2x00dev, 142, 0x07);
6571         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6572         rt2800_bbp_write(rt2x00dev, 142, 0x08);
6573         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6574 
6575         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6576 
6577         if (rt2x00_rt(rt2x00dev, RT5350)) {
6578                 /* Antenna Software OFDM */
6579                 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6580                 /* Antenna Software CCK */
6581                 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6582                 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6583                 /* Clear previously selected antenna */
6584                 rt2800_bbp_write(rt2x00dev, 154, 0);
6585         }
6586 }
6587 
6588 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6589 {
6590         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6591         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6592 
6593         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6594         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6595 
6596         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6597 
6598         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6599         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6600         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6601 
6602         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6603 
6604         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6605 
6606         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6607 
6608         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6609 
6610         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6611 
6612         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6613 
6614         if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6615                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6616         else
6617                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6618 
6619         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6620 
6621         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6622 
6623         rt2800_disable_unused_dac_adc(rt2x00dev);
6624 }
6625 
6626 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6627 {
6628         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6629 
6630         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6631         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6632 
6633         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6634         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6635 
6636         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6637 
6638         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6639         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6640         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6641 
6642         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6643 
6644         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6645 
6646         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6647 
6648         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6649 
6650         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6651 
6652         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6653 
6654         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6655 
6656         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6657 
6658         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6659 
6660         rt2800_disable_unused_dac_adc(rt2x00dev);
6661 }
6662 
6663 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6664 {
6665         rt2800_init_bbp_early(rt2x00dev);
6666 
6667         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6668         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6669         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6670         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6671 
6672         rt2800_bbp_write(rt2x00dev, 84, 0x19);
6673 
6674         /* Enable DC filter */
6675         if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6676                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6677 }
6678 
6679 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
6680 {
6681         rt2800_init_bbp_early(rt2x00dev);
6682 
6683         rt2800_bbp_write(rt2x00dev, 4, 0x50);
6684         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6685 
6686         rt2800_bbp_write(rt2x00dev, 86, 0x46);
6687         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6688 
6689         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6690 
6691         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6692         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6693         rt2800_bbp_write(rt2x00dev, 105, 0x34);
6694         rt2800_bbp_write(rt2x00dev, 106, 0x12);
6695         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6696         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6697         rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6698 
6699         /* Set ITxBF timeout to 0x9C40=1000msec */
6700         rt2800_bbp_write(rt2x00dev, 179, 0x02);
6701         rt2800_bbp_write(rt2x00dev, 180, 0x00);
6702         rt2800_bbp_write(rt2x00dev, 182, 0x40);
6703         rt2800_bbp_write(rt2x00dev, 180, 0x01);
6704         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6705 
6706         rt2800_bbp_write(rt2x00dev, 179, 0x00);
6707 
6708         /* Reprogram the inband interface to put right values in RXWI */
6709         rt2800_bbp_write(rt2x00dev, 142, 0x04);
6710         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6711         rt2800_bbp_write(rt2x00dev, 142, 0x06);
6712         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6713         rt2800_bbp_write(rt2x00dev, 142, 0x07);
6714         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6715         rt2800_bbp_write(rt2x00dev, 142, 0x08);
6716         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6717         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6718 }
6719 
6720 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6721 {
6722         int ant, div_mode;
6723         u16 eeprom;
6724         u8 value;
6725 
6726         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6727 
6728         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6729 
6730         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6731         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6732 
6733         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6734 
6735         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6736         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6737         rt2800_bbp_write(rt2x00dev, 75, 0x46);
6738         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6739 
6740         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6741 
6742         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6743 
6744         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6745         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6746         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6747 
6748         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6749 
6750         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6751 
6752         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6753 
6754         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6755 
6756         if (rt2x00_rt(rt2x00dev, RT5392))
6757                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6758 
6759         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6760 
6761         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6762 
6763         if (rt2x00_rt(rt2x00dev, RT5392)) {
6764                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6765                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6766         }
6767 
6768         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6769 
6770         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6771 
6772         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6773 
6774         if (rt2x00_rt(rt2x00dev, RT5390))
6775                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6776         else if (rt2x00_rt(rt2x00dev, RT5392))
6777                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6778         else
6779                 WARN_ON(1);
6780 
6781         rt2800_bbp_write(rt2x00dev, 128, 0x12);
6782 
6783         if (rt2x00_rt(rt2x00dev, RT5392)) {
6784                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6785                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6786         }
6787 
6788         rt2800_disable_unused_dac_adc(rt2x00dev);
6789 
6790         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6791         div_mode = rt2x00_get_field16(eeprom,
6792                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
6793         ant = (div_mode == 3) ? 1 : 0;
6794 
6795         /* check if this is a Bluetooth combo card */
6796         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6797                 u32 reg;
6798 
6799                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6800                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
6801                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
6802                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
6803                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
6804                 if (ant == 0)
6805                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
6806                 else if (ant == 1)
6807                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
6808                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6809         }
6810 
6811         /* These chips have hardware RX antenna diversity */
6812         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6813             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6814                 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6815                 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6816                 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6817         }
6818 
6819         value = rt2800_bbp_read(rt2x00dev, 152);
6820         if (ant == 0)
6821                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6822         else
6823                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6824         rt2800_bbp_write(rt2x00dev, 152, value);
6825 
6826         rt2800_init_freq_calibration(rt2x00dev);
6827 }
6828 
6829 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6830 {
6831         int ant, div_mode;
6832         u16 eeprom;
6833         u8 value;
6834 
6835         rt2800_init_bbp_early(rt2x00dev);
6836 
6837         value = rt2800_bbp_read(rt2x00dev, 105);
6838         rt2x00_set_field8(&value, BBP105_MLD,
6839                           rt2x00dev->default_ant.rx_chain_num == 2);
6840         rt2800_bbp_write(rt2x00dev, 105, value);
6841 
6842         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6843 
6844         rt2800_bbp_write(rt2x00dev, 20, 0x06);
6845         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6846         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6847         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6848         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6849         rt2800_bbp_write(rt2x00dev, 70, 0x05);
6850         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6851         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6852         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6853         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6854         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6855         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6856         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6857         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6858         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6859         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6860         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6861         rt2800_bbp_write(rt2x00dev, 98, 0x12);
6862         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6863         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6864         /* FIXME BBP105 owerwrite */
6865         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6866         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6867         rt2800_bbp_write(rt2x00dev, 128, 0x12);
6868         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6869         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6870         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6871 
6872         /* Initialize GLRT (Generalized Likehood Radio Test) */
6873         rt2800_init_bbp_5592_glrt(rt2x00dev);
6874 
6875         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6876 
6877         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6878         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6879         ant = (div_mode == 3) ? 1 : 0;
6880         value = rt2800_bbp_read(rt2x00dev, 152);
6881         if (ant == 0) {
6882                 /* Main antenna */
6883                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6884         } else {
6885                 /* Auxiliary antenna */
6886                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6887         }
6888         rt2800_bbp_write(rt2x00dev, 152, value);
6889 
6890         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6891                 value = rt2800_bbp_read(rt2x00dev, 254);
6892                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
6893                 rt2800_bbp_write(rt2x00dev, 254, value);
6894         }
6895 
6896         rt2800_init_freq_calibration(rt2x00dev);
6897 
6898         rt2800_bbp_write(rt2x00dev, 84, 0x19);
6899         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6900                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6901 }
6902 
6903 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6904                                   const u8 reg, const u8 value)
6905 {
6906         rt2800_bbp_write(rt2x00dev, 195, reg);
6907         rt2800_bbp_write(rt2x00dev, 196, value);
6908 }
6909 
6910 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6911                                   const u8 reg, const u8 value)
6912 {
6913         rt2800_bbp_write(rt2x00dev, 158, reg);
6914         rt2800_bbp_write(rt2x00dev, 159, value);
6915 }
6916 
6917 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
6918 {
6919         rt2800_bbp_write(rt2x00dev, 158, reg);
6920         return rt2800_bbp_read(rt2x00dev, 159);
6921 }
6922 
6923 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6924 {
6925         u8 bbp;
6926 
6927         /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
6928         bbp = rt2800_bbp_read(rt2x00dev, 105);
6929         rt2x00_set_field8(&bbp, BBP105_MLD,
6930                           rt2x00dev->default_ant.rx_chain_num == 2);
6931         rt2800_bbp_write(rt2x00dev, 105, bbp);
6932 
6933         /* Avoid data loss and CRC errors */
6934         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6935 
6936         /* Fix I/Q swap issue */
6937         bbp = rt2800_bbp_read(rt2x00dev, 1);
6938         bbp |= 0x04;
6939         rt2800_bbp_write(rt2x00dev, 1, bbp);
6940 
6941         /* BBP for G band */
6942         rt2800_bbp_write(rt2x00dev, 3, 0x08);
6943         rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6944         rt2800_bbp_write(rt2x00dev, 6, 0x08);
6945         rt2800_bbp_write(rt2x00dev, 14, 0x09);
6946         rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6947         rt2800_bbp_write(rt2x00dev, 16, 0x01);
6948         rt2800_bbp_write(rt2x00dev, 20, 0x06);
6949         rt2800_bbp_write(rt2x00dev, 21, 0x00);
6950         rt2800_bbp_write(rt2x00dev, 22, 0x00);
6951         rt2800_bbp_write(rt2x00dev, 27, 0x00);
6952         rt2800_bbp_write(rt2x00dev, 28, 0x00);
6953         rt2800_bbp_write(rt2x00dev, 30, 0x00);
6954         rt2800_bbp_write(rt2x00dev, 31, 0x48);
6955         rt2800_bbp_write(rt2x00dev, 47, 0x40);
6956         rt2800_bbp_write(rt2x00dev, 62, 0x00);
6957         rt2800_bbp_write(rt2x00dev, 63, 0x00);
6958         rt2800_bbp_write(rt2x00dev, 64, 0x00);
6959         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6960         rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6961         rt2800_bbp_write(rt2x00dev, 67, 0x20);
6962         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6963         rt2800_bbp_write(rt2x00dev, 69, 0x10);
6964         rt2800_bbp_write(rt2x00dev, 70, 0x05);
6965         rt2800_bbp_write(rt2x00dev, 73, 0x18);
6966         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6967         rt2800_bbp_write(rt2x00dev, 75, 0x60);
6968         rt2800_bbp_write(rt2x00dev, 76, 0x44);
6969         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6970         rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6971         rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6972         rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6973         rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6974         rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6975         rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6976         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6977         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6978         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6979         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6980         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6981         rt2800_bbp_write(rt2x00dev, 95, 0x9A);
6982         rt2800_bbp_write(rt2x00dev, 96, 0x00);
6983         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6984         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6985         /* FIXME BBP105 owerwrite */
6986         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6987         rt2800_bbp_write(rt2x00dev, 106, 0x12);
6988         rt2800_bbp_write(rt2x00dev, 109, 0x00);
6989         rt2800_bbp_write(rt2x00dev, 134, 0x10);
6990         rt2800_bbp_write(rt2x00dev, 135, 0xA6);
6991         rt2800_bbp_write(rt2x00dev, 137, 0x04);
6992         rt2800_bbp_write(rt2x00dev, 142, 0x30);
6993         rt2800_bbp_write(rt2x00dev, 143, 0xF7);
6994         rt2800_bbp_write(rt2x00dev, 160, 0xEC);
6995         rt2800_bbp_write(rt2x00dev, 161, 0xC4);
6996         rt2800_bbp_write(rt2x00dev, 162, 0x77);
6997         rt2800_bbp_write(rt2x00dev, 163, 0xF9);
6998         rt2800_bbp_write(rt2x00dev, 164, 0x00);
6999         rt2800_bbp_write(rt2x00dev, 165, 0x00);
7000         rt2800_bbp_write(rt2x00dev, 186, 0x00);
7001         rt2800_bbp_write(rt2x00dev, 187, 0x00);
7002         rt2800_bbp_write(rt2x00dev, 188, 0x00);
7003         rt2800_bbp_write(rt2x00dev, 186, 0x00);
7004         rt2800_bbp_write(rt2x00dev, 187, 0x01);
7005         rt2800_bbp_write(rt2x00dev, 188, 0x00);
7006         rt2800_bbp_write(rt2x00dev, 189, 0x00);
7007 
7008         rt2800_bbp_write(rt2x00dev, 91, 0x06);
7009         rt2800_bbp_write(rt2x00dev, 92, 0x04);
7010         rt2800_bbp_write(rt2x00dev, 93, 0x54);
7011         rt2800_bbp_write(rt2x00dev, 99, 0x50);
7012         rt2800_bbp_write(rt2x00dev, 148, 0x84);
7013         rt2800_bbp_write(rt2x00dev, 167, 0x80);
7014         rt2800_bbp_write(rt2x00dev, 178, 0xFF);
7015         rt2800_bbp_write(rt2x00dev, 106, 0x13);
7016 
7017         /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
7018         rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
7019         rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
7020         rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
7021         rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
7022         rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
7023         rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
7024         rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
7025         rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
7026         rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
7027         rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
7028         rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
7029         rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
7030         rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
7031         rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
7032         rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
7033         rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
7034         rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
7035         rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
7036         rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
7037         rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
7038         rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
7039         rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
7040         rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
7041         rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
7042         rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
7043         rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
7044         rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
7045         rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
7046         rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
7047         rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
7048         rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
7049         rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
7050         rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
7051         rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
7052         rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
7053         rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
7054         rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
7055         rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
7056         rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
7057         rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
7058         rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
7059         rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
7060         rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
7061         rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
7062         rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
7063         rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
7064         rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
7065         rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
7066         rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
7067         rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
7068         rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
7069         rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
7070         rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
7071         rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
7072         rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
7073         rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
7074         rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
7075         rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
7076         rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
7077         rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
7078         rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
7079         rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
7080         rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
7081         rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
7082         rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
7083         rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
7084         rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
7085         rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
7086         rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
7087         rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
7088         rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
7089         rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
7090         rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
7091         rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
7092         rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
7093         rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
7094         rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
7095         rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
7096         rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
7097         rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
7098         rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
7099         rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
7100         rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
7101 
7102         /* BBP for G band DCOC function */
7103         rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
7104         rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
7105         rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
7106         rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
7107         rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
7108         rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
7109         rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
7110         rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
7111         rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
7112         rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
7113         rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
7114         rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
7115         rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
7116         rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
7117         rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
7118         rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
7119         rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
7120         rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
7121         rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
7122         rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
7123 
7124         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7125 }
7126 
7127 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
7128 {
7129         unsigned int i;
7130         u16 eeprom;
7131         u8 reg_id;
7132         u8 value;
7133 
7134         if (rt2800_is_305x_soc(rt2x00dev))
7135                 rt2800_init_bbp_305x_soc(rt2x00dev);
7136 
7137         switch (rt2x00dev->chip.rt) {
7138         case RT2860:
7139         case RT2872:
7140         case RT2883:
7141                 rt2800_init_bbp_28xx(rt2x00dev);
7142                 break;
7143         case RT3070:
7144         case RT3071:
7145         case RT3090:
7146                 rt2800_init_bbp_30xx(rt2x00dev);
7147                 break;
7148         case RT3290:
7149                 rt2800_init_bbp_3290(rt2x00dev);
7150                 break;
7151         case RT3352:
7152         case RT5350:
7153                 rt2800_init_bbp_3352(rt2x00dev);
7154                 break;
7155         case RT3390:
7156                 rt2800_init_bbp_3390(rt2x00dev);
7157                 break;
7158         case RT3572:
7159                 rt2800_init_bbp_3572(rt2x00dev);
7160                 break;
7161         case RT3593:
7162                 rt2800_init_bbp_3593(rt2x00dev);
7163                 return;
7164         case RT3883:
7165                 rt2800_init_bbp_3883(rt2x00dev);
7166                 return;
7167         case RT5390:
7168         case RT5392:
7169                 rt2800_init_bbp_53xx(rt2x00dev);
7170                 break;
7171         case RT5592:
7172                 rt2800_init_bbp_5592(rt2x00dev);
7173                 return;
7174         case RT6352:
7175                 rt2800_init_bbp_6352(rt2x00dev);
7176                 break;
7177         }
7178 
7179         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
7180                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
7181                                                        EEPROM_BBP_START, i);
7182 
7183                 if (eeprom != 0xffff && eeprom != 0x0000) {
7184                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
7185                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
7186                         rt2800_bbp_write(rt2x00dev, reg_id, value);
7187                 }
7188         }
7189 }
7190 
7191 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
7192 {
7193         u32 reg;
7194 
7195         reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
7196         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
7197         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
7198 }
7199 
7200 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
7201                                 u8 filter_target)
7202 {
7203         unsigned int i;
7204         u8 bbp;
7205         u8 rfcsr;
7206         u8 passband;
7207         u8 stopband;
7208         u8 overtuned = 0;
7209         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
7210 
7211         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7212 
7213         bbp = rt2800_bbp_read(rt2x00dev, 4);
7214         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
7215         rt2800_bbp_write(rt2x00dev, 4, bbp);
7216 
7217         rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
7218         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
7219         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
7220 
7221         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7222         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
7223         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7224 
7225         /*
7226          * Set power & frequency of passband test tone
7227          */
7228         rt2800_bbp_write(rt2x00dev, 24, 0);
7229 
7230         for (i = 0; i < 100; i++) {
7231                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7232                 msleep(1);
7233 
7234                 passband = rt2800_bbp_read(rt2x00dev, 55);
7235                 if (passband)
7236                         break;
7237         }
7238 
7239         /*
7240          * Set power & frequency of stopband test tone
7241          */
7242         rt2800_bbp_write(rt2x00dev, 24, 0x06);
7243 
7244         for (i = 0; i < 100; i++) {
7245                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7246                 msleep(1);
7247 
7248                 stopband = rt2800_bbp_read(rt2x00dev, 55);
7249 
7250                 if ((passband - stopband) <= filter_target) {
7251                         rfcsr24++;
7252                         overtuned += ((passband - stopband) == filter_target);
7253                 } else
7254                         break;
7255 
7256                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7257         }
7258 
7259         rfcsr24 -= !!overtuned;
7260 
7261         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7262         return rfcsr24;
7263 }
7264 
7265 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
7266                                        const unsigned int rf_reg)
7267 {
7268         u8 rfcsr;
7269 
7270         rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
7271         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
7272         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7273         msleep(1);
7274         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
7275         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7276 }
7277 
7278 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
7279 {
7280         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7281         u8 filter_tgt_bw20;
7282         u8 filter_tgt_bw40;
7283         u8 rfcsr, bbp;
7284 
7285         /*
7286          * TODO: sync filter_tgt values with vendor driver
7287          */
7288         if (rt2x00_rt(rt2x00dev, RT3070)) {
7289                 filter_tgt_bw20 = 0x16;
7290                 filter_tgt_bw40 = 0x19;
7291         } else {
7292                 filter_tgt_bw20 = 0x13;
7293                 filter_tgt_bw40 = 0x15;
7294         }
7295 
7296         drv_data->calibration_bw20 =
7297                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
7298         drv_data->calibration_bw40 =
7299                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
7300 
7301         /*
7302          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
7303          */
7304         drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7305         drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7306 
7307         /*
7308          * Set back to initial state
7309          */
7310         rt2800_bbp_write(rt2x00dev, 24, 0);
7311 
7312         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7313         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
7314         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7315 
7316         /*
7317          * Set BBP back to BW20
7318          */
7319         bbp = rt2800_bbp_read(rt2x00dev, 4);
7320         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
7321         rt2800_bbp_write(rt2x00dev, 4, bbp);
7322 }
7323 
7324 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
7325 {
7326         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7327         u8 min_gain, rfcsr, bbp;
7328         u16 eeprom;
7329 
7330         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
7331 
7332         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
7333         if (rt2x00_rt(rt2x00dev, RT3070) ||
7334             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7335             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
7336             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7337                 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
7338                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
7339         }
7340 
7341         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
7342         if (drv_data->txmixer_gain_24g >= min_gain) {
7343                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
7344                                   drv_data->txmixer_gain_24g);
7345         }
7346 
7347         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
7348 
7349         if (rt2x00_rt(rt2x00dev, RT3090)) {
7350                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7351                 bbp = rt2800_bbp_read(rt2x00dev, 138);
7352                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7353                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7354                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
7355                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7356                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
7357                 rt2800_bbp_write(rt2x00dev, 138, bbp);
7358         }
7359 
7360         if (rt2x00_rt(rt2x00dev, RT3070)) {
7361                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
7362                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
7363                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
7364                 else
7365                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
7366                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
7367                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
7368                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
7369                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
7370         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7371                    rt2x00_rt(rt2x00dev, RT3090) ||
7372                    rt2x00_rt(rt2x00dev, RT3390)) {
7373                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7374                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7375                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7376                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7377                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
7378                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
7379                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7380 
7381                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
7382                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
7383                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
7384 
7385                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
7386                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
7387                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
7388 
7389                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
7390                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
7391                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
7392         }
7393 }
7394 
7395 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
7396 {
7397         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7398         u8 rfcsr;
7399         u8 tx_gain;
7400 
7401         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
7402         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
7403         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7404 
7405         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
7406         tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
7407                                     RFCSR17_TXMIXER_GAIN);
7408         rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
7409         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
7410 
7411         rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
7412         rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
7413         rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
7414 
7415         rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
7416         rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
7417         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
7418 
7419         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7420         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7421         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
7422         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7423 
7424         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
7425         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
7426         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
7427 
7428         /* TODO: enable stream mode */
7429 }
7430 
7431 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
7432 {
7433         u8 reg;
7434         u16 eeprom;
7435 
7436         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7437         reg = rt2800_bbp_read(rt2x00dev, 138);
7438         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7439         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7440                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
7441         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7442                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
7443         rt2800_bbp_write(rt2x00dev, 138, reg);
7444 
7445         reg = rt2800_rfcsr_read(rt2x00dev, 38);
7446         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
7447         rt2800_rfcsr_write(rt2x00dev, 38, reg);
7448 
7449         reg = rt2800_rfcsr_read(rt2x00dev, 39);
7450         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
7451         rt2800_rfcsr_write(rt2x00dev, 39, reg);
7452 
7453         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7454 
7455         reg = rt2800_rfcsr_read(rt2x00dev, 30);
7456         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
7457         rt2800_rfcsr_write(rt2x00dev, 30, reg);
7458 }
7459 
7460 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
7461 {
7462         rt2800_rf_init_calibration(rt2x00dev, 30);
7463 
7464         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
7465         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
7466         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
7467         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
7468         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7469         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7470         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7471         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
7472         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
7473         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7474         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
7475         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7476         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
7477         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
7478         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7479         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7480         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7481         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7482         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7483         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7484         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7485         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7486         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7487         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
7488         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7489         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
7490         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
7491         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
7492         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
7493         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
7494         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
7495         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
7496 }
7497 
7498 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
7499 {
7500         u8 rfcsr;
7501         u16 eeprom;
7502         u32 reg;
7503 
7504         /* XXX vendor driver do this only for 3070 */
7505         rt2800_rf_init_calibration(rt2x00dev, 30);
7506 
7507         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7508         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7509         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7510         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
7511         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7512         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
7513         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7514         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
7515         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7516         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7517         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7518         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7519         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7520         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7521         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7522         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7523         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7524         rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
7525         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
7526 
7527         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
7528                 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7529                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7530                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7531                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7532         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7533                    rt2x00_rt(rt2x00dev, RT3090)) {
7534                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
7535 
7536                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7537                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7538                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7539 
7540                 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7541                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7542                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7543                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
7544                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7545                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
7546                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7547                         else
7548                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7549                 }
7550                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7551 
7552                 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7553                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7554                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7555         }
7556 
7557         rt2800_rx_filter_calibration(rt2x00dev);
7558 
7559         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
7560             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7561             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
7562                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7563 
7564         rt2800_led_open_drain_enable(rt2x00dev);
7565         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7566 }
7567 
7568 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7569 {
7570         u8 rfcsr;
7571 
7572         rt2800_rf_init_calibration(rt2x00dev, 2);
7573 
7574         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7575         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7576         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7577         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7578         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7579         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7580         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7581         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7582         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7583         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7584         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7585         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7586         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7587         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7588         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7589         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7590         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7591         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7592         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7593         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7594         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7595         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7596         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7597         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7598         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7599         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7600         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7601         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7602         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7603         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7604         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7605         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7606         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7607         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7608         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7609         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7610         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7611         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7612         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7613         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7614         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7615         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7616         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7617         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7618         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7619         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7620 
7621         rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7622         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7623         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7624 
7625         rt2800_led_open_drain_enable(rt2x00dev);
7626         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7627 }
7628 
7629 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7630 {
7631         int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
7632                                   &rt2x00dev->cap_flags);
7633         int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
7634                                   &rt2x00dev->cap_flags);
7635         u8 rfcsr;
7636 
7637         rt2800_rf_init_calibration(rt2x00dev, 30);
7638 
7639         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7640         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7641         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7642         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7643         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7644         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7645         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7646         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7647         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7648         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7649         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7650         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7651         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7652         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7653         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7654         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7655         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7656         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7657         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7658         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7659         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7660         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7661         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7662         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7663         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7664         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7665         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7666         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7667         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7668         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7669         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7670         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7671         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7672         rfcsr = 0x01;
7673         if (tx0_ext_pa)
7674                 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7675         if (tx1_ext_pa)
7676                 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7677         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7678         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7679         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7680         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7681         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7682         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7683         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7684         rfcsr = 0x52;
7685         if (!tx0_ext_pa) {
7686                 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7687                 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7688         }
7689         rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7690         rfcsr = 0x52;
7691         if (!tx1_ext_pa) {
7692                 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7693                 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7694         }
7695         rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7696         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7697         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7698         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7699         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7700         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7701         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7702         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7703         rfcsr = 0x2d;
7704         if (tx0_ext_pa)
7705                 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7706         if (tx1_ext_pa)
7707                 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7708         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7709         rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7710         rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7711         rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7712         rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7713         rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7714         rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7715         rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7716         rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7717         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7718         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7719         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7720         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7721         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7722 
7723         rt2800_rx_filter_calibration(rt2x00dev);
7724         rt2800_led_open_drain_enable(rt2x00dev);
7725         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7726 }
7727 
7728 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7729 {
7730         u32 reg;
7731 
7732         rt2800_rf_init_calibration(rt2x00dev, 30);
7733 
7734         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7735         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7736         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7737         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7738         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7739         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7740         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7741         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7742         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7743         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7744         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7745         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7746         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7747         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7748         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7749         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7750         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7751         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7752         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7753         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7754         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7755         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7756         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7757         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7758         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7759         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7760         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7761         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7762         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7763         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7764         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7765         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7766 
7767         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7768         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7769         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7770 
7771         rt2800_rx_filter_calibration(rt2x00dev);
7772 
7773         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7774                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7775 
7776         rt2800_led_open_drain_enable(rt2x00dev);
7777         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7778 }
7779 
7780 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7781 {
7782         u8 rfcsr;
7783         u32 reg;
7784 
7785         rt2800_rf_init_calibration(rt2x00dev, 30);
7786 
7787         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7788         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7789         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7790         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7791         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7792         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7793         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7794         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7795         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7796         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7797         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7798         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7799         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7800         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7801         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7802         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7803         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7804         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7805         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7806         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7807         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7808         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7809         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7810         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7811         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7812         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7813         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7814         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7815         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7816         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7817         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7818 
7819         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7820         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7821         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7822 
7823         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7824         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7825         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7826         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7827         msleep(1);
7828         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7829         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7830         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7831         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7832 
7833         rt2800_rx_filter_calibration(rt2x00dev);
7834         rt2800_led_open_drain_enable(rt2x00dev);
7835         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7836 }
7837 
7838 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7839 {
7840         u8 bbp;
7841         bool txbf_enabled = false; /* FIXME */
7842 
7843         bbp = rt2800_bbp_read(rt2x00dev, 105);
7844         if (rt2x00dev->default_ant.rx_chain_num == 1)
7845                 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7846         else
7847                 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7848         rt2800_bbp_write(rt2x00dev, 105, bbp);
7849 
7850         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7851 
7852         rt2800_bbp_write(rt2x00dev, 92, 0x02);
7853         rt2800_bbp_write(rt2x00dev, 82, 0x82);
7854         rt2800_bbp_write(rt2x00dev, 106, 0x05);
7855         rt2800_bbp_write(rt2x00dev, 104, 0x92);
7856         rt2800_bbp_write(rt2x00dev, 88, 0x90);
7857         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7858         rt2800_bbp_write(rt2x00dev, 47, 0x48);
7859         rt2800_bbp_write(rt2x00dev, 120, 0x50);
7860 
7861         if (txbf_enabled)
7862                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7863         else
7864                 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7865 
7866         /* SNR mapping */
7867         rt2800_bbp_write(rt2x00dev, 142, 6);
7868         rt2800_bbp_write(rt2x00dev, 143, 160);
7869         rt2800_bbp_write(rt2x00dev, 142, 7);
7870         rt2800_bbp_write(rt2x00dev, 143, 161);
7871         rt2800_bbp_write(rt2x00dev, 142, 8);
7872         rt2800_bbp_write(rt2x00dev, 143, 162);
7873 
7874         /* ADC/DAC control */
7875         rt2800_bbp_write(rt2x00dev, 31, 0x08);
7876 
7877         /* RX AGC energy lower bound in log2 */
7878         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7879 
7880         /* FIXME: BBP 105 owerwrite? */
7881         rt2800_bbp_write(rt2x00dev, 105, 0x04);
7882 
7883 }
7884 
7885 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7886 {
7887         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7888         u32 reg;
7889         u8 rfcsr;
7890 
7891         /* Disable GPIO #4 and #7 function for LAN PE control */
7892         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7893         rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
7894         rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
7895         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7896 
7897         /* Initialize default register values */
7898         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7899         rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7900         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7901         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7902         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7903         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7904         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7905         rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7906         rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7907         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7908         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7909         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7910         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7911         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7912         rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7913         rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7914         rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7915         rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7916         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7917         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7918         rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7919         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7920         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7921         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7922         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7923         rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7924         rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7925         rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7926         rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7927         rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7928         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7929         rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7930 
7931         /* Initiate calibration */
7932         /* TODO: use rt2800_rf_init_calibration ? */
7933         rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
7934         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
7935         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7936 
7937         rt2800_freq_cal_mode1(rt2x00dev);
7938 
7939         rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
7940         rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
7941         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7942 
7943         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7944         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7945         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7946         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7947         usleep_range(1000, 1500);
7948         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7949         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7950         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7951 
7952         /* Set initial values for RX filter calibration */
7953         drv_data->calibration_bw20 = 0x1f;
7954         drv_data->calibration_bw40 = 0x2f;
7955 
7956         /* Save BBP 25 & 26 values for later use in channel switching */
7957         drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7958         drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7959 
7960         rt2800_led_open_drain_enable(rt2x00dev);
7961         rt2800_normal_mode_setup_3593(rt2x00dev);
7962 
7963         rt3593_post_bbp_init(rt2x00dev);
7964 
7965         /* TODO: enable stream mode support */
7966 }
7967 
7968 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7969 {
7970         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7971         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7972         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7973         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7974         rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7975         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7976         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7977         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7978         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7979         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7980         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7981         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7982         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7983         if (rt2800_clk_is_20mhz(rt2x00dev))
7984                 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
7985         else
7986                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7987         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7988         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7989         rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
7990         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7991         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7992         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7993         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7994         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7995         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7996         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7997         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7998         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7999         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8000         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8001         rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
8002         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8003         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8004         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8005         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8006         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8007         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8008         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8009         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8010         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8011         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8012         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8013         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8014         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8015         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8016         rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
8017         rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
8018         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8019         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8020         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8021         rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
8022         rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
8023         rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
8024         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8025         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8026         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8027         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8028         rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
8029         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8030         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8031         rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
8032         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8033         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8034         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8035         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8036 }
8037 
8038 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
8039 {
8040         u8 rfcsr;
8041 
8042         /* TODO: get the actual ECO value from the SoC */
8043         const unsigned int eco = 5;
8044 
8045         rt2800_rf_init_calibration(rt2x00dev, 2);
8046 
8047         rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
8048         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8049         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8050         rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
8051         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
8052         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8053         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8054         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8055         rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
8056         rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
8057         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8058         rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
8059         rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
8060         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8061         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8062         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8063         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8064 
8065         /* RFCSR 17 will be initialized later based on the
8066          * frequency offset stored in the EEPROM
8067          */
8068 
8069         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8070         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8071         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8072         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8073         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8074         rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
8075         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8076         rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8077         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8078         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8079         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8080         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
8081         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8082         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8083         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8084         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8085         rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
8086         rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8087         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8088         rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8089         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8090         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8091         rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8092         rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
8093         rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
8094         rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8095         rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
8096         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8097         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8098         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8099         rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
8100         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8101         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8102         rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
8103         rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
8104         rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
8105         rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
8106         rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
8107         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8108         rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
8109         rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
8110         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
8111         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
8112         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
8113         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8114         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8115 
8116         /* TODO: rx filter calibration? */
8117 
8118         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
8119 
8120         rt2800_bbp_write(rt2x00dev, 163, 0x9d);
8121 
8122         rt2800_bbp_write(rt2x00dev, 105, 0x05);
8123 
8124         rt2800_bbp_write(rt2x00dev, 179, 0x02);
8125         rt2800_bbp_write(rt2x00dev, 180, 0x00);
8126         rt2800_bbp_write(rt2x00dev, 182, 0x40);
8127         rt2800_bbp_write(rt2x00dev, 180, 0x01);
8128         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
8129 
8130         rt2800_bbp_write(rt2x00dev, 179, 0x00);
8131 
8132         rt2800_bbp_write(rt2x00dev, 142, 0x04);
8133         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
8134         rt2800_bbp_write(rt2x00dev, 142, 0x06);
8135         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
8136         rt2800_bbp_write(rt2x00dev, 142, 0x07);
8137         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
8138         rt2800_bbp_write(rt2x00dev, 142, 0x08);
8139         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
8140         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
8141 
8142         if (eco == 5) {
8143                 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
8144                 rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
8145         }
8146 
8147         rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8148         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
8149         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
8150         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8151         msleep(1);
8152         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
8153         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8154 
8155         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8156         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
8157         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
8158 
8159         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
8160         rfcsr |= 0xc0;
8161         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8162 
8163         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
8164         rfcsr |= 0x20;
8165         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
8166 
8167         rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
8168         rfcsr |= 0x20;
8169         rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
8170 
8171         rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
8172         rfcsr &= ~0xee;
8173         rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
8174 }
8175 
8176 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
8177 {
8178         rt2800_rf_init_calibration(rt2x00dev, 2);
8179 
8180         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
8181         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8182         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8183         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8184         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8185                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8186         else
8187                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
8188         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8189         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8190         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8191         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8192         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8193         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8194         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8195         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8196         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8197         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8198 
8199         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8200         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8201         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8202         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8203         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8204         if (rt2x00_is_usb(rt2x00dev) &&
8205             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8206                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8207         else
8208                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
8209         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8210         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8211         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8212         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8213 
8214         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8215         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8216         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8217         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8218         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8219         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8220         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8221         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8222         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8223         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8224 
8225         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8226         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8227         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
8228         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
8229         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8230         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8231         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8232                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8233         else
8234                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
8235         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8236         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8237         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8238 
8239         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8240         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8241                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8242         else
8243                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
8244         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
8245         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
8246         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8247                 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
8248         else
8249                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
8250         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
8251         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
8252         rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
8253 
8254         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8255         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
8256                 if (rt2x00_is_usb(rt2x00dev))
8257                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8258                 else
8259                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
8260         } else {
8261                 if (rt2x00_is_usb(rt2x00dev))
8262                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
8263                 else
8264                         rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
8265         }
8266         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8267         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8268 
8269         rt2800_normal_mode_setup_5xxx(rt2x00dev);
8270 
8271         rt2800_led_open_drain_enable(rt2x00dev);
8272 }
8273 
8274 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
8275 {
8276         rt2800_rf_init_calibration(rt2x00dev, 2);
8277 
8278         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
8279         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8280         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8281         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8282         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8283         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8284         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8285         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8286         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8287         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8288         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8289         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8290         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8291         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
8292         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8293         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
8294         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8295         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
8296         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
8297         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8298         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8299         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8300         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8301         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8302         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8303         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8304         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
8305         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8306         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8307         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8308         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8309         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8310         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
8311         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8312         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
8313         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8314         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8315         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8316         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8317         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8318         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8319         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
8320         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8321         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8322         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
8323         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
8324         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
8325         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
8326         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8327         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8328         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
8329         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8330         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8331         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
8332         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8333         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
8334         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
8335         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8336 
8337         rt2800_normal_mode_setup_5xxx(rt2x00dev);
8338 
8339         rt2800_led_open_drain_enable(rt2x00dev);
8340 }
8341 
8342 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
8343 {
8344         rt2800_rf_init_calibration(rt2x00dev, 30);
8345 
8346         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
8347         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8348         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8349         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
8350         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8351         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8352         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8353         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8354         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8355         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
8356         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
8357         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
8358         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8359         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8360         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8361         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8362         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8363         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8364         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
8365         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
8366         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8367 
8368         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8369         msleep(1);
8370 
8371         rt2800_freq_cal_mode1(rt2x00dev);
8372 
8373         /* Enable DC filter */
8374         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
8375                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
8376 
8377         rt2800_normal_mode_setup_5xxx(rt2x00dev);
8378 
8379         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
8380                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8381 
8382         rt2800_led_open_drain_enable(rt2x00dev);
8383 }
8384 
8385 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
8386                                        bool set_bw, bool is_ht40)
8387 {
8388         u8 bbp_val;
8389 
8390         bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8391         bbp_val |= 0x1;
8392         rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8393         usleep_range(100, 200);
8394 
8395         if (set_bw) {
8396                 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8397                 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
8398                 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8399                 usleep_range(100, 200);
8400         }
8401 
8402         bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8403         bbp_val &= (~0x1);
8404         rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8405         usleep_range(100, 200);
8406 }
8407 
8408 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
8409 {
8410         u8 rf_val;
8411 
8412         if (btxcal)
8413                 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
8414         else
8415                 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
8416 
8417         rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
8418 
8419         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8420         rf_val |= 0x80;
8421         rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
8422 
8423         if (btxcal) {
8424                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
8425                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
8426                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8427                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8428                 rf_val &= (~0x3F);
8429                 rf_val |= 0x3F;
8430                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8431                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8432                 rf_val &= (~0x3F);
8433                 rf_val |= 0x3F;
8434                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8435                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
8436         } else {
8437                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
8438                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
8439                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8440                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8441                 rf_val &= (~0x3F);
8442                 rf_val |= 0x34;
8443                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8444                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8445                 rf_val &= (~0x3F);
8446                 rf_val |= 0x34;
8447                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8448         }
8449 
8450         return 0;
8451 }
8452 
8453 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
8454 {
8455         unsigned int cnt;
8456         u8 bbp_val;
8457         char cal_val;
8458 
8459         rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
8460 
8461         cnt = 0;
8462         do {
8463                 usleep_range(500, 2000);
8464                 bbp_val = rt2800_bbp_read(rt2x00dev, 159);
8465                 if (bbp_val == 0x02 || cnt == 20)
8466                         break;
8467 
8468                 cnt++;
8469         } while (cnt < 20);
8470 
8471         bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
8472         cal_val = bbp_val & 0x7F;
8473         if (cal_val >= 0x40)
8474                 cal_val -= 128;
8475 
8476         return cal_val;
8477 }
8478 
8479 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
8480                                          bool btxcal)
8481 {
8482         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8483         u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
8484         u8 filter_target;
8485         u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
8486         u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
8487         int loop = 0, is_ht40, cnt;
8488         u8 bbp_val, rf_val;
8489         char cal_r32_init, cal_r32_val, cal_diff;
8490         u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
8491         u8 saverfb5r06, saverfb5r07;
8492         u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
8493         u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
8494         u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
8495         u8 saverfb5r58, saverfb5r59;
8496         u8 savebbp159r0, savebbp159r2, savebbpr23;
8497         u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
8498 
8499         /* Save MAC registers */
8500         MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8501         MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8502 
8503         /* save BBP registers */
8504         savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
8505 
8506         savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
8507         savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8508 
8509         /* Save RF registers */
8510         saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8511         saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8512         saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8513         saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8514         saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
8515         saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8516         saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8517         saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8518         saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8519         saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8520         saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8521         saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8522 
8523         saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
8524         saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
8525         saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
8526         saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
8527         saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
8528         saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
8529         saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
8530         saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
8531         saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
8532         saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
8533 
8534         saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8535         saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8536 
8537         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8538         rf_val |= 0x3;
8539         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8540 
8541         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8542         rf_val |= 0x1;
8543         rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
8544 
8545         cnt = 0;
8546         do {
8547                 usleep_range(500, 2000);
8548                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8549                 if (((rf_val & 0x1) == 0x00) || (cnt == 40))
8550                         break;
8551                 cnt++;
8552         } while (cnt < 40);
8553 
8554         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8555         rf_val &= (~0x3);
8556         rf_val |= 0x1;
8557         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8558 
8559         /* I-3 */
8560         bbp_val = rt2800_bbp_read(rt2x00dev, 23);
8561         bbp_val &= (~0x1F);
8562         bbp_val |= 0x10;
8563         rt2800_bbp_write(rt2x00dev, 23, bbp_val);
8564 
8565         do {
8566                 /* I-4,5,6,7,8,9 */
8567                 if (loop == 0) {
8568                         is_ht40 = false;
8569 
8570                         if (btxcal)
8571                                 filter_target = tx_filter_target_20m;
8572                         else
8573                                 filter_target = rx_filter_target_20m;
8574                 } else {
8575                         is_ht40 = true;
8576 
8577                         if (btxcal)
8578                                 filter_target = tx_filter_target_40m;
8579                         else
8580                                 filter_target = rx_filter_target_40m;
8581                 }
8582 
8583                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8584                 rf_val &= (~0x04);
8585                 if (loop == 1)
8586                         rf_val |= 0x4;
8587 
8588                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
8589 
8590                 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
8591 
8592                 rt2800_rf_lp_config(rt2x00dev, btxcal);
8593                 if (btxcal) {
8594                         tx_agc_fc = 0;
8595                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8596                         rf_val &= (~0x7F);
8597                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8598                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8599                         rf_val &= (~0x7F);
8600                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8601                 } else {
8602                         rx_agc_fc = 0;
8603                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8604                         rf_val &= (~0x7F);
8605                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8606                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8607                         rf_val &= (~0x7F);
8608                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8609                 }
8610 
8611                 usleep_range(1000, 2000);
8612 
8613                 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8614                 bbp_val &= (~0x6);
8615                 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8616 
8617                 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8618 
8619                 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8620 
8621                 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8622                 bbp_val |= 0x6;
8623                 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8624 do_cal:
8625                 if (btxcal) {
8626                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8627                         rf_val &= (~0x7F);
8628                         rf_val |= tx_agc_fc;
8629                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8630                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8631                         rf_val &= (~0x7F);
8632                         rf_val |= tx_agc_fc;
8633                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8634                 } else {
8635                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8636                         rf_val &= (~0x7F);
8637                         rf_val |= rx_agc_fc;
8638                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8639                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8640                         rf_val &= (~0x7F);
8641                         rf_val |= rx_agc_fc;
8642                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8643                 }
8644 
8645                 usleep_range(500, 1000);
8646 
8647                 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8648 
8649                 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8650 
8651                 cal_diff = cal_r32_init - cal_r32_val;
8652 
8653                 if (btxcal)
8654                         cmm_agc_fc = tx_agc_fc;
8655                 else
8656                         cmm_agc_fc = rx_agc_fc;
8657 
8658                 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
8659                     ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
8660                         if (btxcal)
8661                                 tx_agc_fc = 0;
8662                         else
8663                                 rx_agc_fc = 0;
8664                 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
8665                         if (btxcal)
8666                                 tx_agc_fc++;
8667                         else
8668                                 rx_agc_fc++;
8669                         goto do_cal;
8670                 }
8671 
8672                 if (btxcal) {
8673                         if (loop == 0)
8674                                 drv_data->tx_calibration_bw20 = tx_agc_fc;
8675                         else
8676                                 drv_data->tx_calibration_bw40 = tx_agc_fc;
8677                 } else {
8678                         if (loop == 0)
8679                                 drv_data->rx_calibration_bw20 = rx_agc_fc;
8680                         else
8681                                 drv_data->rx_calibration_bw40 = rx_agc_fc;
8682                 }
8683 
8684                 loop++;
8685         } while (loop <= 1);
8686 
8687         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
8688         rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
8689         rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
8690         rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
8691         rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
8692         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
8693         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
8694         rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
8695         rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
8696         rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
8697         rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
8698         rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
8699 
8700         rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
8701         rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
8702         rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
8703         rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
8704         rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
8705         rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
8706         rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
8707         rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
8708         rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
8709         rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
8710 
8711         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
8712         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
8713 
8714         rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
8715 
8716         rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
8717         rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
8718 
8719         bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8720         rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
8721                           2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
8722         rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8723 
8724         rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8725         rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8726 }
8727 
8728 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
8729 {
8730         /* Initialize RF central register to default value */
8731         rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
8732         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8733         rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
8734         rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
8735         rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8736         rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8737         rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8738         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8739         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8740         rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8741         rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8742         rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8743         rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8744         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8745         rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8746         rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8747         rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8748         rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8749         rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8750         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8751         rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8752         rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8753         rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8754         rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8755         rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8756         rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8757         rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8758         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8759         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8760         rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8761         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8762         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8763         rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8764         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8765         rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8766         rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8767         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8768         rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8769         rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8770         rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8771         rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8772         rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8773         rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8774         rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8775 
8776         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8777         if (rt2800_clk_is_20mhz(rt2x00dev))
8778                 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8779         else
8780                 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8781         rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8782         rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8783         rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8784         rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8785         rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8786         rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8787         rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8788         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8789         rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8790         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8791         rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8792         rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8793         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8794         rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8795         rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8796         rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8797 
8798         rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8799         rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8800         rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8801 
8802         /* Initialize RF channel register to default value */
8803         rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8804         rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8805         rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8806         rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8807         rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8808         rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8809         rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8810         rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8811         rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8812         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8813         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8814         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8815         rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8816         rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8817         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8818         rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8819         rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8820         rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8821         rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8822         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8823         rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8824         rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8825         rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8826         rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8827         rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8828         rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8829         rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8830         rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8831         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8832         rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8833         rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8834         rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8835         rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8836         rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8837         rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8838         rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8839         rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8840         rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8841         rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8842         rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8843         rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8844         rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8845         rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8846         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8847         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8848         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8849         rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8850         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8851         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8852         rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8853         rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8854         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8855         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8856         rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8857         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8858         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8859         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8860         rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8861         rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8862         rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8863 
8864         rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8865 
8866         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8867         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8868         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8869         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8870         rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8871         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8872         rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8873         rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8874         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8875         rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8876         rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8877         rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8878         rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8879         rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8880         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8881         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8882         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8883         rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
8884         rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8885         rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
8886         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
8887         rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8888         rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
8889         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8890         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8891         rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8892         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8893         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8894         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8895         rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8896 
8897         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8898         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8899         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8900         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8901         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8902         rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8903         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8904         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8905         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8906 
8907         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8908         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8909         rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8910         rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8911         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8912         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8913 
8914         /* Initialize RF channel register for DRQFN */
8915         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8916         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8917         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8918         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8919         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8920         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8921         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8922         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8923 
8924         /* Initialize RF DC calibration register to default value */
8925         rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8926         rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8927         rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8928         rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8929         rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8930         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8931         rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8932         rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8933         rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8934         rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8935         rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8936         rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8937         rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8938         rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8939         rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8940         rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8941         rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8942         rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8943         rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8944         rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8945         rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8946         rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8947         rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8948         rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8949         rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8950         rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8951         rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8952         rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8953         rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8954         rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8955         rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8956         rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8957         rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8958         rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8959         rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8960         rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8961         rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8962         rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8963         rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8964         rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8965         rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8966         rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8967         rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8968         rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8969         rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8970         rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8971         rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8972         rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8973         rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8974         rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8975         rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8976         rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
8977         rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
8978         rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
8979         rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
8980         rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
8981         rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
8982         rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
8983         rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
8984 
8985         rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
8986         rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
8987         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
8988 
8989         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8990         rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
8991 
8992         rt2800_bw_filter_calibration(rt2x00dev, true);
8993         rt2800_bw_filter_calibration(rt2x00dev, false);
8994 }
8995 
8996 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
8997 {
8998         if (rt2800_is_305x_soc(rt2x00dev)) {
8999                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
9000                 return;
9001         }
9002 
9003         switch (rt2x00dev->chip.rt) {
9004         case RT3070:
9005         case RT3071:
9006         case RT3090:
9007                 rt2800_init_rfcsr_30xx(rt2x00dev);
9008                 break;
9009         case RT3290:
9010                 rt2800_init_rfcsr_3290(rt2x00dev);
9011                 break;
9012         case RT3352:
9013                 rt2800_init_rfcsr_3352(rt2x00dev);
9014                 break;
9015         case RT3390:
9016                 rt2800_init_rfcsr_3390(rt2x00dev);
9017                 break;
9018         case RT3883:
9019                 rt2800_init_rfcsr_3883(rt2x00dev);
9020                 break;
9021         case RT3572:
9022                 rt2800_init_rfcsr_3572(rt2x00dev);
9023                 break;
9024         case RT3593:
9025                 rt2800_init_rfcsr_3593(rt2x00dev);
9026                 break;
9027         case RT5350:
9028                 rt2800_init_rfcsr_5350(rt2x00dev);
9029                 break;
9030         case RT5390:
9031                 rt2800_init_rfcsr_5390(rt2x00dev);
9032                 break;
9033         case RT5392:
9034                 rt2800_init_rfcsr_5392(rt2x00dev);
9035                 break;
9036         case RT5592:
9037                 rt2800_init_rfcsr_5592(rt2x00dev);
9038                 break;
9039         case RT6352:
9040                 rt2800_init_rfcsr_6352(rt2x00dev);
9041                 break;
9042         }
9043 }
9044 
9045 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
9046 {
9047         u32 reg;
9048         u16 word;
9049 
9050         /*
9051          * Initialize MAC registers.
9052          */
9053         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
9054                      rt2800_init_registers(rt2x00dev)))
9055                 return -EIO;
9056 
9057         /*
9058          * Wait BBP/RF to wake up.
9059          */
9060         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
9061                 return -EIO;
9062 
9063         /*
9064          * Send signal during boot time to initialize firmware.
9065          */
9066         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
9067         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
9068         if (rt2x00_is_usb(rt2x00dev))
9069                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
9070         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
9071         msleep(1);
9072 
9073         /*
9074          * Make sure BBP is up and running.
9075          */
9076         if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
9077                 return -EIO;
9078 
9079         /*
9080          * Initialize BBP/RF registers.
9081          */
9082         rt2800_init_bbp(rt2x00dev);
9083         rt2800_init_rfcsr(rt2x00dev);
9084 
9085         if (rt2x00_is_usb(rt2x00dev) &&
9086             (rt2x00_rt(rt2x00dev, RT3070) ||
9087              rt2x00_rt(rt2x00dev, RT3071) ||
9088              rt2x00_rt(rt2x00dev, RT3572))) {
9089                 udelay(200);
9090                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
9091                 udelay(10);
9092         }
9093 
9094         /*
9095          * Enable RX.
9096          */
9097         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9098         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
9099         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9100         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9101 
9102         udelay(50);
9103 
9104         reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
9105         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
9106         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
9107         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9108         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
9109 
9110         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9111         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
9112         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9113         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9114 
9115         /*
9116          * Initialize LED control
9117          */
9118         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
9119         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
9120                            word & 0xff, (word >> 8) & 0xff);
9121 
9122         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
9123         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
9124                            word & 0xff, (word >> 8) & 0xff);
9125 
9126         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
9127         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
9128                            word & 0xff, (word >> 8) & 0xff);
9129 
9130         return 0;
9131 }
9132 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
9133 
9134 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
9135 {
9136         u32 reg;
9137 
9138         rt2800_disable_wpdma(rt2x00dev);
9139 
9140         /* Wait for DMA, ignore error */
9141         rt2800_wait_wpdma_ready(rt2x00dev);
9142 
9143         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9144         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
9145         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9146         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9147 }
9148 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
9149 
9150 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
9151 {
9152         u32 reg;
9153         u16 efuse_ctrl_reg;
9154 
9155         if (rt2x00_rt(rt2x00dev, RT3290))
9156                 efuse_ctrl_reg = EFUSE_CTRL_3290;
9157         else
9158                 efuse_ctrl_reg = EFUSE_CTRL;
9159 
9160         reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
9161         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
9162 }
9163 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
9164 
9165 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
9166 {
9167         u32 reg;
9168         u16 efuse_ctrl_reg;
9169         u16 efuse_data0_reg;
9170         u16 efuse_data1_reg;
9171         u16 efuse_data2_reg;
9172         u16 efuse_data3_reg;
9173 
9174         if (rt2x00_rt(rt2x00dev, RT3290)) {
9175                 efuse_ctrl_reg = EFUSE_CTRL_3290;
9176                 efuse_data0_reg = EFUSE_DATA0_3290;
9177                 efuse_data1_reg = EFUSE_DATA1_3290;
9178                 efuse_data2_reg = EFUSE_DATA2_3290;
9179                 efuse_data3_reg = EFUSE_DATA3_3290;
9180         } else {
9181                 efuse_ctrl_reg = EFUSE_CTRL;
9182                 efuse_data0_reg = EFUSE_DATA0;
9183                 efuse_data1_reg = EFUSE_DATA1;
9184                 efuse_data2_reg = EFUSE_DATA2;
9185                 efuse_data3_reg = EFUSE_DATA3;
9186         }
9187         mutex_lock(&rt2x00dev->csr_mutex);
9188 
9189         reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
9190         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
9191         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
9192         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
9193         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
9194 
9195         /* Wait until the EEPROM has been loaded */
9196         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
9197         /* Apparently the data is read from end to start */
9198         reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
9199         /* The returned value is in CPU order, but eeprom is le */
9200         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
9201         reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
9202         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
9203         reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
9204         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
9205         reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
9206         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
9207 
9208         mutex_unlock(&rt2x00dev->csr_mutex);
9209 }
9210 
9211 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
9212 {
9213         unsigned int i;
9214 
9215         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
9216                 rt2800_efuse_read(rt2x00dev, i);
9217 
9218         return 0;
9219 }
9220 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
9221 
9222 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
9223 {
9224         u16 word;
9225 
9226         if (rt2x00_rt(rt2x00dev, RT3593) ||
9227             rt2x00_rt(rt2x00dev, RT3883))
9228                 return 0;
9229 
9230         word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
9231         if ((word & 0x00ff) != 0x00ff)
9232                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
9233 
9234         return 0;
9235 }
9236 
9237 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
9238 {
9239         u16 word;
9240 
9241         if (rt2x00_rt(rt2x00dev, RT3593) ||
9242             rt2x00_rt(rt2x00dev, RT3883))
9243                 return 0;
9244 
9245         word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
9246         if ((word & 0x00ff) != 0x00ff)
9247                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
9248 
9249         return 0;
9250 }
9251 
9252 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
9253 {
9254         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
9255         u16 word;
9256         u8 *mac;
9257         u8 default_lna_gain;
9258         int retval;
9259 
9260         /*
9261          * Read the EEPROM.
9262          */
9263         retval = rt2800_read_eeprom(rt2x00dev);
9264         if (retval)
9265                 return retval;
9266 
9267         /*
9268          * Start validation of the data that has been read.
9269          */
9270         mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
9271         rt2x00lib_set_mac_address(rt2x00dev, mac);
9272 
9273         word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9274         if (word == 0xffff) {
9275                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
9276                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
9277                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
9278                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9279                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
9280         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
9281                    rt2x00_rt(rt2x00dev, RT2872)) {
9282                 /*
9283                  * There is a max of 2 RX streams for RT28x0 series
9284                  */
9285                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
9286                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
9287                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9288         }
9289 
9290         word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9291         if (word == 0xffff) {
9292                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
9293                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
9294                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
9295                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
9296                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
9297                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
9298                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
9299                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
9300                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
9301                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
9302                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
9303                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
9304                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
9305                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
9306                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
9307                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
9308                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
9309         }
9310 
9311         word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9312         if ((word & 0x00ff) == 0x00ff) {
9313                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
9314                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9315                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
9316         }
9317         if ((word & 0xff00) == 0xff00) {
9318                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
9319                                    LED_MODE_TXRX_ACTIVITY);
9320                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
9321                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9322                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
9323                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
9324                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
9325                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
9326         }
9327 
9328         /*
9329          * During the LNA validation we are going to use
9330          * lna0 as correct value. Note that EEPROM_LNA
9331          * is never validated.
9332          */
9333         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
9334         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
9335 
9336         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
9337         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
9338                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
9339         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
9340                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
9341         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
9342 
9343         drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
9344 
9345         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
9346         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
9347                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
9348         if (!rt2x00_rt(rt2x00dev, RT3593) &&
9349             !rt2x00_rt(rt2x00dev, RT3883)) {
9350                 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
9351                     rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
9352                         rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
9353                                            default_lna_gain);
9354         }
9355         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
9356 
9357         drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
9358 
9359         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
9360         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
9361                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
9362         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
9363                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
9364         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
9365 
9366         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
9367         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
9368                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
9369         if (!rt2x00_rt(rt2x00dev, RT3593) &&
9370             !rt2x00_rt(rt2x00dev, RT3883)) {
9371                 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
9372                     rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
9373                         rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
9374                                            default_lna_gain);
9375         }
9376         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
9377 
9378         if (rt2x00_rt(rt2x00dev, RT3593) ||
9379             rt2x00_rt(rt2x00dev, RT3883)) {
9380                 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
9381                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
9382                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
9383                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
9384                                            default_lna_gain);
9385                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
9386                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
9387                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
9388                                            default_lna_gain);
9389                 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
9390         }
9391 
9392         return 0;
9393 }
9394 
9395 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
9396 {
9397         u16 value;
9398         u16 eeprom;
9399         u16 rf;
9400 
9401         /*
9402          * Read EEPROM word for configuration.
9403          */
9404         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9405 
9406         /*
9407          * Identify RF chipset by EEPROM value
9408          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
9409          * RT53xx: defined in "EEPROM_CHIP_ID" field
9410          */
9411         if (rt2x00_rt(rt2x00dev, RT3290) ||
9412             rt2x00_rt(rt2x00dev, RT5390) ||
9413             rt2x00_rt(rt2x00dev, RT5392) ||
9414             rt2x00_rt(rt2x00dev, RT6352))
9415                 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
9416         else if (rt2x00_rt(rt2x00dev, RT3352))
9417                 rf = RF3322;
9418         else if (rt2x00_rt(rt2x00dev, RT3883))
9419                 rf = RF3853;
9420         else if (rt2x00_rt(rt2x00dev, RT5350))
9421                 rf = RF5350;
9422         else
9423                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
9424 
9425         switch (rf) {
9426         case RF2820:
9427         case RF2850:
9428         case RF2720:
9429         case RF2750:
9430         case RF3020:
9431         case RF2020:
9432         case RF3021:
9433         case RF3022:
9434         case RF3052:
9435         case RF3053:
9436         case RF3070:
9437         case RF3290:
9438         case RF3320:
9439         case RF3322:
9440         case RF3853:
9441         case RF5350:
9442         case RF5360:
9443         case RF5362:
9444         case RF5370:
9445         case RF5372:
9446         case RF5390:
9447         case RF5392:
9448         case RF5592:
9449         case RF7620:
9450                 break;
9451         default:
9452                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
9453                            rf);
9454                 return -ENODEV;
9455         }
9456 
9457         rt2x00_set_rf(rt2x00dev, rf);
9458 
9459         /*
9460          * Identify default antenna configuration.
9461          */
9462         rt2x00dev->default_ant.tx_chain_num =
9463             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
9464         rt2x00dev->default_ant.rx_chain_num =
9465             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
9466 
9467         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9468 
9469         if (rt2x00_rt(rt2x00dev, RT3070) ||
9470             rt2x00_rt(rt2x00dev, RT3090) ||
9471             rt2x00_rt(rt2x00dev, RT3352) ||
9472             rt2x00_rt(rt2x00dev, RT3390)) {
9473                 value = rt2x00_get_field16(eeprom,
9474                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
9475                 switch (value) {
9476                 case 0:
9477                 case 1:
9478                 case 2:
9479                         rt2x00dev->default_ant.tx = ANTENNA_A;
9480                         rt2x00dev->default_ant.rx = ANTENNA_A;
9481                         break;
9482                 case 3:
9483                         rt2x00dev->default_ant.tx = ANTENNA_A;
9484                         rt2x00dev->default_ant.rx = ANTENNA_B;
9485                         break;
9486                 }
9487         } else {
9488                 rt2x00dev->default_ant.tx = ANTENNA_A;
9489                 rt2x00dev->default_ant.rx = ANTENNA_A;
9490         }
9491 
9492         /* These chips have hardware RX antenna diversity */
9493         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
9494             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
9495                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
9496                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
9497         }
9498 
9499         /*
9500          * Determine external LNA informations.
9501          */
9502         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
9503                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
9504         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
9505                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
9506 
9507         /*
9508          * Detect if this device has an hardware controlled radio.
9509          */
9510         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
9511                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
9512 
9513         /*
9514          * Detect if this device has Bluetooth co-existence.
9515          */
9516         if (!rt2x00_rt(rt2x00dev, RT3352) &&
9517             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
9518                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
9519 
9520         /*
9521          * Read frequency offset and RF programming sequence.
9522          */
9523         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9524         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
9525 
9526         /*
9527          * Store led settings, for correct led behaviour.
9528          */
9529 #ifdef CONFIG_RT2X00_LIB_LEDS
9530         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
9531         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
9532         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
9533 
9534         rt2x00dev->led_mcu_reg = eeprom;
9535 #endif /* CONFIG_RT2X00_LIB_LEDS */
9536 
9537         /*
9538          * Check if support EIRP tx power limit feature.
9539          */
9540         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
9541 
9542         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
9543                                         EIRP_MAX_TX_POWER_LIMIT)
9544                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
9545 
9546         /*
9547          * Detect if device uses internal or external PA
9548          */
9549         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9550 
9551         if (rt2x00_rt(rt2x00dev, RT3352)) {
9552                 if (rt2x00_get_field16(eeprom,
9553                     EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
9554                     __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
9555                               &rt2x00dev->cap_flags);
9556                 if (rt2x00_get_field16(eeprom,
9557                     EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
9558                     __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
9559                               &rt2x00dev->cap_flags);
9560         }
9561 
9562         return 0;
9563 }
9564 
9565 /*
9566  * RF value list for rt28xx
9567  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
9568  */
9569 static const struct rf_channel rf_vals[] = {
9570         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
9571         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
9572         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
9573         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
9574         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
9575         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
9576         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
9577         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
9578         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
9579         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
9580         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
9581         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
9582         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
9583         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
9584 
9585         /* 802.11 UNI / HyperLan 2 */
9586         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
9587         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
9588         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
9589         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
9590         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
9591         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
9592         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
9593         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
9594         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
9595         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
9596         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
9597         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
9598 
9599         /* 802.11 HyperLan 2 */
9600         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
9601         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
9602         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
9603         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
9604         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
9605         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
9606         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
9607         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
9608         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
9609         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
9610         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
9611         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
9612         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
9613         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
9614         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
9615         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
9616 
9617         /* 802.11 UNII */
9618         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
9619         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
9620         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
9621         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
9622         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
9623         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
9624         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
9625         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
9626         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
9627         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
9628         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
9629 
9630         /* 802.11 Japan */
9631         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
9632         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
9633         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
9634         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
9635         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
9636         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
9637         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
9638 };
9639 
9640 /*
9641  * RF value list for rt3xxx
9642  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
9643  */
9644 static const struct rf_channel rf_vals_3x[] = {
9645         {1,  241, 2, 2 },
9646         {2,  241, 2, 7 },
9647         {3,  242, 2, 2 },
9648         {4,  242, 2, 7 },
9649         {5,  243, 2, 2 },
9650         {6,  243, 2, 7 },
9651         {7,  244, 2, 2 },
9652         {8,  244, 2, 7 },
9653         {9,  245, 2, 2 },
9654         {10, 245, 2, 7 },
9655         {11, 246, 2, 2 },
9656         {12, 246, 2, 7 },
9657         {13, 247, 2, 2 },
9658         {14, 248, 2, 4 },
9659 
9660         /* 802.11 UNI / HyperLan 2 */
9661         {36, 0x56, 0, 4},
9662         {38, 0x56, 0, 6},
9663         {40, 0x56, 0, 8},
9664         {44, 0x57, 0, 0},
9665         {46, 0x57, 0, 2},
9666         {48, 0x57, 0, 4},
9667         {52, 0x57, 0, 8},
9668         {54, 0x57, 0, 10},
9669         {56, 0x58, 0, 0},
9670         {60, 0x58, 0, 4},
9671         {62, 0x58, 0, 6},
9672         {64, 0x58, 0, 8},
9673 
9674         /* 802.11 HyperLan 2 */
9675         {100, 0x5b, 0, 8},
9676         {102, 0x5b, 0, 10},
9677         {104, 0x5c, 0, 0},
9678         {108, 0x5c, 0, 4},
9679         {110, 0x5c, 0, 6},
9680         {112, 0x5c, 0, 8},
9681         {116, 0x5d, 0, 0},
9682         {118, 0x5d, 0, 2},
9683         {120, 0x5d, 0, 4},
9684         {124, 0x5d, 0, 8},
9685         {126, 0x5d, 0, 10},
9686         {128, 0x5e, 0, 0},
9687         {132, 0x5e, 0, 4},
9688         {134, 0x5e, 0, 6},
9689         {136, 0x5e, 0, 8},
9690         {140, 0x5f, 0, 0},
9691 
9692         /* 802.11 UNII */
9693         {149, 0x5f, 0, 9},
9694         {151, 0x5f, 0, 11},
9695         {153, 0x60, 0, 1},
9696         {157, 0x60, 0, 5},
9697         {159, 0x60, 0, 7},
9698         {161, 0x60, 0, 9},
9699         {165, 0x61, 0, 1},
9700         {167, 0x61, 0, 3},
9701         {169, 0x61, 0, 5},
9702         {171, 0x61, 0, 7},
9703         {173, 0x61, 0, 9},
9704 };
9705 
9706 /*
9707  * RF value list for rt3xxx with Xtal20MHz
9708  * Supports: 2.4 GHz (all) (RF3322)
9709  */
9710 static const struct rf_channel rf_vals_3x_xtal20[] = {
9711         {1,    0xE2,     2,  0x14},
9712         {2,    0xE3,     2,  0x14},
9713         {3,    0xE4,     2,  0x14},
9714         {4,    0xE5,     2,  0x14},
9715         {5,    0xE6,     2,  0x14},
9716         {6,    0xE7,     2,  0x14},
9717         {7,    0xE8,     2,  0x14},
9718         {8,    0xE9,     2,  0x14},
9719         {9,    0xEA,     2,  0x14},
9720         {10,   0xEB,     2,  0x14},
9721         {11,   0xEC,     2,  0x14},
9722         {12,   0xED,     2,  0x14},
9723         {13,   0xEE,     2,  0x14},
9724         {14,   0xF0,     2,  0x18},
9725 };
9726 
9727 static const struct rf_channel rf_vals_3853[] = {
9728         {1,  241, 6, 2},
9729         {2,  241, 6, 7},
9730         {3,  242, 6, 2},
9731         {4,  242, 6, 7},
9732         {5,  243, 6, 2},
9733         {6,  243, 6, 7},
9734         {7,  244, 6, 2},
9735         {8,  244, 6, 7},
9736         {9,  245, 6, 2},
9737         {10, 245, 6, 7},
9738         {11, 246, 6, 2},
9739         {12, 246, 6, 7},
9740         {13, 247, 6, 2},
9741         {14, 248, 6, 4},
9742 
9743         {36, 0x56, 8, 4},
9744         {38, 0x56, 8, 6},
9745         {40, 0x56, 8, 8},
9746         {44, 0x57, 8, 0},
9747         {46, 0x57, 8, 2},
9748         {48, 0x57, 8, 4},
9749         {52, 0x57, 8, 8},
9750         {54, 0x57, 8, 10},
9751         {56, 0x58, 8, 0},
9752         {60, 0x58, 8, 4},
9753         {62, 0x58, 8, 6},
9754         {64, 0x58, 8, 8},
9755 
9756         {100, 0x5b, 8, 8},
9757         {102, 0x5b, 8, 10},
9758         {104, 0x5c, 8, 0},
9759         {108, 0x5c, 8, 4},
9760         {110, 0x5c, 8, 6},
9761         {112, 0x5c, 8, 8},
9762         {114, 0x5c, 8, 10},
9763         {116, 0x5d, 8, 0},
9764         {118, 0x5d, 8, 2},
9765         {120, 0x5d, 8, 4},
9766         {124, 0x5d, 8, 8},
9767         {126, 0x5d, 8, 10},
9768         {128, 0x5e, 8, 0},
9769         {132, 0x5e, 8, 4},
9770         {134, 0x5e, 8, 6},
9771         {136, 0x5e, 8, 8},
9772         {140, 0x5f, 8, 0},
9773 
9774         {149, 0x5f, 8, 9},
9775         {151, 0x5f, 8, 11},
9776         {153, 0x60, 8, 1},
9777         {157, 0x60, 8, 5},
9778         {159, 0x60, 8, 7},
9779         {161, 0x60, 8, 9},
9780         {165, 0x61, 8, 1},
9781         {167, 0x61, 8, 3},
9782         {169, 0x61, 8, 5},
9783         {171, 0x61, 8, 7},
9784         {173, 0x61, 8, 9},
9785 };
9786 
9787 static const struct rf_channel rf_vals_5592_xtal20[] = {
9788         /* Channel, N, K, mod, R */
9789         {1, 482, 4, 10, 3},
9790         {2, 483, 4, 10, 3},
9791         {3, 484, 4, 10, 3},
9792         {4, 485, 4, 10, 3},
9793         {5, 486, 4, 10, 3},
9794         {6, 487, 4, 10, 3},
9795         {7, 488, 4, 10, 3},
9796         {8, 489, 4, 10, 3},
9797         {9, 490, 4, 10, 3},
9798         {10, 491, 4, 10, 3},
9799         {11, 492, 4, 10, 3},
9800         {12, 493, 4, 10, 3},
9801         {13, 494, 4, 10, 3},
9802         {14, 496, 8, 10, 3},
9803         {36, 172, 8, 12, 1},
9804         {38, 173, 0, 12, 1},
9805         {40, 173, 4, 12, 1},
9806         {42, 173, 8, 12, 1},
9807         {44, 174, 0, 12, 1},
9808         {46, 174, 4, 12, 1},
9809         {48, 174, 8, 12, 1},
9810         {50, 175, 0, 12, 1},
9811         {52, 175, 4, 12, 1},
9812         {54, 175, 8, 12, 1},
9813         {56, 176, 0, 12, 1},
9814         {58, 176, 4, 12, 1},
9815         {60, 176, 8, 12, 1},
9816         {62, 177, 0, 12, 1},
9817         {64, 177, 4, 12, 1},
9818         {100, 183, 4, 12, 1},
9819         {102, 183, 8, 12, 1},
9820         {104, 184, 0, 12, 1},
9821         {106, 184, 4, 12, 1},
9822         {108, 184, 8, 12, 1},
9823         {110, 185, 0, 12, 1},
9824         {112, 185, 4, 12, 1},
9825         {114, 185, 8, 12, 1},
9826         {116, 186, 0, 12, 1},
9827         {118, 186, 4, 12, 1},
9828         {120, 186, 8, 12, 1},
9829         {122, 187, 0, 12, 1},
9830         {124, 187, 4, 12, 1},
9831         {126, 187, 8, 12, 1},
9832         {128, 188, 0, 12, 1},
9833         {130, 188, 4, 12, 1},
9834         {132, 188, 8, 12, 1},
9835         {134, 189, 0, 12, 1},
9836         {136, 189, 4, 12, 1},
9837         {138, 189, 8, 12, 1},
9838         {140, 190, 0, 12, 1},
9839         {149, 191, 6, 12, 1},
9840         {151, 191, 10, 12, 1},
9841         {153, 192, 2, 12, 1},
9842         {155, 192, 6, 12, 1},
9843         {157, 192, 10, 12, 1},
9844         {159, 193, 2, 12, 1},
9845         {161, 193, 6, 12, 1},
9846         {165, 194, 2, 12, 1},
9847         {184, 164, 0, 12, 1},
9848         {188, 164, 4, 12, 1},
9849         {192, 165, 8, 12, 1},
9850         {196, 166, 0, 12, 1},
9851 };
9852 
9853 static const struct rf_channel rf_vals_5592_xtal40[] = {
9854         /* Channel, N, K, mod, R */
9855         {1, 241, 2, 10, 3},
9856         {2, 241, 7, 10, 3},
9857         {3, 242, 2, 10, 3},
9858         {4, 242, 7, 10, 3},
9859         {5, 243, 2, 10, 3},
9860         {6, 243, 7, 10, 3},
9861         {7, 244, 2, 10, 3},
9862         {8, 244, 7, 10, 3},
9863         {9, 245, 2, 10, 3},
9864         {10, 245, 7, 10, 3},
9865         {11, 246, 2, 10, 3},
9866         {12, 246, 7, 10, 3},
9867         {13, 247, 2, 10, 3},
9868         {14, 248, 4, 10, 3},
9869         {36, 86, 4, 12, 1},
9870         {38, 86, 6, 12, 1},
9871         {40, 86, 8, 12, 1},
9872         {42, 86, 10, 12, 1},
9873         {44, 87, 0, 12, 1},
9874         {46, 87, 2, 12, 1},
9875         {48, 87, 4, 12, 1},
9876         {50, 87, 6, 12, 1},
9877         {52, 87, 8, 12, 1},
9878         {54, 87, 10, 12, 1},
9879         {56, 88, 0, 12, 1},
9880         {58, 88, 2, 12, 1},
9881         {60, 88, 4, 12, 1},
9882         {62, 88, 6, 12, 1},
9883         {64, 88, 8, 12, 1},
9884         {100, 91, 8, 12, 1},
9885         {102, 91, 10, 12, 1},
9886         {104, 92, 0, 12, 1},
9887         {106, 92, 2, 12, 1},
9888         {108, 92, 4, 12, 1},
9889         {110, 92, 6, 12, 1},
9890         {112, 92, 8, 12, 1},
9891         {114, 92, 10, 12, 1},
9892         {116, 93, 0, 12, 1},
9893         {118, 93, 2, 12, 1},
9894         {120, 93, 4, 12, 1},
9895         {122, 93, 6, 12, 1},
9896         {124, 93, 8, 12, 1},
9897         {126, 93, 10, 12, 1},
9898         {128, 94, 0, 12, 1},
9899         {130, 94, 2, 12, 1},
9900         {132, 94, 4, 12, 1},
9901         {134, 94, 6, 12, 1},
9902         {136, 94, 8, 12, 1},
9903         {138, 94, 10, 12, 1},
9904         {140, 95, 0, 12, 1},
9905         {149, 95, 9, 12, 1},
9906         {151, 95, 11, 12, 1},
9907         {153, 96, 1, 12, 1},
9908         {155, 96, 3, 12, 1},
9909         {157, 96, 5, 12, 1},
9910         {159, 96, 7, 12, 1},
9911         {161, 96, 9, 12, 1},
9912         {165, 97, 1, 12, 1},
9913         {184, 82, 0, 12, 1},
9914         {188, 82, 4, 12, 1},
9915         {192, 82, 8, 12, 1},
9916         {196, 83, 0, 12, 1},
9917 };
9918 
9919 static const struct rf_channel rf_vals_7620[] = {
9920         {1, 0x50, 0x99, 0x99, 1},
9921         {2, 0x50, 0x44, 0x44, 2},
9922         {3, 0x50, 0xEE, 0xEE, 2},
9923         {4, 0x50, 0x99, 0x99, 3},
9924         {5, 0x51, 0x44, 0x44, 0},
9925         {6, 0x51, 0xEE, 0xEE, 0},
9926         {7, 0x51, 0x99, 0x99, 1},
9927         {8, 0x51, 0x44, 0x44, 2},
9928         {9, 0x51, 0xEE, 0xEE, 2},
9929         {10, 0x51, 0x99, 0x99, 3},
9930         {11, 0x52, 0x44, 0x44, 0},
9931         {12, 0x52, 0xEE, 0xEE, 0},
9932         {13, 0x52, 0x99, 0x99, 1},
9933         {14, 0x52, 0x33, 0x33, 3},
9934 };
9935 
9936 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
9937 {
9938         struct hw_mode_spec *spec = &rt2x00dev->spec;
9939         struct channel_info *info;
9940         char *default_power1;
9941         char *default_power2;
9942         char *default_power3;
9943         unsigned int i, tx_chains, rx_chains;
9944         u32 reg;
9945 
9946         /*
9947          * Disable powersaving as default.
9948          */
9949         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
9950 
9951         /*
9952          * Change default retry settings to values corresponding more closely
9953          * to rate[0].count setting of minstrel rate control algorithm.
9954          */
9955         rt2x00dev->hw->wiphy->retry_short = 2;
9956         rt2x00dev->hw->wiphy->retry_long = 2;
9957 
9958         /*
9959          * Initialize all hw fields.
9960          */
9961         ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9962         ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9963         ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9964         ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9965         ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9966 
9967         /*
9968          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
9969          * unless we are capable of sending the buffered frames out after the
9970          * DTIM transmission using rt2x00lib_beacondone. This will send out
9971          * multicast and broadcast traffic immediately instead of buffering it
9972          * infinitly and thus dropping it after some time.
9973          */
9974         if (!rt2x00_is_usb(rt2x00dev))
9975                 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
9976 
9977         /* Set MFP if HW crypto is disabled. */
9978         if (rt2800_hwcrypt_disabled(rt2x00dev))
9979                 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
9980 
9981         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
9982         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
9983                                 rt2800_eeprom_addr(rt2x00dev,
9984                                                    EEPROM_MAC_ADDR_0));
9985 
9986         /*
9987          * As rt2800 has a global fallback table we cannot specify
9988          * more then one tx rate per frame but since the hw will
9989          * try several rates (based on the fallback table) we should
9990          * initialize max_report_rates to the maximum number of rates
9991          * we are going to try. Otherwise mac80211 will truncate our
9992          * reported tx rates and the rc algortihm will end up with
9993          * incorrect data.
9994          */
9995         rt2x00dev->hw->max_rates = 1;
9996         rt2x00dev->hw->max_report_rates = 7;
9997         rt2x00dev->hw->max_rate_tries = 1;
9998 
9999         /*
10000          * Initialize hw_mode information.
10001          */
10002         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
10003 
10004         switch (rt2x00dev->chip.rf) {
10005         case RF2720:
10006         case RF2820:
10007                 spec->num_channels = 14;
10008                 spec->channels = rf_vals;
10009                 break;
10010 
10011         case RF2750:
10012         case RF2850:
10013                 spec->num_channels = ARRAY_SIZE(rf_vals);
10014                 spec->channels = rf_vals;
10015                 break;
10016 
10017         case RF2020:
10018         case RF3020:
10019         case RF3021:
10020         case RF3022:
10021         case RF3070:
10022         case RF3290:
10023         case RF3320:
10024         case RF3322:
10025         case RF5350:
10026         case RF5360:
10027         case RF5362:
10028         case RF5370:
10029         case RF5372:
10030         case RF5390:
10031         case RF5392:
10032                 spec->num_channels = 14;
10033                 if (rt2800_clk_is_20mhz(rt2x00dev))
10034                         spec->channels = rf_vals_3x_xtal20;
10035                 else
10036                         spec->channels = rf_vals_3x;
10037                 break;
10038 
10039         case RF7620:
10040                 spec->num_channels = ARRAY_SIZE(rf_vals_7620);
10041                 spec->channels = rf_vals_7620;
10042                 break;
10043 
10044         case RF3052:
10045         case RF3053:
10046                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
10047                 spec->channels = rf_vals_3x;
10048                 break;
10049 
10050         case RF3853:
10051                 spec->num_channels = ARRAY_SIZE(rf_vals_3853);
10052                 spec->channels = rf_vals_3853;
10053                 break;
10054 
10055         case RF5592:
10056                 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
10057                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
10058                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
10059                         spec->channels = rf_vals_5592_xtal40;
10060                 } else {
10061                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
10062                         spec->channels = rf_vals_5592_xtal20;
10063                 }
10064                 break;
10065         }
10066 
10067         if (WARN_ON_ONCE(!spec->channels))
10068                 return -ENODEV;
10069 
10070         spec->supported_bands = SUPPORT_BAND_2GHZ;
10071         if (spec->num_channels > 14)
10072                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
10073 
10074         /*
10075          * Initialize HT information.
10076          */
10077         if (!rt2x00_rf(rt2x00dev, RF2020))
10078                 spec->ht.ht_supported = true;
10079         else
10080                 spec->ht.ht_supported = false;
10081 
10082         spec->ht.cap =
10083             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
10084             IEEE80211_HT_CAP_GRN_FLD |
10085             IEEE80211_HT_CAP_SGI_20 |
10086             IEEE80211_HT_CAP_SGI_40;
10087 
10088         tx_chains = rt2x00dev->default_ant.tx_chain_num;
10089         rx_chains = rt2x00dev->default_ant.rx_chain_num;
10090 
10091         if (tx_chains >= 2)
10092                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
10093 
10094         spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
10095 
10096         spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
10097         spec->ht.ampdu_density = 4;
10098         spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
10099         if (tx_chains != rx_chains) {
10100                 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
10101                 spec->ht.mcs.tx_params |=
10102                     (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
10103         }
10104 
10105         switch (rx_chains) {
10106         case 3:
10107                 spec->ht.mcs.rx_mask[2] = 0xff;
10108                 /* fall through */
10109         case 2:
10110                 spec->ht.mcs.rx_mask[1] = 0xff;
10111                 /* fall through */
10112         case 1:
10113                 spec->ht.mcs.rx_mask[0] = 0xff;
10114                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
10115                 break;
10116         }
10117 
10118         /*
10119          * Create channel information array
10120          */
10121         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
10122         if (!info)
10123                 return -ENOMEM;
10124 
10125         spec->channels_info = info;
10126 
10127         default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
10128         default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
10129 
10130         if (rt2x00dev->default_ant.tx_chain_num > 2)
10131                 default_power3 = rt2800_eeprom_addr(rt2x00dev,
10132                                                     EEPROM_EXT_TXPOWER_BG3);
10133         else
10134                 default_power3 = NULL;
10135 
10136         for (i = 0; i < 14; i++) {
10137                 info[i].default_power1 = default_power1[i];
10138                 info[i].default_power2 = default_power2[i];
10139                 if (default_power3)
10140                         info[i].default_power3 = default_power3[i];
10141         }
10142 
10143         if (spec->num_channels > 14) {
10144                 default_power1 = rt2800_eeprom_addr(rt2x00dev,
10145                                                     EEPROM_TXPOWER_A1);
10146                 default_power2 = rt2800_eeprom_addr(rt2x00dev,
10147                                                     EEPROM_TXPOWER_A2);
10148 
10149                 if (rt2x00dev->default_ant.tx_chain_num > 2)
10150                         default_power3 =
10151                                 rt2800_eeprom_addr(rt2x00dev,
10152                                                    EEPROM_EXT_TXPOWER_A3);
10153                 else
10154                         default_power3 = NULL;
10155 
10156                 for (i = 14; i < spec->num_channels; i++) {
10157                         info[i].default_power1 = default_power1[i - 14];
10158                         info[i].default_power2 = default_power2[i - 14];
10159                         if (default_power3)
10160                                 info[i].default_power3 = default_power3[i - 14];
10161                 }
10162         }
10163 
10164         switch (rt2x00dev->chip.rf) {
10165         case RF2020:
10166         case RF3020:
10167         case RF3021:
10168         case RF3022:
10169         case RF3320:
10170         case RF3052:
10171         case RF3053:
10172         case RF3070:
10173         case RF3290:
10174         case RF3853:
10175         case RF5350:
10176         case RF5360:
10177         case RF5362:
10178         case RF5370:
10179         case RF5372:
10180         case RF5390:
10181         case RF5392:
10182         case RF5592:
10183         case RF7620:
10184                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
10185                 break;
10186         }
10187 
10188         return 0;
10189 }
10190 
10191 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
10192 {
10193         u32 reg;
10194         u32 rt;
10195         u32 rev;
10196 
10197         if (rt2x00_rt(rt2x00dev, RT3290))
10198                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
10199         else
10200                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
10201 
10202         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
10203         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
10204 
10205         switch (rt) {
10206         case RT2860:
10207         case RT2872:
10208         case RT2883:
10209         case RT3070:
10210         case RT3071:
10211         case RT3090:
10212         case RT3290:
10213         case RT3352:
10214         case RT3390:
10215         case RT3572:
10216         case RT3593:
10217         case RT3883:
10218         case RT5350:
10219         case RT5390:
10220         case RT5392:
10221         case RT5592:
10222                 break;
10223         default:
10224                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
10225                            rt, rev);
10226                 return -ENODEV;
10227         }
10228 
10229         if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
10230                 rt = RT6352;
10231 
10232         rt2x00_set_rt(rt2x00dev, rt, rev);
10233 
10234         return 0;
10235 }
10236 
10237 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
10238 {
10239         int retval;
10240         u32 reg;
10241 
10242         retval = rt2800_probe_rt(rt2x00dev);
10243         if (retval)
10244                 return retval;
10245 
10246         /*
10247          * Allocate eeprom data.
10248          */
10249         retval = rt2800_validate_eeprom(rt2x00dev);
10250         if (retval)
10251                 return retval;
10252 
10253         retval = rt2800_init_eeprom(rt2x00dev);
10254         if (retval)
10255                 return retval;
10256 
10257         /*
10258          * Enable rfkill polling by setting GPIO direction of the
10259          * rfkill switch GPIO pin correctly.
10260          */
10261         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
10262         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
10263         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
10264 
10265         /*
10266          * Initialize hw specifications.
10267          */
10268         retval = rt2800_probe_hw_mode(rt2x00dev);
10269         if (retval)
10270                 return retval;
10271 
10272         /*
10273          * Set device capabilities.
10274          */
10275         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
10276         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
10277         if (!rt2x00_is_usb(rt2x00dev))
10278                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
10279 
10280         /*
10281          * Set device requirements.
10282          */
10283         if (!rt2x00_is_soc(rt2x00dev))
10284                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
10285         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
10286         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
10287         if (!rt2800_hwcrypt_disabled(rt2x00dev))
10288                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
10289         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
10290         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
10291         if (rt2x00_is_usb(rt2x00dev))
10292                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
10293         else {
10294                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
10295                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
10296         }
10297 
10298         if (modparam_watchdog) {
10299                 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags);
10300                 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100);
10301         } else {
10302                 rt2x00dev->link.watchdog_disabled = true;
10303         }
10304 
10305         /*
10306          * Set the rssi offset.
10307          */
10308         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
10309 
10310         return 0;
10311 }
10312 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
10313 
10314 /*
10315  * IEEE80211 stack callback functions.
10316  */
10317 void rt2800_get_key_seq(struct ieee80211_hw *hw,
10318                         struct ieee80211_key_conf *key,
10319                         struct ieee80211_key_seq *seq)
10320 {
10321         struct rt2x00_dev *rt2x00dev = hw->priv;
10322         struct mac_iveiv_entry iveiv_entry;
10323         u32 offset;
10324 
10325         if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
10326                 return;
10327 
10328         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
10329         rt2800_register_multiread(rt2x00dev, offset,
10330                                       &iveiv_entry, sizeof(iveiv_entry));
10331 
10332         memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
10333         memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
10334 }
10335 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
10336 
10337 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
10338 {
10339         struct rt2x00_dev *rt2x00dev = hw->priv;
10340         u32 reg;
10341         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
10342 
10343         reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
10344         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
10345         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
10346 
10347         reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
10348         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
10349         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
10350 
10351         reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
10352         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
10353         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
10354 
10355         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
10356         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
10357         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
10358 
10359         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
10360         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
10361         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
10362 
10363         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
10364         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
10365         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
10366 
10367         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
10368         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
10369         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
10370 
10371         return 0;
10372 }
10373 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
10374 
10375 int rt2800_conf_tx(struct ieee80211_hw *hw,
10376                    struct ieee80211_vif *vif, u16 queue_idx,
10377                    const struct ieee80211_tx_queue_params *params)
10378 {
10379         struct rt2x00_dev *rt2x00dev = hw->priv;
10380         struct data_queue *queue;
10381         struct rt2x00_field32 field;
10382         int retval;
10383         u32 reg;
10384         u32 offset;
10385 
10386         /*
10387          * First pass the configuration through rt2x00lib, that will
10388          * update the queue settings and validate the input. After that
10389          * we are free to update the registers based on the value
10390          * in the queue parameter.
10391          */
10392         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
10393         if (retval)
10394                 return retval;
10395 
10396         /*
10397          * We only need to perform additional register initialization
10398          * for WMM queues/
10399          */
10400         if (queue_idx >= 4)
10401                 return 0;
10402 
10403         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
10404 
10405         /* Update WMM TXOP register */
10406         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
10407         field.bit_offset = (queue_idx & 1) * 16;
10408         field.bit_mask = 0xffff << field.bit_offset;
10409 
10410         reg = rt2800_register_read(rt2x00dev, offset);
10411         rt2x00_set_field32(&reg, field, queue->txop);
10412         rt2800_register_write(rt2x00dev, offset, reg);
10413 
10414         /* Update WMM registers */
10415         field.bit_offset = queue_idx * 4;
10416         field.bit_mask = 0xf << field.bit_offset;
10417 
10418         reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
10419         rt2x00_set_field32(&reg, field, queue->aifs);
10420         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
10421 
10422         reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
10423         rt2x00_set_field32(&reg, field, queue->cw_min);
10424         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
10425 
10426         reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
10427         rt2x00_set_field32(&reg, field, queue->cw_max);
10428         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
10429 
10430         /* Update EDCA registers */
10431         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
10432 
10433         reg = rt2800_register_read(rt2x00dev, offset);
10434         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
10435         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
10436         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
10437         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
10438         rt2800_register_write(rt2x00dev, offset, reg);
10439 
10440         return 0;
10441 }
10442 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
10443 
10444 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
10445 {
10446         struct rt2x00_dev *rt2x00dev = hw->priv;
10447         u64 tsf;
10448         u32 reg;
10449 
10450         reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
10451         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
10452         reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
10453         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
10454 
10455         return tsf;
10456 }
10457 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
10458 
10459 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
10460                         struct ieee80211_ampdu_params *params)
10461 {
10462         struct ieee80211_sta *sta = params->sta;
10463         enum ieee80211_ampdu_mlme_action action = params->action;
10464         u16 tid = params->tid;
10465         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
10466         int ret = 0;
10467 
10468         /*
10469          * Don't allow aggregation for stations the hardware isn't aware
10470          * of because tx status reports for frames to an unknown station
10471          * always contain wcid=WCID_END+1 and thus we can't distinguish
10472          * between multiple stations which leads to unwanted situations
10473          * when the hw reorders frames due to aggregation.
10474          */
10475         if (sta_priv->wcid > WCID_END)
10476                 return 1;
10477 
10478         switch (action) {
10479         case IEEE80211_AMPDU_RX_START:
10480         case IEEE80211_AMPDU_RX_STOP:
10481                 /*
10482                  * The hw itself takes care of setting up BlockAck mechanisms.
10483                  * So, we only have to allow mac80211 to nagotiate a BlockAck
10484                  * agreement. Once that is done, the hw will BlockAck incoming
10485                  * AMPDUs without further setup.
10486                  */
10487                 break;
10488         case IEEE80211_AMPDU_TX_START:
10489                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
10490                 break;
10491         case IEEE80211_AMPDU_TX_STOP_CONT:
10492         case IEEE80211_AMPDU_TX_STOP_FLUSH:
10493         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
10494                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
10495                 break;
10496         case IEEE80211_AMPDU_TX_OPERATIONAL:
10497                 break;
10498         default:
10499                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
10500                             "Unknown AMPDU action\n");
10501         }
10502 
10503         return ret;
10504 }
10505 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
10506 
10507 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
10508                       struct survey_info *survey)
10509 {
10510         struct rt2x00_dev *rt2x00dev = hw->priv;
10511         struct ieee80211_conf *conf = &hw->conf;
10512         u32 idle, busy, busy_ext;
10513 
10514         if (idx != 0)
10515                 return -ENOENT;
10516 
10517         survey->channel = conf->chandef.chan;
10518 
10519         idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
10520         busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
10521         busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
10522 
10523         if (idle || busy) {
10524                 survey->filled = SURVEY_INFO_TIME |
10525                                  SURVEY_INFO_TIME_BUSY |
10526                                  SURVEY_INFO_TIME_EXT_BUSY;
10527 
10528                 survey->time = (idle + busy) / 1000;
10529                 survey->time_busy = busy / 1000;
10530                 survey->time_ext_busy = busy_ext / 1000;
10531         }
10532 
10533         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
10534                 survey->filled |= SURVEY_INFO_IN_USE;
10535 
10536         return 0;
10537 
10538 }
10539 EXPORT_SYMBOL_GPL(rt2800_get_survey);
10540 
10541 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
10542 MODULE_VERSION(DRV_VERSION);
10543 MODULE_DESCRIPTION("Ralink RT2800 library");
10544 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/wireless/ralink/rt2x00/rt2800lib.c

DEFINITIONS
