root/drivers/net/wireless/ti/wl1251/acx.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * This file is part of wl1251
   4  *
   5  * Copyright (c) 1998-2007 Texas Instruments Incorporated
   6  * Copyright (C) 2008 Nokia Corporation
   7  */
   8 
   9 #ifndef __WL1251_ACX_H__
  10 #define __WL1251_ACX_H__
  11 
  12 #include "wl1251.h"
  13 #include "cmd.h"
  14 
  15 /* Target's information element */
  16 struct acx_header {
  17         struct wl1251_cmd_header cmd;
  18 
  19         /* acx (or information element) header */
  20         u16 id;
  21 
  22         /* payload length (not including headers */
  23         u16 len;
  24 } __packed;
  25 
  26 struct acx_error_counter {
  27         struct acx_header header;
  28 
  29         /* The number of PLCP errors since the last time this */
  30         /* information element was interrogated. This field is */
  31         /* automatically cleared when it is interrogated.*/
  32         u32 PLCP_error;
  33 
  34         /* The number of FCS errors since the last time this */
  35         /* information element was interrogated. This field is */
  36         /* automatically cleared when it is interrogated.*/
  37         u32 FCS_error;
  38 
  39         /* The number of MPDUs without PLCP header errors received*/
  40         /* since the last time this information element was interrogated. */
  41         /* This field is automatically cleared when it is interrogated.*/
  42         u32 valid_frame;
  43 
  44         /* the number of missed sequence numbers in the squentially */
  45         /* values of frames seq numbers */
  46         u32 seq_num_miss;
  47 } __packed;
  48 
  49 struct acx_revision {
  50         struct acx_header header;
  51 
  52         /*
  53          * The WiLink firmware version, an ASCII string x.x.x.x,
  54          * that uniquely identifies the current firmware.
  55          * The left most digit is incremented each time a
  56          * significant change is made to the firmware, such as
  57          * code redesign or new platform support.
  58          * The second digit is incremented when major enhancements
  59          * are added or major fixes are made.
  60          * The third digit is incremented for each GA release.
  61          * The fourth digit is incremented for each build.
  62          * The first two digits identify a firmware release version,
  63          * in other words, a unique set of features.
  64          * The first three digits identify a GA release.
  65          */
  66         char fw_version[20];
  67 
  68         /*
  69          * This 4 byte field specifies the WiLink hardware version.
  70          * bits 0  - 15: Reserved.
  71          * bits 16 - 23: Version ID - The WiLink version ID
  72          *              (1 = first spin, 2 = second spin, and so on).
  73          * bits 24 - 31: Chip ID - The WiLink chip ID.
  74          */
  75         u32 hw_version;
  76 } __packed;
  77 
  78 enum wl1251_psm_mode {
  79         /* Active mode */
  80         WL1251_PSM_CAM = 0,
  81 
  82         /* Power save mode */
  83         WL1251_PSM_PS = 1,
  84 
  85         /* Extreme low power */
  86         WL1251_PSM_ELP = 2,
  87 };
  88 
  89 struct acx_sleep_auth {
  90         struct acx_header header;
  91 
  92         /* The sleep level authorization of the device. */
  93         /* 0 - Always active*/
  94         /* 1 - Power down mode: light / fast sleep*/
  95         /* 2 - ELP mode: Deep / Max sleep*/
  96         u8  sleep_auth;
  97         u8  padding[3];
  98 } __packed;
  99 
 100 enum {
 101         HOSTIF_PCI_MASTER_HOST_INDIRECT,
 102         HOSTIF_PCI_MASTER_HOST_DIRECT,
 103         HOSTIF_SLAVE,
 104         HOSTIF_PKT_RING,
 105         HOSTIF_DONTCARE = 0xFF
 106 };
 107 
 108 #define DEFAULT_UCAST_PRIORITY          0
 109 #define DEFAULT_RX_Q_PRIORITY           0
 110 #define DEFAULT_NUM_STATIONS            1
 111 #define DEFAULT_RXQ_PRIORITY            0 /* low 0 .. 15 high  */
 112 #define DEFAULT_RXQ_TYPE                0x07    /* All frames, Data/Ctrl/Mgmt */
 113 #define TRACE_BUFFER_MAX_SIZE           256
 114 
 115 #define  DP_RX_PACKET_RING_CHUNK_SIZE 1600
 116 #define  DP_TX_PACKET_RING_CHUNK_SIZE 1600
 117 #define  DP_RX_PACKET_RING_CHUNK_NUM 2
 118 #define  DP_TX_PACKET_RING_CHUNK_NUM 2
 119 #define  DP_TX_COMPLETE_TIME_OUT 20
 120 #define  FW_TX_CMPLT_BLOCK_SIZE 16
 121 
 122 struct acx_data_path_params {
 123         struct acx_header header;
 124 
 125         u16 rx_packet_ring_chunk_size;
 126         u16 tx_packet_ring_chunk_size;
 127 
 128         u8 rx_packet_ring_chunk_num;
 129         u8 tx_packet_ring_chunk_num;
 130 
 131         /*
 132          * Maximum number of packets that can be gathered
 133          * in the TX complete ring before an interrupt
 134          * is generated.
 135          */
 136         u8 tx_complete_threshold;
 137 
 138         /* Number of pending TX complete entries in cyclic ring.*/
 139         u8 tx_complete_ring_depth;
 140 
 141         /*
 142          * Max num microseconds since a packet enters the TX
 143          * complete ring until an interrupt is generated.
 144          */
 145         u32 tx_complete_timeout;
 146 } __packed;
 147 
 148 
 149 struct acx_data_path_params_resp {
 150         struct acx_header header;
 151 
 152         u16 rx_packet_ring_chunk_size;
 153         u16 tx_packet_ring_chunk_size;
 154 
 155         u8 rx_packet_ring_chunk_num;
 156         u8 tx_packet_ring_chunk_num;
 157 
 158         u8 pad[2];
 159 
 160         u32 rx_packet_ring_addr;
 161         u32 tx_packet_ring_addr;
 162 
 163         u32 rx_control_addr;
 164         u32 tx_control_addr;
 165 
 166         u32 tx_complete_addr;
 167 } __packed;
 168 
 169 #define TX_MSDU_LIFETIME_MIN       0
 170 #define TX_MSDU_LIFETIME_MAX       3000
 171 #define TX_MSDU_LIFETIME_DEF       512
 172 #define RX_MSDU_LIFETIME_MIN       0
 173 #define RX_MSDU_LIFETIME_MAX       0xFFFFFFFF
 174 #define RX_MSDU_LIFETIME_DEF       512000
 175 
 176 struct acx_rx_msdu_lifetime {
 177         struct acx_header header;
 178 
 179         /*
 180          * The maximum amount of time, in TU, before the
 181          * firmware discards the MSDU.
 182          */
 183         u32 lifetime;
 184 } __packed;
 185 
 186 /*
 187  * RX Config Options Table
 188  * Bit          Definition
 189  * ===          ==========
 190  * 31:14                Reserved
 191  * 13           Copy RX Status - when set, write three receive status words
 192  *              to top of rx'd MPDUs.
 193  *              When cleared, do not write three status words (added rev 1.5)
 194  * 12           Reserved
 195  * 11           RX Complete upon FCS error - when set, give rx complete
 196  *              interrupt for FCS errors, after the rx filtering, e.g. unicast
 197  *              frames not to us with FCS error will not generate an interrupt.
 198  * 10           SSID Filter Enable - When set, the WiLink discards all beacon,
 199  *              probe request, and probe response frames with an SSID that does
 200  *              not match the SSID specified by the host in the START/JOIN
 201  *              command.
 202  *              When clear, the WiLink receives frames with any SSID.
 203  * 9            Broadcast Filter Enable - When set, the WiLink discards all
 204  *              broadcast frames. When clear, the WiLink receives all received
 205  *              broadcast frames.
 206  * 8:6          Reserved
 207  * 5            BSSID Filter Enable - When set, the WiLink discards any frames
 208  *              with a BSSID that does not match the BSSID specified by the
 209  *              host.
 210  *              When clear, the WiLink receives frames from any BSSID.
 211  * 4            MAC Addr Filter - When set, the WiLink discards any frames
 212  *              with a destination address that does not match the MAC address
 213  *              of the adaptor.
 214  *              When clear, the WiLink receives frames destined to any MAC
 215  *              address.
 216  * 3            Promiscuous - When set, the WiLink receives all valid frames
 217  *              (i.e., all frames that pass the FCS check).
 218  *              When clear, only frames that pass the other filters specified
 219  *              are received.
 220  * 2            FCS - When set, the WiLink includes the FCS with the received
 221  *              frame.
 222  *              When cleared, the FCS is discarded.
 223  * 1            PLCP header - When set, write all data from baseband to frame
 224  *              buffer including PHY header.
 225  * 0            Reserved - Always equal to 0.
 226  *
 227  * RX Filter Options Table
 228  * Bit          Definition
 229  * ===          ==========
 230  * 31:12                Reserved - Always equal to 0.
 231  * 11           Association - When set, the WiLink receives all association
 232  *              related frames (association request/response, reassocation
 233  *              request/response, and disassociation). When clear, these frames
 234  *              are discarded.
 235  * 10           Auth/De auth - When set, the WiLink receives all authentication
 236  *              and de-authentication frames. When clear, these frames are
 237  *              discarded.
 238  * 9            Beacon - When set, the WiLink receives all beacon frames.
 239  *              When clear, these frames are discarded.
 240  * 8            Contention Free - When set, the WiLink receives all contention
 241  *              free frames.
 242  *              When clear, these frames are discarded.
 243  * 7            Control - When set, the WiLink receives all control frames.
 244  *              When clear, these frames are discarded.
 245  * 6            Data - When set, the WiLink receives all data frames.
 246  *              When clear, these frames are discarded.
 247  * 5            FCS Error - When set, the WiLink receives frames that have FCS
 248  *              errors.
 249  *              When clear, these frames are discarded.
 250  * 4            Management - When set, the WiLink receives all management
 251  *              frames.
 252  *              When clear, these frames are discarded.
 253  * 3            Probe Request - When set, the WiLink receives all probe request
 254  *              frames.
 255  *              When clear, these frames are discarded.
 256  * 2            Probe Response - When set, the WiLink receives all probe
 257  *              response frames.
 258  *              When clear, these frames are discarded.
 259  * 1            RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK
 260  *              frames.
 261  *              When clear, these frames are discarded.
 262  * 0            Rsvd Type/Sub Type - When set, the WiLink receives all frames
 263  *              that have reserved frame types and sub types as defined by the
 264  *              802.11 specification.
 265  *              When clear, these frames are discarded.
 266  */
 267 struct acx_rx_config {
 268         struct acx_header header;
 269 
 270         u32 config_options;
 271         u32 filter_options;
 272 } __packed;
 273 
 274 enum {
 275         QOS_AC_BE = 0,
 276         QOS_AC_BK,
 277         QOS_AC_VI,
 278         QOS_AC_VO,
 279         QOS_HIGHEST_AC_INDEX = QOS_AC_VO,
 280 };
 281 
 282 #define MAX_NUM_OF_AC             (QOS_HIGHEST_AC_INDEX+1)
 283 #define FIRST_AC_INDEX            QOS_AC_BE
 284 #define MAX_NUM_OF_802_1d_TAGS    8
 285 #define AC_PARAMS_MAX_TSID        15
 286 #define MAX_APSD_CONF             0xffff
 287 
 288 #define  QOS_TX_HIGH_MIN      (0)
 289 #define  QOS_TX_HIGH_MAX      (100)
 290 
 291 #define  QOS_TX_HIGH_BK_DEF   (25)
 292 #define  QOS_TX_HIGH_BE_DEF   (35)
 293 #define  QOS_TX_HIGH_VI_DEF   (35)
 294 #define  QOS_TX_HIGH_VO_DEF   (35)
 295 
 296 #define  QOS_TX_LOW_BK_DEF    (15)
 297 #define  QOS_TX_LOW_BE_DEF    (25)
 298 #define  QOS_TX_LOW_VI_DEF    (25)
 299 #define  QOS_TX_LOW_VO_DEF    (25)
 300 
 301 struct acx_tx_queue_qos_config {
 302         struct acx_header header;
 303 
 304         u8 qid;
 305         u8 pad[3];
 306 
 307         /* Max number of blocks allowd in the queue */
 308         u16 high_threshold;
 309 
 310         /* Lowest memory blocks guaranteed for this queue */
 311         u16 low_threshold;
 312 } __packed;
 313 
 314 struct acx_packet_detection {
 315         struct acx_header header;
 316 
 317         u32 threshold;
 318 } __packed;
 319 
 320 
 321 enum acx_slot_type {
 322         SLOT_TIME_LONG = 0,
 323         SLOT_TIME_SHORT = 1,
 324         DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
 325         MAX_SLOT_TIMES = 0xFF
 326 };
 327 
 328 #define STATION_WONE_INDEX 0
 329 
 330 struct acx_slot {
 331         struct acx_header header;
 332 
 333         u8 wone_index; /* Reserved */
 334         u8 slot_time;
 335         u8 reserved[6];
 336 } __packed;
 337 
 338 
 339 #define ACX_MC_ADDRESS_GROUP_MAX        (8)
 340 #define ACX_MC_ADDRESS_GROUP_MAX_LEN    (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
 341 
 342 struct acx_dot11_grp_addr_tbl {
 343         struct acx_header header;
 344 
 345         u8 enabled;
 346         u8 num_groups;
 347         u8 pad[2];
 348         u8 mac_table[ACX_MC_ADDRESS_GROUP_MAX_LEN];
 349 } __packed;
 350 
 351 
 352 #define  RX_TIMEOUT_PS_POLL_MIN    0
 353 #define  RX_TIMEOUT_PS_POLL_MAX    (200000)
 354 #define  RX_TIMEOUT_PS_POLL_DEF    (15)
 355 #define  RX_TIMEOUT_UPSD_MIN       0
 356 #define  RX_TIMEOUT_UPSD_MAX       (200000)
 357 #define  RX_TIMEOUT_UPSD_DEF       (15)
 358 
 359 struct acx_rx_timeout {
 360         struct acx_header header;
 361 
 362         /*
 363          * The longest time the STA will wait to receive
 364          * traffic from the AP after a PS-poll has been
 365          * transmitted.
 366          */
 367         u16 ps_poll_timeout;
 368 
 369         /*
 370          * The longest time the STA will wait to receive
 371          * traffic from the AP after a frame has been sent
 372          * from an UPSD enabled queue.
 373          */
 374         u16 upsd_timeout;
 375 } __packed;
 376 
 377 #define RTS_THRESHOLD_MIN              0
 378 #define RTS_THRESHOLD_MAX              4096
 379 #define RTS_THRESHOLD_DEF              2347
 380 
 381 struct acx_rts_threshold {
 382         struct acx_header header;
 383 
 384         u16 threshold;
 385         u8 pad[2];
 386 } __packed;
 387 
 388 enum wl1251_acx_low_rssi_type {
 389         /*
 390          * The event is a "Level" indication which keeps triggering
 391          * as long as the average RSSI is below the threshold.
 392          */
 393         WL1251_ACX_LOW_RSSI_TYPE_LEVEL = 0,
 394 
 395         /*
 396          * The event is an "Edge" indication which triggers
 397          * only when the RSSI threshold is crossed from above.
 398          */
 399         WL1251_ACX_LOW_RSSI_TYPE_EDGE = 1,
 400 };
 401 
 402 struct acx_low_rssi {
 403         struct acx_header header;
 404 
 405         /*
 406          * The threshold (in dBm) below (or above after low rssi
 407          * indication) which the firmware generates an interrupt to the
 408          * host. This parameter is signed.
 409          */
 410         s8 threshold;
 411 
 412         /*
 413          * The weight of the current RSSI sample, before adding the new
 414          * sample, that is used to calculate the average RSSI.
 415          */
 416         u8 weight;
 417 
 418         /*
 419          * The number of Beacons/Probe response frames that will be
 420          * received before issuing the Low or Regained RSSI event.
 421          */
 422         u8 depth;
 423 
 424         /*
 425          * Configures how the Low RSSI Event is triggered. Refer to
 426          * enum wl1251_acx_low_rssi_type for more.
 427          */
 428         u8 type;
 429 } __packed;
 430 
 431 struct acx_beacon_filter_option {
 432         struct acx_header header;
 433 
 434         u8 enable;
 435 
 436         /*
 437          * The number of beacons without the unicast TIM
 438          * bit set that the firmware buffers before
 439          * signaling the host about ready frames.
 440          * When set to 0 and the filter is enabled, beacons
 441          * without the unicast TIM bit set are dropped.
 442          */
 443         u8 max_num_beacons;
 444         u8 pad[2];
 445 } __packed;
 446 
 447 /*
 448  * ACXBeaconFilterEntry (not 221)
 449  * Byte Offset     Size (Bytes)    Definition
 450  * ===========     ============    ==========
 451  * 0                            1               IE identifier
 452  * 1               1               Treatment bit mask
 453  *
 454  * ACXBeaconFilterEntry (221)
 455  * Byte Offset     Size (Bytes)    Definition
 456  * ===========     ============    ==========
 457  * 0               1               IE identifier
 458  * 1               1               Treatment bit mask
 459  * 2               3               OUI
 460  * 5               1               Type
 461  * 6               2               Version
 462  *
 463  *
 464  * Treatment bit mask - The information element handling:
 465  * bit 0 - The information element is compared and transferred
 466  * in case of change.
 467  * bit 1 - The information element is transferred to the host
 468  * with each appearance or disappearance.
 469  * Note that both bits can be set at the same time.
 470  */
 471 #define BEACON_FILTER_TABLE_MAX_IE_NUM                 (32)
 472 #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
 473 #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE              (2)
 474 #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
 475 #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
 476                             BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
 477                            (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
 478                             BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
 479 
 480 #define BEACON_RULE_PASS_ON_CHANGE                     BIT(0)
 481 #define BEACON_RULE_PASS_ON_APPEARANCE                 BIT(1)
 482 
 483 #define BEACON_FILTER_IE_ID_CHANNEL_SWITCH_ANN         (37)
 484 
 485 struct acx_beacon_filter_ie_table {
 486         struct acx_header header;
 487 
 488         u8 num_ie;
 489         u8 pad[3];
 490         u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
 491 } __packed;
 492 
 493 #define SYNCH_FAIL_DEFAULT_THRESHOLD    10     /* number of beacons */
 494 #define NO_BEACON_DEFAULT_TIMEOUT       (500) /* in microseconds */
 495 
 496 struct acx_conn_monit_params {
 497         struct acx_header header;
 498 
 499         u32 synch_fail_thold; /* number of beacons missed */
 500         u32 bss_lose_timeout; /* number of TU's from synch fail */
 501 } __packed;
 502 
 503 enum {
 504         SG_ENABLE = 0,
 505         SG_DISABLE,
 506         SG_SENSE_NO_ACTIVITY,
 507         SG_SENSE_ACTIVE
 508 };
 509 
 510 struct acx_bt_wlan_coex {
 511         struct acx_header header;
 512 
 513         /*
 514          * 0 -> PTA enabled
 515          * 1 -> PTA disabled
 516          * 2 -> sense no active mode, i.e.
 517          *      an interrupt is sent upon
 518          *      BT activity.
 519          * 3 -> PTA is switched on in response
 520          *      to the interrupt sending.
 521          */
 522         u8 enable;
 523         u8 pad[3];
 524 } __packed;
 525 
 526 #define PTA_ANTENNA_TYPE_DEF              (0)
 527 #define PTA_BT_HP_MAXTIME_DEF             (2000)
 528 #define PTA_WLAN_HP_MAX_TIME_DEF          (5000)
 529 #define PTA_SENSE_DISABLE_TIMER_DEF       (1350)
 530 #define PTA_PROTECTIVE_RX_TIME_DEF        (1500)
 531 #define PTA_PROTECTIVE_TX_TIME_DEF        (1500)
 532 #define PTA_TIMEOUT_NEXT_BT_LP_PACKET_DEF (3000)
 533 #define PTA_SIGNALING_TYPE_DEF            (1)
 534 #define PTA_AFH_LEVERAGE_ON_DEF           (0)
 535 #define PTA_NUMBER_QUIET_CYCLE_DEF        (0)
 536 #define PTA_MAX_NUM_CTS_DEF               (3)
 537 #define PTA_NUMBER_OF_WLAN_PACKETS_DEF    (2)
 538 #define PTA_NUMBER_OF_BT_PACKETS_DEF      (2)
 539 #define PTA_PROTECTIVE_RX_TIME_FAST_DEF   (1500)
 540 #define PTA_PROTECTIVE_TX_TIME_FAST_DEF   (3000)
 541 #define PTA_CYCLE_TIME_FAST_DEF           (8700)
 542 #define PTA_RX_FOR_AVALANCHE_DEF          (5)
 543 #define PTA_ELP_HP_DEF                    (0)
 544 #define PTA_ANTI_STARVE_PERIOD_DEF        (500)
 545 #define PTA_ANTI_STARVE_NUM_CYCLE_DEF     (4)
 546 #define PTA_ALLOW_PA_SD_DEF               (1)
 547 #define PTA_TIME_BEFORE_BEACON_DEF        (6300)
 548 #define PTA_HPDM_MAX_TIME_DEF             (1600)
 549 #define PTA_TIME_OUT_NEXT_WLAN_DEF        (2550)
 550 #define PTA_AUTO_MODE_NO_CTS_DEF          (0)
 551 #define PTA_BT_HP_RESPECTED_DEF           (3)
 552 #define PTA_WLAN_RX_MIN_RATE_DEF          (24)
 553 #define PTA_ACK_MODE_DEF                  (1)
 554 
 555 struct acx_bt_wlan_coex_param {
 556         struct acx_header header;
 557 
 558         /*
 559          * The minimum rate of a received WLAN packet in the STA,
 560          * during protective mode, of which a new BT-HP request
 561          * during this Rx will always be respected and gain the antenna.
 562          */
 563         u32 min_rate;
 564 
 565         /* Max time the BT HP will be respected. */
 566         u16 bt_hp_max_time;
 567 
 568         /* Max time the WLAN HP will be respected. */
 569         u16 wlan_hp_max_time;
 570 
 571         /*
 572          * The time between the last BT activity
 573          * and the moment when the sense mode returns
 574          * to SENSE_INACTIVE.
 575          */
 576         u16 sense_disable_timer;
 577 
 578         /* Time before the next BT HP instance */
 579         u16 rx_time_bt_hp;
 580         u16 tx_time_bt_hp;
 581 
 582         /* range: 10-20000    default: 1500 */
 583         u16 rx_time_bt_hp_fast;
 584         u16 tx_time_bt_hp_fast;
 585 
 586         /* range: 2000-65535  default: 8700 */
 587         u16 wlan_cycle_fast;
 588 
 589         /* range: 0 - 15000 (Msec) default: 1000 */
 590         u16 bt_anti_starvation_period;
 591 
 592         /* range 400-10000(Usec) default: 3000 */
 593         u16 next_bt_lp_packet;
 594 
 595         /* Deafult: worst case for BT DH5 traffic */
 596         u16 wake_up_beacon;
 597 
 598         /* range: 0-50000(Usec) default: 1050 */
 599         u16 hp_dm_max_guard_time;
 600 
 601         /*
 602          * This is to prevent both BT & WLAN antenna
 603          * starvation.
 604          * Range: 100-50000(Usec) default:2550
 605          */
 606         u16 next_wlan_packet;
 607 
 608         /* 0 -> shared antenna */
 609         u8 antenna_type;
 610 
 611         /*
 612          * 0 -> TI legacy
 613          * 1 -> Palau
 614          */
 615         u8 signal_type;
 616 
 617         /*
 618          * BT AFH status
 619          * 0 -> no AFH
 620          * 1 -> from dedicated GPIO
 621          * 2 -> AFH on (from host)
 622          */
 623         u8 afh_leverage_on;
 624 
 625         /*
 626          * The number of cycles during which no
 627          * TX will be sent after 1 cycle of RX
 628          * transaction in protective mode
 629          */
 630         u8 quiet_cycle_num;
 631 
 632         /*
 633          * The maximum number of CTSs that will
 634          * be sent for receiving RX packet in
 635          * protective mode
 636          */
 637         u8 max_cts;
 638 
 639         /*
 640          * The number of WLAN packets
 641          * transferred in common mode before
 642          * switching to BT.
 643          */
 644         u8 wlan_packets_num;
 645 
 646         /*
 647          * The number of BT packets
 648          * transferred in common mode before
 649          * switching to WLAN.
 650          */
 651         u8 bt_packets_num;
 652 
 653         /* range: 1-255  default: 5 */
 654         u8 missed_rx_avalanche;
 655 
 656         /* range: 0-1    default: 1 */
 657         u8 wlan_elp_hp;
 658 
 659         /* range: 0 - 15  default: 4 */
 660         u8 bt_anti_starvation_cycles;
 661 
 662         u8 ack_mode_dual_ant;
 663 
 664         /*
 665          * Allow PA_SD assertion/de-assertion
 666          * during enabled BT activity.
 667          */
 668         u8 pa_sd_enable;
 669 
 670         /*
 671          * Enable/Disable PTA in auto mode:
 672          * Support Both Active & P.S modes
 673          */
 674         u8 pta_auto_mode_enable;
 675 
 676         /* range: 0 - 20  default: 1 */
 677         u8 bt_hp_respected_num;
 678 } __packed;
 679 
 680 #define CCA_THRSH_ENABLE_ENERGY_D       0x140A
 681 #define CCA_THRSH_DISABLE_ENERGY_D      0xFFEF
 682 
 683 struct acx_energy_detection {
 684         struct acx_header header;
 685 
 686         /* The RX Clear Channel Assessment threshold in the PHY */
 687         u16 rx_cca_threshold;
 688         u8 tx_energy_detection;
 689         u8 pad;
 690 } __packed;
 691 
 692 #define BCN_RX_TIMEOUT_DEF_VALUE        10000
 693 #define BROADCAST_RX_TIMEOUT_DEF_VALUE  20000
 694 #define RX_BROADCAST_IN_PS_DEF_VALUE    1
 695 #define CONSECUTIVE_PS_POLL_FAILURE_DEF 4
 696 
 697 struct acx_beacon_broadcast {
 698         struct acx_header header;
 699 
 700         u16 beacon_rx_timeout;
 701         u16 broadcast_timeout;
 702 
 703         /* Enables receiving of broadcast packets in PS mode */
 704         u8 rx_broadcast_in_ps;
 705 
 706         /* Consecutive PS Poll failures before updating the host */
 707         u8 ps_poll_threshold;
 708         u8 pad[2];
 709 } __packed;
 710 
 711 struct acx_event_mask {
 712         struct acx_header header;
 713 
 714         u32 event_mask;
 715         u32 high_event_mask; /* Unused */
 716 } __packed;
 717 
 718 #define CFG_RX_FCS              BIT(2)
 719 #define CFG_RX_ALL_GOOD         BIT(3)
 720 #define CFG_UNI_FILTER_EN       BIT(4)
 721 #define CFG_BSSID_FILTER_EN     BIT(5)
 722 #define CFG_MC_FILTER_EN        BIT(6)
 723 #define CFG_MC_ADDR0_EN         BIT(7)
 724 #define CFG_MC_ADDR1_EN         BIT(8)
 725 #define CFG_BC_REJECT_EN        BIT(9)
 726 #define CFG_SSID_FILTER_EN      BIT(10)
 727 #define CFG_RX_INT_FCS_ERROR    BIT(11)
 728 #define CFG_RX_INT_ENCRYPTED    BIT(12)
 729 #define CFG_RX_WR_RX_STATUS     BIT(13)
 730 #define CFG_RX_FILTER_NULTI     BIT(14)
 731 #define CFG_RX_RESERVE          BIT(15)
 732 #define CFG_RX_TIMESTAMP_TSF    BIT(16)
 733 
 734 #define CFG_RX_RSV_EN           BIT(0)
 735 #define CFG_RX_RCTS_ACK         BIT(1)
 736 #define CFG_RX_PRSP_EN          BIT(2)
 737 #define CFG_RX_PREQ_EN          BIT(3)
 738 #define CFG_RX_MGMT_EN          BIT(4)
 739 #define CFG_RX_FCS_ERROR        BIT(5)
 740 #define CFG_RX_DATA_EN          BIT(6)
 741 #define CFG_RX_CTL_EN           BIT(7)
 742 #define CFG_RX_CF_EN            BIT(8)
 743 #define CFG_RX_BCN_EN           BIT(9)
 744 #define CFG_RX_AUTH_EN          BIT(10)
 745 #define CFG_RX_ASSOC_EN         BIT(11)
 746 
 747 #define SCAN_PASSIVE            BIT(0)
 748 #define SCAN_5GHZ_BAND          BIT(1)
 749 #define SCAN_TRIGGERED          BIT(2)
 750 #define SCAN_PRIORITY_HIGH      BIT(3)
 751 
 752 struct acx_fw_gen_frame_rates {
 753         struct acx_header header;
 754 
 755         u8 tx_ctrl_frame_rate; /* RATE_* */
 756         u8 tx_ctrl_frame_mod; /* CCK_* or PBCC_* */
 757         u8 tx_mgt_frame_rate;
 758         u8 tx_mgt_frame_mod;
 759 } __packed;
 760 
 761 /* STA MAC */
 762 struct acx_dot11_station_id {
 763         struct acx_header header;
 764 
 765         u8 mac[ETH_ALEN];
 766         u8 pad[2];
 767 } __packed;
 768 
 769 struct acx_feature_config {
 770         struct acx_header header;
 771 
 772         u32 options;
 773         u32 data_flow_options;
 774 } __packed;
 775 
 776 struct acx_current_tx_power {
 777         struct acx_header header;
 778 
 779         u8  current_tx_power;
 780         u8  padding[3];
 781 } __packed;
 782 
 783 struct acx_dot11_default_key {
 784         struct acx_header header;
 785 
 786         u8 id;
 787         u8 pad[3];
 788 } __packed;
 789 
 790 struct acx_tsf_info {
 791         struct acx_header header;
 792 
 793         u32 current_tsf_msb;
 794         u32 current_tsf_lsb;
 795         u32 last_TBTT_msb;
 796         u32 last_TBTT_lsb;
 797         u8 last_dtim_count;
 798         u8 pad[3];
 799 } __packed;
 800 
 801 enum acx_wake_up_event {
 802         WAKE_UP_EVENT_BEACON_BITMAP     = 0x01, /* Wake on every Beacon*/
 803         WAKE_UP_EVENT_DTIM_BITMAP       = 0x02, /* Wake on every DTIM*/
 804         WAKE_UP_EVENT_N_DTIM_BITMAP     = 0x04, /* Wake on every Nth DTIM */
 805         WAKE_UP_EVENT_N_BEACONS_BITMAP  = 0x08, /* Wake on every Nth Beacon */
 806         WAKE_UP_EVENT_BITS_MASK         = 0x0F
 807 };
 808 
 809 struct acx_wake_up_condition {
 810         struct acx_header header;
 811 
 812         u8 wake_up_event; /* Only one bit can be set */
 813         u8 listen_interval;
 814         u8 pad[2];
 815 } __packed;
 816 
 817 struct acx_aid {
 818         struct acx_header header;
 819 
 820         /*
 821          * To be set when associated with an AP.
 822          */
 823         u16 aid;
 824         u8 pad[2];
 825 } __packed;
 826 
 827 enum acx_preamble_type {
 828         ACX_PREAMBLE_LONG = 0,
 829         ACX_PREAMBLE_SHORT = 1
 830 };
 831 
 832 struct acx_preamble {
 833         struct acx_header header;
 834 
 835         /*
 836          * When set, the WiLink transmits the frames with a short preamble and
 837          * when cleared, the WiLink transmits the frames with a long preamble.
 838          */
 839         u8 preamble;
 840         u8 padding[3];
 841 } __packed;
 842 
 843 enum acx_ctsprotect_type {
 844         CTSPROTECT_DISABLE = 0,
 845         CTSPROTECT_ENABLE = 1
 846 };
 847 
 848 struct acx_ctsprotect {
 849         struct acx_header header;
 850         u8 ctsprotect;
 851         u8 padding[3];
 852 } __packed;
 853 
 854 struct acx_tx_statistics {
 855         u32 internal_desc_overflow;
 856 }  __packed;
 857 
 858 struct acx_rx_statistics {
 859         u32 out_of_mem;
 860         u32 hdr_overflow;
 861         u32 hw_stuck;
 862         u32 dropped;
 863         u32 fcs_err;
 864         u32 xfr_hint_trig;
 865         u32 path_reset;
 866         u32 reset_counter;
 867 } __packed;
 868 
 869 struct acx_dma_statistics {
 870         u32 rx_requested;
 871         u32 rx_errors;
 872         u32 tx_requested;
 873         u32 tx_errors;
 874 }  __packed;
 875 
 876 struct acx_isr_statistics {
 877         /* host command complete */
 878         u32 cmd_cmplt;
 879 
 880         /* fiqisr() */
 881         u32 fiqs;
 882 
 883         /* (INT_STS_ND & INT_TRIG_RX_HEADER) */
 884         u32 rx_headers;
 885 
 886         /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
 887         u32 rx_completes;
 888 
 889         /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
 890         u32 rx_mem_overflow;
 891 
 892         /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
 893         u32 rx_rdys;
 894 
 895         /* irqisr() */
 896         u32 irqs;
 897 
 898         /* (INT_STS_ND & INT_TRIG_TX_PROC) */
 899         u32 tx_procs;
 900 
 901         /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
 902         u32 decrypt_done;
 903 
 904         /* (INT_STS_ND & INT_TRIG_DMA0) */
 905         u32 dma0_done;
 906 
 907         /* (INT_STS_ND & INT_TRIG_DMA1) */
 908         u32 dma1_done;
 909 
 910         /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
 911         u32 tx_exch_complete;
 912 
 913         /* (INT_STS_ND & INT_TRIG_COMMAND) */
 914         u32 commands;
 915 
 916         /* (INT_STS_ND & INT_TRIG_RX_PROC) */
 917         u32 rx_procs;
 918 
 919         /* (INT_STS_ND & INT_TRIG_PM_802) */
 920         u32 hw_pm_mode_changes;
 921 
 922         /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
 923         u32 host_acknowledges;
 924 
 925         /* (INT_STS_ND & INT_TRIG_PM_PCI) */
 926         u32 pci_pm;
 927 
 928         /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
 929         u32 wakeups;
 930 
 931         /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
 932         u32 low_rssi;
 933 } __packed;
 934 
 935 struct acx_wep_statistics {
 936         /* WEP address keys configured */
 937         u32 addr_key_count;
 938 
 939         /* default keys configured */
 940         u32 default_key_count;
 941 
 942         u32 reserved;
 943 
 944         /* number of times that WEP key not found on lookup */
 945         u32 key_not_found;
 946 
 947         /* number of times that WEP key decryption failed */
 948         u32 decrypt_fail;
 949 
 950         /* WEP packets decrypted */
 951         u32 packets;
 952 
 953         /* WEP decrypt interrupts */
 954         u32 interrupt;
 955 } __packed;
 956 
 957 #define ACX_MISSED_BEACONS_SPREAD 10
 958 
 959 struct acx_pwr_statistics {
 960         /* the amount of enters into power save mode (both PD & ELP) */
 961         u32 ps_enter;
 962 
 963         /* the amount of enters into ELP mode */
 964         u32 elp_enter;
 965 
 966         /* the amount of missing beacon interrupts to the host */
 967         u32 missing_bcns;
 968 
 969         /* the amount of wake on host-access times */
 970         u32 wake_on_host;
 971 
 972         /* the amount of wake on timer-expire */
 973         u32 wake_on_timer_exp;
 974 
 975         /* the number of packets that were transmitted with PS bit set */
 976         u32 tx_with_ps;
 977 
 978         /* the number of packets that were transmitted with PS bit clear */
 979         u32 tx_without_ps;
 980 
 981         /* the number of received beacons */
 982         u32 rcvd_beacons;
 983 
 984         /* the number of entering into PowerOn (power save off) */
 985         u32 power_save_off;
 986 
 987         /* the number of entries into power save mode */
 988         u16 enable_ps;
 989 
 990         /*
 991          * the number of exits from power save, not including failed PS
 992          * transitions
 993          */
 994         u16 disable_ps;
 995 
 996         /*
 997          * the number of times the TSF counter was adjusted because
 998          * of drift
 999          */
1000         u32 fix_tsf_ps;
1001 
1002         /* Gives statistics about the spread continuous missed beacons.
1003          * The 16 LSB are dedicated for the PS mode.
1004          * The 16 MSB are dedicated for the PS mode.
1005          * cont_miss_bcns_spread[0] - single missed beacon.
1006          * cont_miss_bcns_spread[1] - two continuous missed beacons.
1007          * cont_miss_bcns_spread[2] - three continuous missed beacons.
1008          * ...
1009          * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
1010         */
1011         u32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
1012 
1013         /* the number of beacons in awake mode */
1014         u32 rcvd_awake_beacons;
1015 } __packed;
1016 
1017 struct acx_mic_statistics {
1018         u32 rx_pkts;
1019         u32 calc_failure;
1020 } __packed;
1021 
1022 struct acx_aes_statistics {
1023         u32 encrypt_fail;
1024         u32 decrypt_fail;
1025         u32 encrypt_packets;
1026         u32 decrypt_packets;
1027         u32 encrypt_interrupt;
1028         u32 decrypt_interrupt;
1029 } __packed;
1030 
1031 struct acx_event_statistics {
1032         u32 heart_beat;
1033         u32 calibration;
1034         u32 rx_mismatch;
1035         u32 rx_mem_empty;
1036         u32 rx_pool;
1037         u32 oom_late;
1038         u32 phy_transmit_error;
1039         u32 tx_stuck;
1040 } __packed;
1041 
1042 struct acx_ps_statistics {
1043         u32 pspoll_timeouts;
1044         u32 upsd_timeouts;
1045         u32 upsd_max_sptime;
1046         u32 upsd_max_apturn;
1047         u32 pspoll_max_apturn;
1048         u32 pspoll_utilization;
1049         u32 upsd_utilization;
1050 } __packed;
1051 
1052 struct acx_rxpipe_statistics {
1053         u32 rx_prep_beacon_drop;
1054         u32 descr_host_int_trig_rx_data;
1055         u32 beacon_buffer_thres_host_int_trig_rx_data;
1056         u32 missed_beacon_host_int_trig_rx_data;
1057         u32 tx_xfr_host_int_trig_rx_data;
1058 } __packed;
1059 
1060 struct acx_statistics {
1061         struct acx_header header;
1062 
1063         struct acx_tx_statistics tx;
1064         struct acx_rx_statistics rx;
1065         struct acx_dma_statistics dma;
1066         struct acx_isr_statistics isr;
1067         struct acx_wep_statistics wep;
1068         struct acx_pwr_statistics pwr;
1069         struct acx_aes_statistics aes;
1070         struct acx_mic_statistics mic;
1071         struct acx_event_statistics event;
1072         struct acx_ps_statistics ps;
1073         struct acx_rxpipe_statistics rxpipe;
1074 } __packed;
1075 
1076 #define ACX_MAX_RATE_CLASSES       8
1077 #define ACX_RATE_MASK_UNSPECIFIED  0
1078 #define ACX_RATE_RETRY_LIMIT      10
1079 
1080 struct acx_rate_class {
1081         u32 enabled_rates;
1082         u8 short_retry_limit;
1083         u8 long_retry_limit;
1084         u8 aflags;
1085         u8 reserved;
1086 } __packed;
1087 
1088 struct acx_rate_policy {
1089         struct acx_header header;
1090 
1091         u32 rate_class_cnt;
1092         struct acx_rate_class rate_class[ACX_MAX_RATE_CLASSES];
1093 } __packed;
1094 
1095 struct wl1251_acx_memory {
1096         __le16 num_stations; /* number of STAs to be supported. */
1097         u16 reserved_1;
1098 
1099         /*
1100          * Nmber of memory buffers for the RX mem pool.
1101          * The actual number may be less if there are
1102          * not enough blocks left for the minimum num
1103          * of TX ones.
1104          */
1105         u8 rx_mem_block_num;
1106         u8 reserved_2;
1107         u8 num_tx_queues; /* From 1 to 16 */
1108         u8 host_if_options; /* HOST_IF* */
1109         u8 tx_min_mem_block_num;
1110         u8 num_ssid_profiles;
1111         __le16 debug_buffer_size;
1112 } __packed;
1113 
1114 
1115 #define ACX_RX_DESC_MIN                1
1116 #define ACX_RX_DESC_MAX                127
1117 #define ACX_RX_DESC_DEF                32
1118 struct wl1251_acx_rx_queue_config {
1119         u8 num_descs;
1120         u8 pad;
1121         u8 type;
1122         u8 priority;
1123         __le32 dma_address;
1124 } __packed;
1125 
1126 #define ACX_TX_DESC_MIN                1
1127 #define ACX_TX_DESC_MAX                127
1128 #define ACX_TX_DESC_DEF                16
1129 struct wl1251_acx_tx_queue_config {
1130     u8 num_descs;
1131     u8 pad[2];
1132     u8 attributes;
1133 } __packed;
1134 
1135 #define MAX_TX_QUEUE_CONFIGS 5
1136 #define MAX_TX_QUEUES 4
1137 struct wl1251_acx_config_memory {
1138         struct acx_header header;
1139 
1140         struct wl1251_acx_memory mem_config;
1141         struct wl1251_acx_rx_queue_config rx_queue_config;
1142         struct wl1251_acx_tx_queue_config tx_queue_config[MAX_TX_QUEUE_CONFIGS];
1143 } __packed;
1144 
1145 struct wl1251_acx_mem_map {
1146         struct acx_header header;
1147 
1148         void *code_start;
1149         void *code_end;
1150 
1151         void *wep_defkey_start;
1152         void *wep_defkey_end;
1153 
1154         void *sta_table_start;
1155         void *sta_table_end;
1156 
1157         void *packet_template_start;
1158         void *packet_template_end;
1159 
1160         void *queue_memory_start;
1161         void *queue_memory_end;
1162 
1163         void *packet_memory_pool_start;
1164         void *packet_memory_pool_end;
1165 
1166         void *debug_buffer1_start;
1167         void *debug_buffer1_end;
1168 
1169         void *debug_buffer2_start;
1170         void *debug_buffer2_end;
1171 
1172         /* Number of blocks FW allocated for TX packets */
1173         u32 num_tx_mem_blocks;
1174 
1175         /* Number of blocks FW allocated for RX packets */
1176         u32 num_rx_mem_blocks;
1177 } __packed;
1178 
1179 
1180 struct wl1251_acx_wr_tbtt_and_dtim {
1181 
1182         struct acx_header header;
1183 
1184         /* Time in TUs between two consecutive beacons */
1185         u16 tbtt;
1186 
1187         /*
1188          * DTIM period
1189          * For BSS: Number of TBTTs in a DTIM period (range: 1-10)
1190          * For IBSS: value shall be set to 1
1191         */
1192         u8  dtim;
1193         u8  padding;
1194 } __packed;
1195 
1196 enum wl1251_acx_bet_mode {
1197         WL1251_ACX_BET_DISABLE = 0,
1198         WL1251_ACX_BET_ENABLE = 1,
1199 };
1200 
1201 struct wl1251_acx_bet_enable {
1202         struct acx_header header;
1203 
1204         /*
1205          * Specifies if beacon early termination procedure is enabled or
1206          * disabled, see enum wl1251_acx_bet_mode.
1207          */
1208         u8 enable;
1209 
1210         /*
1211          * Specifies the maximum number of consecutive beacons that may be
1212          * early terminated. After this number is reached at least one full
1213          * beacon must be correctly received in FW before beacon ET
1214          * resumes. Range 0 - 255.
1215          */
1216         u8 max_consecutive;
1217 
1218         u8 padding[2];
1219 } __packed;
1220 
1221 #define ACX_IPV4_VERSION 4
1222 #define ACX_IPV6_VERSION 6
1223 #define ACX_IPV4_ADDR_SIZE 4
1224 struct wl1251_acx_arp_filter {
1225         struct acx_header header;
1226         u8 version;     /* The IP version: 4 - IPv4, 6 - IPv6.*/
1227         u8 enable;      /* 1 - ARP filtering is enabled, 0 - disabled */
1228         u8 padding[2];
1229         u8 address[16]; /* The IP address used to filter ARP packets.
1230                            ARP packets that do not match this address are
1231                            dropped. When the IP Version is 4, the last 12
1232                            bytes of the the address are ignored. */
1233 } __attribute__((packed));
1234 
1235 struct wl1251_acx_ac_cfg {
1236         struct acx_header header;
1237 
1238         /*
1239          * Access Category - The TX queue's access category
1240          * (refer to AccessCategory_enum)
1241          */
1242         u8 ac;
1243 
1244         /*
1245          * The contention window minimum size (in slots) for
1246          * the access class.
1247          */
1248         u8 cw_min;
1249 
1250         /*
1251          * The contention window maximum size (in slots) for
1252          * the access class.
1253          */
1254         u16 cw_max;
1255 
1256         /* The AIF value (in slots) for the access class. */
1257         u8 aifsn;
1258 
1259         u8 reserved;
1260 
1261         /* The TX Op Limit (in microseconds) for the access class. */
1262         u16 txop_limit;
1263 } __packed;
1264 
1265 
1266 enum wl1251_acx_channel_type {
1267         CHANNEL_TYPE_DCF        = 0,
1268         CHANNEL_TYPE_EDCF       = 1,
1269         CHANNEL_TYPE_HCCA       = 2,
1270 };
1271 
1272 enum wl1251_acx_ps_scheme {
1273         /* regular ps: simple sending of packets */
1274         WL1251_ACX_PS_SCHEME_LEGACY     = 0,
1275 
1276         /* sending a packet triggers a unscheduled apsd downstream */
1277         WL1251_ACX_PS_SCHEME_UPSD_TRIGGER       = 1,
1278 
1279         /* a pspoll packet will be sent before every data packet */
1280         WL1251_ACX_PS_SCHEME_LEGACY_PSPOLL      = 2,
1281 
1282         /* scheduled apsd mode */
1283         WL1251_ACX_PS_SCHEME_SAPSD              = 3,
1284 };
1285 
1286 enum wl1251_acx_ack_policy {
1287         WL1251_ACX_ACK_POLICY_LEGACY    = 0,
1288         WL1251_ACX_ACK_POLICY_NO_ACK    = 1,
1289         WL1251_ACX_ACK_POLICY_BLOCK     = 2,
1290 };
1291 
1292 struct wl1251_acx_tid_cfg {
1293         struct acx_header header;
1294 
1295         /* tx queue id number (0-7) */
1296         u8 queue;
1297 
1298         /* channel access type for the queue, enum wl1251_acx_channel_type */
1299         u8 type;
1300 
1301         /* EDCA: ac index (0-3), HCCA: traffic stream id (8-15) */
1302         u8 tsid;
1303 
1304         /* ps scheme of the specified queue, enum wl1251_acx_ps_scheme */
1305         u8 ps_scheme;
1306 
1307         /* the tx queue ack policy, enum wl1251_acx_ack_policy */
1308         u8 ack_policy;
1309 
1310         u8 padding[3];
1311 
1312         /* not supported */
1313         u32 apsdconf[2];
1314 } __packed;
1315 
1316 /*************************************************************************
1317 
1318     Host Interrupt Register (WiLink -> Host)
1319 
1320 **************************************************************************/
1321 
1322 /* RX packet is ready in Xfer buffer #0 */
1323 #define WL1251_ACX_INTR_RX0_DATA      BIT(0)
1324 
1325 /* TX result(s) are in the TX complete buffer */
1326 #define WL1251_ACX_INTR_TX_RESULT       BIT(1)
1327 
1328 /* OBSOLETE */
1329 #define WL1251_ACX_INTR_TX_XFR          BIT(2)
1330 
1331 /* RX packet is ready in Xfer buffer #1 */
1332 #define WL1251_ACX_INTR_RX1_DATA        BIT(3)
1333 
1334 /* Event was entered to Event MBOX #A */
1335 #define WL1251_ACX_INTR_EVENT_A         BIT(4)
1336 
1337 /* Event was entered to Event MBOX #B */
1338 #define WL1251_ACX_INTR_EVENT_B         BIT(5)
1339 
1340 /* OBSOLETE */
1341 #define WL1251_ACX_INTR_WAKE_ON_HOST    BIT(6)
1342 
1343 /* Trace message on MBOX #A */
1344 #define WL1251_ACX_INTR_TRACE_A         BIT(7)
1345 
1346 /* Trace message on MBOX #B */
1347 #define WL1251_ACX_INTR_TRACE_B         BIT(8)
1348 
1349 /* Command processing completion */
1350 #define WL1251_ACX_INTR_CMD_COMPLETE    BIT(9)
1351 
1352 /* Init sequence is done */
1353 #define WL1251_ACX_INTR_INIT_COMPLETE   BIT(14)
1354 
1355 #define WL1251_ACX_INTR_ALL           0xFFFFFFFF
1356 
1357 enum {
1358         ACX_WAKE_UP_CONDITIONS      = 0x0002,
1359         ACX_MEM_CFG                 = 0x0003,
1360         ACX_SLOT                    = 0x0004,
1361         ACX_QUEUE_HEAD              = 0x0005, /* for MASTER mode only */
1362         ACX_AC_CFG                  = 0x0007,
1363         ACX_MEM_MAP                 = 0x0008,
1364         ACX_AID                     = 0x000A,
1365         ACX_RADIO_PARAM             = 0x000B, /* Not used */
1366         ACX_CFG                     = 0x000C, /* Not used */
1367         ACX_FW_REV                  = 0x000D,
1368         ACX_MEDIUM_USAGE            = 0x000F,
1369         ACX_RX_CFG                  = 0x0010,
1370         ACX_TX_QUEUE_CFG            = 0x0011, /* FIXME: only used by wl1251 */
1371         ACX_BSS_IN_PS               = 0x0012, /* for AP only */
1372         ACX_STATISTICS              = 0x0013, /* Debug API */
1373         ACX_FEATURE_CFG             = 0x0015,
1374         ACX_MISC_CFG                = 0x0017, /* Not used */
1375         ACX_TID_CFG                 = 0x001A,
1376         ACX_BEACON_FILTER_OPT       = 0x001F,
1377         ACX_LOW_RSSI                = 0x0020,
1378         ACX_NOISE_HIST              = 0x0021,
1379         ACX_HDK_VERSION             = 0x0022, /* ??? */
1380         ACX_PD_THRESHOLD            = 0x0023,
1381         ACX_DATA_PATH_PARAMS        = 0x0024, /* WO */
1382         ACX_DATA_PATH_RESP_PARAMS   = 0x0024, /* RO */
1383         ACX_CCA_THRESHOLD           = 0x0025,
1384         ACX_EVENT_MBOX_MASK         = 0x0026,
1385 #ifdef FW_RUNNING_AS_AP
1386         ACX_DTIM_PERIOD             = 0x0027, /* for AP only */
1387 #else
1388         ACX_WR_TBTT_AND_DTIM        = 0x0027, /* STA only */
1389 #endif
1390         ACX_ACI_OPTION_CFG          = 0x0029, /* OBSOLETE (for 1251)*/
1391         ACX_GPIO_CFG                = 0x002A, /* Not used */
1392         ACX_GPIO_SET                = 0x002B, /* Not used */
1393         ACX_PM_CFG                  = 0x002C, /* To Be Documented */
1394         ACX_CONN_MONIT_PARAMS       = 0x002D,
1395         ACX_AVERAGE_RSSI            = 0x002E, /* Not used */
1396         ACX_CONS_TX_FAILURE         = 0x002F,
1397         ACX_BCN_DTIM_OPTIONS        = 0x0031,
1398         ACX_SG_ENABLE               = 0x0032,
1399         ACX_SG_CFG                  = 0x0033,
1400         ACX_ANTENNA_DIVERSITY_CFG   = 0x0035, /* To Be Documented */
1401         ACX_LOW_SNR                 = 0x0037, /* To Be Documented */
1402         ACX_BEACON_FILTER_TABLE     = 0x0038,
1403         ACX_ARP_IP_FILTER           = 0x0039,
1404         ACX_ROAMING_STATISTICS_TBL  = 0x003B,
1405         ACX_RATE_POLICY             = 0x003D,
1406         ACX_CTS_PROTECTION          = 0x003E,
1407         ACX_SLEEP_AUTH              = 0x003F,
1408         ACX_PREAMBLE_TYPE           = 0x0040,
1409         ACX_ERROR_CNT               = 0x0041,
1410         ACX_FW_GEN_FRAME_RATES      = 0x0042,
1411         ACX_IBSS_FILTER             = 0x0044,
1412         ACX_SERVICE_PERIOD_TIMEOUT  = 0x0045,
1413         ACX_TSF_INFO                = 0x0046,
1414         ACX_CONFIG_PS_WMM           = 0x0049,
1415         ACX_ENABLE_RX_DATA_FILTER   = 0x004A,
1416         ACX_SET_RX_DATA_FILTER      = 0x004B,
1417         ACX_GET_DATA_FILTER_STATISTICS = 0x004C,
1418         ACX_POWER_LEVEL_TABLE       = 0x004D,
1419         ACX_BET_ENABLE              = 0x0050,
1420         DOT11_STATION_ID            = 0x1001,
1421         DOT11_RX_MSDU_LIFE_TIME     = 0x1004,
1422         DOT11_CUR_TX_PWR            = 0x100D,
1423         DOT11_DEFAULT_KEY           = 0x1010,
1424         DOT11_RX_DOT11_MODE         = 0x1012,
1425         DOT11_RTS_THRESHOLD         = 0x1013,
1426         DOT11_GROUP_ADDRESS_TBL     = 0x1014,
1427 
1428         MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL,
1429 
1430         MAX_IE = 0xFFFF
1431 };
1432 
1433 
1434 int wl1251_acx_frame_rates(struct wl1251 *wl, u8 ctrl_rate, u8 ctrl_mod,
1435                            u8 mgt_rate, u8 mgt_mod);
1436 int wl1251_acx_station_id(struct wl1251 *wl);
1437 int wl1251_acx_default_key(struct wl1251 *wl, u8 key_id);
1438 int wl1251_acx_wake_up_conditions(struct wl1251 *wl, u8 wake_up_event,
1439                                   u8 listen_interval);
1440 int wl1251_acx_sleep_auth(struct wl1251 *wl, u8 sleep_auth);
1441 int wl1251_acx_fw_version(struct wl1251 *wl, char *buf, size_t len);
1442 int wl1251_acx_tx_power(struct wl1251 *wl, int power);
1443 int wl1251_acx_feature_cfg(struct wl1251 *wl, u32 data_flow_options);
1444 int wl1251_acx_mem_map(struct wl1251 *wl,
1445                        struct acx_header *mem_map, size_t len);
1446 int wl1251_acx_data_path_params(struct wl1251 *wl,
1447                                 struct acx_data_path_params_resp *data_path);
1448 int wl1251_acx_rx_msdu_life_time(struct wl1251 *wl, u32 life_time);
1449 int wl1251_acx_rx_config(struct wl1251 *wl, u32 config, u32 filter);
1450 int wl1251_acx_pd_threshold(struct wl1251 *wl);
1451 int wl1251_acx_slot(struct wl1251 *wl, enum acx_slot_type slot_time);
1452 int wl1251_acx_group_address_tbl(struct wl1251 *wl, bool enable,
1453                                  void *mc_list, u32 mc_list_len);
1454 int wl1251_acx_service_period_timeout(struct wl1251 *wl);
1455 int wl1251_acx_rts_threshold(struct wl1251 *wl, u16 rts_threshold);
1456 int wl1251_acx_beacon_filter_opt(struct wl1251 *wl, bool enable_filter);
1457 int wl1251_acx_beacon_filter_table(struct wl1251 *wl);
1458 int wl1251_acx_conn_monit_params(struct wl1251 *wl);
1459 int wl1251_acx_sg_enable(struct wl1251 *wl);
1460 int wl1251_acx_sg_cfg(struct wl1251 *wl);
1461 int wl1251_acx_cca_threshold(struct wl1251 *wl);
1462 int wl1251_acx_bcn_dtim_options(struct wl1251 *wl);
1463 int wl1251_acx_aid(struct wl1251 *wl, u16 aid);
1464 int wl1251_acx_event_mbox_mask(struct wl1251 *wl, u32 event_mask);
1465 int wl1251_acx_low_rssi(struct wl1251 *wl, s8 threshold, u8 weight,
1466                         u8 depth, enum wl1251_acx_low_rssi_type type);
1467 int wl1251_acx_set_preamble(struct wl1251 *wl, enum acx_preamble_type preamble);
1468 int wl1251_acx_cts_protect(struct wl1251 *wl,
1469                             enum acx_ctsprotect_type ctsprotect);
1470 int wl1251_acx_statistics(struct wl1251 *wl, struct acx_statistics *stats);
1471 int wl1251_acx_tsf_info(struct wl1251 *wl, u64 *mactime);
1472 int wl1251_acx_rate_policies(struct wl1251 *wl);
1473 int wl1251_acx_mem_cfg(struct wl1251 *wl);
1474 int wl1251_acx_wr_tbtt_and_dtim(struct wl1251 *wl, u16 tbtt, u8 dtim);
1475 int wl1251_acx_bet_enable(struct wl1251 *wl, enum wl1251_acx_bet_mode mode,
1476                           u8 max_consecutive);
1477 int wl1251_acx_arp_ip_filter(struct wl1251 *wl, bool enable, __be32 address);
1478 int wl1251_acx_ac_cfg(struct wl1251 *wl, u8 ac, u8 cw_min, u16 cw_max,
1479                       u8 aifs, u16 txop);
1480 int wl1251_acx_tid_cfg(struct wl1251 *wl, u8 queue,
1481                        enum wl1251_acx_channel_type type,
1482                        u8 tsid, enum wl1251_acx_ps_scheme ps_scheme,
1483                        enum wl1251_acx_ack_policy ack_policy);
1484 
1485 #endif /* __WL1251_ACX_H__ */