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8 #ifndef __WL12XX_PRIV_H__
9 #define __WL12XX_PRIV_H__
10
11 #include "conf.h"
12
13
14 #define CHIP_ID_127X_PG10 (0x04030101)
15 #define CHIP_ID_127X_PG20 (0x04030111)
16 #define CHIP_ID_128X_PG10 (0x05030101)
17 #define CHIP_ID_128X_PG20 (0x05030111)
18
19
20 #define WL127X_CHIP_VER 6
21
22 #define WL127X_IFTYPE_SR_VER 3
23 #define WL127X_MAJOR_SR_VER 10
24 #define WL127X_SUBTYPE_SR_VER WLCORE_FW_VER_IGNORE
25 #define WL127X_MINOR_SR_VER 133
26
27 #define WL127X_IFTYPE_MR_VER 5
28 #define WL127X_MAJOR_MR_VER 7
29 #define WL127X_SUBTYPE_MR_VER WLCORE_FW_VER_IGNORE
30 #define WL127X_MINOR_MR_VER 42
31
32
33 #define WL128X_CHIP_VER 7
34
35 #define WL128X_IFTYPE_SR_VER 3
36 #define WL128X_MAJOR_SR_VER 10
37 #define WL128X_SUBTYPE_SR_VER WLCORE_FW_VER_IGNORE
38 #define WL128X_MINOR_SR_VER 133
39
40 #define WL128X_IFTYPE_MR_VER 5
41 #define WL128X_MAJOR_MR_VER 7
42 #define WL128X_SUBTYPE_MR_VER WLCORE_FW_VER_IGNORE
43 #define WL128X_MINOR_MR_VER 42
44
45 #define WL12XX_AGGR_BUFFER_SIZE (4 * PAGE_SIZE)
46
47 #define WL12XX_NUM_TX_DESCRIPTORS 16
48 #define WL12XX_NUM_RX_DESCRIPTORS 8
49
50 #define WL12XX_NUM_MAC_ADDRESSES 2
51
52 #define WL12XX_RX_BA_MAX_SESSIONS 3
53
54 #define WL12XX_MAX_AP_STATIONS 8
55 #define WL12XX_MAX_LINKS 12
56
57 struct wl127x_rx_mem_pool_addr {
58 u32 addr;
59 u32 addr_extra;
60 };
61
62 struct wl12xx_priv {
63 struct wl12xx_priv_conf conf;
64
65 int ref_clock;
66 int tcxo_clock;
67
68 struct wl127x_rx_mem_pool_addr *rx_mem_addr;
69 };
70
71
72 enum {
73 WL12XX_REFCLOCK_19 = 0,
74 WL12XX_REFCLOCK_26 = 1,
75 WL12XX_REFCLOCK_38 = 2,
76 WL12XX_REFCLOCK_52 = 3,
77 WL12XX_REFCLOCK_38_XTAL = 4,
78 WL12XX_REFCLOCK_26_XTAL = 5,
79 };
80
81
82 enum {
83 WL12XX_TCXOCLOCK_19_2 = 0,
84 WL12XX_TCXOCLOCK_26 = 1,
85 WL12XX_TCXOCLOCK_38_4 = 2,
86 WL12XX_TCXOCLOCK_52 = 3,
87 WL12XX_TCXOCLOCK_16_368 = 4,
88 WL12XX_TCXOCLOCK_32_736 = 5,
89 WL12XX_TCXOCLOCK_16_8 = 6,
90 WL12XX_TCXOCLOCK_33_6 = 7,
91 };
92
93 struct wl12xx_clock {
94 u32 freq;
95 bool xtal;
96 u8 hw_idx;
97 };
98
99 struct wl12xx_fw_packet_counters {
100
101 u8 tx_released_pkts[NUM_TX_QUEUES];
102
103
104 u8 tx_lnk_free_pkts[WL12XX_MAX_LINKS];
105
106
107 u8 tx_voice_released_blks;
108
109
110 u8 tx_last_rate;
111
112 u8 padding[2];
113 } __packed;
114
115
116 struct wl12xx_fw_status {
117 __le32 intr;
118 u8 fw_rx_counter;
119 u8 drv_rx_counter;
120 u8 reserved;
121 u8 tx_results_counter;
122 __le32 rx_pkt_descs[WL12XX_NUM_RX_DESCRIPTORS];
123
124 __le32 fw_localtime;
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129
130 __le32 link_ps_bitmap;
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136 __le32 link_fast_bitmap;
137
138
139 __le32 total_released_blks;
140
141
142 __le32 tx_total;
143
144 struct wl12xx_fw_packet_counters counters;
145
146 __le32 log_start_addr;
147 } __packed;
148
149 #endif