root/drivers/net/wireless/ath/ath5k/rfbuffer.h

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   1 /*
   2  * RF Buffer handling functions
   3  *
   4  * Copyright (c) 2009 Nick Kossifidis <mickflemm@gmail.com>
   5  *
   6  * Permission to use, copy, modify, and distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19 
  20 
  21 /**
  22  * DOC: RF Buffer registers
  23  *
  24  * There are some special registers on the RF chip
  25  * that control various operation settings related mostly to
  26  * the analog parts (channel, gain adjustment etc).
  27  *
  28  * We don't write on those registers directly but
  29  * we send a data packet on the chip, using a special register,
  30  * that holds all the settings we need. After we've sent the
  31  * data packet, we write on another special register to notify hw
  32  * to apply the settings. This is done so that control registers
  33  * can be dynamically programmed during operation and the settings
  34  * are applied faster on the hw.
  35  *
  36  * We call each data packet an "RF Bank" and all the data we write
  37  * (all RF Banks) "RF Buffer". This file holds initial RF Buffer
  38  * data for the different RF chips, and various info to match RF
  39  * Buffer offsets with specific RF registers so that we can access
  40  * them. We tweak these settings on rfregs_init function.
  41  *
  42  * Also check out reg.h and U.S. Patent 6677779 B1 (about buffer
  43  * registers and control registers):
  44  *
  45  * http://www.google.com/patents?id=qNURAAAAEBAJ
  46  */
  47 
  48 
  49 /**
  50  * struct ath5k_ini_rfbuffer - Initial RF Buffer settings
  51  * @rfb_bank: RF Bank number
  52  * @rfb_ctrl_register: RF Buffer control register
  53  * @rfb_mode_data: RF Buffer data for each mode
  54  *
  55  * Struct to hold default mode specific RF
  56  * register values (RF Banks) for each chip.
  57  */
  58 struct ath5k_ini_rfbuffer {
  59         u8      rfb_bank;
  60         u16     rfb_ctrl_register;
  61         u32     rfb_mode_data[3];
  62 };
  63 
  64 /**
  65  * struct ath5k_rfb_field - An RF Buffer field (register/value)
  66  * @len: Field length
  67  * @pos: Offset on the raw packet
  68  * @col: Used for shifting
  69  *
  70  * Struct to hold RF Buffer field
  71  * infos used to access certain RF
  72  * analog registers
  73  */
  74 struct ath5k_rfb_field {
  75         u8      len;
  76         u16     pos;
  77         u8      col;
  78 };
  79 
  80 /**
  81  * struct ath5k_rf_reg - RF analog register definition
  82  * @bank: RF Buffer Bank number
  83  * @index: Register's index on ath5k_rf_regx_idx
  84  * @field: The &struct ath5k_rfb_field
  85  *
  86  * We use this struct to define the set of RF registers
  87  * on each chip that we want to tweak. Some RF registers
  88  * are common between different chip versions so this saves
  89  * us space and complexity because we can refer to an rf
  90  * register by it's index no matter what chip we work with
  91  * as long as it has that register.
  92  */
  93 struct ath5k_rf_reg {
  94         u8                      bank;
  95         u8                      index;
  96         struct ath5k_rfb_field  field;
  97 };
  98 
  99 /**
 100  * enum ath5k_rf_regs_idx - Map RF registers to indexes
 101  *
 102  * We do this to handle common bits and make our
 103  * life easier by using an index for each register
 104  * instead of a full rfb_field
 105  */
 106 enum ath5k_rf_regs_idx {
 107         /* BANK 2 */
 108         AR5K_RF_TURBO = 0,
 109         /* BANK 6 */
 110         AR5K_RF_OB_2GHZ,
 111         AR5K_RF_OB_5GHZ,
 112         AR5K_RF_DB_2GHZ,
 113         AR5K_RF_DB_5GHZ,
 114         AR5K_RF_FIXED_BIAS_A,
 115         AR5K_RF_FIXED_BIAS_B,
 116         AR5K_RF_PWD_XPD,
 117         AR5K_RF_XPD_SEL,
 118         AR5K_RF_XPD_GAIN,
 119         AR5K_RF_PD_GAIN_LO,
 120         AR5K_RF_PD_GAIN_HI,
 121         AR5K_RF_HIGH_VC_CP,
 122         AR5K_RF_MID_VC_CP,
 123         AR5K_RF_LOW_VC_CP,
 124         AR5K_RF_PUSH_UP,
 125         AR5K_RF_PAD2GND,
 126         AR5K_RF_XB2_LVL,
 127         AR5K_RF_XB5_LVL,
 128         AR5K_RF_PWD_ICLOBUF_2G,
 129         AR5K_RF_PWD_84,
 130         AR5K_RF_PWD_90,
 131         AR5K_RF_PWD_130,
 132         AR5K_RF_PWD_131,
 133         AR5K_RF_PWD_132,
 134         AR5K_RF_PWD_136,
 135         AR5K_RF_PWD_137,
 136         AR5K_RF_PWD_138,
 137         AR5K_RF_PWD_166,
 138         AR5K_RF_PWD_167,
 139         AR5K_RF_DERBY_CHAN_SEL_MODE,
 140         /* BANK 7 */
 141         AR5K_RF_GAIN_I,
 142         AR5K_RF_PLO_SEL,
 143         AR5K_RF_RFGAIN_SEL,
 144         AR5K_RF_RFGAIN_STEP,
 145         AR5K_RF_WAIT_S,
 146         AR5K_RF_WAIT_I,
 147         AR5K_RF_MAX_TIME,
 148         AR5K_RF_MIXVGA_OVR,
 149         AR5K_RF_MIXGAIN_OVR,
 150         AR5K_RF_MIXGAIN_STEP,
 151         AR5K_RF_PD_DELAY_A,
 152         AR5K_RF_PD_DELAY_B,
 153         AR5K_RF_PD_DELAY_XR,
 154         AR5K_RF_PD_PERIOD_A,
 155         AR5K_RF_PD_PERIOD_B,
 156         AR5K_RF_PD_PERIOD_XR,
 157 };
 158 
 159 
 160 /*******************\
 161 * RF5111 (Sombrero) *
 162 \*******************/
 163 
 164 /* BANK 2                               len  pos col */
 165 #define AR5K_RF5111_RF_TURBO            { 1, 3,   0 }
 166 
 167 /* BANK 6                               len  pos col */
 168 #define AR5K_RF5111_OB_2GHZ             { 3, 119, 0 }
 169 #define AR5K_RF5111_DB_2GHZ             { 3, 122, 0 }
 170 
 171 #define AR5K_RF5111_OB_5GHZ             { 3, 104, 0 }
 172 #define AR5K_RF5111_DB_5GHZ             { 3, 107, 0 }
 173 
 174 #define AR5K_RF5111_PWD_XPD             { 1, 95,  0 }
 175 #define AR5K_RF5111_XPD_GAIN            { 4, 96,  0 }
 176 
 177 /* Access to PWD registers */
 178 #define AR5K_RF5111_PWD(_n)             { 1, (135 - _n), 3 }
 179 
 180 /* BANK 7                               len  pos col */
 181 #define AR5K_RF5111_GAIN_I              { 6, 29,  0 }
 182 #define AR5K_RF5111_PLO_SEL             { 1, 4,   0 }
 183 #define AR5K_RF5111_RFGAIN_SEL          { 1, 36,  0 }
 184 #define AR5K_RF5111_RFGAIN_STEP         { 6, 37,  0 }
 185 /* Only on AR5212 BaseBand and up */
 186 #define AR5K_RF5111_WAIT_S              { 5, 19,  0 }
 187 #define AR5K_RF5111_WAIT_I              { 5, 24,  0 }
 188 #define AR5K_RF5111_MAX_TIME            { 2, 49,  0 }
 189 
 190 static const struct ath5k_rf_reg rf_regs_5111[] = {
 191         {2, AR5K_RF_TURBO,              AR5K_RF5111_RF_TURBO},
 192         {6, AR5K_RF_OB_2GHZ,            AR5K_RF5111_OB_2GHZ},
 193         {6, AR5K_RF_DB_2GHZ,            AR5K_RF5111_DB_2GHZ},
 194         {6, AR5K_RF_OB_5GHZ,            AR5K_RF5111_OB_5GHZ},
 195         {6, AR5K_RF_DB_5GHZ,            AR5K_RF5111_DB_5GHZ},
 196         {6, AR5K_RF_PWD_XPD,            AR5K_RF5111_PWD_XPD},
 197         {6, AR5K_RF_XPD_GAIN,           AR5K_RF5111_XPD_GAIN},
 198         {6, AR5K_RF_PWD_84,             AR5K_RF5111_PWD(84)},
 199         {6, AR5K_RF_PWD_90,             AR5K_RF5111_PWD(90)},
 200         {7, AR5K_RF_GAIN_I,             AR5K_RF5111_GAIN_I},
 201         {7, AR5K_RF_PLO_SEL,            AR5K_RF5111_PLO_SEL},
 202         {7, AR5K_RF_RFGAIN_SEL,         AR5K_RF5111_RFGAIN_SEL},
 203         {7, AR5K_RF_RFGAIN_STEP,        AR5K_RF5111_RFGAIN_STEP},
 204         {7, AR5K_RF_WAIT_S,             AR5K_RF5111_WAIT_S},
 205         {7, AR5K_RF_WAIT_I,             AR5K_RF5111_WAIT_I},
 206         {7, AR5K_RF_MAX_TIME,           AR5K_RF5111_MAX_TIME}
 207 };
 208 
 209 /* Default mode specific settings */
 210 static const struct ath5k_ini_rfbuffer rfb_5111[] = {
 211         /* BANK / C.R.     A/XR         B           G      */
 212         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 213         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 214         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 215         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 216         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 217         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 218         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 219         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 220         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 221         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 222         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 223         { 0, 0x989c, { 0x00380000, 0x00380000, 0x00380000 } },
 224         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 225         { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 226         { 0, 0x989c, { 0x00000000, 0x000000c0, 0x00000080 } },
 227         { 0, 0x989c, { 0x000400f9, 0x000400ff, 0x000400fd } },
 228         { 0, 0x98d4, { 0x00000000, 0x00000004, 0x00000004 } },
 229         { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
 230         { 2, 0x98d4, { 0x00000010, 0x00000010, 0x00000010 } },
 231         { 3, 0x98d8, { 0x00601068, 0x00601068, 0x00601068 } },
 232         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 233         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 234         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 235         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 236         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 237         { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
 238         { 6, 0x989c, { 0x04000000, 0x04000000, 0x04000000 } },
 239         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 240         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 241         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 242         { 6, 0x989c, { 0x00000000, 0x0a000000, 0x00000000 } },
 243         { 6, 0x989c, { 0x003800c0, 0x023800c0, 0x003800c0 } },
 244         { 6, 0x989c, { 0x00020006, 0x00000006, 0x00020006 } },
 245         { 6, 0x989c, { 0x00000089, 0x00000089, 0x00000089 } },
 246         { 6, 0x989c, { 0x000000a0, 0x000000a0, 0x000000a0 } },
 247         { 6, 0x989c, { 0x00040007, 0x00040007, 0x00040007 } },
 248         { 6, 0x98d4, { 0x0000001a, 0x0000001a, 0x0000001a } },
 249         { 7, 0x989c, { 0x00000040, 0x00000040, 0x00000040 } },
 250         { 7, 0x989c, { 0x00000010, 0x00000010, 0x00000010 } },
 251         { 7, 0x989c, { 0x00000008, 0x00000008, 0x00000008 } },
 252         { 7, 0x989c, { 0x0000004f, 0x0000004f, 0x0000004f } },
 253         { 7, 0x989c, { 0x000000f1, 0x00000061, 0x000000f1 } },
 254         { 7, 0x989c, { 0x0000904f, 0x0000904c, 0x0000904f } },
 255         { 7, 0x989c, { 0x0000125a, 0x0000129a, 0x0000125a } },
 256         { 7, 0x98cc, { 0x0000000e, 0x0000000f, 0x0000000e } },
 257 };
 258 
 259 
 260 
 261 /***********************\
 262 * RF5112/RF2112 (Derby) *
 263 \***********************/
 264 
 265 /* BANK 2 (Common)                      len  pos col */
 266 #define AR5K_RF5112X_RF_TURBO           { 1, 1,   2 }
 267 
 268 /* BANK 7 (Common)                      len  pos col */
 269 #define AR5K_RF5112X_GAIN_I             { 6, 14,  0 }
 270 #define AR5K_RF5112X_MIXVGA_OVR         { 1, 36,  0 }
 271 #define AR5K_RF5112X_MIXGAIN_OVR        { 2, 37,  0 }
 272 #define AR5K_RF5112X_MIXGAIN_STEP       { 4, 32,  0 }
 273 #define AR5K_RF5112X_PD_DELAY_A         { 4, 58,  0 }
 274 #define AR5K_RF5112X_PD_DELAY_B         { 4, 62,  0 }
 275 #define AR5K_RF5112X_PD_DELAY_XR        { 4, 66,  0 }
 276 #define AR5K_RF5112X_PD_PERIOD_A        { 4, 70,  0 }
 277 #define AR5K_RF5112X_PD_PERIOD_B        { 4, 74,  0 }
 278 #define AR5K_RF5112X_PD_PERIOD_XR       { 4, 78,  0 }
 279 
 280 /* RFX112 (Derby 1) */
 281 
 282 /* BANK 6                               len  pos col */
 283 #define AR5K_RF5112_OB_2GHZ             { 3, 269, 0 }
 284 #define AR5K_RF5112_DB_2GHZ             { 3, 272, 0 }
 285 
 286 #define AR5K_RF5112_OB_5GHZ             { 3, 261, 0 }
 287 #define AR5K_RF5112_DB_5GHZ             { 3, 264, 0 }
 288 
 289 #define AR5K_RF5112_FIXED_BIAS_A        { 1, 260, 0 }
 290 #define AR5K_RF5112_FIXED_BIAS_B        { 1, 259, 0 }
 291 
 292 #define AR5K_RF5112_XPD_SEL             { 1, 284, 0 }
 293 #define AR5K_RF5112_XPD_GAIN            { 2, 252, 0 }
 294 
 295 /* Access to PWD registers */
 296 #define AR5K_RF5112_PWD(_n)             { 1, (302 - _n), 3 }
 297 
 298 static const struct ath5k_rf_reg rf_regs_5112[] = {
 299         {2, AR5K_RF_TURBO,              AR5K_RF5112X_RF_TURBO},
 300         {6, AR5K_RF_OB_2GHZ,            AR5K_RF5112_OB_2GHZ},
 301         {6, AR5K_RF_DB_2GHZ,            AR5K_RF5112_DB_2GHZ},
 302         {6, AR5K_RF_OB_5GHZ,            AR5K_RF5112_OB_5GHZ},
 303         {6, AR5K_RF_DB_5GHZ,            AR5K_RF5112_DB_5GHZ},
 304         {6, AR5K_RF_FIXED_BIAS_A,       AR5K_RF5112_FIXED_BIAS_A},
 305         {6, AR5K_RF_FIXED_BIAS_B,       AR5K_RF5112_FIXED_BIAS_B},
 306         {6, AR5K_RF_XPD_SEL,            AR5K_RF5112_XPD_SEL},
 307         {6, AR5K_RF_XPD_GAIN,           AR5K_RF5112_XPD_GAIN},
 308         {6, AR5K_RF_PWD_130,            AR5K_RF5112_PWD(130)},
 309         {6, AR5K_RF_PWD_131,            AR5K_RF5112_PWD(131)},
 310         {6, AR5K_RF_PWD_132,            AR5K_RF5112_PWD(132)},
 311         {6, AR5K_RF_PWD_136,            AR5K_RF5112_PWD(136)},
 312         {6, AR5K_RF_PWD_137,            AR5K_RF5112_PWD(137)},
 313         {6, AR5K_RF_PWD_138,            AR5K_RF5112_PWD(138)},
 314         {7, AR5K_RF_GAIN_I,             AR5K_RF5112X_GAIN_I},
 315         {7, AR5K_RF_MIXVGA_OVR,         AR5K_RF5112X_MIXVGA_OVR},
 316         {7, AR5K_RF_MIXGAIN_OVR,        AR5K_RF5112X_MIXGAIN_OVR},
 317         {7, AR5K_RF_MIXGAIN_STEP,       AR5K_RF5112X_MIXGAIN_STEP},
 318         {7, AR5K_RF_PD_DELAY_A,         AR5K_RF5112X_PD_DELAY_A},
 319         {7, AR5K_RF_PD_DELAY_B,         AR5K_RF5112X_PD_DELAY_B},
 320         {7, AR5K_RF_PD_DELAY_XR,        AR5K_RF5112X_PD_DELAY_XR},
 321         {7, AR5K_RF_PD_PERIOD_A,        AR5K_RF5112X_PD_PERIOD_A},
 322         {7, AR5K_RF_PD_PERIOD_B,        AR5K_RF5112X_PD_PERIOD_B},
 323         {7, AR5K_RF_PD_PERIOD_XR,       AR5K_RF5112X_PD_PERIOD_XR},
 324 };
 325 
 326 /* Default mode specific settings */
 327 static const struct ath5k_ini_rfbuffer rfb_5112[] = {
 328         /* BANK / C.R.     A/XR         B           G      */
 329         { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
 330         { 2, 0x98d0, { 0x03060408, 0x03060408, 0x03060408 } },
 331         { 3, 0x98dc, { 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
 332         { 6, 0x989c, { 0x00a00000, 0x00a00000, 0x00a00000 } },
 333         { 6, 0x989c, { 0x000a0000, 0x000a0000, 0x000a0000 } },
 334         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 335         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 336         { 6, 0x989c, { 0x00660000, 0x00660000, 0x00660000 } },
 337         { 6, 0x989c, { 0x00db0000, 0x00db0000, 0x00db0000 } },
 338         { 6, 0x989c, { 0x00f10000, 0x00f10000, 0x00f10000 } },
 339         { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
 340         { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
 341         { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
 342         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 343         { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
 344         { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 345         { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 346         { 6, 0x989c, { 0x008b0000, 0x008b0000, 0x008b0000 } },
 347         { 6, 0x989c, { 0x00600000, 0x00600000, 0x00600000 } },
 348         { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
 349         { 6, 0x989c, { 0x00840000, 0x00840000, 0x00840000 } },
 350         { 6, 0x989c, { 0x00640000, 0x00640000, 0x00640000 } },
 351         { 6, 0x989c, { 0x00200000, 0x00200000, 0x00200000 } },
 352         { 6, 0x989c, { 0x00240000, 0x00240000, 0x00240000 } },
 353         { 6, 0x989c, { 0x00250000, 0x00250000, 0x00250000 } },
 354         { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
 355         { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
 356         { 6, 0x989c, { 0x00510000, 0x00510000, 0x00510000 } },
 357         { 6, 0x989c, { 0x1c040000, 0x1c040000, 0x1c040000 } },
 358         { 6, 0x989c, { 0x000a0000, 0x000a0000, 0x000a0000 } },
 359         { 6, 0x989c, { 0x00a10000, 0x00a10000, 0x00a10000 } },
 360         { 6, 0x989c, { 0x00400000, 0x00400000, 0x00400000 } },
 361         { 6, 0x989c, { 0x03090000, 0x03090000, 0x03090000 } },
 362         { 6, 0x989c, { 0x06000000, 0x06000000, 0x06000000 } },
 363         { 6, 0x989c, { 0x000000b0, 0x000000a8, 0x000000a8 } },
 364         { 6, 0x989c, { 0x0000002e, 0x0000002e, 0x0000002e } },
 365         { 6, 0x989c, { 0x006c4a41, 0x006c4af1, 0x006c4a61 } },
 366         { 6, 0x989c, { 0x0050892a, 0x0050892b, 0x0050892b } },
 367         { 6, 0x989c, { 0x00842400, 0x00842400, 0x00842400 } },
 368         { 6, 0x989c, { 0x00c69200, 0x00c69200, 0x00c69200 } },
 369         { 6, 0x98d0, { 0x0002000c, 0x0002000c, 0x0002000c } },
 370         { 7, 0x989c, { 0x00000094, 0x00000094, 0x00000094 } },
 371         { 7, 0x989c, { 0x00000091, 0x00000091, 0x00000091 } },
 372         { 7, 0x989c, { 0x0000000a, 0x00000012, 0x00000012 } },
 373         { 7, 0x989c, { 0x00000080, 0x00000080, 0x00000080 } },
 374         { 7, 0x989c, { 0x000000c1, 0x000000c1, 0x000000c1 } },
 375         { 7, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
 376         { 7, 0x989c, { 0x000000f0, 0x000000f0, 0x000000f0 } },
 377         { 7, 0x989c, { 0x00000022, 0x00000022, 0x00000022 } },
 378         { 7, 0x989c, { 0x00000092, 0x00000092, 0x00000092 } },
 379         { 7, 0x989c, { 0x000000d4, 0x000000d4, 0x000000d4 } },
 380         { 7, 0x989c, { 0x000014cc, 0x000014cc, 0x000014cc } },
 381         { 7, 0x989c, { 0x0000048c, 0x0000048c, 0x0000048c } },
 382         { 7, 0x98c4, { 0x00000003, 0x00000003, 0x00000003 } },
 383 };
 384 
 385 /* RFX112A (Derby 2) */
 386 
 387 /* BANK 6                               len  pos col */
 388 #define AR5K_RF5112A_OB_2GHZ            { 3, 287, 0 }
 389 #define AR5K_RF5112A_DB_2GHZ            { 3, 290, 0 }
 390 
 391 #define AR5K_RF5112A_OB_5GHZ            { 3, 279, 0 }
 392 #define AR5K_RF5112A_DB_5GHZ            { 3, 282, 0 }
 393 
 394 #define AR5K_RF5112A_FIXED_BIAS_A       { 1, 278, 0 }
 395 #define AR5K_RF5112A_FIXED_BIAS_B       { 1, 277, 0 }
 396 
 397 #define AR5K_RF5112A_XPD_SEL            { 1, 302, 0 }
 398 #define AR5K_RF5112A_PDGAINLO           { 2, 270, 0 }
 399 #define AR5K_RF5112A_PDGAINHI           { 2, 257, 0 }
 400 
 401 /* Access to PWD registers */
 402 #define AR5K_RF5112A_PWD(_n)            { 1, (306 - _n), 3 }
 403 
 404 /* Voltage regulators */
 405 #define AR5K_RF5112A_HIGH_VC_CP         { 2, 90,  2 }
 406 #define AR5K_RF5112A_MID_VC_CP          { 2, 92,  2 }
 407 #define AR5K_RF5112A_LOW_VC_CP          { 2, 94,  2 }
 408 #define AR5K_RF5112A_PUSH_UP            { 1, 254,  2 }
 409 
 410 /* Power consumption */
 411 #define AR5K_RF5112A_PAD2GND            { 1, 281, 1 }
 412 #define AR5K_RF5112A_XB2_LVL            { 2, 1,   3 }
 413 #define AR5K_RF5112A_XB5_LVL            { 2, 3,   3 }
 414 
 415 static const struct ath5k_rf_reg rf_regs_5112a[] = {
 416         {2, AR5K_RF_TURBO,              AR5K_RF5112X_RF_TURBO},
 417         {6, AR5K_RF_OB_2GHZ,            AR5K_RF5112A_OB_2GHZ},
 418         {6, AR5K_RF_DB_2GHZ,            AR5K_RF5112A_DB_2GHZ},
 419         {6, AR5K_RF_OB_5GHZ,            AR5K_RF5112A_OB_5GHZ},
 420         {6, AR5K_RF_DB_5GHZ,            AR5K_RF5112A_DB_5GHZ},
 421         {6, AR5K_RF_FIXED_BIAS_A,       AR5K_RF5112A_FIXED_BIAS_A},
 422         {6, AR5K_RF_FIXED_BIAS_B,       AR5K_RF5112A_FIXED_BIAS_B},
 423         {6, AR5K_RF_XPD_SEL,            AR5K_RF5112A_XPD_SEL},
 424         {6, AR5K_RF_PD_GAIN_LO,         AR5K_RF5112A_PDGAINLO},
 425         {6, AR5K_RF_PD_GAIN_HI,         AR5K_RF5112A_PDGAINHI},
 426         {6, AR5K_RF_PWD_130,            AR5K_RF5112A_PWD(130)},
 427         {6, AR5K_RF_PWD_131,            AR5K_RF5112A_PWD(131)},
 428         {6, AR5K_RF_PWD_132,            AR5K_RF5112A_PWD(132)},
 429         {6, AR5K_RF_PWD_136,            AR5K_RF5112A_PWD(136)},
 430         {6, AR5K_RF_PWD_137,            AR5K_RF5112A_PWD(137)},
 431         {6, AR5K_RF_PWD_138,            AR5K_RF5112A_PWD(138)},
 432         {6, AR5K_RF_PWD_166,            AR5K_RF5112A_PWD(166)},
 433         {6, AR5K_RF_PWD_167,            AR5K_RF5112A_PWD(167)},
 434         {6, AR5K_RF_HIGH_VC_CP,         AR5K_RF5112A_HIGH_VC_CP},
 435         {6, AR5K_RF_MID_VC_CP,          AR5K_RF5112A_MID_VC_CP},
 436         {6, AR5K_RF_LOW_VC_CP,          AR5K_RF5112A_LOW_VC_CP},
 437         {6, AR5K_RF_PUSH_UP,            AR5K_RF5112A_PUSH_UP},
 438         {6, AR5K_RF_PAD2GND,            AR5K_RF5112A_PAD2GND},
 439         {6, AR5K_RF_XB2_LVL,            AR5K_RF5112A_XB2_LVL},
 440         {6, AR5K_RF_XB5_LVL,            AR5K_RF5112A_XB5_LVL},
 441         {7, AR5K_RF_GAIN_I,             AR5K_RF5112X_GAIN_I},
 442         {7, AR5K_RF_MIXVGA_OVR,         AR5K_RF5112X_MIXVGA_OVR},
 443         {7, AR5K_RF_MIXGAIN_OVR,        AR5K_RF5112X_MIXGAIN_OVR},
 444         {7, AR5K_RF_MIXGAIN_STEP,       AR5K_RF5112X_MIXGAIN_STEP},
 445         {7, AR5K_RF_PD_DELAY_A,         AR5K_RF5112X_PD_DELAY_A},
 446         {7, AR5K_RF_PD_DELAY_B,         AR5K_RF5112X_PD_DELAY_B},
 447         {7, AR5K_RF_PD_DELAY_XR,        AR5K_RF5112X_PD_DELAY_XR},
 448         {7, AR5K_RF_PD_PERIOD_A,        AR5K_RF5112X_PD_PERIOD_A},
 449         {7, AR5K_RF_PD_PERIOD_B,        AR5K_RF5112X_PD_PERIOD_B},
 450         {7, AR5K_RF_PD_PERIOD_XR,       AR5K_RF5112X_PD_PERIOD_XR},
 451 };
 452 
 453 /* Default mode specific settings */
 454 static const struct ath5k_ini_rfbuffer rfb_5112a[] = {
 455         /* BANK / C.R.     A/XR         B           G      */
 456         { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
 457         { 2, 0x98d0, { 0x03060408, 0x03060408, 0x03060408 } },
 458         { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
 459         { 6, 0x989c, { 0x0f000000, 0x0f000000, 0x0f000000 } },
 460         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 461         { 6, 0x989c, { 0x00800000, 0x00800000, 0x00800000 } },
 462         { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
 463         { 6, 0x989c, { 0x00010000, 0x00010000, 0x00010000 } },
 464         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 465         { 6, 0x989c, { 0x00180000, 0x00180000, 0x00180000 } },
 466         { 6, 0x989c, { 0x00600000, 0x006e0000, 0x006e0000 } },
 467         { 6, 0x989c, { 0x00c70000, 0x00c70000, 0x00c70000 } },
 468         { 6, 0x989c, { 0x004b0000, 0x004b0000, 0x004b0000 } },
 469         { 6, 0x989c, { 0x04480000, 0x04480000, 0x04480000 } },
 470         { 6, 0x989c, { 0x004c0000, 0x004c0000, 0x004c0000 } },
 471         { 6, 0x989c, { 0x00e40000, 0x00e40000, 0x00e40000 } },
 472         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 473         { 6, 0x989c, { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
 474         { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 475         { 6, 0x989c, { 0x043f0000, 0x043f0000, 0x043f0000 } },
 476         { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
 477         { 6, 0x989c, { 0x02190000, 0x02190000, 0x02190000 } },
 478         { 6, 0x989c, { 0x00240000, 0x00240000, 0x00240000 } },
 479         { 6, 0x989c, { 0x00b40000, 0x00b40000, 0x00b40000 } },
 480         { 6, 0x989c, { 0x00990000, 0x00990000, 0x00990000 } },
 481         { 6, 0x989c, { 0x00500000, 0x00500000, 0x00500000 } },
 482         { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
 483         { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
 484         { 6, 0x989c, { 0xc0320000, 0xc0320000, 0xc0320000 } },
 485         { 6, 0x989c, { 0x01740000, 0x01740000, 0x01740000 } },
 486         { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
 487         { 6, 0x989c, { 0x86280000, 0x86280000, 0x86280000 } },
 488         { 6, 0x989c, { 0x31840000, 0x31840000, 0x31840000 } },
 489         { 6, 0x989c, { 0x00f20080, 0x00f20080, 0x00f20080 } },
 490         { 6, 0x989c, { 0x00270019, 0x00270019, 0x00270019 } },
 491         { 6, 0x989c, { 0x00000003, 0x00000003, 0x00000003 } },
 492         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 493         { 6, 0x989c, { 0x000000b2, 0x000000b2, 0x000000b2 } },
 494         { 6, 0x989c, { 0x00b02084, 0x00b02084, 0x00b02084 } },
 495         { 6, 0x989c, { 0x004125a4, 0x004125a4, 0x004125a4 } },
 496         { 6, 0x989c, { 0x00119220, 0x00119220, 0x00119220 } },
 497         { 6, 0x989c, { 0x001a4800, 0x001a4800, 0x001a4800 } },
 498         { 6, 0x98d8, { 0x000b0230, 0x000b0230, 0x000b0230 } },
 499         { 7, 0x989c, { 0x00000094, 0x00000094, 0x00000094 } },
 500         { 7, 0x989c, { 0x00000091, 0x00000091, 0x00000091 } },
 501         { 7, 0x989c, { 0x00000012, 0x00000012, 0x00000012 } },
 502         { 7, 0x989c, { 0x00000080, 0x00000080, 0x00000080 } },
 503         { 7, 0x989c, { 0x000000d9, 0x000000d9, 0x000000d9 } },
 504         { 7, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
 505         { 7, 0x989c, { 0x000000f0, 0x000000f0, 0x000000f0 } },
 506         { 7, 0x989c, { 0x000000a2, 0x000000a2, 0x000000a2 } },
 507         { 7, 0x989c, { 0x00000052, 0x00000052, 0x00000052 } },
 508         { 7, 0x989c, { 0x000000d4, 0x000000d4, 0x000000d4 } },
 509         { 7, 0x989c, { 0x000014cc, 0x000014cc, 0x000014cc } },
 510         { 7, 0x989c, { 0x0000048c, 0x0000048c, 0x0000048c } },
 511         { 7, 0x98c4, { 0x00000003, 0x00000003, 0x00000003 } },
 512 };
 513 
 514 
 515 
 516 /******************\
 517 * RF2413 (Griffin) *
 518 \******************/
 519 
 520 /* BANK 2                               len  pos col */
 521 #define AR5K_RF2413_RF_TURBO            { 1, 1,   2 }
 522 
 523 /* BANK 6                               len  pos col */
 524 #define AR5K_RF2413_OB_2GHZ             { 3, 168, 0 }
 525 #define AR5K_RF2413_DB_2GHZ             { 3, 165, 0 }
 526 
 527 static const struct ath5k_rf_reg rf_regs_2413[] = {
 528         {2, AR5K_RF_TURBO,              AR5K_RF2413_RF_TURBO},
 529         {6, AR5K_RF_OB_2GHZ,            AR5K_RF2413_OB_2GHZ},
 530         {6, AR5K_RF_DB_2GHZ,            AR5K_RF2413_DB_2GHZ},
 531 };
 532 
 533 /* Default mode specific settings
 534  * XXX: a/aTurbo ???
 535  */
 536 static const struct ath5k_ini_rfbuffer rfb_2413[] = {
 537         /* BANK / C.R.     A/XR         B           G      */
 538         { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
 539         { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
 540         { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
 541         { 6, 0x989c, { 0xf0000000, 0xf0000000, 0xf0000000 } },
 542         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 543         { 6, 0x989c, { 0x03000000, 0x03000000, 0x03000000 } },
 544         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 545         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 546         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 547         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 548         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 549         { 6, 0x989c, { 0x40400000, 0x40400000, 0x40400000 } },
 550         { 6, 0x989c, { 0x65050000, 0x65050000, 0x65050000 } },
 551         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 552         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 553         { 6, 0x989c, { 0x00420000, 0x00420000, 0x00420000 } },
 554         { 6, 0x989c, { 0x00b50000, 0x00b50000, 0x00b50000 } },
 555         { 6, 0x989c, { 0x00030000, 0x00030000, 0x00030000 } },
 556         { 6, 0x989c, { 0x00f70000, 0x00f70000, 0x00f70000 } },
 557         { 6, 0x989c, { 0x009d0000, 0x009d0000, 0x009d0000 } },
 558         { 6, 0x989c, { 0x00220000, 0x00220000, 0x00220000 } },
 559         { 6, 0x989c, { 0x04220000, 0x04220000, 0x04220000 } },
 560         { 6, 0x989c, { 0x00230018, 0x00230018, 0x00230018 } },
 561         { 6, 0x989c, { 0x00280000, 0x00280060, 0x00280060 } },
 562         { 6, 0x989c, { 0x005000c0, 0x005000c3, 0x005000c3 } },
 563         { 6, 0x989c, { 0x0004007f, 0x0004007f, 0x0004007f } },
 564         { 6, 0x989c, { 0x00000458, 0x00000458, 0x00000458 } },
 565         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 566         { 6, 0x989c, { 0x0000c000, 0x0000c000, 0x0000c000 } },
 567         { 6, 0x98d8, { 0x00400230, 0x00400230, 0x00400230 } },
 568         { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
 569         { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
 570         { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 571 };
 572 
 573 
 574 
 575 /***************************\
 576 * RF2315/RF2316 (Cobra SoC) *
 577 \***************************/
 578 
 579 /* BANK 2                               len  pos col */
 580 #define AR5K_RF2316_RF_TURBO            { 1, 1,   2 }
 581 
 582 /* BANK 6                               len  pos col */
 583 #define AR5K_RF2316_OB_2GHZ             { 3, 178, 0 }
 584 #define AR5K_RF2316_DB_2GHZ             { 3, 175, 0 }
 585 
 586 static const struct ath5k_rf_reg rf_regs_2316[] = {
 587         {2, AR5K_RF_TURBO,              AR5K_RF2316_RF_TURBO},
 588         {6, AR5K_RF_OB_2GHZ,            AR5K_RF2316_OB_2GHZ},
 589         {6, AR5K_RF_DB_2GHZ,            AR5K_RF2316_DB_2GHZ},
 590 };
 591 
 592 /* Default mode specific settings */
 593 static const struct ath5k_ini_rfbuffer rfb_2316[] = {
 594         /* BANK / C.R.     A/XR         B           G      */
 595         { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
 596         { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
 597         { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
 598         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 599         { 6, 0x989c, { 0xc0000000, 0xc0000000, 0xc0000000 } },
 600         { 6, 0x989c, { 0x0f000000, 0x0f000000, 0x0f000000 } },
 601         { 6, 0x989c, { 0x02000000, 0x02000000, 0x02000000 } },
 602         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 603         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 604         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 605         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 606         { 6, 0x989c, { 0xf8000000, 0xf8000000, 0xf8000000 } },
 607         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 608         { 6, 0x989c, { 0x95150000, 0x95150000, 0x95150000 } },
 609         { 6, 0x989c, { 0xc1000000, 0xc1000000, 0xc1000000 } },
 610         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 611         { 6, 0x989c, { 0x00080000, 0x00080000, 0x00080000 } },
 612         { 6, 0x989c, { 0x00d50000, 0x00d50000, 0x00d50000 } },
 613         { 6, 0x989c, { 0x000e0000, 0x000e0000, 0x000e0000 } },
 614         { 6, 0x989c, { 0x00dc0000, 0x00dc0000, 0x00dc0000 } },
 615         { 6, 0x989c, { 0x00770000, 0x00770000, 0x00770000 } },
 616         { 6, 0x989c, { 0x008a0000, 0x008a0000, 0x008a0000 } },
 617         { 6, 0x989c, { 0x10880000, 0x10880000, 0x10880000 } },
 618         { 6, 0x989c, { 0x008c0060, 0x008c0060, 0x008c0060 } },
 619         { 6, 0x989c, { 0x00a00000, 0x00a00080, 0x00a00080 } },
 620         { 6, 0x989c, { 0x00400000, 0x0040000d, 0x0040000d } },
 621         { 6, 0x989c, { 0x00110400, 0x00110400, 0x00110400 } },
 622         { 6, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
 623         { 6, 0x989c, { 0x00000001, 0x00000001, 0x00000001 } },
 624         { 6, 0x989c, { 0x00000b00, 0x00000b00, 0x00000b00 } },
 625         { 6, 0x989c, { 0x00000be8, 0x00000be8, 0x00000be8 } },
 626         { 6, 0x98c0, { 0x00010000, 0x00010000, 0x00010000 } },
 627         { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
 628         { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
 629         { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 630 };
 631 
 632 
 633 
 634 /******************************\
 635 * RF5413/RF5424 (Eagle/Condor) *
 636 \******************************/
 637 
 638 /* BANK 6                               len  pos col */
 639 #define AR5K_RF5413_OB_2GHZ             { 3, 241, 0 }
 640 #define AR5K_RF5413_DB_2GHZ             { 3, 238, 0 }
 641 
 642 #define AR5K_RF5413_OB_5GHZ             { 3, 247, 0 }
 643 #define AR5K_RF5413_DB_5GHZ             { 3, 244, 0 }
 644 
 645 #define AR5K_RF5413_PWD_ICLOBUF2G       { 3, 131, 3 }
 646 #define AR5K_RF5413_DERBY_CHAN_SEL_MODE { 1, 291, 2 }
 647 
 648 static const struct ath5k_rf_reg rf_regs_5413[] = {
 649         {6, AR5K_RF_OB_2GHZ,             AR5K_RF5413_OB_2GHZ},
 650         {6, AR5K_RF_DB_2GHZ,             AR5K_RF5413_DB_2GHZ},
 651         {6, AR5K_RF_OB_5GHZ,             AR5K_RF5413_OB_5GHZ},
 652         {6, AR5K_RF_DB_5GHZ,             AR5K_RF5413_DB_5GHZ},
 653         {6, AR5K_RF_PWD_ICLOBUF_2G,      AR5K_RF5413_PWD_ICLOBUF2G},
 654         {6, AR5K_RF_DERBY_CHAN_SEL_MODE, AR5K_RF5413_DERBY_CHAN_SEL_MODE},
 655 };
 656 
 657 /* Default mode specific settings */
 658 static const struct ath5k_ini_rfbuffer rfb_5413[] = {
 659         /* BANK / C.R.     A/XR         B           G      */
 660         { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
 661         { 2, 0x98d0, { 0x00000008, 0x00000008, 0x00000008 } },
 662         { 3, 0x98dc, { 0x00a000c0, 0x00e000c0, 0x00e000c0 } },
 663         { 6, 0x989c, { 0x33000000, 0x33000000, 0x33000000 } },
 664         { 6, 0x989c, { 0x01000000, 0x01000000, 0x01000000 } },
 665         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 666         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 667         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 668         { 6, 0x989c, { 0x1f000000, 0x1f000000, 0x1f000000 } },
 669         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 670         { 6, 0x989c, { 0x00b80000, 0x00b80000, 0x00b80000 } },
 671         { 6, 0x989c, { 0x00b70000, 0x00b70000, 0x00b70000 } },
 672         { 6, 0x989c, { 0x00840000, 0x00840000, 0x00840000 } },
 673         { 6, 0x989c, { 0x00980000, 0x00980000, 0x00980000 } },
 674         { 6, 0x989c, { 0x00c00000, 0x00c00000, 0x00c00000 } },
 675         { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 676         { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 677         { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 678         { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
 679         { 6, 0x989c, { 0x00d70000, 0x00d70000, 0x00d70000 } },
 680         { 6, 0x989c, { 0x00610000, 0x00610000, 0x00610000 } },
 681         { 6, 0x989c, { 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
 682         { 6, 0x989c, { 0x00de0000, 0x00de0000, 0x00de0000 } },
 683         { 6, 0x989c, { 0x007f0000, 0x007f0000, 0x007f0000 } },
 684         { 6, 0x989c, { 0x043d0000, 0x043d0000, 0x043d0000 } },
 685         { 6, 0x989c, { 0x00770000, 0x00770000, 0x00770000 } },
 686         { 6, 0x989c, { 0x00440000, 0x00440000, 0x00440000 } },
 687         { 6, 0x989c, { 0x00980000, 0x00980000, 0x00980000 } },
 688         { 6, 0x989c, { 0x00100080, 0x00100080, 0x00100080 } },
 689         { 6, 0x989c, { 0x0005c034, 0x0005c034, 0x0005c034 } },
 690         { 6, 0x989c, { 0x003100f0, 0x003100f0, 0x003100f0 } },
 691         { 6, 0x989c, { 0x000c011f, 0x000c011f, 0x000c011f } },
 692         { 6, 0x989c, { 0x00510040, 0x00510040, 0x00510040 } },
 693         { 6, 0x989c, { 0x005000da, 0x005000da, 0x005000da } },
 694         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 695         { 6, 0x989c, { 0x00004044, 0x00004044, 0x00004044 } },
 696         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 697         { 6, 0x989c, { 0x000060c0, 0x000060c0, 0x000060c0 } },
 698         { 6, 0x989c, { 0x00002c00, 0x00003600, 0x00003600 } },
 699         { 6, 0x98c8, { 0x00000403, 0x00040403, 0x00040403 } },
 700         { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
 701         { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
 702         { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 703 };
 704 
 705 
 706 
 707 /***************************\
 708 * RF2425/RF2417 (Swan/Nala) *
 709 * AR2317 (Spider SoC)       *
 710 \***************************/
 711 
 712 /* BANK 2                               len  pos col */
 713 #define AR5K_RF2425_RF_TURBO            { 1, 1,   2 }
 714 
 715 /* BANK 6                               len  pos col */
 716 #define AR5K_RF2425_OB_2GHZ             { 3, 193, 0 }
 717 #define AR5K_RF2425_DB_2GHZ             { 3, 190, 0 }
 718 
 719 static const struct ath5k_rf_reg rf_regs_2425[] = {
 720         {2, AR5K_RF_TURBO,              AR5K_RF2425_RF_TURBO},
 721         {6, AR5K_RF_OB_2GHZ,            AR5K_RF2425_OB_2GHZ},
 722         {6, AR5K_RF_DB_2GHZ,            AR5K_RF2425_DB_2GHZ},
 723 };
 724 
 725 /* Default mode specific settings
 726  */
 727 static const struct ath5k_ini_rfbuffer rfb_2425[] = {
 728         /* BANK / C.R.     A/XR         B           G      */
 729         { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
 730         { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
 731         { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
 732         { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
 733         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 734         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 735         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 736         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 737         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 738         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 739         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 740         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 741         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 742         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 743         { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
 744         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 745         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 746         { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
 747         { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
 748         { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
 749         { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
 750         { 6, 0x989c, { 0x00e70000, 0x00e70000, 0x00e70000 } },
 751         { 6, 0x989c, { 0x00140000, 0x00140000, 0x00140000 } },
 752         { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
 753         { 6, 0x989c, { 0x0007001a, 0x0007001a, 0x0007001a } },
 754         { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
 755         { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
 756         { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
 757         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 758         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 759         { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
 760         { 6, 0x989c, { 0x00001688, 0x00001688, 0x00001688 } },
 761         { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
 762         { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
 763         { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
 764         { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 765 };
 766 
 767 /*
 768  * TODO: Handle the few differences with swan during
 769  * bank modification and get rid of this
 770  */
 771 static const struct ath5k_ini_rfbuffer rfb_2317[] = {
 772         /* BANK / C.R.     A/XR         B           G      */
 773         { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
 774         { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
 775         { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
 776         { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
 777         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 778         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 779         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 780         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 781         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 782         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 783         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 784         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 785         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 786         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 787         { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
 788         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 789         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 790         { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
 791         { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
 792         { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
 793         { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
 794         { 6, 0x989c, { 0x00e70000, 0x00e70000, 0x00e70000 } },
 795         { 6, 0x989c, { 0x00140100, 0x00140100, 0x00140100 } },
 796         { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
 797         { 6, 0x989c, { 0x0007001a, 0x0007001a, 0x0007001a } },
 798         { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
 799         { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
 800         { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
 801         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 802         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 803         { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
 804         { 6, 0x989c, { 0x00009688, 0x00009688, 0x00009688 } },
 805         { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
 806         { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
 807         { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
 808         { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 809 };
 810 
 811 /*
 812  * TODO: Handle the few differences with swan during
 813  * bank modification and get rid of this
 814  */
 815 static const struct ath5k_ini_rfbuffer rfb_2417[] = {
 816         /* BANK / C.R.     A/XR         B           G      */
 817         { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
 818         { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
 819         { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
 820         { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
 821         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 822         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 823         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 824         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 825         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 826         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 827         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 828         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 829         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 830         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 831         { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
 832         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 833         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 834         { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
 835         { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
 836         { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
 837         { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
 838         { 6, 0x989c, { 0x00e70000, 0x80e70000, 0x80e70000 } },
 839         { 6, 0x989c, { 0x00140000, 0x00140000, 0x00140000 } },
 840         { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
 841         { 6, 0x989c, { 0x0007001a, 0x0207001a, 0x0207001a } },
 842         { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
 843         { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
 844         { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
 845         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 846         { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
 847         { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
 848         { 6, 0x989c, { 0x00001688, 0x00001688, 0x00001688 } },
 849         { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
 850         { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
 851         { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
 852         { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 853 };

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