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28 struct ath5k_hw_rx_ctl {
29 u32 rx_control_0;
30 u32 rx_control_1;
31 } __packed __aligned(4);
32
33
34 #define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff
35 #define AR5K_DESC_RX_CTL1_INTREQ 0x00002000
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44 struct ath5k_hw_rx_status {
45 u32 rx_status_0;
46 u32 rx_status_1;
47 } __packed __aligned(4);
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50
51 #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff
52 #define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000
53 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210 0x00004000
54 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000
55 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S 15
56 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000
57 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19
58 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211 0x38000000
59 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211_S 27
60
61
62 #define AR5K_5210_RX_DESC_STATUS1_DONE 0x00000001
63 #define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
64 #define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004
65 #define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210 0x00000008
66 #define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010
67 #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0
68 #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S 5
69 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
70 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00
71 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S 9
72 #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000
73 #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15
74 #define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000
75
76
77
78 #define AR5K_5212_RX_DESC_STATUS0_DATA_LEN 0x00000fff
79 #define AR5K_5212_RX_DESC_STATUS0_MORE 0x00001000
80 #define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000
81 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000
82 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S 15
83 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000
84 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20
85 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000
86 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28
87
88
89 #define AR5K_5212_RX_DESC_STATUS1_DONE 0x00000001
90 #define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
91 #define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR 0x00000004
92 #define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008
93 #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR 0x00000010
94 #define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR 0x00000020
95 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
96 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00
97 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S 9
98 #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000
99 #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16
100 #define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000
101 #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE 0x0000ff00
102 #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE_S 8
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127 enum ath5k_phy_error_code {
128 AR5K_RX_PHY_ERROR_UNDERRUN = 0,
129 AR5K_RX_PHY_ERROR_TIMING = 1,
130 AR5K_RX_PHY_ERROR_PARITY = 2,
131 AR5K_RX_PHY_ERROR_RATE = 3,
132 AR5K_RX_PHY_ERROR_LENGTH = 4,
133 AR5K_RX_PHY_ERROR_RADAR = 5,
134 AR5K_RX_PHY_ERROR_SERVICE = 6,
135 AR5K_RX_PHY_ERROR_TOR = 7,
136 AR5K_RX_PHY_ERROR_OFDM_TIMING = 17,
137 AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY = 18,
138 AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL = 19,
139 AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL = 20,
140 AR5K_RX_PHY_ERROR_OFDM_POWER_DROP = 21,
141 AR5K_RX_PHY_ERROR_OFDM_SERVICE = 22,
142 AR5K_RX_PHY_ERROR_OFDM_RESTART = 23,
143 AR5K_RX_PHY_ERROR_CCK_TIMING = 25,
144 AR5K_RX_PHY_ERROR_CCK_HEADER_CRC = 26,
145 AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL = 27,
146 AR5K_RX_PHY_ERROR_CCK_SERVICE = 30,
147 AR5K_RX_PHY_ERROR_CCK_RESTART = 31,
148 };
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155 struct ath5k_hw_2w_tx_ctl {
156 u32 tx_control_0;
157 u32 tx_control_1;
158 } __packed __aligned(4);
159
160
161 #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
162 #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210 0x0003f000
163 #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210_S 12
164 #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000
165 #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18
166 #define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000
167 #define AR5K_2W_TX_DESC_CTL0_LONG_PACKET_5210 0x00800000
168 #define AR5K_2W_TX_DESC_CTL0_VEOL_5211 0x00800000
169 #define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000
170 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000
171 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000
172 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT \
173 (ah->ah_version == AR5K_AR5210 ? \
174 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \
175 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211)
176 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25
177 #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210 0x1c000000
178 #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210_S 26
179 #define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000
180 #define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
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183 #define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff
184 #define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000
185 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5210 0x0007e000
186 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5211 0x000fe000
187 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX \
188 (ah->ah_version == AR5K_AR5210 ? \
189 AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5210 : \
190 AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5211)
191 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_S 13
192 #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211 0x00700000
193 #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211_S 20
194 #define AR5K_2W_TX_DESC_CTL1_NOACK_5211 0x00800000
195 #define AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210 0xfff80000
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198 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0
199 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 1
200 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 2
201 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 3
202 #define AR5K_AR5211_TX_DESC_FRAME_TYPE_BEACON 3
203 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 4
204 #define AR5K_AR5211_TX_DESC_FRAME_TYPE_PRESP 4
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213 struct ath5k_hw_4w_tx_ctl {
214 u32 tx_control_0;
215 u32 tx_control_1;
216 u32 tx_control_2;
217 u32 tx_control_3;
218 } __packed __aligned(4);
219
220
221 #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
222 #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000
223 #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16
224 #define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000
225 #define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000
226 #define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000
227 #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000
228 #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25
229 #define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000
230 #define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
231 #define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000
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234 #define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff
235 #define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000
236 #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX 0x000fe000
237 #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX_S 13
238 #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000
239 #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20
240 #define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000
241 #define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000
242 #define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25
243 #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000
244 #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27
245 #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000
246 #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29
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248
249 #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff
250 #define AR5K_4W_TX_DESC_CTL2_DURATION_UPD_EN 0x00008000
251 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000
252 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16
253 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000
254 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20
255 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000
256 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24
257 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000
258 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28
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261 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f
262 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0
263 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5
264 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00
265 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10
266 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000
267 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15
268 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000
269 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20
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276 struct ath5k_hw_tx_status {
277 u32 tx_status_0;
278 u32 tx_status_1;
279 } __packed __aligned(4);
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282 #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001
283 #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002
284 #define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004
285 #define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008
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291 #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0
292 #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4
293 #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00
294 #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8
295 #define AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5211 0x0000f000
296 #define AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5212_S 12
297 #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000
298 #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16
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301 #define AR5K_DESC_TX_STATUS1_DONE 0x00000001
302 #define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe
303 #define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1
304 #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000
305 #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13
306 #define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212 0x00600000
307 #define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212_S 21
308 #define AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212 0x00800000
309 #define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212 0x01000000
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316 struct ath5k_hw_5210_tx_desc {
317 struct ath5k_hw_2w_tx_ctl tx_ctl;
318 struct ath5k_hw_tx_status tx_stat;
319 } __packed __aligned(4);
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326 struct ath5k_hw_5212_tx_desc {
327 struct ath5k_hw_4w_tx_ctl tx_ctl;
328 struct ath5k_hw_tx_status tx_stat;
329 } __packed __aligned(4);
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336 struct ath5k_hw_all_rx_desc {
337 struct ath5k_hw_rx_ctl rx_ctl;
338 struct ath5k_hw_rx_status rx_stat;
339 } __packed __aligned(4);
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349 struct ath5k_desc {
350 u32 ds_link;
351 u32 ds_data;
352
353 union {
354 struct ath5k_hw_5210_tx_desc ds_tx5210;
355 struct ath5k_hw_5212_tx_desc ds_tx5212;
356 struct ath5k_hw_all_rx_desc ds_rx;
357 } ud;
358 } __packed __aligned(4);
359
360 #define AR5K_RXDESC_INTREQ 0x0020
361
362 #define AR5K_TXDESC_CLRDMASK 0x0001
363 #define AR5K_TXDESC_NOACK 0x0002
364 #define AR5K_TXDESC_RTSENA 0x0004
365 #define AR5K_TXDESC_CTSENA 0x0008
366 #define AR5K_TXDESC_INTREQ 0x0010
367 #define AR5K_TXDESC_VEOL 0x0020