root/drivers/net/wireless/ath/ath5k/eeprom.h

INCLUDED FROM

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
   4  *
   5  * Permission to use, copy, modify, and distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  */
  18 
  19 /*
  20  * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE)
  21  */
  22 #define AR5K_EEPROM_PCIE_OFFSET         0x02    /* Contains offset to PCI-E infos */
  23 #define AR5K_EEPROM_PCIE_SERDES_SECTION 0x40    /* PCIE_OFFSET points here when
  24                                                  * SERDES infos are present */
  25 #define AR5K_EEPROM_MAGIC               0x003d  /* EEPROM Magic number */
  26 #define AR5K_EEPROM_MAGIC_VALUE         0x5aa5  /* Default - found on EEPROM */
  27 
  28 #define AR5K_EEPROM_IS_HB63             0x000b  /* Talon detect */
  29 
  30 #define AR5K_EEPROM_RFKILL              0x0f
  31 #define AR5K_EEPROM_RFKILL_GPIO_SEL     0x0000001c
  32 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S   2
  33 #define AR5K_EEPROM_RFKILL_POLARITY     0x00000002
  34 #define AR5K_EEPROM_RFKILL_POLARITY_S   1
  35 
  36 #define AR5K_EEPROM_REG_DOMAIN          0x00bf  /* EEPROM regdom */
  37 
  38 /* FLASH(EEPROM) Defines for AR531X chips */
  39 #define AR5K_EEPROM_SIZE_LOWER          0x1b /* size info -- lower */
  40 #define AR5K_EEPROM_SIZE_UPPER          0x1c /* size info -- upper */
  41 #define AR5K_EEPROM_SIZE_UPPER_MASK     0xfff0
  42 #define AR5K_EEPROM_SIZE_UPPER_SHIFT    4
  43 #define AR5K_EEPROM_SIZE_ENDLOC_SHIFT   12
  44 
  45 #define AR5K_EEPROM_CHECKSUM            0x00c0  /* EEPROM checksum */
  46 #define AR5K_EEPROM_INFO_BASE           0x00c0  /* EEPROM header */
  47 #define AR5K_EEPROM_INFO_MAX            (0x400 - AR5K_EEPROM_INFO_BASE)
  48 #define AR5K_EEPROM_INFO_CKSUM          0xffff
  49 #define AR5K_EEPROM_INFO(_n)            (AR5K_EEPROM_INFO_BASE + (_n))
  50 
  51 #define AR5K_EEPROM_VERSION             AR5K_EEPROM_INFO(1)     /* EEPROM Version */
  52 #define AR5K_EEPROM_VERSION_3_0         0x3000  /* No idea what's going on before this version */
  53 #define AR5K_EEPROM_VERSION_3_1         0x3001  /* ob/db values for 2GHz (ar5211_rfregs) */
  54 #define AR5K_EEPROM_VERSION_3_2         0x3002  /* different frequency representation (eeprom_bin2freq) */
  55 #define AR5K_EEPROM_VERSION_3_3         0x3003  /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
  56 #define AR5K_EEPROM_VERSION_3_4         0x3004  /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */
  57 #define AR5K_EEPROM_VERSION_4_0         0x4000  /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */
  58 #define AR5K_EEPROM_VERSION_4_1         0x4001  /* has ee_margin_tx_rx (eeprom_init) */
  59 #define AR5K_EEPROM_VERSION_4_2         0x4002  /* has ee_cck_ofdm_gain_delta (eeprom_init) */
  60 #define AR5K_EEPROM_VERSION_4_3         0x4003  /* power calibration changes */
  61 #define AR5K_EEPROM_VERSION_4_4         0x4004
  62 #define AR5K_EEPROM_VERSION_4_5         0x4005
  63 #define AR5K_EEPROM_VERSION_4_6         0x4006  /* has ee_scaled_cck_delta */
  64 #define AR5K_EEPROM_VERSION_4_7         0x3007  /* 4007 ? */
  65 #define AR5K_EEPROM_VERSION_4_9         0x4009  /* EAR futureproofing */
  66 #define AR5K_EEPROM_VERSION_5_0         0x5000  /* Has 2413 PDADC calibration etc */
  67 #define AR5K_EEPROM_VERSION_5_1         0x5001  /* Has capability values */
  68 #define AR5K_EEPROM_VERSION_5_3         0x5003  /* Has spur mitigation tables */
  69 
  70 #define AR5K_EEPROM_MODE_11A            0
  71 #define AR5K_EEPROM_MODE_11B            1
  72 #define AR5K_EEPROM_MODE_11G            2
  73 
  74 #define AR5K_EEPROM_HDR                 AR5K_EEPROM_INFO(2)     /* Header that contains the device caps */
  75 #define AR5K_EEPROM_HDR_11A(_v)         (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
  76 #define AR5K_EEPROM_HDR_11B(_v)         (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
  77 #define AR5K_EEPROM_HDR_11G(_v)         (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
  78 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v)  (((_v) >> 3) & 0x1)     /* Disable turbo for 2GHz */
  79 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v)  (((_v) >> 4) & 0x7f)    /* Max turbo power for < 2W power consumption */
  80 #define AR5K_EEPROM_HDR_DEVICE(_v)      (((_v) >> 11) & 0x7)    /* Device type (1 Cardbus, 2 PCI, 3 MiniPCI, 4 AP) */
  81 #define AR5K_EEPROM_HDR_RFKILL(_v)      (((_v) >> 14) & 0x1)    /* Device has RFKill support */
  82 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v)  (((_v) >> 15) & 0x1)    /* Disable turbo for 5GHz */
  83 
  84 /* Newer EEPROMs are using a different offset */
  85 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
  86         (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
  87 
  88 #define AR5K_EEPROM_ANT_GAIN(_v)        AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
  89 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v)   ((s8)(((_v) >> 8) & 0xff))
  90 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v)   ((s8)((_v) & 0xff))
  91 
  92 /* Misc values available since EEPROM 4.0 */
  93 #define AR5K_EEPROM_MISC0               AR5K_EEPROM_INFO(4)
  94 #define AR5K_EEPROM_EARSTART(_v)        ((_v) & 0xfff)
  95 #define AR5K_EEPROM_HDR_XR2_DIS(_v)     (((_v) >> 12) & 0x1)
  96 #define AR5K_EEPROM_HDR_XR5_DIS(_v)     (((_v) >> 13) & 0x1)
  97 #define AR5K_EEPROM_EEMAP(_v)           (((_v) >> 14) & 0x3)
  98 
  99 #define AR5K_EEPROM_MISC1                       AR5K_EEPROM_INFO(5)
 100 #define AR5K_EEPROM_TARGET_PWRSTART(_v)         ((_v) & 0xfff)
 101 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v)         (((_v) >> 14) & 0x1)    /* has 32KHz crystal for sleep mode */
 102 #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v)     (((_v) >> 15) & 0x1)
 103 
 104 #define AR5K_EEPROM_MISC2                       AR5K_EEPROM_INFO(6)
 105 #define AR5K_EEPROM_EEP_FILE_VERSION(_v)        (((_v) >> 8) & 0xff)
 106 #define AR5K_EEPROM_EAR_FILE_VERSION(_v)        ((_v) & 0xff)
 107 
 108 #define AR5K_EEPROM_MISC3               AR5K_EEPROM_INFO(7)
 109 #define AR5K_EEPROM_ART_BUILD_NUM(_v)   (((_v) >> 10) & 0x3f)
 110 #define AR5K_EEPROM_EAR_FILE_ID(_v)     ((_v) & 0xff)
 111 
 112 #define AR5K_EEPROM_MISC4               AR5K_EEPROM_INFO(8)
 113 #define AR5K_EEPROM_CAL_DATA_START(_v)  (((_v) >> 4) & 0xfff)
 114 #define AR5K_EEPROM_MASK_R0(_v)         (((_v) >> 2) & 0x3)     /* modes supported by radio 0 (bit 1: G, bit 2: A) */
 115 #define AR5K_EEPROM_MASK_R1(_v)         ((_v) & 0x3)            /* modes supported by radio 1 (bit 1: G, bit 2: A) */
 116 
 117 #define AR5K_EEPROM_MISC5               AR5K_EEPROM_INFO(9)
 118 #define AR5K_EEPROM_COMP_DIS(_v)        ((_v) & 0x1)            /* disable compression */
 119 #define AR5K_EEPROM_AES_DIS(_v)         (((_v) >> 1) & 0x1)     /* disable AES */
 120 #define AR5K_EEPROM_FF_DIS(_v)          (((_v) >> 2) & 0x1)     /* disable fast frames */
 121 #define AR5K_EEPROM_BURST_DIS(_v)       (((_v) >> 3) & 0x1)     /* disable bursting */
 122 #define AR5K_EEPROM_MAX_QCU(_v)         (((_v) >> 4) & 0xf)     /* max number of QCUs. defaults to 10 */
 123 #define AR5K_EEPROM_HEAVY_CLIP_EN(_v)   (((_v) >> 8) & 0x1)     /* enable heavy clipping */
 124 #define AR5K_EEPROM_KEY_CACHE_SIZE(_v)  (((_v) >> 12) & 0xf)    /* key cache size. defaults to 128 */
 125 
 126 #define AR5K_EEPROM_MISC6               AR5K_EEPROM_INFO(10)
 127 #define AR5K_EEPROM_TX_CHAIN_DIS        ((_v) & 0x7)            /* MIMO chains disabled for TX bitmask */
 128 #define AR5K_EEPROM_RX_CHAIN_DIS        (((_v) >> 3) & 0x7)     /* MIMO chains disabled for RX bitmask */
 129 #define AR5K_EEPROM_FCC_MID_EN          (((_v) >> 6) & 0x1)     /* 5.47-5.7GHz supported */
 130 #define AR5K_EEPROM_JAP_U1EVEN_EN       (((_v) >> 7) & 0x1)     /* Japan UNII1 band (5.15-5.25GHz) on even channels (5180, 5200, 5220, 5240) supported */
 131 #define AR5K_EEPROM_JAP_U2_EN           (((_v) >> 8) & 0x1)     /* Japan UNII2 band (5.25-5.35GHz) supported */
 132 #define AR5K_EEPROM_JAP_MID_EN          (((_v) >> 9) & 0x1)     /* Japan band from 5.47-5.7GHz supported */
 133 #define AR5K_EEPROM_JAP_U1ODD_EN        (((_v) >> 10) & 0x1)    /* Japan UNII2 band (5.15-5.25GHz) on odd channels (5170, 5190, 5210, 5230) supported */
 134 #define AR5K_EEPROM_JAP_11A_NEW_EN      (((_v) >> 11) & 0x1)    /* Japan A mode enabled (using even channels) */
 135 
 136 /* calibration settings */
 137 #define AR5K_EEPROM_MODES_11A(_v)       AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
 138 #define AR5K_EEPROM_MODES_11B(_v)       AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
 139 #define AR5K_EEPROM_MODES_11G(_v)       AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
 140 #define AR5K_EEPROM_CTL(_v)             AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128)     /* Conformance test limits */
 141 #define AR5K_EEPROM_GROUPS_START(_v)    AR5K_EEPROM_OFF(_v, 0x0100, 0x0150)     /* Start of Groups */
 142 #define AR5K_EEPROM_GROUP1_OFFSET       0x0
 143 #define AR5K_EEPROM_GROUP2_OFFSET       0x5
 144 #define AR5K_EEPROM_GROUP3_OFFSET       0x37
 145 #define AR5K_EEPROM_GROUP4_OFFSET       0x46
 146 #define AR5K_EEPROM_GROUP5_OFFSET       0x55
 147 #define AR5K_EEPROM_GROUP6_OFFSET       0x65
 148 #define AR5K_EEPROM_GROUP7_OFFSET       0x69
 149 #define AR5K_EEPROM_GROUP8_OFFSET       0x6f
 150 
 151 #define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
 152                                                                 AR5K_EEPROM_GROUP5_OFFSET, 0x0000)
 153 #define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
 154                                                                 AR5K_EEPROM_GROUP6_OFFSET, 0x0010)
 155 #define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
 156                                                                 AR5K_EEPROM_GROUP7_OFFSET, 0x0014)
 157 
 158 /* [3.1 - 3.3] */
 159 #define AR5K_EEPROM_OBDB0_2GHZ          0x00ec
 160 #define AR5K_EEPROM_OBDB1_2GHZ          0x00ed
 161 
 162 #define AR5K_EEPROM_PROTECT             0x003f  /* EEPROM protect status */
 163 #define AR5K_EEPROM_PROTECT_RD_0_31     0x0001  /* Read protection bit for offsets 0x0 - 0x1f */
 164 #define AR5K_EEPROM_PROTECT_WR_0_31     0x0002  /* Write protection bit for offsets 0x0 - 0x1f */
 165 #define AR5K_EEPROM_PROTECT_RD_32_63    0x0004  /* 0x20 - 0x3f */
 166 #define AR5K_EEPROM_PROTECT_WR_32_63    0x0008
 167 #define AR5K_EEPROM_PROTECT_RD_64_127   0x0010  /* 0x40 - 0x7f */
 168 #define AR5K_EEPROM_PROTECT_WR_64_127   0x0020
 169 #define AR5K_EEPROM_PROTECT_RD_128_191  0x0040  /* 0x80 - 0xbf (regdom) */
 170 #define AR5K_EEPROM_PROTECT_WR_128_191  0x0080
 171 #define AR5K_EEPROM_PROTECT_RD_192_207  0x0100  /* 0xc0 - 0xcf */
 172 #define AR5K_EEPROM_PROTECT_WR_192_207  0x0200
 173 #define AR5K_EEPROM_PROTECT_RD_208_223  0x0400  /* 0xd0 - 0xdf */
 174 #define AR5K_EEPROM_PROTECT_WR_208_223  0x0800
 175 #define AR5K_EEPROM_PROTECT_RD_224_239  0x1000  /* 0xe0 - 0xef */
 176 #define AR5K_EEPROM_PROTECT_WR_224_239  0x2000
 177 #define AR5K_EEPROM_PROTECT_RD_240_255  0x4000  /* 0xf0 - 0xff */
 178 #define AR5K_EEPROM_PROTECT_WR_240_255  0x8000
 179 
 180 /* Some EEPROM defines */
 181 #define AR5K_EEPROM_EEP_SCALE           100
 182 #define AR5K_EEPROM_EEP_DELTA           10
 183 #define AR5K_EEPROM_N_MODES             3
 184 #define AR5K_EEPROM_N_5GHZ_CHAN         10
 185 #define AR5K_EEPROM_N_5GHZ_RATE_CHAN    8
 186 #define AR5K_EEPROM_N_2GHZ_CHAN         3
 187 #define AR5K_EEPROM_N_2GHZ_CHAN_2413    4
 188 #define AR5K_EEPROM_N_2GHZ_CHAN_MAX     4
 189 #define AR5K_EEPROM_MAX_CHAN            10
 190 #define AR5K_EEPROM_N_PWR_POINTS_5111   11
 191 #define AR5K_EEPROM_N_PCDAC             11
 192 #define AR5K_EEPROM_N_PHASE_CAL         5
 193 #define AR5K_EEPROM_N_TEST_FREQ         8
 194 #define AR5K_EEPROM_N_EDGES             8
 195 #define AR5K_EEPROM_N_INTERCEPTS        11
 196 #define AR5K_EEPROM_FREQ_M(_v)          AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
 197 #define AR5K_EEPROM_PCDAC_M             0x3f
 198 #define AR5K_EEPROM_PCDAC_START         1
 199 #define AR5K_EEPROM_PCDAC_STOP          63
 200 #define AR5K_EEPROM_PCDAC_STEP          1
 201 #define AR5K_EEPROM_NON_EDGE_M          0x40
 202 #define AR5K_EEPROM_CHANNEL_POWER       8
 203 #define AR5K_EEPROM_N_OBDB              4
 204 #define AR5K_EEPROM_OBDB_DIS            0xffff
 205 #define AR5K_EEPROM_CHANNEL_DIS         0xff
 206 #define AR5K_EEPROM_SCALE_OC_DELTA(_x)  (((_x) * 2) / 10)
 207 #define AR5K_EEPROM_N_CTLS(_v)          AR5K_EEPROM_OFF(_v, 16, 32)
 208 #define AR5K_EEPROM_MAX_CTLS            32
 209 #define AR5K_EEPROM_N_PD_CURVES         4
 210 #define AR5K_EEPROM_N_XPD0_POINTS       4
 211 #define AR5K_EEPROM_N_XPD3_POINTS       3
 212 #define AR5K_EEPROM_N_PD_GAINS          4
 213 #define AR5K_EEPROM_N_PD_POINTS         5
 214 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
 215 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
 216 #define AR5K_EEPROM_POWER_M             0x3f
 217 #define AR5K_EEPROM_POWER_MIN           0
 218 #define AR5K_EEPROM_POWER_MAX           3150
 219 #define AR5K_EEPROM_POWER_STEP          50
 220 #define AR5K_EEPROM_POWER_TABLE_SIZE    64
 221 #define AR5K_EEPROM_N_POWER_LOC_11B     4
 222 #define AR5K_EEPROM_N_POWER_LOC_11G     6
 223 #define AR5K_EEPROM_I_GAIN              10
 224 #define AR5K_EEPROM_CCK_OFDM_DELTA      15
 225 #define AR5K_EEPROM_N_IQ_CAL            2
 226 /* 5GHz/2GHz */
 227 enum ath5k_eeprom_freq_bands {
 228         AR5K_EEPROM_BAND_5GHZ = 0,
 229         AR5K_EEPROM_BAND_2GHZ = 1,
 230         AR5K_EEPROM_N_FREQ_BANDS,
 231 };
 232 /* Spur chans per freq band */
 233 #define AR5K_EEPROM_N_SPUR_CHANS        5
 234 /* fbin value for chan 2464 x2 */
 235 #define AR5K_EEPROM_5413_SPUR_CHAN_1    1640
 236 /* fbin value for chan 2420 x2 */
 237 #define AR5K_EEPROM_5413_SPUR_CHAN_2    1200
 238 #define AR5K_EEPROM_SPUR_CHAN_MASK      0x3FFF
 239 #define AR5K_EEPROM_NO_SPUR             0x8000
 240 #define AR5K_SPUR_CHAN_WIDTH                    87
 241 #define AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz       3125
 242 #define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz      6250
 243 
 244 #define AR5K_EEPROM_READ(_o, _v) do {                   \
 245         if (!ath5k_hw_nvram_read(ah, (_o), &(_v)))      \
 246                 return -EIO;                            \
 247 } while (0)
 248 
 249 #define AR5K_EEPROM_READ_HDR(_o, _v)                                    \
 250         AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v);        \
 251 
 252 enum ath5k_ant_table {
 253         AR5K_ANT_CTL            = 0,    /* Idle switch table settings */
 254         AR5K_ANT_SWTABLE_A      = 1,    /* Switch table for antenna A */
 255         AR5K_ANT_SWTABLE_B      = 2,    /* Switch table for antenna B */
 256         AR5K_ANT_MAX,
 257 };
 258 
 259 enum ath5k_ctl_mode {
 260         AR5K_CTL_11A = 0,
 261         AR5K_CTL_11B = 1,
 262         AR5K_CTL_11G = 2,
 263         AR5K_CTL_TURBO = 3,
 264         AR5K_CTL_TURBOG = 4,
 265         AR5K_CTL_2GHT20 = 5,
 266         AR5K_CTL_5GHT20 = 6,
 267         AR5K_CTL_2GHT40 = 7,
 268         AR5K_CTL_5GHT40 = 8,
 269         AR5K_CTL_MODE_M = 15,
 270 };
 271 
 272 /* Per channel calibration data, used for power table setup */
 273 struct ath5k_chan_pcal_info_rf5111 {
 274         /* Power levels in half dBm units
 275          * for one power curve. */
 276         u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111];
 277         /* PCDAC table steps
 278          * for the above values */
 279         u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111];
 280         /* Starting PCDAC step */
 281         u8 pcdac_min;
 282         /* Final PCDAC step */
 283         u8 pcdac_max;
 284 };
 285 
 286 struct ath5k_chan_pcal_info_rf5112 {
 287         /* Power levels in quarter dBm units
 288          * for lower (0) and higher (3)
 289          * level curves in 0.25dB units */
 290         s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS];
 291         s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS];
 292         /* PCDAC table steps
 293          * for the above values */
 294         u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS];
 295         u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS];
 296 };
 297 
 298 struct ath5k_chan_pcal_info_rf2413 {
 299         /* Starting pwr/pddac values */
 300         s8 pwr_i[AR5K_EEPROM_N_PD_GAINS];
 301         u8 pddac_i[AR5K_EEPROM_N_PD_GAINS];
 302         /* (pwr,pddac) points
 303          * power levels in 0.5dB units */
 304         s8 pwr[AR5K_EEPROM_N_PD_GAINS]
 305                 [AR5K_EEPROM_N_PD_POINTS];
 306         u8 pddac[AR5K_EEPROM_N_PD_GAINS]
 307                 [AR5K_EEPROM_N_PD_POINTS];
 308 };
 309 
 310 enum ath5k_powertable_type {
 311         AR5K_PWRTABLE_PWR_TO_PCDAC = 0,
 312         AR5K_PWRTABLE_LINEAR_PCDAC = 1,
 313         AR5K_PWRTABLE_PWR_TO_PDADC = 2,
 314 };
 315 
 316 struct ath5k_pdgain_info {
 317         u8 pd_points;
 318         u8 *pd_step;
 319         /* Power values are in
 320          * 0.25dB units */
 321         s16 *pd_pwr;
 322 };
 323 
 324 struct ath5k_chan_pcal_info {
 325         /* Frequency */
 326         u16     freq;
 327         /* Tx power boundaries */
 328         s16     max_pwr;
 329         s16     min_pwr;
 330         union {
 331                 struct ath5k_chan_pcal_info_rf5111 rf5111_info;
 332                 struct ath5k_chan_pcal_info_rf5112 rf5112_info;
 333                 struct ath5k_chan_pcal_info_rf2413 rf2413_info;
 334         };
 335         /* Raw values used by phy code
 336          * Curves are stored in order from lower
 337          * gain to higher gain (max txpower -> min txpower) */
 338         struct ath5k_pdgain_info *pd_curves;
 339 };
 340 
 341 /* Per rate calibration data for each mode,
 342  * used for rate power table setup.
 343  * Note: Values in 0.5dB units */
 344 struct ath5k_rate_pcal_info {
 345         u16     freq; /* Frequency */
 346         /* Power level for 6-24Mbit/s rates or
 347          * 1Mb rate */
 348         u16     target_power_6to24;
 349         /* Power level for 36Mbit rate or
 350          * 2Mb rate */
 351         u16     target_power_36;
 352         /* Power level for 48Mbit rate or
 353          * 5.5Mbit rate */
 354         u16     target_power_48;
 355         /* Power level for 54Mbit rate or
 356          * 11Mbit rate */
 357         u16     target_power_54;
 358 };
 359 
 360 /* Power edges for conformance test limits */
 361 struct ath5k_edge_power {
 362         u16 freq;
 363         u16 edge; /* in half dBm */
 364         bool flag;
 365 };
 366 
 367 /**
 368  * struct ath5k_eeprom_info - EEPROM calibration data
 369  *
 370  * @ee_regdomain: ath/regd.c takes care of COUNTRY_ERD and WORLDWIDE_ROAMING
 371  *      flags
 372  * @ee_ant_gain: Antenna gain in 0.5dB steps signed [5211 only?]
 373  * @ee_cck_ofdm_gain_delta: difference in gainF to output the same power for
 374  *      OFDM and CCK packets
 375  * @ee_cck_ofdm_power_delta: power difference between OFDM (6Mbps) and CCK
 376  *      (11Mbps) rate in G mode. 0.1dB steps
 377  * @ee_scaled_cck_delta: for Japan Channel 14: 0.1dB resolution
 378  *
 379  * @ee_i_cal: Initial I coefficient to correct I/Q mismatch in the receive path
 380  * @ee_q_cal: Initial Q coefficient to correct I/Q mismatch in the receive path
 381  * @ee_fixed_bias: use ee_ob and ee_db settings or use automatic control
 382  * @ee_switch_settling: RX/TX Switch settling time
 383  * @ee_atn_tx_rx: Difference in attenuation between TX and RX in 1dB steps
 384  * @ee_ant_control: Antenna Control Settings
 385  * @ee_ob: Bias current for Output stage of PA
 386  *      B/G mode: Index [0] is used for AR2112/5112, otherwise [1]
 387  *      A mode: [0] 5.15-5.25 [1] 5.25-5.50 [2] 5.50-5.70 [3] 5.70-5.85 GHz
 388  * @ee_db: Bias current for Output stage of PA. see @ee_ob
 389  * @ee_tx_end2xlna_enable: Time difference from when BB finishes sending a frame
 390  *      to when the external LNA is activated
 391  * @ee_tx_end2xpa_disable: Time difference from when BB finishes sending a frame
 392  *      to when the external PA switch is deactivated
 393  * @ee_tx_frm2xpa_enable: Time difference from when MAC sends frame to when
 394  *      external PA switch is activated
 395  * @ee_thr_62: Clear Channel Assessment (CCA) sensitivity
 396  *      (IEEE802.11a section 17.3.10.5 )
 397  * @ee_xlna_gain: Total gain of the LNA (information only)
 398  * @ee_xpd: Use external (1) or internal power detector
 399  * @ee_x_gain: Gain for external power detector output (differences in EEMAP
 400  *      versions!)
 401  * @ee_i_gain: Initial gain value after reset
 402  * @ee_margin_tx_rx: Margin in dB when final attenuation stage should be used
 403  *
 404  * @ee_false_detect: Backoff in Sensitivity (dB) on channels with spur signals
 405  * @ee_noise_floor_thr: Noise floor threshold in 1dB steps
 406  * @ee_adc_desired_size: Desired amplitude for ADC, used by AGC; in 0.5 dB steps
 407  * @ee_pga_desired_size: Desired output of PGA (for BB gain) in 0.5 dB steps
 408  * @ee_pd_gain_overlap: PD ADC curves need to overlap in 0.5dB steps (ee_map>=2)
 409  */
 410 struct ath5k_eeprom_info {
 411 
 412         /* Header information */
 413         u16     ee_magic;
 414         u16     ee_protect;
 415         u16     ee_regdomain;
 416         u16     ee_version;
 417         u16     ee_header;
 418         u16     ee_ant_gain;
 419         u8      ee_rfkill_pin;
 420         bool    ee_rfkill_pol;
 421         bool    ee_is_hb63;
 422         bool    ee_serdes;
 423         u16     ee_misc0;
 424         u16     ee_misc1;
 425         u16     ee_misc2;
 426         u16     ee_misc3;
 427         u16     ee_misc4;
 428         u16     ee_misc5;
 429         u16     ee_misc6;
 430         u16     ee_cck_ofdm_gain_delta;
 431         u16     ee_cck_ofdm_power_delta;
 432         u16     ee_scaled_cck_delta;
 433 
 434         /* RF Calibration settings (reset, rfregs) */
 435         u16     ee_i_cal[AR5K_EEPROM_N_MODES];
 436         u16     ee_q_cal[AR5K_EEPROM_N_MODES];
 437         u16     ee_fixed_bias[AR5K_EEPROM_N_MODES];
 438         u16     ee_turbo_max_power[AR5K_EEPROM_N_MODES];
 439         u16     ee_xr_power[AR5K_EEPROM_N_MODES];
 440         u16     ee_switch_settling[AR5K_EEPROM_N_MODES];
 441         u16     ee_atn_tx_rx[AR5K_EEPROM_N_MODES];
 442         u16     ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
 443         u16     ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
 444         u16     ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
 445         u16     ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
 446         u16     ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
 447         u16     ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
 448         u16     ee_thr_62[AR5K_EEPROM_N_MODES];
 449         u16     ee_xlna_gain[AR5K_EEPROM_N_MODES];
 450         u16     ee_xpd[AR5K_EEPROM_N_MODES];
 451         u16     ee_x_gain[AR5K_EEPROM_N_MODES];
 452         u16     ee_i_gain[AR5K_EEPROM_N_MODES];
 453         u16     ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
 454         u16     ee_switch_settling_turbo[AR5K_EEPROM_N_MODES];
 455         u16     ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES];
 456         u16     ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES];
 457 
 458         /* Power calibration data */
 459         u16     ee_false_detect[AR5K_EEPROM_N_MODES];
 460 
 461         /* Number of pd gain curves per mode */
 462         u8      ee_pd_gains[AR5K_EEPROM_N_MODES];
 463         /* Back mapping pdcurve number -> pdcurve index in pd->pd_curves */
 464         u8      ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS];
 465 
 466         u8      ee_n_piers[AR5K_EEPROM_N_MODES];
 467         struct ath5k_chan_pcal_info     ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN];
 468         struct ath5k_chan_pcal_info     ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
 469         struct ath5k_chan_pcal_info     ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
 470 
 471         /* Per rate target power levels */
 472         u8      ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
 473         struct ath5k_rate_pcal_info     ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN];
 474         struct ath5k_rate_pcal_info     ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
 475         struct ath5k_rate_pcal_info     ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
 476 
 477         /* Conformance test limits (Unused) */
 478         u8      ee_ctls;
 479         u8      ee_ctl[AR5K_EEPROM_MAX_CTLS];
 480         struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS];
 481 
 482         /* Noise Floor Calibration settings */
 483         s16     ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
 484         s8      ee_adc_desired_size[AR5K_EEPROM_N_MODES];
 485         s8      ee_pga_desired_size[AR5K_EEPROM_N_MODES];
 486         s8      ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES];
 487         s8      ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES];
 488         s8      ee_pd_gain_overlap;
 489 
 490         /* Spur mitigation data (fbin values for spur channels) */
 491         u16     ee_spur_chans[AR5K_EEPROM_N_SPUR_CHANS][AR5K_EEPROM_N_FREQ_BANDS];
 492 
 493         /* Antenna raw switch tables */
 494         u32     ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
 495 };