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17 #ifndef AR9003_AIC_H
18 #define AR9003_AIC_H
19
20 #define ATH_AIC_MAX_COM_ATT_DB_TABLE 6
21 #define ATH_AIC_MAX_AIC_LIN_TABLE 69
22 #define ATH_AIC_MIN_ROT_DIR_ATT_DB 0
23 #define ATH_AIC_MIN_ROT_QUAD_ATT_DB 0
24 #define ATH_AIC_MAX_ROT_DIR_ATT_DB 37
25 #define ATH_AIC_MAX_ROT_QUAD_ATT_DB 37
26 #define ATH_AIC_SRAM_AUTO_INCREMENT 0x80000000
27 #define ATH_AIC_SRAM_GAIN_TABLE_OFFSET 0x280
28 #define ATH_AIC_SRAM_CAL_OFFSET 0x140
29 #define ATH_AIC_SRAM_OFFSET 0x00
30 #define ATH_AIC_MEAS_MAG_THRESH 20
31 #define ATH_AIC_BT_JUPITER_CTRL 0x66820
32 #define ATH_AIC_BT_AIC_ENABLE 0x02
33
34 enum aic_cal_state {
35 AIC_CAL_STATE_IDLE = 0,
36 AIC_CAL_STATE_STARTED,
37 AIC_CAL_STATE_DONE,
38 AIC_CAL_STATE_ERROR
39 };
40
41 struct ath_aic_sram_info {
42 bool valid:1;
43 bool vga_quad_sign:1;
44 bool vga_dir_sign:1;
45 u8 rot_quad_att_db;
46 u8 rot_dir_att_db;
47 u8 com_att_6db;
48 };
49
50 struct ath_aic_out_info {
51 int16_t dir_path_gain_lin;
52 int16_t quad_path_gain_lin;
53 };
54
55 u8 ar9003_aic_calibration(struct ath_hw *ah);
56 u8 ar9003_aic_start_normal(struct ath_hw *ah);
57 u8 ar9003_aic_cal_reset(struct ath_hw *ah);
58 u8 ar9003_aic_calibration_single(struct ath_hw *ah);
59
60 #endif