root/drivers/net/wireless/ath/wcn36xx/txrx.h

INCLUDED FROM

   1 /*
   2  * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com>
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16 
  17 #ifndef _TXRX_H_
  18 #define _TXRX_H_
  19 
  20 #include <linux/etherdevice.h>
  21 #include "wcn36xx.h"
  22 
  23 /* TODO describe all properties */
  24 #define WCN36XX_802_11_HEADER_LEN       24
  25 #define WCN36XX_BMU_WQ_TX               25
  26 #define WCN36XX_TID                     7
  27 /* broadcast wq ID */
  28 #define WCN36XX_TX_B_WQ_ID              0xA
  29 #define WCN36XX_TX_U_WQ_ID              0x9
  30 /* bd_rate */
  31 #define WCN36XX_BD_RATE_DATA 0
  32 #define WCN36XX_BD_RATE_MGMT 2
  33 #define WCN36XX_BD_RATE_CTRL 3
  34 
  35 enum wcn36xx_txbd_ssn_type {
  36         WCN36XX_TXBD_SSN_FILL_HOST = 0,
  37         WCN36XX_TXBD_SSN_FILL_DPU_NON_QOS = 1,
  38         WCN36XX_TXBD_SSN_FILL_DPU_QOS = 2,
  39 };
  40 
  41 struct wcn36xx_pdu {
  42         u32     dpu_fb:8;
  43         u32     adu_fb:8;
  44         u32     pdu_id:16;
  45 
  46         /* 0x04*/
  47         u32     tail_pdu_idx:16;
  48         u32     head_pdu_idx:16;
  49 
  50         /* 0x08*/
  51         u32     pdu_count:7;
  52         u32     mpdu_data_off:9;
  53         u32     mpdu_header_off:8;
  54         u32     mpdu_header_len:8;
  55 
  56         /* 0x0c*/
  57         u32     reserved4:8;
  58         u32     tid:4;
  59         u32     bd_ssn:2;
  60         u32     reserved3:2;
  61         u32     mpdu_len:16;
  62 };
  63 
  64 struct wcn36xx_rx_bd {
  65         u32     bdt:2;
  66         u32     ft:1;
  67         u32     dpu_ne:1;
  68         u32     rx_key_id:3;
  69         u32     ub:1;
  70         u32     rmf:1;
  71         u32     uma_bypass:1;
  72         u32     csr11:1;
  73         u32     reserved0:1;
  74         u32     scan_learn:1;
  75         u32     rx_ch:4;
  76         u32     rtsf:1;
  77         u32     bsf:1;
  78         u32     a2hf:1;
  79         u32     st_auf:1;
  80         u32     dpu_sign:3;
  81         u32     dpu_rf:8;
  82 
  83         struct wcn36xx_pdu pdu;
  84 
  85         /* 0x14*/
  86         u32     addr3:8;
  87         u32     addr2:8;
  88         u32     addr1:8;
  89         u32     dpu_desc_idx:8;
  90 
  91         /* 0x18*/
  92         u32     rxp_flags:23;
  93         u32     rate_id:9;
  94 
  95         u32     phy_stat0;
  96         u32     phy_stat1;
  97 
  98         /* 0x24 */
  99         u32     rx_times;
 100 
 101         u32     pmi_cmd[6];
 102 
 103         /* 0x40 */
 104         u32     reserved7:4;
 105         u32     reorder_slot_id:6;
 106         u32     reorder_fwd_id:6;
 107         u32     reserved6:12;
 108         u32     reorder_code:4;
 109 
 110         /* 0x44 */
 111         u32     exp_seq_num:12;
 112         u32     cur_seq_num:12;
 113         u32     fr_type_subtype:8;
 114 
 115         /* 0x48 */
 116         u32     msdu_size:16;
 117         u32     sub_fr_id:4;
 118         u32     proc_order:4;
 119         u32     reserved9:4;
 120         u32     aef:1;
 121         u32     lsf:1;
 122         u32     esf:1;
 123         u32     asf:1;
 124 };
 125 
 126 struct wcn36xx_tx_bd {
 127         u32     bdt:2;
 128         u32     ft:1;
 129         u32     dpu_ne:1;
 130         u32     fw_tx_comp:1;
 131         u32     tx_comp:1;
 132         u32     reserved1:1;
 133         u32     ub:1;
 134         u32     rmf:1;
 135         u32     reserved0:12;
 136         u32     dpu_sign:3;
 137         u32     dpu_rf:8;
 138 
 139         struct wcn36xx_pdu pdu;
 140 
 141         /* 0x14*/
 142         u32     reserved5:7;
 143         u32     queue_id:5;
 144         u32     bd_rate:2;
 145         u32     ack_policy:2;
 146         u32     sta_index:8;
 147         u32     dpu_desc_idx:8;
 148 
 149         u32     tx_bd_sign;
 150         u32     reserved6;
 151         u32     dxe_start_time;
 152         u32     dxe_end_time;
 153 
 154         /*u32   tcp_udp_start_off:10;
 155         u32     header_cks:16;
 156         u32     reserved7:6;*/
 157 };
 158 
 159 struct wcn36xx_sta;
 160 struct wcn36xx;
 161 
 162 int  wcn36xx_rx_skb(struct wcn36xx *wcn, struct sk_buff *skb);
 163 int wcn36xx_start_tx(struct wcn36xx *wcn,
 164                      struct wcn36xx_sta *sta_priv,
 165                      struct sk_buff *skb);
 166 
 167 #endif  /* _TXRX_H_ */