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39 #ifndef __CARL9170_SHARED_HW_H
40 #define __CARL9170_SHARED_HW_H
41
42
43 #define AR9170_UART_REG_BASE 0x1c0000
44
45
46 #define AR9170_UART_REG_RX_BUFFER (AR9170_UART_REG_BASE + 0x000)
47 #define AR9170_UART_REG_TX_HOLDING (AR9170_UART_REG_BASE + 0x004)
48 #define AR9170_UART_REG_FIFO_CONTROL (AR9170_UART_REG_BASE + 0x010)
49 #define AR9170_UART_FIFO_CTRL_RESET_RX_FIFO 0x02
50 #define AR9170_UART_FIFO_CTRL_RESET_TX_FIFO 0x04
51
52 #define AR9170_UART_REG_LINE_CONTROL (AR9170_UART_REG_BASE + 0x014)
53 #define AR9170_UART_REG_MODEM_CONTROL (AR9170_UART_REG_BASE + 0x018)
54 #define AR9170_UART_MODEM_CTRL_DTR_BIT 0x01
55 #define AR9170_UART_MODEM_CTRL_RTS_BIT 0x02
56 #define AR9170_UART_MODEM_CTRL_INTERNAL_LOOP_BACK 0x10
57 #define AR9170_UART_MODEM_CTRL_AUTO_RTS 0x20
58 #define AR9170_UART_MODEM_CTRL_AUTO_CTR 0x40
59
60 #define AR9170_UART_REG_LINE_STATUS (AR9170_UART_REG_BASE + 0x01c)
61 #define AR9170_UART_LINE_STS_RX_DATA_READY 0x01
62 #define AR9170_UART_LINE_STS_RX_BUFFER_OVERRUN 0x02
63 #define AR9170_UART_LINE_STS_RX_BREAK_IND 0x10
64 #define AR9170_UART_LINE_STS_TX_FIFO_NEAR_EMPTY 0x20
65 #define AR9170_UART_LINE_STS_TRANSMITTER_EMPTY 0x40
66
67 #define AR9170_UART_REG_MODEM_STATUS (AR9170_UART_REG_BASE + 0x020)
68 #define AR9170_UART_MODEM_STS_CTS_CHANGE 0x01
69 #define AR9170_UART_MODEM_STS_DSR_CHANGE 0x02
70 #define AR9170_UART_MODEM_STS_DCD_CHANGE 0x08
71 #define AR9170_UART_MODEM_STS_CTS_COMPL 0x10
72 #define AR9170_UART_MODEM_STS_DSR_COMPL 0x20
73 #define AR9170_UART_MODEM_STS_DCD_COMPL 0x80
74
75 #define AR9170_UART_REG_SCRATCH (AR9170_UART_REG_BASE + 0x024)
76 #define AR9170_UART_REG_DIVISOR_LSB (AR9170_UART_REG_BASE + 0x028)
77 #define AR9170_UART_REG_DIVISOR_MSB (AR9170_UART_REG_BASE + 0x02c)
78 #define AR9170_UART_REG_WORD_RX_BUFFER (AR9170_UART_REG_BASE + 0x034)
79 #define AR9170_UART_REG_WORD_TX_HOLDING (AR9170_UART_REG_BASE + 0x038)
80 #define AR9170_UART_REG_FIFO_COUNT (AR9170_UART_REG_BASE + 0x03c)
81 #define AR9170_UART_REG_REMAINDER (AR9170_UART_REG_BASE + 0x04c)
82
83
84 #define AR9170_TIMER_REG_BASE 0x1c1000
85
86 #define AR9170_TIMER_REG_WATCH_DOG (AR9170_TIMER_REG_BASE + 0x000)
87 #define AR9170_TIMER_REG_TIMER0 (AR9170_TIMER_REG_BASE + 0x010)
88 #define AR9170_TIMER_REG_TIMER1 (AR9170_TIMER_REG_BASE + 0x014)
89 #define AR9170_TIMER_REG_TIMER2 (AR9170_TIMER_REG_BASE + 0x018)
90 #define AR9170_TIMER_REG_TIMER3 (AR9170_TIMER_REG_BASE + 0x01c)
91 #define AR9170_TIMER_REG_TIMER4 (AR9170_TIMER_REG_BASE + 0x020)
92 #define AR9170_TIMER_REG_CONTROL (AR9170_TIMER_REG_BASE + 0x024)
93 #define AR9170_TIMER_CTRL_DISABLE_CLOCK 0x100
94
95 #define AR9170_TIMER_REG_INTERRUPT (AR9170_TIMER_REG_BASE + 0x028)
96 #define AR9170_TIMER_INT_TIMER0 0x001
97 #define AR9170_TIMER_INT_TIMER1 0x002
98 #define AR9170_TIMER_INT_TIMER2 0x004
99 #define AR9170_TIMER_INT_TIMER3 0x008
100 #define AR9170_TIMER_INT_TIMER4 0x010
101 #define AR9170_TIMER_INT_TICK_TIMER 0x100
102
103 #define AR9170_TIMER_REG_TICK_TIMER (AR9170_TIMER_REG_BASE + 0x030)
104 #define AR9170_TIMER_REG_CLOCK_LOW (AR9170_TIMER_REG_BASE + 0x040)
105 #define AR9170_TIMER_REG_CLOCK_HIGH (AR9170_TIMER_REG_BASE + 0x044)
106
107 #define AR9170_MAC_REG_BASE 0x1c3000
108
109 #define AR9170_MAC_REG_POWER_STATE_CTRL (AR9170_MAC_REG_BASE + 0x500)
110 #define AR9170_MAC_POWER_STATE_CTRL_RESET 0x20
111
112 #define AR9170_MAC_REG_MAC_POWER_STATE_CTRL (AR9170_MAC_REG_BASE + 0x50c)
113
114 #define AR9170_MAC_REG_INT_CTRL (AR9170_MAC_REG_BASE + 0x510)
115 #define AR9170_MAC_INT_TXC BIT(0)
116 #define AR9170_MAC_INT_RXC BIT(1)
117 #define AR9170_MAC_INT_RETRY_FAIL BIT(2)
118 #define AR9170_MAC_INT_WAKEUP BIT(3)
119 #define AR9170_MAC_INT_ATIM BIT(4)
120 #define AR9170_MAC_INT_DTIM BIT(5)
121 #define AR9170_MAC_INT_CFG_BCN BIT(6)
122 #define AR9170_MAC_INT_ABORT BIT(7)
123 #define AR9170_MAC_INT_QOS BIT(8)
124 #define AR9170_MAC_INT_MIMO_PS BIT(9)
125 #define AR9170_MAC_INT_KEY_GEN BIT(10)
126 #define AR9170_MAC_INT_DECRY_NOUSER BIT(11)
127 #define AR9170_MAC_INT_RADAR BIT(12)
128 #define AR9170_MAC_INT_QUIET_FRAME BIT(13)
129 #define AR9170_MAC_INT_PRETBTT BIT(14)
130
131 #define AR9170_MAC_REG_TSF_L (AR9170_MAC_REG_BASE + 0x514)
132 #define AR9170_MAC_REG_TSF_H (AR9170_MAC_REG_BASE + 0x518)
133
134 #define AR9170_MAC_REG_ATIM_WINDOW (AR9170_MAC_REG_BASE + 0x51c)
135 #define AR9170_MAC_ATIM_PERIOD_S 0
136 #define AR9170_MAC_ATIM_PERIOD 0x0000ffff
137
138 #define AR9170_MAC_REG_BCN_PERIOD (AR9170_MAC_REG_BASE + 0x520)
139 #define AR9170_MAC_BCN_PERIOD_S 0
140 #define AR9170_MAC_BCN_PERIOD 0x0000ffff
141 #define AR9170_MAC_BCN_DTIM_S 16
142 #define AR9170_MAC_BCN_DTIM 0x00ff0000
143 #define AR9170_MAC_BCN_AP_MODE BIT(24)
144 #define AR9170_MAC_BCN_IBSS_MODE BIT(25)
145 #define AR9170_MAC_BCN_PWR_MGT BIT(26)
146 #define AR9170_MAC_BCN_STA_PS BIT(27)
147
148 #define AR9170_MAC_REG_PRETBTT (AR9170_MAC_REG_BASE + 0x524)
149 #define AR9170_MAC_PRETBTT_S 0
150 #define AR9170_MAC_PRETBTT 0x0000ffff
151 #define AR9170_MAC_PRETBTT2_S 16
152 #define AR9170_MAC_PRETBTT2 0xffff0000
153
154 #define AR9170_MAC_REG_MAC_ADDR_L (AR9170_MAC_REG_BASE + 0x610)
155 #define AR9170_MAC_REG_MAC_ADDR_H (AR9170_MAC_REG_BASE + 0x614)
156 #define AR9170_MAC_REG_BSSID_L (AR9170_MAC_REG_BASE + 0x618)
157 #define AR9170_MAC_REG_BSSID_H (AR9170_MAC_REG_BASE + 0x61c)
158
159 #define AR9170_MAC_REG_GROUP_HASH_TBL_L (AR9170_MAC_REG_BASE + 0x624)
160 #define AR9170_MAC_REG_GROUP_HASH_TBL_H (AR9170_MAC_REG_BASE + 0x628)
161
162 #define AR9170_MAC_REG_RX_TIMEOUT (AR9170_MAC_REG_BASE + 0x62c)
163
164 #define AR9170_MAC_REG_BASIC_RATE (AR9170_MAC_REG_BASE + 0x630)
165 #define AR9170_MAC_REG_MANDATORY_RATE (AR9170_MAC_REG_BASE + 0x634)
166 #define AR9170_MAC_REG_RTS_CTS_RATE (AR9170_MAC_REG_BASE + 0x638)
167 #define AR9170_MAC_REG_BACKOFF_PROTECT (AR9170_MAC_REG_BASE + 0x63c)
168 #define AR9170_MAC_REG_RX_THRESHOLD (AR9170_MAC_REG_BASE + 0x640)
169 #define AR9170_MAC_REG_AFTER_PNP (AR9170_MAC_REG_BASE + 0x648)
170 #define AR9170_MAC_REG_RX_PE_DELAY (AR9170_MAC_REG_BASE + 0x64c)
171
172 #define AR9170_MAC_REG_DYNAMIC_SIFS_ACK (AR9170_MAC_REG_BASE + 0x658)
173 #define AR9170_MAC_REG_SNIFFER (AR9170_MAC_REG_BASE + 0x674)
174 #define AR9170_MAC_SNIFFER_ENABLE_PROMISC BIT(0)
175 #define AR9170_MAC_SNIFFER_DEFAULTS 0x02000000
176 #define AR9170_MAC_REG_ENCRYPTION (AR9170_MAC_REG_BASE + 0x678)
177 #define AR9170_MAC_ENCRYPTION_MGMT_RX_SOFTWARE BIT(2)
178 #define AR9170_MAC_ENCRYPTION_RX_SOFTWARE BIT(3)
179 #define AR9170_MAC_ENCRYPTION_DEFAULTS 0x70
180
181 #define AR9170_MAC_REG_MISC_680 (AR9170_MAC_REG_BASE + 0x680)
182 #define AR9170_MAC_REG_MISC_684 (AR9170_MAC_REG_BASE + 0x684)
183 #define AR9170_MAC_REG_TX_UNDERRUN (AR9170_MAC_REG_BASE + 0x688)
184
185 #define AR9170_MAC_REG_FRAMETYPE_FILTER (AR9170_MAC_REG_BASE + 0x68c)
186 #define AR9170_MAC_FTF_ASSOC_REQ BIT(0)
187 #define AR9170_MAC_FTF_ASSOC_RESP BIT(1)
188 #define AR9170_MAC_FTF_REASSOC_REQ BIT(2)
189 #define AR9170_MAC_FTF_REASSOC_RESP BIT(3)
190 #define AR9170_MAC_FTF_PRB_REQ BIT(4)
191 #define AR9170_MAC_FTF_PRB_RESP BIT(5)
192 #define AR9170_MAC_FTF_BIT6 BIT(6)
193 #define AR9170_MAC_FTF_BIT7 BIT(7)
194 #define AR9170_MAC_FTF_BEACON BIT(8)
195 #define AR9170_MAC_FTF_ATIM BIT(9)
196 #define AR9170_MAC_FTF_DEASSOC BIT(10)
197 #define AR9170_MAC_FTF_AUTH BIT(11)
198 #define AR9170_MAC_FTF_DEAUTH BIT(12)
199 #define AR9170_MAC_FTF_BIT13 BIT(13)
200 #define AR9170_MAC_FTF_BIT14 BIT(14)
201 #define AR9170_MAC_FTF_BIT15 BIT(15)
202 #define AR9170_MAC_FTF_BAR BIT(24)
203 #define AR9170_MAC_FTF_BA BIT(25)
204 #define AR9170_MAC_FTF_PSPOLL BIT(26)
205 #define AR9170_MAC_FTF_RTS BIT(27)
206 #define AR9170_MAC_FTF_CTS BIT(28)
207 #define AR9170_MAC_FTF_ACK BIT(29)
208 #define AR9170_MAC_FTF_CFE BIT(30)
209 #define AR9170_MAC_FTF_CFE_ACK BIT(31)
210 #define AR9170_MAC_FTF_DEFAULTS 0x0500ffff
211 #define AR9170_MAC_FTF_MONITOR 0xff00ffff
212
213 #define AR9170_MAC_REG_ACK_EXTENSION (AR9170_MAC_REG_BASE + 0x690)
214 #define AR9170_MAC_REG_ACK_TPC (AR9170_MAC_REG_BASE + 0x694)
215 #define AR9170_MAC_REG_EIFS_AND_SIFS (AR9170_MAC_REG_BASE + 0x698)
216 #define AR9170_MAC_REG_RX_TIMEOUT_COUNT (AR9170_MAC_REG_BASE + 0x69c)
217 #define AR9170_MAC_REG_RX_TOTAL (AR9170_MAC_REG_BASE + 0x6a0)
218 #define AR9170_MAC_REG_RX_CRC32 (AR9170_MAC_REG_BASE + 0x6a4)
219 #define AR9170_MAC_REG_RX_CRC16 (AR9170_MAC_REG_BASE + 0x6a8)
220 #define AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI (AR9170_MAC_REG_BASE + 0x6ac)
221 #define AR9170_MAC_REG_RX_OVERRUN (AR9170_MAC_REG_BASE + 0x6b0)
222 #define AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL (AR9170_MAC_REG_BASE + 0x6bc)
223 #define AR9170_MAC_REG_TX_BLOCKACKS (AR9170_MAC_REG_BASE + 0x6c0)
224 #define AR9170_MAC_REG_NAV_COUNT (AR9170_MAC_REG_BASE + 0x6c4)
225 #define AR9170_MAC_REG_BACKOFF_STATUS (AR9170_MAC_REG_BASE + 0x6c8)
226 #define AR9170_MAC_BACKOFF_CCA BIT(24)
227 #define AR9170_MAC_BACKOFF_TX_PEX BIT(25)
228 #define AR9170_MAC_BACKOFF_RX_PE BIT(26)
229 #define AR9170_MAC_BACKOFF_MD_READY BIT(27)
230 #define AR9170_MAC_BACKOFF_TX_PE BIT(28)
231
232 #define AR9170_MAC_REG_TX_RETRY (AR9170_MAC_REG_BASE + 0x6cc)
233
234 #define AR9170_MAC_REG_TX_COMPLETE (AR9170_MAC_REG_BASE + 0x6d4)
235
236 #define AR9170_MAC_REG_CHANNEL_BUSY (AR9170_MAC_REG_BASE + 0x6e8)
237 #define AR9170_MAC_REG_EXT_BUSY (AR9170_MAC_REG_BASE + 0x6ec)
238
239 #define AR9170_MAC_REG_SLOT_TIME (AR9170_MAC_REG_BASE + 0x6f0)
240 #define AR9170_MAC_REG_TX_TOTAL (AR9170_MAC_REG_BASE + 0x6f4)
241 #define AR9170_MAC_REG_ACK_FC (AR9170_MAC_REG_BASE + 0x6f8)
242
243 #define AR9170_MAC_REG_CAM_MODE (AR9170_MAC_REG_BASE + 0x700)
244 #define AR9170_MAC_CAM_IBSS 0xe0
245 #define AR9170_MAC_CAM_AP 0xa1
246 #define AR9170_MAC_CAM_STA 0x2
247 #define AR9170_MAC_CAM_AP_WDS 0x3
248 #define AR9170_MAC_CAM_DEFAULTS (0xf << 24)
249 #define AR9170_MAC_CAM_HOST_PENDING 0x80000000
250
251 #define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_L (AR9170_MAC_REG_BASE + 0x704)
252 #define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_H (AR9170_MAC_REG_BASE + 0x708)
253
254 #define AR9170_MAC_REG_CAM_ADDR (AR9170_MAC_REG_BASE + 0x70c)
255 #define AR9170_MAC_CAM_ADDR_WRITE 0x80000000
256 #define AR9170_MAC_REG_CAM_DATA0 (AR9170_MAC_REG_BASE + 0x720)
257 #define AR9170_MAC_REG_CAM_DATA1 (AR9170_MAC_REG_BASE + 0x724)
258 #define AR9170_MAC_REG_CAM_DATA2 (AR9170_MAC_REG_BASE + 0x728)
259 #define AR9170_MAC_REG_CAM_DATA3 (AR9170_MAC_REG_BASE + 0x72c)
260
261 #define AR9170_MAC_REG_CAM_DBG0 (AR9170_MAC_REG_BASE + 0x730)
262 #define AR9170_MAC_REG_CAM_DBG1 (AR9170_MAC_REG_BASE + 0x734)
263 #define AR9170_MAC_REG_CAM_DBG2 (AR9170_MAC_REG_BASE + 0x738)
264 #define AR9170_MAC_REG_CAM_STATE (AR9170_MAC_REG_BASE + 0x73c)
265 #define AR9170_MAC_CAM_STATE_READ_PENDING 0x40000000
266 #define AR9170_MAC_CAM_STATE_WRITE_PENDING 0x80000000
267
268 #define AR9170_MAC_REG_CAM_TXKEY (AR9170_MAC_REG_BASE + 0x740)
269 #define AR9170_MAC_REG_CAM_RXKEY (AR9170_MAC_REG_BASE + 0x750)
270
271 #define AR9170_MAC_REG_CAM_TX_ENC_TYPE (AR9170_MAC_REG_BASE + 0x760)
272 #define AR9170_MAC_REG_CAM_RX_ENC_TYPE (AR9170_MAC_REG_BASE + 0x770)
273 #define AR9170_MAC_REG_CAM_TX_SERACH_HIT (AR9170_MAC_REG_BASE + 0x780)
274 #define AR9170_MAC_REG_CAM_RX_SERACH_HIT (AR9170_MAC_REG_BASE + 0x790)
275
276 #define AR9170_MAC_REG_AC0_CW (AR9170_MAC_REG_BASE + 0xb00)
277 #define AR9170_MAC_REG_AC1_CW (AR9170_MAC_REG_BASE + 0xb04)
278 #define AR9170_MAC_REG_AC2_CW (AR9170_MAC_REG_BASE + 0xb08)
279 #define AR9170_MAC_REG_AC3_CW (AR9170_MAC_REG_BASE + 0xb0c)
280 #define AR9170_MAC_REG_AC4_CW (AR9170_MAC_REG_BASE + 0xb10)
281 #define AR9170_MAC_REG_AC2_AC1_AC0_AIFS (AR9170_MAC_REG_BASE + 0xb14)
282 #define AR9170_MAC_REG_AC4_AC3_AC2_AIFS (AR9170_MAC_REG_BASE + 0xb18)
283 #define AR9170_MAC_REG_TXOP_ACK_EXTENSION (AR9170_MAC_REG_BASE + 0xb1c)
284 #define AR9170_MAC_REG_TXOP_ACK_INTERVAL (AR9170_MAC_REG_BASE + 0xb20)
285 #define AR9170_MAC_REG_CONTENTION_POINT (AR9170_MAC_REG_BASE + 0xb24)
286 #define AR9170_MAC_REG_RETRY_MAX (AR9170_MAC_REG_BASE + 0xb28)
287 #define AR9170_MAC_REG_TID_CFACK_CFEND_RATE (AR9170_MAC_REG_BASE + 0xb2c)
288 #define AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND (AR9170_MAC_REG_BASE + 0xb30)
289 #define AR9170_MAC_REG_TKIP_TSC (AR9170_MAC_REG_BASE + 0xb34)
290 #define AR9170_MAC_REG_TXOP_DURATION (AR9170_MAC_REG_BASE + 0xb38)
291 #define AR9170_MAC_REG_TX_QOS_THRESHOLD (AR9170_MAC_REG_BASE + 0xb3c)
292 #define AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA (AR9170_MAC_REG_BASE + 0xb40)
293 #define AR9170_MAC_VIRTUAL_CCA_Q0 BIT(15)
294 #define AR9170_MAC_VIRTUAL_CCA_Q1 BIT(16)
295 #define AR9170_MAC_VIRTUAL_CCA_Q2 BIT(17)
296 #define AR9170_MAC_VIRTUAL_CCA_Q3 BIT(18)
297 #define AR9170_MAC_VIRTUAL_CCA_Q4 BIT(19)
298 #define AR9170_MAC_VIRTUAL_CCA_ALL (0xf8000)
299
300 #define AR9170_MAC_REG_AC1_AC0_TXOP (AR9170_MAC_REG_BASE + 0xb44)
301 #define AR9170_MAC_REG_AC3_AC2_TXOP (AR9170_MAC_REG_BASE + 0xb48)
302
303 #define AR9170_MAC_REG_AMPDU_COUNT (AR9170_MAC_REG_BASE + 0xb88)
304 #define AR9170_MAC_REG_MPDU_COUNT (AR9170_MAC_REG_BASE + 0xb8c)
305
306 #define AR9170_MAC_REG_AMPDU_FACTOR (AR9170_MAC_REG_BASE + 0xb9c)
307 #define AR9170_MAC_AMPDU_FACTOR 0x7f0000
308 #define AR9170_MAC_AMPDU_FACTOR_S 16
309 #define AR9170_MAC_REG_AMPDU_DENSITY (AR9170_MAC_REG_BASE + 0xba0)
310 #define AR9170_MAC_AMPDU_DENSITY 0x7
311 #define AR9170_MAC_AMPDU_DENSITY_S 0
312
313 #define AR9170_MAC_REG_FCS_SELECT (AR9170_MAC_REG_BASE + 0xbb0)
314 #define AR9170_MAC_FCS_SWFCS 0x1
315 #define AR9170_MAC_FCS_FIFO_PROT 0x4
316
317 #define AR9170_MAC_REG_RTS_CTS_TPC (AR9170_MAC_REG_BASE + 0xbb4)
318 #define AR9170_MAC_REG_CFEND_QOSNULL_TPC (AR9170_MAC_REG_BASE + 0xbb8)
319
320 #define AR9170_MAC_REG_ACK_TABLE (AR9170_MAC_REG_BASE + 0xc00)
321 #define AR9170_MAC_REG_RX_CONTROL (AR9170_MAC_REG_BASE + 0xc40)
322 #define AR9170_MAC_RX_CTRL_DEAGG 0x1
323 #define AR9170_MAC_RX_CTRL_SHORT_FILTER 0x2
324 #define AR9170_MAC_RX_CTRL_SA_DA_SEARCH 0x20
325 #define AR9170_MAC_RX_CTRL_PASS_TO_HOST BIT(28)
326 #define AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER BIT(30)
327
328 #define AR9170_MAC_REG_RX_CONTROL_1 (AR9170_MAC_REG_BASE + 0xc44)
329
330 #define AR9170_MAC_REG_AMPDU_RX_THRESH (AR9170_MAC_REG_BASE + 0xc50)
331
332 #define AR9170_MAC_REG_RX_MPDU (AR9170_MAC_REG_BASE + 0xca0)
333 #define AR9170_MAC_REG_RX_DROPPED_MPDU (AR9170_MAC_REG_BASE + 0xca4)
334 #define AR9170_MAC_REG_RX_DEL_MPDU (AR9170_MAC_REG_BASE + 0xca8)
335 #define AR9170_MAC_REG_RX_PHY_MISC_ERROR (AR9170_MAC_REG_BASE + 0xcac)
336 #define AR9170_MAC_REG_RX_PHY_XR_ERROR (AR9170_MAC_REG_BASE + 0xcb0)
337 #define AR9170_MAC_REG_RX_PHY_OFDM_ERROR (AR9170_MAC_REG_BASE + 0xcb4)
338 #define AR9170_MAC_REG_RX_PHY_CCK_ERROR (AR9170_MAC_REG_BASE + 0xcb8)
339 #define AR9170_MAC_REG_RX_PHY_HT_ERROR (AR9170_MAC_REG_BASE + 0xcbc)
340 #define AR9170_MAC_REG_RX_PHY_TOTAL (AR9170_MAC_REG_BASE + 0xcc0)
341
342 #define AR9170_MAC_REG_DMA_TXQ_ADDR (AR9170_MAC_REG_BASE + 0xd00)
343 #define AR9170_MAC_REG_DMA_TXQ_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd04)
344 #define AR9170_MAC_REG_DMA_TXQ0_ADDR (AR9170_MAC_REG_BASE + 0xd00)
345 #define AR9170_MAC_REG_DMA_TXQ0_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd04)
346 #define AR9170_MAC_REG_DMA_TXQ1_ADDR (AR9170_MAC_REG_BASE + 0xd08)
347 #define AR9170_MAC_REG_DMA_TXQ1_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd0c)
348 #define AR9170_MAC_REG_DMA_TXQ2_ADDR (AR9170_MAC_REG_BASE + 0xd10)
349 #define AR9170_MAC_REG_DMA_TXQ2_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd14)
350 #define AR9170_MAC_REG_DMA_TXQ3_ADDR (AR9170_MAC_REG_BASE + 0xd18)
351 #define AR9170_MAC_REG_DMA_TXQ3_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd1c)
352 #define AR9170_MAC_REG_DMA_TXQ4_ADDR (AR9170_MAC_REG_BASE + 0xd20)
353 #define AR9170_MAC_REG_DMA_TXQ4_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd24)
354 #define AR9170_MAC_REG_DMA_RXQ_ADDR (AR9170_MAC_REG_BASE + 0xd28)
355 #define AR9170_MAC_REG_DMA_RXQ_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd2c)
356
357 #define AR9170_MAC_REG_DMA_TRIGGER (AR9170_MAC_REG_BASE + 0xd30)
358 #define AR9170_DMA_TRIGGER_TXQ0 BIT(0)
359 #define AR9170_DMA_TRIGGER_TXQ1 BIT(1)
360 #define AR9170_DMA_TRIGGER_TXQ2 BIT(2)
361 #define AR9170_DMA_TRIGGER_TXQ3 BIT(3)
362 #define AR9170_DMA_TRIGGER_TXQ4 BIT(4)
363 #define AR9170_DMA_TRIGGER_RXQ BIT(8)
364
365 #define AR9170_MAC_REG_DMA_WLAN_STATUS (AR9170_MAC_REG_BASE + 0xd38)
366 #define AR9170_MAC_REG_DMA_STATUS (AR9170_MAC_REG_BASE + 0xd3c)
367 #define AR9170_MAC_REG_DMA_TXQ_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd40)
368 #define AR9170_MAC_REG_DMA_TXQ0_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd40)
369 #define AR9170_MAC_REG_DMA_TXQ1_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd44)
370 #define AR9170_MAC_REG_DMA_TXQ2_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd48)
371 #define AR9170_MAC_REG_DMA_TXQ3_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd4c)
372 #define AR9170_MAC_REG_DMA_TXQ4_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd50)
373 #define AR9170_MAC_REG_DMA_TXQ0Q1_LEN (AR9170_MAC_REG_BASE + 0xd54)
374 #define AR9170_MAC_REG_DMA_TXQ2Q3_LEN (AR9170_MAC_REG_BASE + 0xd58)
375 #define AR9170_MAC_REG_DMA_TXQ4_LEN (AR9170_MAC_REG_BASE + 0xd5c)
376
377 #define AR9170_MAC_REG_DMA_TXQX_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd74)
378 #define AR9170_MAC_REG_DMA_TXQX_FAIL_ADDR (AR9170_MAC_REG_BASE + 0xd78)
379 #define AR9170_MAC_REG_TXRX_MPI (AR9170_MAC_REG_BASE + 0xd7c)
380 #define AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f
381 #define AR9170_MAC_TXRX_MPI_TX_TO_MASK 0x0000fff0
382 #define AR9170_MAC_TXRX_MPI_RX_MPI_MASK 0x000f0000
383 #define AR9170_MAC_TXRX_MPI_RX_TO_MASK 0xfff00000
384
385 #define AR9170_MAC_REG_BCN_ADDR (AR9170_MAC_REG_BASE + 0xd84)
386 #define AR9170_MAC_REG_BCN_LENGTH (AR9170_MAC_REG_BASE + 0xd88)
387 #define AR9170_MAC_BCN_LENGTH_MAX (512 - 32)
388
389 #define AR9170_MAC_REG_BCN_STATUS (AR9170_MAC_REG_BASE + 0xd8c)
390
391 #define AR9170_MAC_REG_BCN_PLCP (AR9170_MAC_REG_BASE + 0xd90)
392 #define AR9170_MAC_REG_BCN_CTRL (AR9170_MAC_REG_BASE + 0xd94)
393 #define AR9170_BCN_CTRL_READY 0x01
394 #define AR9170_BCN_CTRL_LOCK 0x02
395
396 #define AR9170_MAC_REG_BCN_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd98)
397 #define AR9170_MAC_REG_BCN_COUNT (AR9170_MAC_REG_BASE + 0xd9c)
398 #define AR9170_MAC_REG_BCN_HT1 (AR9170_MAC_REG_BASE + 0xda0)
399 #define AR9170_MAC_BCN_HT1_HT_EN BIT(0)
400 #define AR9170_MAC_BCN_HT1_GF_PMB BIT(1)
401 #define AR9170_MAC_BCN_HT1_SP_EXP BIT(2)
402 #define AR9170_MAC_BCN_HT1_TX_BF BIT(3)
403 #define AR9170_MAC_BCN_HT1_PWR_CTRL_S 4
404 #define AR9170_MAC_BCN_HT1_PWR_CTRL 0x70
405 #define AR9170_MAC_BCN_HT1_TX_ANT1 BIT(7)
406 #define AR9170_MAC_BCN_HT1_TX_ANT0 BIT(8)
407 #define AR9170_MAC_BCN_HT1_NUM_LFT_S 9
408 #define AR9170_MAC_BCN_HT1_NUM_LFT 0x600
409 #define AR9170_MAC_BCN_HT1_BWC_20M_EXT BIT(16)
410 #define AR9170_MAC_BCN_HT1_BWC_40M_SHARED BIT(17)
411 #define AR9170_MAC_BCN_HT1_BWC_40M_DUP (BIT(16) | BIT(17))
412 #define AR9170_MAC_BCN_HT1_BF_MCS_S 18
413 #define AR9170_MAC_BCN_HT1_BF_MCS 0x1c0000
414 #define AR9170_MAC_BCN_HT1_TPC_S 21
415 #define AR9170_MAC_BCN_HT1_TPC 0x7e00000
416 #define AR9170_MAC_BCN_HT1_CHAIN_MASK_S 27
417 #define AR9170_MAC_BCN_HT1_CHAIN_MASK 0x38000000
418
419 #define AR9170_MAC_REG_BCN_HT2 (AR9170_MAC_REG_BASE + 0xda4)
420 #define AR9170_MAC_BCN_HT2_MCS_S 0
421 #define AR9170_MAC_BCN_HT2_MCS 0x7f
422 #define AR9170_MAC_BCN_HT2_BW40 BIT(8)
423 #define AR9170_MAC_BCN_HT2_SMOOTHING BIT(9)
424 #define AR9170_MAC_BCN_HT2_SS BIT(10)
425 #define AR9170_MAC_BCN_HT2_NSS BIT(11)
426 #define AR9170_MAC_BCN_HT2_STBC_S 12
427 #define AR9170_MAC_BCN_HT2_STBC 0x3000
428 #define AR9170_MAC_BCN_HT2_ADV_COD BIT(14)
429 #define AR9170_MAC_BCN_HT2_SGI BIT(15)
430 #define AR9170_MAC_BCN_HT2_LEN_S 16
431 #define AR9170_MAC_BCN_HT2_LEN 0xffff0000
432
433 #define AR9170_MAC_REG_DMA_TXQX_ADDR_CURR (AR9170_MAC_REG_BASE + 0xdc0)
434
435
436 #define AR9170_RAND_REG_BASE 0x1d0000
437
438 #define AR9170_RAND_REG_NUM (AR9170_RAND_REG_BASE + 0x000)
439 #define AR9170_RAND_REG_MODE (AR9170_RAND_REG_BASE + 0x004)
440 #define AR9170_RAND_MODE_MANUAL 0x000
441 #define AR9170_RAND_MODE_FREE 0x001
442
443
444 #define AR9170_GPIO_REG_BASE 0x1d0100
445 #define AR9170_GPIO_REG_PORT_TYPE (AR9170_GPIO_REG_BASE + 0x000)
446 #define AR9170_GPIO_REG_PORT_DATA (AR9170_GPIO_REG_BASE + 0x004)
447 #define AR9170_GPIO_PORT_LED_0 1
448 #define AR9170_GPIO_PORT_LED_1 2
449
450 #define AR9170_GPIO_PORT_WPS_BUTTON_PRESSED 4
451
452
453 #define AR9170_MC_REG_BASE 0x1d1000
454
455 #define AR9170_MC_REG_FLASH_WAIT_STATE (AR9170_MC_REG_BASE + 0x000)
456
457 #define AR9170_SPI_REG_BASE (AR9170_MC_REG_BASE + 0x200)
458 #define AR9170_SPI_REG_CONTROL0 (AR9170_SPI_REG_BASE + 0x000)
459 #define AR9170_SPI_CONTROL0_BUSY BIT(0)
460 #define AR9170_SPI_CONTROL0_CMD_GO BIT(1)
461 #define AR9170_SPI_CONTROL0_PAGE_WR BIT(2)
462 #define AR9170_SPI_CONTROL0_SEQ_RD BIT(3)
463 #define AR9170_SPI_CONTROL0_CMD_ABORT BIT(4)
464 #define AR9170_SPI_CONTROL0_CMD_LEN_S 8
465 #define AR9170_SPI_CONTROL0_CMD_LEN 0x00000f00
466 #define AR9170_SPI_CONTROL0_RD_LEN_S 12
467 #define AR9170_SPI_CONTROL0_RD_LEN 0x00007000
468
469 #define AR9170_SPI_REG_CONTROL1 (AR9170_SPI_REG_BASE + 0x004)
470 #define AR9170_SPI_CONTROL1_SCK_RATE BIT(0)
471 #define AR9170_SPI_CONTROL1_DRIVE_SDO BIT(1)
472 #define AR9170_SPI_CONTROL1_MODE_SEL_S 2
473 #define AR9170_SPI_CONTROL1_MODE_SEL 0x000000c0
474 #define AR9170_SPI_CONTROL1_WRITE_PROTECT BIT(4)
475
476 #define AR9170_SPI_REG_COMMAND_PORT0 (AR9170_SPI_REG_BASE + 0x008)
477 #define AR9170_SPI_COMMAND_PORT0_CMD0_S 0
478 #define AR9170_SPI_COMMAND_PORT0_CMD0 0x000000ff
479 #define AR9170_SPI_COMMAND_PORT0_CMD1_S 8
480 #define AR9170_SPI_COMMAND_PORT0_CMD1 0x0000ff00
481 #define AR9170_SPI_COMMAND_PORT0_CMD2_S 16
482 #define AR9170_SPI_COMMAND_PORT0_CMD2 0x00ff0000
483 #define AR9170_SPI_COMMAND_PORT0_CMD3_S 24
484 #define AR9170_SPI_COMMAND_PORT0_CMD3 0xff000000
485
486 #define AR9170_SPI_REG_COMMAND_PORT1 (AR9170_SPI_REG_BASE + 0x00C)
487 #define AR9170_SPI_COMMAND_PORT1_CMD4_S 0
488 #define AR9170_SPI_COMMAND_PORT1_CMD4 0x000000ff
489 #define AR9170_SPI_COMMAND_PORT1_CMD5_S 8
490 #define AR9170_SPI_COMMAND_PORT1_CMD5 0x0000ff00
491 #define AR9170_SPI_COMMAND_PORT1_CMD6_S 16
492 #define AR9170_SPI_COMMAND_PORT1_CMD6 0x00ff0000
493 #define AR9170_SPI_COMMAND_PORT1_CMD7_S 24
494 #define AR9170_SPI_COMMAND_PORT1_CMD7 0xff000000
495
496 #define AR9170_SPI_REG_DATA_PORT (AR9170_SPI_REG_BASE + 0x010)
497 #define AR9170_SPI_REG_PAGE_WRITE_LEN (AR9170_SPI_REG_BASE + 0x014)
498
499 #define AR9170_EEPROM_REG_BASE (AR9170_MC_REG_BASE + 0x400)
500 #define AR9170_EEPROM_REG_WP_MAGIC1 (AR9170_EEPROM_REG_BASE + 0x000)
501 #define AR9170_EEPROM_WP_MAGIC1 0x12345678
502
503 #define AR9170_EEPROM_REG_WP_MAGIC2 (AR9170_EEPROM_REG_BASE + 0x004)
504 #define AR9170_EEPROM_WP_MAGIC2 0x55aa00ff
505
506 #define AR9170_EEPROM_REG_WP_MAGIC3 (AR9170_EEPROM_REG_BASE + 0x008)
507 #define AR9170_EEPROM_WP_MAGIC3 0x13579ace
508
509 #define AR9170_EEPROM_REG_CLOCK_DIV (AR9170_EEPROM_REG_BASE + 0x00C)
510 #define AR9170_EEPROM_CLOCK_DIV_FAC_S 0
511 #define AR9170_EEPROM_CLOCK_DIV_FAC 0x000001ff
512 #define AR9170_EEPROM_CLOCK_DIV_FAC_39KHZ 0xff
513 #define AR9170_EEPROM_CLOCK_DIV_FAC_78KHZ 0x7f
514 #define AR9170_EEPROM_CLOCK_DIV_FAC_312KHZ 0x1f
515 #define AR9170_EEPROM_CLOCK_DIV_FAC_10MHZ 0x0
516 #define AR9170_EEPROM_CLOCK_DIV_SOFT_RST BIT(9)
517
518 #define AR9170_EEPROM_REG_MODE (AR9170_EEPROM_REG_BASE + 0x010)
519 #define AR9170_EEPROM_MODE_EEPROM_SIZE_16K_PLUS BIT(31)
520
521 #define AR9170_EEPROM_REG_WRITE_PROTECT (AR9170_EEPROM_REG_BASE + 0x014)
522 #define AR9170_EEPROM_WRITE_PROTECT_WP_STATUS BIT(0)
523 #define AR9170_EEPROM_WRITE_PROTECT_WP_SET BIT(8)
524
525
526 #define AR9170_MAX_INT_SRC 9
527 #define AR9170_INT_REG_BASE 0x1d2000
528
529 #define AR9170_INT_REG_FLAG (AR9170_INT_REG_BASE + 0x000)
530 #define AR9170_INT_REG_FIQ_MASK (AR9170_INT_REG_BASE + 0x004)
531 #define AR9170_INT_REG_IRQ_MASK (AR9170_INT_REG_BASE + 0x008)
532
533 #define AR9170_INT_FLAG_WLAN 0x001
534 #define AR9170_INT_FLAG_PTAB_BIT 0x002
535 #define AR9170_INT_FLAG_SE_BIT 0x004
536 #define AR9170_INT_FLAG_UART_BIT 0x008
537 #define AR9170_INT_FLAG_TIMER_BIT 0x010
538 #define AR9170_INT_FLAG_EXT_BIT 0x020
539 #define AR9170_INT_FLAG_SW_BIT 0x040
540 #define AR9170_INT_FLAG_USB_BIT 0x080
541 #define AR9170_INT_FLAG_ETHERNET_BIT 0x100
542
543 #define AR9170_INT_REG_PRIORITY1 (AR9170_INT_REG_BASE + 0x00c)
544 #define AR9170_INT_REG_PRIORITY2 (AR9170_INT_REG_BASE + 0x010)
545 #define AR9170_INT_REG_PRIORITY3 (AR9170_INT_REG_BASE + 0x014)
546 #define AR9170_INT_REG_EXT_INT_CONTROL (AR9170_INT_REG_BASE + 0x018)
547 #define AR9170_INT_REG_SW_INT_CONTROL (AR9170_INT_REG_BASE + 0x01c)
548 #define AR9170_INT_SW_INT_ENABLE 0x1
549
550 #define AR9170_INT_REG_FIQ_ENCODE (AR9170_INT_REG_BASE + 0x020)
551 #define AR9170_INT_INT_IRQ_ENCODE (AR9170_INT_REG_BASE + 0x024)
552
553
554 #define AR9170_PWR_REG_BASE 0x1d4000
555
556 #define AR9170_PWR_REG_POWER_STATE (AR9170_PWR_REG_BASE + 0x000)
557
558 #define AR9170_PWR_REG_RESET (AR9170_PWR_REG_BASE + 0x004)
559 #define AR9170_PWR_RESET_COMMIT_RESET_MASK BIT(0)
560 #define AR9170_PWR_RESET_WLAN_MASK BIT(1)
561 #define AR9170_PWR_RESET_DMA_MASK BIT(2)
562 #define AR9170_PWR_RESET_BRIDGE_MASK BIT(3)
563 #define AR9170_PWR_RESET_AHB_MASK BIT(9)
564 #define AR9170_PWR_RESET_BB_WARM_RESET BIT(10)
565 #define AR9170_PWR_RESET_BB_COLD_RESET BIT(11)
566 #define AR9170_PWR_RESET_ADDA_CLK_COLD_RESET BIT(12)
567 #define AR9170_PWR_RESET_PLL BIT(13)
568 #define AR9170_PWR_RESET_USB_PLL BIT(14)
569
570 #define AR9170_PWR_REG_CLOCK_SEL (AR9170_PWR_REG_BASE + 0x008)
571 #define AR9170_PWR_CLK_AHB_40MHZ 0
572 #define AR9170_PWR_CLK_AHB_20_22MHZ 1
573 #define AR9170_PWR_CLK_AHB_40_44MHZ 2
574 #define AR9170_PWR_CLK_AHB_80_88MHZ 3
575 #define AR9170_PWR_CLK_DAC_160_INV_DLY 0x70
576
577 #define AR9170_PWR_REG_CHIP_REVISION (AR9170_PWR_REG_BASE + 0x010)
578 #define AR9170_PWR_REG_PLL_ADDAC (AR9170_PWR_REG_BASE + 0x014)
579 #define AR9170_PWR_PLL_ADDAC_DIV_S 2
580 #define AR9170_PWR_PLL_ADDAC_DIV 0xffc
581 #define AR9170_PWR_REG_WATCH_DOG_MAGIC (AR9170_PWR_REG_BASE + 0x020)
582
583
584 #define AR9170_USB_REG_BASE 0x1e1000
585
586 #define AR9170_USB_REG_MAIN_CTRL (AR9170_USB_REG_BASE + 0x000)
587 #define AR9170_USB_MAIN_CTRL_REMOTE_WAKEUP BIT(0)
588 #define AR9170_USB_MAIN_CTRL_ENABLE_GLOBAL_INT BIT(2)
589 #define AR9170_USB_MAIN_CTRL_GO_TO_SUSPEND BIT(3)
590 #define AR9170_USB_MAIN_CTRL_RESET BIT(4)
591 #define AR9170_USB_MAIN_CTRL_CHIP_ENABLE BIT(5)
592 #define AR9170_USB_MAIN_CTRL_HIGHSPEED BIT(6)
593
594 #define AR9170_USB_REG_DEVICE_ADDRESS (AR9170_USB_REG_BASE + 0x001)
595 #define AR9170_USB_DEVICE_ADDRESS_CONFIGURE BIT(7)
596
597 #define AR9170_USB_REG_TEST (AR9170_USB_REG_BASE + 0x002)
598 #define AR9170_USB_REG_PHY_TEST_SELECT (AR9170_USB_REG_BASE + 0x008)
599 #define AR9170_USB_REG_CX_CONFIG_STATUS (AR9170_USB_REG_BASE + 0x00b)
600 #define AR9170_USB_REG_EP0_DATA (AR9170_USB_REG_BASE + 0x00c)
601 #define AR9170_USB_REG_EP0_DATA1 (AR9170_USB_REG_BASE + 0x00c)
602 #define AR9170_USB_REG_EP0_DATA2 (AR9170_USB_REG_BASE + 0x00d)
603
604 #define AR9170_USB_REG_INTR_MASK_BYTE_0 (AR9170_USB_REG_BASE + 0x011)
605 #define AR9170_USB_REG_INTR_MASK_BYTE_1 (AR9170_USB_REG_BASE + 0x012)
606 #define AR9170_USB_REG_INTR_MASK_BYTE_2 (AR9170_USB_REG_BASE + 0x013)
607 #define AR9170_USB_REG_INTR_MASK_BYTE_3 (AR9170_USB_REG_BASE + 0x014)
608 #define AR9170_USB_REG_INTR_MASK_BYTE_4 (AR9170_USB_REG_BASE + 0x015)
609 #define AR9170_USB_INTR_DISABLE_OUT_INT (BIT(7) | BIT(6))
610
611 #define AR9170_USB_REG_INTR_MASK_BYTE_5 (AR9170_USB_REG_BASE + 0x016)
612 #define AR9170_USB_REG_INTR_MASK_BYTE_6 (AR9170_USB_REG_BASE + 0x017)
613 #define AR9170_USB_INTR_DISABLE_IN_INT BIT(6)
614
615 #define AR9170_USB_REG_INTR_MASK_BYTE_7 (AR9170_USB_REG_BASE + 0x018)
616
617 #define AR9170_USB_REG_INTR_GROUP (AR9170_USB_REG_BASE + 0x020)
618
619 #define AR9170_USB_REG_INTR_SOURCE_0 (AR9170_USB_REG_BASE + 0x021)
620 #define AR9170_USB_INTR_SRC0_SETUP BIT(0)
621 #define AR9170_USB_INTR_SRC0_IN BIT(1)
622 #define AR9170_USB_INTR_SRC0_OUT BIT(2)
623 #define AR9170_USB_INTR_SRC0_FAIL BIT(3)
624 #define AR9170_USB_INTR_SRC0_END BIT(4)
625 #define AR9170_USB_INTR_SRC0_ABORT BIT(7)
626
627 #define AR9170_USB_REG_INTR_SOURCE_1 (AR9170_USB_REG_BASE + 0x022)
628 #define AR9170_USB_REG_INTR_SOURCE_2 (AR9170_USB_REG_BASE + 0x023)
629 #define AR9170_USB_REG_INTR_SOURCE_3 (AR9170_USB_REG_BASE + 0x024)
630 #define AR9170_USB_REG_INTR_SOURCE_4 (AR9170_USB_REG_BASE + 0x025)
631 #define AR9170_USB_REG_INTR_SOURCE_5 (AR9170_USB_REG_BASE + 0x026)
632 #define AR9170_USB_REG_INTR_SOURCE_6 (AR9170_USB_REG_BASE + 0x027)
633 #define AR9170_USB_REG_INTR_SOURCE_7 (AR9170_USB_REG_BASE + 0x028)
634 #define AR9170_USB_INTR_SRC7_USB_RESET BIT(1)
635 #define AR9170_USB_INTR_SRC7_USB_SUSPEND BIT(2)
636 #define AR9170_USB_INTR_SRC7_USB_RESUME BIT(3)
637 #define AR9170_USB_INTR_SRC7_ISO_SEQ_ERR BIT(4)
638 #define AR9170_USB_INTR_SRC7_ISO_SEQ_ABORT BIT(5)
639 #define AR9170_USB_INTR_SRC7_TX0BYTE BIT(6)
640 #define AR9170_USB_INTR_SRC7_RX0BYTE BIT(7)
641
642 #define AR9170_USB_REG_IDLE_COUNT (AR9170_USB_REG_BASE + 0x02f)
643
644 #define AR9170_USB_REG_EP_MAP (AR9170_USB_REG_BASE + 0x030)
645 #define AR9170_USB_REG_EP1_MAP (AR9170_USB_REG_BASE + 0x030)
646 #define AR9170_USB_REG_EP2_MAP (AR9170_USB_REG_BASE + 0x031)
647 #define AR9170_USB_REG_EP3_MAP (AR9170_USB_REG_BASE + 0x032)
648 #define AR9170_USB_REG_EP4_MAP (AR9170_USB_REG_BASE + 0x033)
649 #define AR9170_USB_REG_EP5_MAP (AR9170_USB_REG_BASE + 0x034)
650 #define AR9170_USB_REG_EP6_MAP (AR9170_USB_REG_BASE + 0x035)
651 #define AR9170_USB_REG_EP7_MAP (AR9170_USB_REG_BASE + 0x036)
652 #define AR9170_USB_REG_EP8_MAP (AR9170_USB_REG_BASE + 0x037)
653 #define AR9170_USB_REG_EP9_MAP (AR9170_USB_REG_BASE + 0x038)
654 #define AR9170_USB_REG_EP10_MAP (AR9170_USB_REG_BASE + 0x039)
655
656 #define AR9170_USB_REG_EP_IN_MAX_SIZE_HIGH (AR9170_USB_REG_BASE + 0x03f)
657 #define AR9170_USB_EP_IN_STALL 0x8
658 #define AR9170_USB_EP_IN_TOGGLE 0x10
659
660 #define AR9170_USB_REG_EP_IN_MAX_SIZE_LOW (AR9170_USB_REG_BASE + 0x03e)
661
662 #define AR9170_USB_REG_EP_OUT_MAX_SIZE_HIGH (AR9170_USB_REG_BASE + 0x05f)
663 #define AR9170_USB_EP_OUT_STALL 0x8
664 #define AR9170_USB_EP_OUT_TOGGLE 0x10
665
666 #define AR9170_USB_REG_EP_OUT_MAX_SIZE_LOW (AR9170_USB_REG_BASE + 0x05e)
667
668 #define AR9170_USB_REG_EP3_BYTE_COUNT_HIGH (AR9170_USB_REG_BASE + 0x0ae)
669 #define AR9170_USB_REG_EP3_BYTE_COUNT_LOW (AR9170_USB_REG_BASE + 0x0be)
670 #define AR9170_USB_REG_EP4_BYTE_COUNT_HIGH (AR9170_USB_REG_BASE + 0x0af)
671 #define AR9170_USB_REG_EP4_BYTE_COUNT_LOW (AR9170_USB_REG_BASE + 0x0bf)
672
673 #define AR9170_USB_REG_FIFO_MAP (AR9170_USB_REG_BASE + 0x080)
674 #define AR9170_USB_REG_FIFO0_MAP (AR9170_USB_REG_BASE + 0x080)
675 #define AR9170_USB_REG_FIFO1_MAP (AR9170_USB_REG_BASE + 0x081)
676 #define AR9170_USB_REG_FIFO2_MAP (AR9170_USB_REG_BASE + 0x082)
677 #define AR9170_USB_REG_FIFO3_MAP (AR9170_USB_REG_BASE + 0x083)
678 #define AR9170_USB_REG_FIFO4_MAP (AR9170_USB_REG_BASE + 0x084)
679 #define AR9170_USB_REG_FIFO5_MAP (AR9170_USB_REG_BASE + 0x085)
680 #define AR9170_USB_REG_FIFO6_MAP (AR9170_USB_REG_BASE + 0x086)
681 #define AR9170_USB_REG_FIFO7_MAP (AR9170_USB_REG_BASE + 0x087)
682 #define AR9170_USB_REG_FIFO8_MAP (AR9170_USB_REG_BASE + 0x088)
683 #define AR9170_USB_REG_FIFO9_MAP (AR9170_USB_REG_BASE + 0x089)
684
685 #define AR9170_USB_REG_FIFO_CONFIG (AR9170_USB_REG_BASE + 0x090)
686 #define AR9170_USB_REG_FIFO0_CONFIG (AR9170_USB_REG_BASE + 0x090)
687 #define AR9170_USB_REG_FIFO1_CONFIG (AR9170_USB_REG_BASE + 0x091)
688 #define AR9170_USB_REG_FIFO2_CONFIG (AR9170_USB_REG_BASE + 0x092)
689 #define AR9170_USB_REG_FIFO3_CONFIG (AR9170_USB_REG_BASE + 0x093)
690 #define AR9170_USB_REG_FIFO4_CONFIG (AR9170_USB_REG_BASE + 0x094)
691 #define AR9170_USB_REG_FIFO5_CONFIG (AR9170_USB_REG_BASE + 0x095)
692 #define AR9170_USB_REG_FIFO6_CONFIG (AR9170_USB_REG_BASE + 0x096)
693 #define AR9170_USB_REG_FIFO7_CONFIG (AR9170_USB_REG_BASE + 0x097)
694 #define AR9170_USB_REG_FIFO8_CONFIG (AR9170_USB_REG_BASE + 0x098)
695 #define AR9170_USB_REG_FIFO9_CONFIG (AR9170_USB_REG_BASE + 0x099)
696
697 #define AR9170_USB_REG_EP3_DATA (AR9170_USB_REG_BASE + 0x0f8)
698 #define AR9170_USB_REG_EP4_DATA (AR9170_USB_REG_BASE + 0x0fc)
699
700 #define AR9170_USB_REG_FIFO_SIZE (AR9170_USB_REG_BASE + 0x100)
701 #define AR9170_USB_REG_DMA_CTL (AR9170_USB_REG_BASE + 0x108)
702 #define AR9170_USB_DMA_CTL_ENABLE_TO_DEVICE BIT(0)
703 #define AR9170_USB_DMA_CTL_ENABLE_FROM_DEVICE BIT(1)
704 #define AR9170_USB_DMA_CTL_HIGH_SPEED BIT(2)
705 #define AR9170_USB_DMA_CTL_UP_PACKET_MODE BIT(3)
706 #define AR9170_USB_DMA_CTL_UP_STREAM_S 4
707 #define AR9170_USB_DMA_CTL_UP_STREAM (BIT(4) | BIT(5))
708 #define AR9170_USB_DMA_CTL_UP_STREAM_4K (0)
709 #define AR9170_USB_DMA_CTL_UP_STREAM_8K BIT(4)
710 #define AR9170_USB_DMA_CTL_UP_STREAM_16K BIT(5)
711 #define AR9170_USB_DMA_CTL_UP_STREAM_32K (BIT(4) | BIT(5))
712 #define AR9170_USB_DMA_CTL_DOWN_STREAM BIT(6)
713
714 #define AR9170_USB_REG_DMA_STATUS (AR9170_USB_REG_BASE + 0x10c)
715 #define AR9170_USB_DMA_STATUS_UP_IDLE BIT(8)
716 #define AR9170_USB_DMA_STATUS_DN_IDLE BIT(16)
717
718 #define AR9170_USB_REG_MAX_AGG_UPLOAD (AR9170_USB_REG_BASE + 0x110)
719 #define AR9170_USB_REG_UPLOAD_TIME_CTL (AR9170_USB_REG_BASE + 0x114)
720
721 #define AR9170_USB_REG_WAKE_UP (AR9170_USB_REG_BASE + 0x120)
722 #define AR9170_USB_WAKE_UP_WAKE BIT(0)
723
724 #define AR9170_USB_REG_CBUS_CTRL (AR9170_USB_REG_BASE + 0x1f0)
725 #define AR9170_USB_CBUS_CTRL_BUFFER_END (BIT(1))
726
727
728 #define AR9170_PTA_REG_BASE 0x1e2000
729
730 #define AR9170_PTA_REG_CMD (AR9170_PTA_REG_BASE + 0x000)
731 #define AR9170_PTA_REG_PARAM1 (AR9170_PTA_REG_BASE + 0x004)
732 #define AR9170_PTA_REG_PARAM2 (AR9170_PTA_REG_BASE + 0x008)
733 #define AR9170_PTA_REG_PARAM3 (AR9170_PTA_REG_BASE + 0x00c)
734 #define AR9170_PTA_REG_RSP (AR9170_PTA_REG_BASE + 0x010)
735 #define AR9170_PTA_REG_STATUS1 (AR9170_PTA_REG_BASE + 0x014)
736 #define AR9170_PTA_REG_STATUS2 (AR9170_PTA_REG_BASE + 0x018)
737 #define AR9170_PTA_REG_STATUS3 (AR9170_PTA_REG_BASE + 0x01c)
738 #define AR9170_PTA_REG_AHB_INT_FLAG (AR9170_PTA_REG_BASE + 0x020)
739 #define AR9170_PTA_REG_AHB_INT_MASK (AR9170_PTA_REG_BASE + 0x024)
740 #define AR9170_PTA_REG_AHB_INT_ACK (AR9170_PTA_REG_BASE + 0x028)
741 #define AR9170_PTA_REG_AHB_SCRATCH1 (AR9170_PTA_REG_BASE + 0x030)
742 #define AR9170_PTA_REG_AHB_SCRATCH2 (AR9170_PTA_REG_BASE + 0x034)
743 #define AR9170_PTA_REG_AHB_SCRATCH3 (AR9170_PTA_REG_BASE + 0x038)
744 #define AR9170_PTA_REG_AHB_SCRATCH4 (AR9170_PTA_REG_BASE + 0x03c)
745
746 #define AR9170_PTA_REG_SHARE_MEM_CTRL (AR9170_PTA_REG_BASE + 0x124)
747
748
749
750
751
752 #define AR9170_PTA_REG_INT_FLAG (AR9170_PTA_REG_BASE + 0x100)
753 #define AR9170_PTA_INT_FLAG_DN 0x01
754 #define AR9170_PTA_INT_FLAG_UP 0x02
755 #define AR9170_PTA_INT_FLAG_CMD 0x04
756
757 #define AR9170_PTA_REG_INT_MASK (AR9170_PTA_REG_BASE + 0x104)
758 #define AR9170_PTA_REG_DN_DMA_ADDRL (AR9170_PTA_REG_BASE + 0x108)
759 #define AR9170_PTA_REG_DN_DMA_ADDRH (AR9170_PTA_REG_BASE + 0x10c)
760 #define AR9170_PTA_REG_UP_DMA_ADDRL (AR9170_PTA_REG_BASE + 0x110)
761 #define AR9170_PTA_REG_UP_DMA_ADDRH (AR9170_PTA_REG_BASE + 0x114)
762 #define AR9170_PTA_REG_DN_PEND_TIME (AR9170_PTA_REG_BASE + 0x118)
763 #define AR9170_PTA_REG_UP_PEND_TIME (AR9170_PTA_REG_BASE + 0x11c)
764 #define AR9170_PTA_REG_CONTROL (AR9170_PTA_REG_BASE + 0x120)
765 #define AR9170_PTA_CTRL_4_BEAT_BURST 0x00
766 #define AR9170_PTA_CTRL_8_BEAT_BURST 0x01
767 #define AR9170_PTA_CTRL_16_BEAT_BURST 0x02
768 #define AR9170_PTA_CTRL_LOOPBACK_MODE 0x10
769
770 #define AR9170_PTA_REG_MEM_CTRL (AR9170_PTA_REG_BASE + 0x124)
771 #define AR9170_PTA_REG_MEM_ADDR (AR9170_PTA_REG_BASE + 0x128)
772 #define AR9170_PTA_REG_DN_DMA_TRIGGER (AR9170_PTA_REG_BASE + 0x12c)
773 #define AR9170_PTA_REG_UP_DMA_TRIGGER (AR9170_PTA_REG_BASE + 0x130)
774 #define AR9170_PTA_REG_DMA_STATUS (AR9170_PTA_REG_BASE + 0x134)
775 #define AR9170_PTA_REG_DN_CURR_ADDRL (AR9170_PTA_REG_BASE + 0x138)
776 #define AR9170_PTA_REG_DN_CURR_ADDRH (AR9170_PTA_REG_BASE + 0x13c)
777 #define AR9170_PTA_REG_UP_CURR_ADDRL (AR9170_PTA_REG_BASE + 0x140)
778 #define AR9170_PTA_REG_UP_CURR_ADDRH (AR9170_PTA_REG_BASE + 0x144)
779 #define AR9170_PTA_REG_DMA_MODE_CTRL (AR9170_PTA_REG_BASE + 0x148)
780 #define AR9170_PTA_DMA_MODE_CTRL_RESET BIT(0)
781 #define AR9170_PTA_DMA_MODE_CTRL_DISABLE_USB BIT(1)
782
783
784 #define AR9170_MAC_REG_PC_REG_BASE (AR9170_MAC_REG_BASE + 0xe00)
785
786
787 #define AR9170_NUM_LEDS 2
788
789
790 #define AR9170_CAM_MAX_USER 64
791 #define AR9170_CAM_MAX_KEY_LENGTH 16
792
793 #define AR9170_SRAM_OFFSET 0x100000
794 #define AR9170_SRAM_SIZE 0x18000
795
796 #define AR9170_PRAM_OFFSET 0x200000
797 #define AR9170_PRAM_SIZE 0x8000
798
799 enum cpu_clock {
800 AHB_STATIC_40MHZ = 0,
801 AHB_GMODE_22MHZ = 1,
802 AHB_AMODE_20MHZ = 1,
803 AHB_GMODE_44MHZ = 2,
804 AHB_AMODE_40MHZ = 2,
805 AHB_GMODE_88MHZ = 3,
806 AHB_AMODE_80MHZ = 3
807 };
808
809
810 enum ar9170_usb_ep {
811
812
813
814
815
816
817
818 AR9170_USB_EP_CTRL = 0,
819
820 AR9170_USB_EP_TX,
821 AR9170_USB_EP_RX,
822 AR9170_USB_EP_IRQ,
823 AR9170_USB_EP_CMD,
824 AR9170_USB_NUM_EXTRA_EP = 4,
825
826 __AR9170_USB_NUM_EP,
827
828 __AR9170_USB_NUM_MAX_EP = 10
829 };
830
831 enum ar9170_usb_fifo {
832 __AR9170_USB_NUM_MAX_FIFO = 10
833 };
834
835 enum ar9170_tx_queues {
836 AR9170_TXQ0 = 0,
837 AR9170_TXQ1,
838 AR9170_TXQ2,
839 AR9170_TXQ3,
840 AR9170_TXQ_SPECIAL,
841
842
843 __AR9170_NUM_TX_QUEUES = 5
844 };
845
846 #define AR9170_TX_STREAM_TAG 0x697e
847 #define AR9170_RX_STREAM_TAG 0x4e00
848 #define AR9170_RX_STREAM_MAX_SIZE 0xffff
849
850 struct ar9170_stream {
851 __le16 length;
852 __le16 tag;
853
854 u8 payload[0];
855 } __packed __aligned(4);
856 #define AR9170_STREAM_LEN 4
857
858 #define AR9170_MAX_ACKTABLE_ENTRIES 8
859 #define AR9170_MAX_VIRTUAL_MAC 7
860
861 #define AR9170_USB_EP_CTRL_MAX 64
862 #define AR9170_USB_EP_TX_MAX 512
863 #define AR9170_USB_EP_RX_MAX 512
864 #define AR9170_USB_EP_IRQ_MAX 64
865 #define AR9170_USB_EP_CMD_MAX 64
866
867
868 #define CARL9170_PRETBTT_KUS 6
869
870 #define AR5416_MAX_RATE_POWER 63
871
872 #define SET_VAL(reg, value, newvalue) \
873 (value = ((value) & ~reg) | (((newvalue) << reg##_S) & reg))
874
875 #define SET_CONSTVAL(reg, newvalue) \
876 (((newvalue) << reg##_S) & reg)
877
878 #define MOD_VAL(reg, value, newvalue) \
879 (((value) & ~reg) | (((newvalue) << reg##_S) & reg))
880
881 #define GET_VAL(reg, value) \
882 (((value) & reg) >> reg##_S)
883
884 #endif