This source file includes following definitions.
- ath10k_bus_str
- ATH10K_SKB_CB
- ATH10K_SKB_RXCB
- host_interest_item_address
- ath10k_cal_mode_str
- ath10k_scan_state_str
- ath10k_peer_stats_enabled
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7
8 #ifndef _CORE_H_
9 #define _CORE_H_
10
11 #include <linux/completion.h>
12 #include <linux/if_ether.h>
13 #include <linux/types.h>
14 #include <linux/pci.h>
15 #include <linux/uuid.h>
16 #include <linux/time.h>
17
18 #include "htt.h"
19 #include "htc.h"
20 #include "hw.h"
21 #include "targaddrs.h"
22 #include "wmi.h"
23 #include "../ath.h"
24 #include "../regd.h"
25 #include "../dfs_pattern_detector.h"
26 #include "spectral.h"
27 #include "thermal.h"
28 #include "wow.h"
29 #include "swap.h"
30
31 #define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
32 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
33 #define WO(_f) ((_f##_OFFSET) >> 2)
34
35 #define ATH10K_SCAN_ID 0
36 #define ATH10K_SCAN_CHANNEL_SWITCH_WMI_EVT_OVERHEAD 10
37 #define WMI_READY_TIMEOUT (5 * HZ)
38 #define ATH10K_FLUSH_TIMEOUT_HZ (5 * HZ)
39 #define ATH10K_CONNECTION_LOSS_HZ (3 * HZ)
40 #define ATH10K_NUM_CHANS 41
41 #define ATH10K_MAX_5G_CHAN 173
42
43
44 #define ATH10K_DEFAULT_NOISE_FLOOR -95
45
46 #define ATH10K_INVALID_RSSI 128
47
48 #define ATH10K_MAX_NUM_MGMT_PENDING 128
49
50
51 #define ATH10K_KICKOUT_THRESHOLD (20 * 16)
52
53
54
55
56
57
58 #define ATH10K_KEEPALIVE_MIN_IDLE 3747
59 #define ATH10K_KEEPALIVE_MAX_IDLE 3895
60 #define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900
61
62
63 #define ATH10K_NAPI_BUDGET 64
64
65
66 #define ATH10K_SMBIOS_BDF_EXT_TYPE 0xF8
67
68
69 #define ATH10K_SMBIOS_BDF_EXT_LENGTH 0x9
70
71
72 #define ATH10K_SMBIOS_BDF_EXT_OFFSET 0x8
73
74
75
76
77 #define ATH10K_SMBIOS_BDF_EXT_STR_LENGTH 0x20
78
79
80 #define ATH10K_SMBIOS_BDF_EXT_MAGIC "BDF_"
81
82
83 #define ATH10K_AIRTIME_WEIGHT_MULTIPLIER 4
84
85 struct ath10k;
86
87 static inline const char *ath10k_bus_str(enum ath10k_bus bus)
88 {
89 switch (bus) {
90 case ATH10K_BUS_PCI:
91 return "pci";
92 case ATH10K_BUS_AHB:
93 return "ahb";
94 case ATH10K_BUS_SDIO:
95 return "sdio";
96 case ATH10K_BUS_USB:
97 return "usb";
98 case ATH10K_BUS_SNOC:
99 return "snoc";
100 }
101
102 return "unknown";
103 }
104
105 enum ath10k_skb_flags {
106 ATH10K_SKB_F_NO_HWCRYPT = BIT(0),
107 ATH10K_SKB_F_DTIM_ZERO = BIT(1),
108 ATH10K_SKB_F_DELIVER_CAB = BIT(2),
109 ATH10K_SKB_F_MGMT = BIT(3),
110 ATH10K_SKB_F_QOS = BIT(4),
111 ATH10K_SKB_F_RAW_TX = BIT(5),
112 };
113
114 struct ath10k_skb_cb {
115 dma_addr_t paddr;
116 u8 flags;
117 u8 eid;
118 u16 msdu_id;
119 u16 airtime_est;
120 struct ieee80211_vif *vif;
121 struct ieee80211_txq *txq;
122 } __packed;
123
124 struct ath10k_skb_rxcb {
125 dma_addr_t paddr;
126 struct hlist_node hlist;
127 };
128
129 static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
130 {
131 BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
132 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
133 return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
134 }
135
136 static inline struct ath10k_skb_rxcb *ATH10K_SKB_RXCB(struct sk_buff *skb)
137 {
138 BUILD_BUG_ON(sizeof(struct ath10k_skb_rxcb) > sizeof(skb->cb));
139 return (struct ath10k_skb_rxcb *)skb->cb;
140 }
141
142 #define ATH10K_RXCB_SKB(rxcb) \
143 container_of((void *)rxcb, struct sk_buff, cb)
144
145 static inline u32 host_interest_item_address(u32 item_offset)
146 {
147 return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
148 }
149
150 struct ath10k_bmi {
151 bool done_sent;
152 };
153
154 struct ath10k_mem_chunk {
155 void *vaddr;
156 dma_addr_t paddr;
157 u32 len;
158 u32 req_id;
159 };
160
161 struct ath10k_wmi {
162 enum ath10k_htc_ep_id eid;
163 struct completion service_ready;
164 struct completion unified_ready;
165 struct completion barrier;
166 struct completion radar_confirm;
167 wait_queue_head_t tx_credits_wq;
168 DECLARE_BITMAP(svc_map, WMI_SERVICE_MAX);
169 struct wmi_cmd_map *cmd;
170 struct wmi_vdev_param_map *vdev_param;
171 struct wmi_pdev_param_map *pdev_param;
172 const struct wmi_ops *ops;
173 const struct wmi_peer_flags_map *peer_flags;
174
175 u32 mgmt_max_num_pending_tx;
176
177
178 struct idr mgmt_pending_tx;
179
180 u32 num_mem_chunks;
181 u32 rx_decap_mode;
182 struct ath10k_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
183 };
184
185 struct ath10k_fw_stats_peer {
186 struct list_head list;
187
188 u8 peer_macaddr[ETH_ALEN];
189 u32 peer_rssi;
190 u32 peer_tx_rate;
191 u32 peer_rx_rate;
192 u64 rx_duration;
193 };
194
195 struct ath10k_fw_extd_stats_peer {
196 struct list_head list;
197
198 u8 peer_macaddr[ETH_ALEN];
199 u64 rx_duration;
200 };
201
202 struct ath10k_fw_stats_vdev {
203 struct list_head list;
204
205 u32 vdev_id;
206 u32 beacon_snr;
207 u32 data_snr;
208 u32 num_tx_frames[4];
209 u32 num_rx_frames;
210 u32 num_tx_frames_retries[4];
211 u32 num_tx_frames_failures[4];
212 u32 num_rts_fail;
213 u32 num_rts_success;
214 u32 num_rx_err;
215 u32 num_rx_discard;
216 u32 num_tx_not_acked;
217 u32 tx_rate_history[10];
218 u32 beacon_rssi_history[10];
219 };
220
221 struct ath10k_fw_stats_vdev_extd {
222 struct list_head list;
223
224 u32 vdev_id;
225 u32 ppdu_aggr_cnt;
226 u32 ppdu_noack;
227 u32 mpdu_queued;
228 u32 ppdu_nonaggr_cnt;
229 u32 mpdu_sw_requeued;
230 u32 mpdu_suc_retry;
231 u32 mpdu_suc_multitry;
232 u32 mpdu_fail_retry;
233 u32 tx_ftm_suc;
234 u32 tx_ftm_suc_retry;
235 u32 tx_ftm_fail;
236 u32 rx_ftmr_cnt;
237 u32 rx_ftmr_dup_cnt;
238 u32 rx_iftmr_cnt;
239 u32 rx_iftmr_dup_cnt;
240 };
241
242 struct ath10k_fw_stats_pdev {
243 struct list_head list;
244
245
246 s32 ch_noise_floor;
247 u32 tx_frame_count;
248 u32 rx_frame_count;
249 u32 rx_clear_count;
250 u32 cycle_count;
251 u32 phy_err_count;
252 u32 chan_tx_power;
253 u32 ack_rx_bad;
254 u32 rts_bad;
255 u32 rts_good;
256 u32 fcs_bad;
257 u32 no_beacons;
258 u32 mib_int_count;
259
260
261 s32 comp_queued;
262 s32 comp_delivered;
263 s32 msdu_enqued;
264 s32 mpdu_enqued;
265 s32 wmm_drop;
266 s32 local_enqued;
267 s32 local_freed;
268 s32 hw_queued;
269 s32 hw_reaped;
270 s32 underrun;
271 u32 hw_paused;
272 s32 tx_abort;
273 s32 mpdus_requed;
274 u32 tx_ko;
275 u32 data_rc;
276 u32 self_triggers;
277 u32 sw_retry_failure;
278 u32 illgl_rate_phy_err;
279 u32 pdev_cont_xretry;
280 u32 pdev_tx_timeout;
281 u32 pdev_resets;
282 u32 phy_underrun;
283 u32 txop_ovf;
284 u32 seq_posted;
285 u32 seq_failed_queueing;
286 u32 seq_completed;
287 u32 seq_restarted;
288 u32 mu_seq_posted;
289 u32 mpdus_sw_flush;
290 u32 mpdus_hw_filter;
291 u32 mpdus_truncated;
292 u32 mpdus_ack_failed;
293 u32 mpdus_expired;
294
295
296 s32 mid_ppdu_route_change;
297 s32 status_rcvd;
298 s32 r0_frags;
299 s32 r1_frags;
300 s32 r2_frags;
301 s32 r3_frags;
302 s32 htt_msdus;
303 s32 htt_mpdus;
304 s32 loc_msdus;
305 s32 loc_mpdus;
306 s32 oversize_amsdu;
307 s32 phy_errs;
308 s32 phy_err_drop;
309 s32 mpdu_errs;
310 s32 rx_ovfl_errs;
311 };
312
313 struct ath10k_fw_stats {
314 bool extended;
315 struct list_head pdevs;
316 struct list_head vdevs;
317 struct list_head peers;
318 struct list_head peers_extd;
319 };
320
321 #define ATH10K_TPC_TABLE_TYPE_FLAG 1
322 #define ATH10K_TPC_PREAM_TABLE_END 0xFFFF
323
324 struct ath10k_tpc_table {
325 u32 pream_idx[WMI_TPC_RATE_MAX];
326 u8 rate_code[WMI_TPC_RATE_MAX];
327 char tpc_value[WMI_TPC_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE];
328 };
329
330 struct ath10k_tpc_stats {
331 u32 reg_domain;
332 u32 chan_freq;
333 u32 phy_mode;
334 u32 twice_antenna_reduction;
335 u32 twice_max_rd_power;
336 s32 twice_antenna_gain;
337 u32 power_limit;
338 u32 num_tx_chain;
339 u32 ctl;
340 u32 rate_max;
341 u8 flag[WMI_TPC_FLAG];
342 struct ath10k_tpc_table tpc_table[WMI_TPC_FLAG];
343 };
344
345 struct ath10k_tpc_table_final {
346 u32 pream_idx[WMI_TPC_FINAL_RATE_MAX];
347 u8 rate_code[WMI_TPC_FINAL_RATE_MAX];
348 char tpc_value[WMI_TPC_FINAL_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE];
349 };
350
351 struct ath10k_tpc_stats_final {
352 u32 reg_domain;
353 u32 chan_freq;
354 u32 phy_mode;
355 u32 twice_antenna_reduction;
356 u32 twice_max_rd_power;
357 s32 twice_antenna_gain;
358 u32 power_limit;
359 u32 num_tx_chain;
360 u32 ctl;
361 u32 rate_max;
362 u8 flag[WMI_TPC_FLAG];
363 struct ath10k_tpc_table_final tpc_table_final[WMI_TPC_FLAG];
364 };
365
366 struct ath10k_dfs_stats {
367 u32 phy_errors;
368 u32 pulses_total;
369 u32 pulses_detected;
370 u32 pulses_discarded;
371 u32 radar_detected;
372 };
373
374 enum ath10k_radar_confirmation_state {
375 ATH10K_RADAR_CONFIRMATION_IDLE = 0,
376 ATH10K_RADAR_CONFIRMATION_INPROGRESS,
377 ATH10K_RADAR_CONFIRMATION_STOPPED,
378 };
379
380 struct ath10k_radar_found_info {
381 u32 pri_min;
382 u32 pri_max;
383 u32 width_min;
384 u32 width_max;
385 u32 sidx_min;
386 u32 sidx_max;
387 };
388
389 #define ATH10K_MAX_NUM_PEER_IDS (1 << 11)
390
391 struct ath10k_peer {
392 struct list_head list;
393 struct ieee80211_vif *vif;
394 struct ieee80211_sta *sta;
395
396 bool removed;
397 int vdev_id;
398 u8 addr[ETH_ALEN];
399 DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
400
401
402 struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
403 union htt_rx_pn_t tids_last_pn[ATH10K_TXRX_NUM_EXT_TIDS];
404 bool tids_last_pn_valid[ATH10K_TXRX_NUM_EXT_TIDS];
405 union htt_rx_pn_t frag_tids_last_pn[ATH10K_TXRX_NUM_EXT_TIDS];
406 u32 frag_tids_seq[ATH10K_TXRX_NUM_EXT_TIDS];
407 struct {
408 enum htt_security_types sec_type;
409 int pn_len;
410 } rx_pn[ATH10K_HTT_TXRX_PEER_SECURITY_MAX];
411 };
412
413 struct ath10k_txq {
414 struct list_head list;
415 unsigned long num_fw_queued;
416 unsigned long num_push_allowed;
417 };
418
419 enum ath10k_pkt_rx_err {
420 ATH10K_PKT_RX_ERR_FCS,
421 ATH10K_PKT_RX_ERR_TKIP,
422 ATH10K_PKT_RX_ERR_CRYPT,
423 ATH10K_PKT_RX_ERR_PEER_IDX_INVAL,
424 ATH10K_PKT_RX_ERR_MAX,
425 };
426
427 enum ath10k_ampdu_subfrm_num {
428 ATH10K_AMPDU_SUBFRM_NUM_10,
429 ATH10K_AMPDU_SUBFRM_NUM_20,
430 ATH10K_AMPDU_SUBFRM_NUM_30,
431 ATH10K_AMPDU_SUBFRM_NUM_40,
432 ATH10K_AMPDU_SUBFRM_NUM_50,
433 ATH10K_AMPDU_SUBFRM_NUM_60,
434 ATH10K_AMPDU_SUBFRM_NUM_MORE,
435 ATH10K_AMPDU_SUBFRM_NUM_MAX,
436 };
437
438 enum ath10k_amsdu_subfrm_num {
439 ATH10K_AMSDU_SUBFRM_NUM_1,
440 ATH10K_AMSDU_SUBFRM_NUM_2,
441 ATH10K_AMSDU_SUBFRM_NUM_3,
442 ATH10K_AMSDU_SUBFRM_NUM_4,
443 ATH10K_AMSDU_SUBFRM_NUM_MORE,
444 ATH10K_AMSDU_SUBFRM_NUM_MAX,
445 };
446
447 struct ath10k_sta_tid_stats {
448 unsigned long rx_pkt_from_fw;
449 unsigned long rx_pkt_unchained;
450 unsigned long rx_pkt_drop_chained;
451 unsigned long rx_pkt_drop_filter;
452 unsigned long rx_pkt_err[ATH10K_PKT_RX_ERR_MAX];
453 unsigned long rx_pkt_queued_for_mac;
454 unsigned long rx_pkt_ampdu[ATH10K_AMPDU_SUBFRM_NUM_MAX];
455 unsigned long rx_pkt_amsdu[ATH10K_AMSDU_SUBFRM_NUM_MAX];
456 };
457
458 enum ath10k_counter_type {
459 ATH10K_COUNTER_TYPE_BYTES,
460 ATH10K_COUNTER_TYPE_PKTS,
461 ATH10K_COUNTER_TYPE_MAX,
462 };
463
464 enum ath10k_stats_type {
465 ATH10K_STATS_TYPE_SUCC,
466 ATH10K_STATS_TYPE_FAIL,
467 ATH10K_STATS_TYPE_RETRY,
468 ATH10K_STATS_TYPE_AMPDU,
469 ATH10K_STATS_TYPE_MAX,
470 };
471
472 struct ath10k_htt_data_stats {
473 u64 legacy[ATH10K_COUNTER_TYPE_MAX][ATH10K_LEGACY_NUM];
474 u64 ht[ATH10K_COUNTER_TYPE_MAX][ATH10K_HT_MCS_NUM];
475 u64 vht[ATH10K_COUNTER_TYPE_MAX][ATH10K_VHT_MCS_NUM];
476 u64 bw[ATH10K_COUNTER_TYPE_MAX][ATH10K_BW_NUM];
477 u64 nss[ATH10K_COUNTER_TYPE_MAX][ATH10K_NSS_NUM];
478 u64 gi[ATH10K_COUNTER_TYPE_MAX][ATH10K_GI_NUM];
479 u64 rate_table[ATH10K_COUNTER_TYPE_MAX][ATH10K_RATE_TABLE_NUM];
480 };
481
482 struct ath10k_htt_tx_stats {
483 struct ath10k_htt_data_stats stats[ATH10K_STATS_TYPE_MAX];
484 u64 tx_duration;
485 u64 ba_fails;
486 u64 ack_fails;
487 };
488
489 struct ath10k_sta {
490 struct ath10k_vif *arvif;
491
492
493 u32 changed;
494 u32 bw;
495 u32 nss;
496 u32 smps;
497 u16 peer_id;
498 struct rate_info txrate;
499 struct ieee80211_tx_info tx_info;
500 u32 last_tx_bitrate;
501
502 struct work_struct update_wk;
503 u64 rx_duration;
504 struct ath10k_htt_tx_stats *tx_stats;
505
506 #ifdef CONFIG_MAC80211_DEBUGFS
507
508 bool aggr_mode;
509
510
511 struct ath10k_sta_tid_stats tid_stats[IEEE80211_NUM_TIDS + 1];
512 #endif
513
514 u32 peer_ps_state;
515 };
516
517 #define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5 * HZ)
518 #define ATH10K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
519
520 enum ath10k_beacon_state {
521 ATH10K_BEACON_SCHEDULED = 0,
522 ATH10K_BEACON_SENDING,
523 ATH10K_BEACON_SENT,
524 };
525
526 struct ath10k_vif {
527 struct list_head list;
528
529 u32 vdev_id;
530 u16 peer_id;
531 enum wmi_vdev_type vdev_type;
532 enum wmi_vdev_subtype vdev_subtype;
533 u32 beacon_interval;
534 u32 dtim_period;
535 struct sk_buff *beacon;
536
537 enum ath10k_beacon_state beacon_state;
538 void *beacon_buf;
539 dma_addr_t beacon_paddr;
540 unsigned long tx_paused;
541
542 struct ath10k *ar;
543 struct ieee80211_vif *vif;
544
545 bool is_started;
546 bool is_up;
547 bool spectral_enabled;
548 bool ps;
549 u32 aid;
550 u8 bssid[ETH_ALEN];
551
552 struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
553 s8 def_wep_key_idx;
554
555 u16 tx_seq_no;
556
557 union {
558 struct {
559 u32 uapsd;
560 } sta;
561 struct {
562
563 u8 tim_bitmap[64];
564 u8 tim_len;
565 u32 ssid_len;
566 u8 ssid[IEEE80211_MAX_SSID_LEN];
567 bool hidden_ssid;
568
569 u32 noa_len;
570 u8 *noa_data;
571 } ap;
572 } u;
573
574 bool use_cts_prot;
575 bool nohwcrypt;
576 int num_legacy_stations;
577 int txpower;
578 bool ftm_responder;
579 struct wmi_wmm_params_all_arg wmm_params;
580 struct work_struct ap_csa_work;
581 struct delayed_work connection_loss_work;
582 struct cfg80211_bitrate_mask bitrate_mask;
583
584
585 int vht_num_rates;
586 u8 vht_pfr;
587 };
588
589 struct ath10k_vif_iter {
590 u32 vdev_id;
591 struct ath10k_vif *arvif;
592 };
593
594
595 struct ath10k_ce_crash_data {
596 __le32 base_addr;
597 __le32 src_wr_idx;
598 __le32 src_r_idx;
599 __le32 dst_wr_idx;
600 __le32 dst_r_idx;
601 };
602
603 struct ath10k_ce_crash_hdr {
604 __le32 ce_count;
605 __le32 reserved[3];
606 struct ath10k_ce_crash_data entries[];
607 };
608
609 #define MAX_MEM_DUMP_TYPE 5
610
611
612 struct ath10k_fw_crash_data {
613 guid_t guid;
614 struct timespec64 timestamp;
615 __le32 registers[REG_DUMP_COUNT_QCA988X];
616 struct ath10k_ce_crash_data ce_crash_data[CE_COUNT_MAX];
617
618 u8 *ramdump_buf;
619 size_t ramdump_buf_len;
620 };
621
622 struct ath10k_debug {
623 struct dentry *debugfs_phy;
624
625 struct ath10k_fw_stats fw_stats;
626 struct completion fw_stats_complete;
627 bool fw_stats_done;
628
629 unsigned long htt_stats_mask;
630 unsigned long reset_htt_stats;
631 struct delayed_work htt_stats_dwork;
632 struct ath10k_dfs_stats dfs_stats;
633 struct ath_dfs_pool_stats dfs_pool_stats;
634
635
636 struct ath10k_tpc_stats *tpc_stats;
637 struct ath10k_tpc_stats_final *tpc_stats_final;
638
639 struct completion tpc_complete;
640
641
642 u64 fw_dbglog_mask;
643 u32 fw_dbglog_level;
644 u32 reg_addr;
645 u32 nf_cal_period;
646 void *cal_data;
647 u32 enable_extd_tx_stats;
648 u8 fw_dbglog_mode;
649 };
650
651 enum ath10k_state {
652 ATH10K_STATE_OFF = 0,
653 ATH10K_STATE_ON,
654
655
656
657
658
659
660
661
662
663
664 ATH10K_STATE_RESTARTING,
665 ATH10K_STATE_RESTARTED,
666
667
668
669
670
671
672 ATH10K_STATE_WEDGED,
673
674
675 ATH10K_STATE_UTF,
676 };
677
678 enum ath10k_firmware_mode {
679
680 ATH10K_FIRMWARE_MODE_NORMAL,
681
682
683 ATH10K_FIRMWARE_MODE_UTF,
684 };
685
686 enum ath10k_fw_features {
687
688 ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
689
690
691 ATH10K_FW_FEATURE_WMI_10X = 1,
692
693
694 ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,
695
696
697 ATH10K_FW_FEATURE_NO_P2P = 3,
698
699
700
701
702
703 ATH10K_FW_FEATURE_WMI_10_2 = 4,
704
705
706
707
708
709 ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT = 5,
710
711
712
713
714
715 ATH10K_FW_FEATURE_WOWLAN_SUPPORT = 6,
716
717
718 ATH10K_FW_FEATURE_IGNORE_OTP_RESULT = 7,
719
720
721
722
723 ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING = 8,
724
725
726 ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT = 9,
727
728
729
730
731 ATH10K_FW_FEATURE_RAW_MODE_SUPPORT = 10,
732
733
734 ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA = 11,
735
736
737 ATH10K_FW_FEATURE_MFP_SUPPORT = 12,
738
739
740
741
742
743
744
745
746 ATH10K_FW_FEATURE_PEER_FLOW_CONTROL = 13,
747
748
749
750
751
752
753 ATH10K_FW_FEATURE_BTCOEX_PARAM = 14,
754
755
756
757
758 ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR = 15,
759
760
761
762
763
764
765 ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST = 16,
766
767
768 ATH10K_FW_FEATURE_NO_PS = 17,
769
770
771 ATH10K_FW_FEATURE_MGMT_TX_BY_REF = 18,
772
773
774 ATH10K_FW_FEATURE_NON_BMI = 19,
775
776
777 ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL = 20,
778
779
780 ATH10K_FW_FEATURE_PEER_FIXED_RATE = 21,
781
782
783 ATH10K_FW_FEATURE_COUNT,
784 };
785
786 enum ath10k_dev_flags {
787
788 ATH10K_CAC_RUNNING,
789 ATH10K_FLAG_CORE_REGISTERED,
790
791
792
793
794 ATH10K_FLAG_CRASH_FLUSH,
795
796
797
798
799
800 ATH10K_FLAG_RAW_MODE,
801
802
803 ATH10K_FLAG_HW_CRYPTO_DISABLED,
804
805
806 ATH10K_FLAG_BTCOEX,
807
808
809 ATH10K_FLAG_PEER_STATS,
810 };
811
812 enum ath10k_cal_mode {
813 ATH10K_CAL_MODE_FILE,
814 ATH10K_CAL_MODE_OTP,
815 ATH10K_CAL_MODE_DT,
816 ATH10K_PRE_CAL_MODE_FILE,
817 ATH10K_PRE_CAL_MODE_DT,
818 ATH10K_CAL_MODE_EEPROM,
819 };
820
821 enum ath10k_crypt_mode {
822
823 ATH10K_CRYPT_MODE_HW,
824
825 ATH10K_CRYPT_MODE_SW,
826 };
827
828 static inline const char *ath10k_cal_mode_str(enum ath10k_cal_mode mode)
829 {
830 switch (mode) {
831 case ATH10K_CAL_MODE_FILE:
832 return "file";
833 case ATH10K_CAL_MODE_OTP:
834 return "otp";
835 case ATH10K_CAL_MODE_DT:
836 return "dt";
837 case ATH10K_PRE_CAL_MODE_FILE:
838 return "pre-cal-file";
839 case ATH10K_PRE_CAL_MODE_DT:
840 return "pre-cal-dt";
841 case ATH10K_CAL_MODE_EEPROM:
842 return "eeprom";
843 }
844
845 return "unknown";
846 }
847
848 enum ath10k_scan_state {
849 ATH10K_SCAN_IDLE,
850 ATH10K_SCAN_STARTING,
851 ATH10K_SCAN_RUNNING,
852 ATH10K_SCAN_ABORTING,
853 };
854
855 static inline const char *ath10k_scan_state_str(enum ath10k_scan_state state)
856 {
857 switch (state) {
858 case ATH10K_SCAN_IDLE:
859 return "idle";
860 case ATH10K_SCAN_STARTING:
861 return "starting";
862 case ATH10K_SCAN_RUNNING:
863 return "running";
864 case ATH10K_SCAN_ABORTING:
865 return "aborting";
866 }
867
868 return "unknown";
869 }
870
871 enum ath10k_tx_pause_reason {
872 ATH10K_TX_PAUSE_Q_FULL,
873 ATH10K_TX_PAUSE_MAX,
874 };
875
876 struct ath10k_fw_file {
877 const struct firmware *firmware;
878
879 char fw_version[ETHTOOL_FWVERS_LEN];
880
881 DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
882
883 enum ath10k_fw_wmi_op_version wmi_op_version;
884 enum ath10k_fw_htt_op_version htt_op_version;
885
886 const void *firmware_data;
887 size_t firmware_len;
888
889 const void *otp_data;
890 size_t otp_len;
891
892 const void *codeswap_data;
893 size_t codeswap_len;
894
895
896
897
898
899
900
901
902 struct ath10k_swap_code_seg_info *firmware_swap_code_seg_info;
903 };
904
905 struct ath10k_fw_components {
906 const struct firmware *board;
907 const void *board_data;
908 size_t board_len;
909 const struct firmware *ext_board;
910 const void *ext_board_data;
911 size_t ext_board_len;
912
913 struct ath10k_fw_file fw_file;
914 };
915
916 struct ath10k_per_peer_tx_stats {
917 u32 succ_bytes;
918 u32 retry_bytes;
919 u32 failed_bytes;
920 u8 ratecode;
921 u8 flags;
922 u16 peer_id;
923 u16 succ_pkts;
924 u16 retry_pkts;
925 u16 failed_pkts;
926 u16 duration;
927 u32 reserved1;
928 u32 reserved2;
929 };
930
931 enum ath10k_dev_type {
932 ATH10K_DEV_TYPE_LL,
933 ATH10K_DEV_TYPE_HL,
934 };
935
936 struct ath10k_bus_params {
937 u32 chip_id;
938 enum ath10k_dev_type dev_type;
939 bool link_can_suspend;
940 bool hl_msdu_ids;
941 };
942
943 struct ath10k {
944 struct ath_common ath_common;
945 struct ieee80211_hw *hw;
946 struct ieee80211_ops *ops;
947 struct device *dev;
948 u8 mac_addr[ETH_ALEN];
949
950 enum ath10k_hw_rev hw_rev;
951 u16 dev_id;
952 u32 chip_id;
953 enum ath10k_dev_type dev_type;
954 u32 target_version;
955 u8 fw_version_major;
956 u32 fw_version_minor;
957 u16 fw_version_release;
958 u16 fw_version_build;
959 u32 fw_stats_req_mask;
960 u32 phy_capability;
961 u32 hw_min_tx_power;
962 u32 hw_max_tx_power;
963 u32 hw_eeprom_rd;
964 u32 ht_cap_info;
965 u32 vht_cap_info;
966 u32 num_rf_chains;
967 u32 max_spatial_stream;
968
969 u32 low_5ghz_chan;
970 u32 high_5ghz_chan;
971 bool ani_enabled;
972
973 u8 ps_state_enable;
974
975 bool nlo_enabled;
976 bool p2p;
977
978 struct {
979 enum ath10k_bus bus;
980 const struct ath10k_hif_ops *ops;
981 } hif;
982
983 struct completion target_suspend;
984 struct completion driver_recovery;
985
986 const struct ath10k_hw_regs *regs;
987 const struct ath10k_hw_ce_regs *hw_ce_regs;
988 const struct ath10k_hw_values *hw_values;
989 struct ath10k_bmi bmi;
990 struct ath10k_wmi wmi;
991 struct ath10k_htc htc;
992 struct ath10k_htt htt;
993
994 struct ath10k_hw_params hw_params;
995
996
997 struct ath10k_fw_components normal_mode_fw;
998
999
1000
1001
1002 const struct ath10k_fw_components *running_fw;
1003
1004 const struct firmware *pre_cal_file;
1005 const struct firmware *cal_file;
1006
1007 struct {
1008 u32 vendor;
1009 u32 device;
1010 u32 subsystem_vendor;
1011 u32 subsystem_device;
1012
1013 bool bmi_ids_valid;
1014 bool qmi_ids_valid;
1015 u32 qmi_board_id;
1016 u8 bmi_board_id;
1017 u8 bmi_eboard_id;
1018 u8 bmi_chip_id;
1019 bool ext_bid_supported;
1020
1021 char bdf_ext[ATH10K_SMBIOS_BDF_EXT_STR_LENGTH];
1022 } id;
1023
1024 int fw_api;
1025 int bd_api;
1026 enum ath10k_cal_mode cal_mode;
1027
1028 struct {
1029 struct completion started;
1030 struct completion completed;
1031 struct completion on_channel;
1032 struct delayed_work timeout;
1033 enum ath10k_scan_state state;
1034 bool is_roc;
1035 int vdev_id;
1036 int roc_freq;
1037 bool roc_notify;
1038 } scan;
1039
1040 struct {
1041 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
1042 } mac;
1043
1044
1045 struct ieee80211_channel *rx_channel;
1046
1047
1048 struct ieee80211_channel *scan_channel;
1049
1050
1051 struct cfg80211_chan_def chandef;
1052
1053
1054 struct ieee80211_channel *tgt_oper_chan;
1055
1056 unsigned long long free_vdev_map;
1057 struct ath10k_vif *monitor_arvif;
1058 bool monitor;
1059 int monitor_vdev_id;
1060 bool monitor_started;
1061 unsigned int filter_flags;
1062 unsigned long dev_flags;
1063 bool dfs_block_radar_events;
1064
1065
1066 bool radar_enabled;
1067 int num_started_vdevs;
1068
1069
1070 u8 cfg_tx_chainmask;
1071 u8 cfg_rx_chainmask;
1072
1073 struct completion install_key_done;
1074
1075 int last_wmi_vdev_start_status;
1076 struct completion vdev_setup_done;
1077 struct completion vdev_delete_done;
1078
1079 struct workqueue_struct *workqueue;
1080
1081 struct workqueue_struct *workqueue_aux;
1082
1083
1084 struct mutex conf_mutex;
1085
1086
1087 struct mutex dump_mutex;
1088
1089
1090 spinlock_t data_lock;
1091
1092 struct list_head arvifs;
1093 struct list_head peers;
1094 struct ath10k_peer *peer_map[ATH10K_MAX_NUM_PEER_IDS];
1095 wait_queue_head_t peer_mapping_wq;
1096
1097
1098 int num_peers;
1099 int num_stations;
1100
1101 int max_num_peers;
1102 int max_num_stations;
1103 int max_num_vdevs;
1104 int max_num_tdls_vdevs;
1105 int num_active_peers;
1106 int num_tids;
1107
1108 struct work_struct svc_rdy_work;
1109 struct sk_buff *svc_rdy_skb;
1110
1111 struct work_struct offchan_tx_work;
1112 struct sk_buff_head offchan_tx_queue;
1113 struct completion offchan_tx_completed;
1114 struct sk_buff *offchan_tx_skb;
1115
1116 struct work_struct wmi_mgmt_tx_work;
1117 struct sk_buff_head wmi_mgmt_tx_queue;
1118
1119 enum ath10k_state state;
1120
1121 struct work_struct register_work;
1122 struct work_struct restart_work;
1123
1124
1125
1126
1127 u32 survey_last_rx_clear_count;
1128 u32 survey_last_cycle_count;
1129 struct survey_info survey[ATH10K_NUM_CHANS];
1130
1131
1132
1133
1134
1135
1136
1137 bool ch_info_can_report_survey;
1138 struct completion bss_survey_done;
1139
1140 struct dfs_pattern_detector *dfs_detector;
1141
1142 unsigned long tx_paused;
1143
1144 #ifdef CONFIG_ATH10K_DEBUGFS
1145 struct ath10k_debug debug;
1146 struct {
1147
1148 struct rchan *rfs_chan_spec_scan;
1149
1150
1151 enum ath10k_spectral_mode mode;
1152 struct ath10k_spec_scan config;
1153 } spectral;
1154 #endif
1155
1156 u32 pktlog_filter;
1157
1158 #ifdef CONFIG_DEV_COREDUMP
1159 struct {
1160 struct ath10k_fw_crash_data *fw_crash_data;
1161 } coredump;
1162 #endif
1163
1164 struct {
1165
1166 struct ath10k_fw_components utf_mode_fw;
1167
1168
1169 bool utf_monitor;
1170 } testmode;
1171
1172 struct {
1173
1174 u32 fw_crash_counter;
1175 u32 fw_warm_reset_counter;
1176 u32 fw_cold_reset_counter;
1177 } stats;
1178
1179 struct ath10k_thermal thermal;
1180 struct ath10k_wow wow;
1181 struct ath10k_per_peer_tx_stats peer_tx_stats;
1182
1183
1184 struct net_device napi_dev;
1185 struct napi_struct napi;
1186
1187 struct work_struct set_coverage_class_work;
1188
1189 struct {
1190
1191 s16 coverage_class;
1192
1193 u32 reg_phyclk;
1194 u32 reg_slottime_conf;
1195 u32 reg_slottime_orig;
1196 u32 reg_ack_cts_timeout_conf;
1197 u32 reg_ack_cts_timeout_orig;
1198 } fw_coverage;
1199
1200 u32 ampdu_reference;
1201
1202 const u8 *wmi_key_cipher;
1203 void *ce_priv;
1204
1205 u32 sta_tid_stats_mask;
1206
1207
1208 enum ath10k_radar_confirmation_state radar_conf_state;
1209 struct ath10k_radar_found_info last_radar_info;
1210 struct work_struct radar_confirmation_work;
1211 struct ath10k_bus_params bus_param;
1212 struct completion peer_delete_done;
1213
1214
1215 u8 drv_priv[0] __aligned(sizeof(void *));
1216 };
1217
1218 static inline bool ath10k_peer_stats_enabled(struct ath10k *ar)
1219 {
1220 if (test_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags) &&
1221 test_bit(WMI_SERVICE_PEER_STATS, ar->wmi.svc_map))
1222 return true;
1223
1224 return false;
1225 }
1226
1227 extern unsigned long ath10k_coredump_mask;
1228
1229 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
1230 enum ath10k_bus bus,
1231 enum ath10k_hw_rev hw_rev,
1232 const struct ath10k_hif_ops *hif_ops);
1233 void ath10k_core_destroy(struct ath10k *ar);
1234 void ath10k_core_get_fw_features_str(struct ath10k *ar,
1235 char *buf,
1236 size_t max_len);
1237 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
1238 struct ath10k_fw_file *fw_file);
1239
1240 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
1241 const struct ath10k_fw_components *fw_components);
1242 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
1243 void ath10k_core_stop(struct ath10k *ar);
1244 int ath10k_core_register(struct ath10k *ar,
1245 const struct ath10k_bus_params *bus_params);
1246 void ath10k_core_unregister(struct ath10k *ar);
1247 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type);
1248 void ath10k_core_free_board_files(struct ath10k *ar);
1249
1250 #endif