This source file includes following definitions.
- ath10k_snoc_priv
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6 #ifndef _SNOC_H_
7 #define _SNOC_H_
8
9 #include "hw.h"
10 #include "ce.h"
11 #include "qmi.h"
12
13 struct ath10k_snoc_drv_priv {
14 enum ath10k_hw_rev hw_rev;
15 u64 dma_mask;
16 u32 msa_size;
17 };
18
19 struct snoc_state {
20 u32 pipe_cfg_addr;
21 u32 svc_to_pipe_map;
22 };
23
24 struct ath10k_snoc_pipe {
25 struct ath10k_ce_pipe *ce_hdl;
26 u8 pipe_num;
27 struct ath10k *hif_ce_state;
28 size_t buf_sz;
29
30 spinlock_t pipe_lock;
31 struct ath10k_snoc *ar_snoc;
32 };
33
34 struct ath10k_snoc_target_info {
35 u32 target_version;
36 u32 target_type;
37 u32 target_revision;
38 u32 soc_version;
39 };
40
41 struct ath10k_snoc_ce_irq {
42 u32 irq_line;
43 };
44
45 struct ath10k_vreg_info {
46 struct regulator *reg;
47 const char *name;
48 u32 min_v;
49 u32 max_v;
50 u32 load_ua;
51 unsigned long settle_delay;
52 bool required;
53 };
54
55 struct ath10k_clk_info {
56 struct clk *handle;
57 const char *name;
58 u32 freq;
59 bool required;
60 };
61
62 enum ath10k_snoc_flags {
63 ATH10K_SNOC_FLAG_REGISTERED,
64 ATH10K_SNOC_FLAG_UNREGISTERING,
65 ATH10K_SNOC_FLAG_RECOVERY,
66 ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK,
67 };
68
69 struct ath10k_snoc {
70 struct platform_device *dev;
71 struct ath10k *ar;
72 void __iomem *mem;
73 dma_addr_t mem_pa;
74 struct ath10k_snoc_target_info target_info;
75 size_t mem_len;
76 struct ath10k_snoc_pipe pipe_info[CE_COUNT_MAX];
77 struct ath10k_snoc_ce_irq ce_irqs[CE_COUNT_MAX];
78 struct ath10k_ce ce;
79 struct timer_list rx_post_retry;
80 struct ath10k_vreg_info *vreg;
81 struct ath10k_clk_info *clk;
82 struct ath10k_qmi *qmi;
83 unsigned long flags;
84 };
85
86 static inline struct ath10k_snoc *ath10k_snoc_priv(struct ath10k *ar)
87 {
88 return (struct ath10k_snoc *)ar->drv_priv;
89 }
90
91 int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type);
92
93 #endif