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14 #ifndef _LBS_IF_SPI_H_
15 #define _LBS_IF_SPI_H_
16
17 #define IPFIELD_ALIGN_OFFSET 2
18 #define IF_SPI_CMD_BUF_SIZE 2400
19
20
21
22 #define IF_SPI_FW_NAME_MAX 30
23
24 #define MAX_MAIN_FW_LOAD_CRC_ERR 10
25
26
27 #define HELPER_FW_LOAD_CHUNK_SZ 64
28
29
30 #define FIRMWARE_DNLD_OK 0x0000
31
32
33 #define SUCCESSFUL_FW_DOWNLOAD_MAGIC 0x88888888
34
35
36
37 #define IF_SPI_READ_OPERATION_MASK 0x0
38 #define IF_SPI_WRITE_OPERATION_MASK 0x8000
39
40
41 #define IF_SPI_DEVICEID_CTRL_REG 0x00
42 #define IF_SPI_IO_READBASE_REG 0x04
43 #define IF_SPI_IO_WRITEBASE_REG 0x08
44 #define IF_SPI_IO_RDWRPORT_REG 0x0C
45
46 #define IF_SPI_CMD_READBASE_REG 0x10
47 #define IF_SPI_CMD_WRITEBASE_REG 0x14
48 #define IF_SPI_CMD_RDWRPORT_REG 0x18
49
50 #define IF_SPI_DATA_READBASE_REG 0x1C
51 #define IF_SPI_DATA_WRITEBASE_REG 0x20
52 #define IF_SPI_DATA_RDWRPORT_REG 0x24
53
54 #define IF_SPI_SCRATCH_1_REG 0x28
55 #define IF_SPI_SCRATCH_2_REG 0x2C
56 #define IF_SPI_SCRATCH_3_REG 0x30
57 #define IF_SPI_SCRATCH_4_REG 0x34
58
59 #define IF_SPI_TX_FRAME_SEQ_NUM_REG 0x38
60 #define IF_SPI_TX_FRAME_STATUS_REG 0x3C
61
62 #define IF_SPI_HOST_INT_CTRL_REG 0x40
63
64 #define IF_SPI_CARD_INT_CAUSE_REG 0x44
65 #define IF_SPI_CARD_INT_STATUS_REG 0x48
66 #define IF_SPI_CARD_INT_EVENT_MASK_REG 0x4C
67 #define IF_SPI_CARD_INT_STATUS_MASK_REG 0x50
68
69 #define IF_SPI_CARD_INT_RESET_SELECT_REG 0x54
70
71 #define IF_SPI_HOST_INT_CAUSE_REG 0x58
72 #define IF_SPI_HOST_INT_STATUS_REG 0x5C
73 #define IF_SPI_HOST_INT_EVENT_MASK_REG 0x60
74 #define IF_SPI_HOST_INT_STATUS_MASK_REG 0x64
75 #define IF_SPI_HOST_INT_RESET_SELECT_REG 0x68
76
77 #define IF_SPI_DELAY_READ_REG 0x6C
78 #define IF_SPI_SPU_BUS_MODE_REG 0x70
79
80
81 #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) ((dc & 0xffff0000)>>16)
82 #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) (dc & 0x000000ff)
83
84
85
86 #define IF_SPI_HICT_WAKE_UP (1<<0)
87
88 #define IF_SPI_HICT_WLAN_READY (1<<1)
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91
92
93 #define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO (1<<5)
94
95 #define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO (1<<6)
96
97 #define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO (1<<7)
98
99 #define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO (1<<8)
100
101
102
103 #define IF_SPI_CIC_TX_DOWNLOAD_OVER (1<<0)
104
105 #define IF_SPI_CIC_RX_UPLOAD_OVER (1<<1)
106
107 #define IF_SPI_CIC_CMD_DOWNLOAD_OVER (1<<2)
108
109 #define IF_SPI_CIC_HOST_EVENT (1<<3)
110
111 #define IF_SPI_CIC_CMD_UPLOAD_OVER (1<<4)
112
113 #define IF_SPI_CIC_POWER_DOWN (1<<5)
114
115
116 #define IF_SPI_CIS_TX_DOWNLOAD_OVER (1<<0)
117 #define IF_SPI_CIS_RX_UPLOAD_OVER (1<<1)
118 #define IF_SPI_CIS_CMD_DOWNLOAD_OVER (1<<2)
119 #define IF_SPI_CIS_HOST_EVENT (1<<3)
120 #define IF_SPI_CIS_CMD_UPLOAD_OVER (1<<4)
121 #define IF_SPI_CIS_POWER_DOWN (1<<5)
122
123
124 #define IF_SPI_HICU_TX_DOWNLOAD_RDY (1<<0)
125 #define IF_SPI_HICU_RX_UPLOAD_RDY (1<<1)
126 #define IF_SPI_HICU_CMD_DOWNLOAD_RDY (1<<2)
127 #define IF_SPI_HICU_CARD_EVENT (1<<3)
128 #define IF_SPI_HICU_CMD_UPLOAD_RDY (1<<4)
129 #define IF_SPI_HICU_IO_WR_FIFO_OVERFLOW (1<<5)
130 #define IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW (1<<6)
131 #define IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW (1<<7)
132 #define IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW (1<<8)
133 #define IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW (1<<9)
134 #define IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW (1<<10)
135
136
137
138 #define IF_SPI_HIST_TX_DOWNLOAD_RDY (1<<0)
139
140 #define IF_SPI_HIST_RX_UPLOAD_RDY (1<<1)
141
142 #define IF_SPI_HIST_CMD_DOWNLOAD_RDY (1<<2)
143
144 #define IF_SPI_HIST_CARD_EVENT (1<<3)
145
146 #define IF_SPI_HIST_CMD_UPLOAD_RDY (1<<4)
147
148 #define IF_SPI_HIST_IO_WR_FIFO_OVERFLOW (1<<5)
149
150 #define IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW (1<<6)
151
152 #define IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW (1<<7)
153
154 #define IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW (1<<8)
155
156 #define IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW (1<<9)
157
158 #define IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW (1<<10)
159
160
161
162 #define IF_SPI_HISM_TX_DOWNLOAD_RDY (1<<0)
163
164 #define IF_SPI_HISM_RX_UPLOAD_RDY (1<<1)
165
166 #define IF_SPI_HISM_CMD_DOWNLOAD_RDY (1<<2)
167
168 #define IF_SPI_HISM_CARDEVENT (1<<3)
169
170 #define IF_SPI_HISM_CMD_UPLOAD_RDY (1<<4)
171
172 #define IF_SPI_HISM_IO_WR_FIFO_OVERFLOW (1<<5)
173
174 #define IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW (1<<6)
175
176 #define IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW (1<<7)
177
178 #define IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW (1<<8)
179
180 #define IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW (1<<9)
181
182 #define IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW (1<<10)
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185
186 #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING 0x8
187 #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING 0x0
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192
193 #define IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK 0x4
194 #define IF_SPI_BUS_MODE_DELAY_METHOD_TIMED 0x0
195
196
197 #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA 0x00
198 #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA 0x01
199 #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA 0x02
200 #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA 0x03
201
202 #endif