1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /******************************************************************************
3 *
4 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
5 *
6 * Contact Information:
7 * Intel Linux Wireless <ilw@linux.intel.com>
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
9 *
10 *****************************************************************************/
11
12 #ifndef __il_4965_h__
13 #define __il_4965_h__
14
15 struct il_rx_queue;
16 struct il_rx_buf;
17 struct il_rx_pkt;
18 struct il_tx_queue;
19 struct il_rxon_context;
20
21 /* configuration for the _4965 devices */
22 extern struct il_cfg il4965_cfg;
23 extern const struct il_ops il4965_ops;
24
25 extern struct il_mod_params il4965_mod_params;
26
27 /* tx queue */
28 void il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid,
29 int freed);
30
31 /* RXON */
32 void il4965_set_rxon_chain(struct il_priv *il);
33
34 /* uCode */
35 int il4965_verify_ucode(struct il_priv *il);
36
37 /* lib */
38 void il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status);
39
40 void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
41 int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq);
42 int il4965_hw_nic_init(struct il_priv *il);
43 int il4965_dump_fh(struct il_priv *il, char **buf, bool display);
44
45 void il4965_nic_config(struct il_priv *il);
46
47 /* rx */
48 void il4965_rx_queue_restock(struct il_priv *il);
49 void il4965_rx_replenish(struct il_priv *il);
50 void il4965_rx_replenish_now(struct il_priv *il);
51 void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq);
52 int il4965_rxq_stop(struct il_priv *il);
53 int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum nl80211_band band);
54 void il4965_rx_handle(struct il_priv *il);
55
56 /* tx */
57 void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
58 int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
59 dma_addr_t addr, u16 len, u8 reset, u8 pad);
60 int il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
61 void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
62 struct ieee80211_tx_info *info);
63 int il4965_tx_skb(struct il_priv *il,
64 struct ieee80211_sta *sta,
65 struct sk_buff *skb);
66 int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
67 struct ieee80211_sta *sta, u16 tid, u16 * ssn);
68 int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
69 struct ieee80211_sta *sta, u16 tid);
70 int il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id);
71 int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx);
72 void il4965_hw_txq_ctx_free(struct il_priv *il);
73 int il4965_txq_ctx_alloc(struct il_priv *il);
74 void il4965_txq_ctx_reset(struct il_priv *il);
75 void il4965_txq_ctx_stop(struct il_priv *il);
76 void il4965_txq_set_sched(struct il_priv *il, u32 mask);
77
78 /*
79 * Acquire il->lock before calling this function !
80 */
81 void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx);
82 /**
83 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
84 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
85 * @scd_retry: (1) Indicates queue will be used in aggregation mode
86 *
87 * NOTE: Acquire il->lock before calling this function !
88 */
89 void il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
90 int tx_fifo_id, int scd_retry);
91
92 /* scan */
93 int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
94
95 /* station mgmt */
96 int il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
97 bool add);
98
99 /* hcmd */
100 int il4965_send_beacon_cmd(struct il_priv *il);
101
102 #ifdef CONFIG_IWLEGACY_DEBUG
103 const char *il4965_get_tx_fail_reason(u32 status);
104 #else
105 static inline const char *
106 il4965_get_tx_fail_reason(u32 status)
107 {
108 return "";
109 }
110 #endif
111
112 /* station management */
113 int il4965_alloc_bcast_station(struct il_priv *il);
114 int il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r);
115 int il4965_remove_default_wep_key(struct il_priv *il,
116 struct ieee80211_key_conf *key);
117 int il4965_set_default_wep_key(struct il_priv *il,
118 struct ieee80211_key_conf *key);
119 int il4965_restore_default_wep_keys(struct il_priv *il);
120 int il4965_set_dynamic_key(struct il_priv *il,
121 struct ieee80211_key_conf *key, u8 sta_id);
122 int il4965_remove_dynamic_key(struct il_priv *il,
123 struct ieee80211_key_conf *key, u8 sta_id);
124 void il4965_update_tkip_key(struct il_priv *il,
125 struct ieee80211_key_conf *keyconf,
126 struct ieee80211_sta *sta, u32 iv32,
127 u16 *phase1key);
128 int il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid);
129 int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta,
130 int tid, u16 ssn);
131 int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta,
132 int tid);
133 void il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt);
134 int il4965_update_bcast_stations(struct il_priv *il);
135
136 /* rate */
137 static inline u8
138 il4965_hw_get_rate(__le32 rate_n_flags)
139 {
140 return le32_to_cpu(rate_n_flags) & 0xFF;
141 }
142
143 /* eeprom */
144 void il4965_eeprom_get_mac(const struct il_priv *il, u8 * mac);
145 int il4965_eeprom_acquire_semaphore(struct il_priv *il);
146 void il4965_eeprom_release_semaphore(struct il_priv *il);
147 int il4965_eeprom_check_version(struct il_priv *il);
148
149 /* mac80211 handlers (for 4965) */
150 void il4965_mac_tx(struct ieee80211_hw *hw,
151 struct ieee80211_tx_control *control,
152 struct sk_buff *skb);
153 int il4965_mac_start(struct ieee80211_hw *hw);
154 void il4965_mac_stop(struct ieee80211_hw *hw);
155 void il4965_configure_filter(struct ieee80211_hw *hw,
156 unsigned int changed_flags,
157 unsigned int *total_flags, u64 multicast);
158 int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
159 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
160 struct ieee80211_key_conf *key);
161 void il4965_mac_update_tkip_key(struct ieee80211_hw *hw,
162 struct ieee80211_vif *vif,
163 struct ieee80211_key_conf *keyconf,
164 struct ieee80211_sta *sta, u32 iv32,
165 u16 *phase1key);
166 int il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
167 struct ieee80211_ampdu_params *params);
168 int il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
169 struct ieee80211_sta *sta);
170 void
171 il4965_mac_channel_switch(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
172 struct ieee80211_channel_switch *ch_switch);
173
174 void il4965_led_enable(struct il_priv *il);
175
176 /* EEPROM */
177 #define IL4965_EEPROM_IMG_SIZE 1024
178
179 /*
180 * uCode queue management definitions ...
181 * The first queue used for block-ack aggregation is #7 (4965 only).
182 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
183 */
184 #define IL49_FIRST_AMPDU_QUEUE 7
185
186 /* Sizes and addresses for instruction and data memory (SRAM) in
187 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
188 #define IL49_RTC_INST_LOWER_BOUND (0x000000)
189 #define IL49_RTC_INST_UPPER_BOUND (0x018000)
190
191 #define IL49_RTC_DATA_LOWER_BOUND (0x800000)
192 #define IL49_RTC_DATA_UPPER_BOUND (0x80A000)
193
194 #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
195 IL49_RTC_INST_LOWER_BOUND)
196 #define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \
197 IL49_RTC_DATA_LOWER_BOUND)
198
199 #define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE
200 #define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE
201
202 /* Size of uCode instruction memory in bootstrap state machine */
203 #define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE
204
205 static inline int
206 il4965_hw_valid_rtc_data_addr(u32 addr)
207 {
208 return (addr >= IL49_RTC_DATA_LOWER_BOUND &&
209 addr < IL49_RTC_DATA_UPPER_BOUND);
210 }
211
212 /********************* START TEMPERATURE *************************************/
213
214 /**
215 * 4965 temperature calculation.
216 *
217 * The driver must calculate the device temperature before calculating
218 * a txpower setting (amplifier gain is temperature dependent). The
219 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
220 * values used for the life of the driver, and one of which (R4) is the
221 * real-time temperature indicator.
222 *
223 * uCode provides all 4 values to the driver via the "initialize alive"
224 * notification (see struct il4965_init_alive_resp). After the runtime uCode
225 * image loads, uCode updates the R4 value via stats notifications
226 * (see N_STATS), which occur after each received beacon
227 * when associated, or can be requested via C_STATS.
228 *
229 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
230 * must sign-extend to 32 bits before applying formula below.
231 *
232 * Formula:
233 *
234 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
235 *
236 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
237 * an additional correction, which should be centered around 0 degrees
238 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for
239 * centering the 97/100 correction around 0 degrees K.
240 *
241 * Add 273 to Kelvin value to find degrees Celsius, for comparing current
242 * temperature with factory-measured temperatures when calculating txpower
243 * settings.
244 */
245 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
246 #define TEMPERATURE_CALIB_A_VAL 259
247
248 /* Limit range of calculated temperature to be between these Kelvin values */
249 #define IL_TX_POWER_TEMPERATURE_MIN (263)
250 #define IL_TX_POWER_TEMPERATURE_MAX (410)
251
252 #define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
253 ((t) < IL_TX_POWER_TEMPERATURE_MIN || \
254 (t) > IL_TX_POWER_TEMPERATURE_MAX)
255
256 void il4965_temperature_calib(struct il_priv *il);
257 /********************* END TEMPERATURE ***************************************/
258
259 /********************* START TXPOWER *****************************************/
260
261 /**
262 * 4965 txpower calculations rely on information from three sources:
263 *
264 * 1) EEPROM
265 * 2) "initialize" alive notification
266 * 3) stats notifications
267 *
268 * EEPROM data consists of:
269 *
270 * 1) Regulatory information (max txpower and channel usage flags) is provided
271 * separately for each channel that can possibly supported by 4965.
272 * 40 MHz wide (.11n HT40) channels are listed separately from 20 MHz
273 * (legacy) channels.
274 *
275 * See struct il4965_eeprom_channel for format, and struct il4965_eeprom
276 * for locations in EEPROM.
277 *
278 * 2) Factory txpower calibration information is provided separately for
279 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
280 * but 5 GHz has several sub-bands.
281 *
282 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
283 *
284 * See struct il4965_eeprom_calib_info (and the tree of structures
285 * contained within it) for format, and struct il4965_eeprom for
286 * locations in EEPROM.
287 *
288 * "Initialization alive" notification (see struct il4965_init_alive_resp)
289 * consists of:
290 *
291 * 1) Temperature calculation parameters.
292 *
293 * 2) Power supply voltage measurement.
294 *
295 * 3) Tx gain compensation to balance 2 transmitters for MIMO use.
296 *
297 * Statistics notifications deliver:
298 *
299 * 1) Current values for temperature param R4.
300 */
301
302 /**
303 * To calculate a txpower setting for a given desired target txpower, channel,
304 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to
305 * support MIMO and transmit diversity), driver must do the following:
306 *
307 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
308 * Do not exceed regulatory limit; reduce target txpower if necessary.
309 *
310 * If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
311 * 2 transmitters will be used simultaneously; driver must reduce the
312 * regulatory limit by 3 dB (half-power) for each transmitter, so the
313 * combined total output of the 2 transmitters is within regulatory limits.
314 *
315 *
316 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by
317 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
318 * reduce target txpower if necessary.
319 *
320 * Backoff values below are in 1/2 dB units (equivalent to steps in
321 * txpower gain tables):
322 *
323 * OFDM 6 - 36 MBit: 10 steps (5 dB)
324 * OFDM 48 MBit: 15 steps (7.5 dB)
325 * OFDM 54 MBit: 17 steps (8.5 dB)
326 * OFDM 60 MBit: 20 steps (10 dB)
327 * CCK all rates: 10 steps (5 dB)
328 *
329 * Backoff values apply to saturation txpower on a per-transmitter basis;
330 * when using MIMO (2 transmitters), each transmitter uses the same
331 * saturation level provided in EEPROM, and the same backoff values;
332 * no reduction (such as with regulatory txpower limits) is required.
333 *
334 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
335 * widths and 40 Mhz (.11n HT40) channel widths; there is no separate
336 * factory measurement for ht40 channels.
337 *
338 * The result of this step is the final target txpower. The rest of
339 * the steps figure out the proper settings for the device to achieve
340 * that target txpower.
341 *
342 *
343 * 3) Determine (EEPROM) calibration sub band for the target channel, by
344 * comparing against first and last channels in each sub band
345 * (see struct il4965_eeprom_calib_subband_info).
346 *
347 *
348 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets,
349 * referencing the 2 factory-measured (sample) channels within the sub band.
350 *
351 * Interpolation is based on difference between target channel's frequency
352 * and the sample channels' frequencies. Since channel numbers are based
353 * on frequency (5 MHz between each channel number), this is equivalent
354 * to interpolating based on channel number differences.
355 *
356 * Note that the sample channels may or may not be the channels at the
357 * edges of the sub band. The target channel may be "outside" of the
358 * span of the sampled channels.
359 *
360 * Driver may choose the pair (for 2 Tx chains) of measurements (see
361 * struct il4965_eeprom_calib_ch_info) for which the actual measured
362 * txpower comes closest to the desired txpower. Usually, though,
363 * the middle set of measurements is closest to the regulatory limits,
364 * and is therefore a good choice for all txpower calculations (this
365 * assumes that high accuracy is needed for maximizing legal txpower,
366 * while lower txpower configurations do not need as much accuracy).
367 *
368 * Driver should interpolate both members of the chosen measurement pair,
369 * i.e. for both Tx chains (radio transmitters), unless the driver knows
370 * that only one of the chains will be used (e.g. only one tx antenna
371 * connected, but this should be unusual). The rate scaling algorithm
372 * switches antennas to find best performance, so both Tx chains will
373 * be used (although only one at a time) even for non-MIMO transmissions.
374 *
375 * Driver should interpolate factory values for temperature, gain table
376 * idx, and actual power. The power amplifier detector values are
377 * not used by the driver.
378 *
379 * Sanity check: If the target channel happens to be one of the sample
380 * channels, the results should agree with the sample channel's
381 * measurements!
382 *
383 *
384 * 5) Find difference between desired txpower and (interpolated)
385 * factory-measured txpower. Using (interpolated) factory gain table idx
386 * (shown elsewhere) as a starting point, adjust this idx lower to
387 * increase txpower, or higher to decrease txpower, until the target
388 * txpower is reached. Each step in the gain table is 1/2 dB.
389 *
390 * For example, if factory measured txpower is 16 dBm, and target txpower
391 * is 13 dBm, add 6 steps to the factory gain idx to reduce txpower
392 * by 3 dB.
393 *
394 *
395 * 6) Find difference between current device temperature and (interpolated)
396 * factory-measured temperature for sub-band. Factory values are in
397 * degrees Celsius. To calculate current temperature, see comments for
398 * "4965 temperature calculation".
399 *
400 * If current temperature is higher than factory temperature, driver must
401 * increase gain (lower gain table idx), and vice verse.
402 *
403 * Temperature affects gain differently for different channels:
404 *
405 * 2.4 GHz all channels: 3.5 degrees per half-dB step
406 * 5 GHz channels 34-43: 4.5 degrees per half-dB step
407 * 5 GHz channels >= 44: 4.0 degrees per half-dB step
408 *
409 * NOTE: Temperature can increase rapidly when transmitting, especially
410 * with heavy traffic at high txpowers. Driver should update
411 * temperature calculations often under these conditions to
412 * maintain strong txpower in the face of rising temperature.
413 *
414 *
415 * 7) Find difference between current power supply voltage indicator
416 * (from "initialize alive") and factory-measured power supply voltage
417 * indicator (EEPROM).
418 *
419 * If the current voltage is higher (indicator is lower) than factory
420 * voltage, gain should be reduced (gain table idx increased) by:
421 *
422 * (eeprom - current) / 7
423 *
424 * If the current voltage is lower (indicator is higher) than factory
425 * voltage, gain should be increased (gain table idx decreased) by:
426 *
427 * 2 * (current - eeprom) / 7
428 *
429 * If number of idx steps in either direction turns out to be > 2,
430 * something is wrong ... just use 0.
431 *
432 * NOTE: Voltage compensation is independent of band/channel.
433 *
434 * NOTE: "Initialize" uCode measures current voltage, which is assumed
435 * to be constant after this initial measurement. Voltage
436 * compensation for txpower (number of steps in gain table)
437 * may be calculated once and used until the next uCode bootload.
438 *
439 *
440 * 8) If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
441 * adjust txpower for each transmitter chain, so txpower is balanced
442 * between the two chains. There are 5 pairs of tx_atten[group][chain]
443 * values in "initialize alive", one pair for each of 5 channel ranges:
444 *
445 * Group 0: 5 GHz channel 34-43
446 * Group 1: 5 GHz channel 44-70
447 * Group 2: 5 GHz channel 71-124
448 * Group 3: 5 GHz channel 125-200
449 * Group 4: 2.4 GHz all channels
450 *
451 * Add the tx_atten[group][chain] value to the idx for the target chain.
452 * The values are signed, but are in pairs of 0 and a non-negative number,
453 * so as to reduce gain (if necessary) of the "hotter" channel. This
454 * avoids any need to double-check for regulatory compliance after
455 * this step.
456 *
457 *
458 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation
459 * value to the idx:
460 *
461 * Hardware rev B: 9 steps (4.5 dB)
462 * Hardware rev C: 5 steps (2.5 dB)
463 *
464 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
465 * bits [3:2], 1 = B, 2 = C.
466 *
467 * NOTE: This compensation is in addition to any saturation backoff that
468 * might have been applied in an earlier step.
469 *
470 *
471 * 10) Select the gain table, based on band (2.4 vs 5 GHz).
472 *
473 * Limit the adjusted idx to stay within the table!
474 *
475 *
476 * 11) Read gain table entries for DSP and radio gain, place into appropriate
477 * location(s) in command (struct il4965_txpowertable_cmd).
478 */
479
480 /**
481 * When MIMO is used (2 transmitters operating simultaneously), driver should
482 * limit each transmitter to deliver a max of 3 dB below the regulatory limit
483 * for the device. That is, use half power for each transmitter, so total
484 * txpower is within regulatory limits.
485 *
486 * The value "6" represents number of steps in gain table to reduce power 3 dB.
487 * Each step is 1/2 dB.
488 */
489 #define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
490
491 /**
492 * CCK gain compensation.
493 *
494 * When calculating txpowers for CCK, after making sure that the target power
495 * is within regulatory and saturation limits, driver must additionally
496 * back off gain by adding these values to the gain table idx.
497 *
498 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
499 * bits [3:2], 1 = B, 2 = C.
500 */
501 #define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
502 #define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
503
504 /*
505 * 4965 power supply voltage compensation for txpower
506 */
507 #define TX_POWER_IL_VOLTAGE_CODES_PER_03V (7)
508
509 /**
510 * Gain tables.
511 *
512 * The following tables contain pair of values for setting txpower, i.e.
513 * gain settings for the output of the device's digital signal processor (DSP),
514 * and for the analog gain structure of the transmitter.
515 *
516 * Each entry in the gain tables represents a step of 1/2 dB. Note that these
517 * are *relative* steps, not indications of absolute output power. Output
518 * power varies with temperature, voltage, and channel frequency, and also
519 * requires consideration of average power (to satisfy regulatory constraints),
520 * and peak power (to avoid distortion of the output signal).
521 *
522 * Each entry contains two values:
523 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
524 * linear value that multiplies the output of the digital signal processor,
525 * before being sent to the analog radio.
526 * 2) Radio gain. This sets the analog gain of the radio Tx path.
527 * It is a coarser setting, and behaves in a logarithmic (dB) fashion.
528 *
529 * EEPROM contains factory calibration data for txpower. This maps actual
530 * measured txpower levels to gain settings in the "well known" tables
531 * below ("well-known" means here that both factory calibration *and* the
532 * driver work with the same table).
533 *
534 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table
535 * has an extension (into negative idxes), in case the driver needs to
536 * boost power setting for high device temperatures (higher than would be
537 * present during factory calibration). A 5 Ghz EEPROM idx of "40"
538 * corresponds to the 49th entry in the table used by the driver.
539 */
540 #define MIN_TX_GAIN_IDX (0) /* highest gain, lowest idx, 2.4 */
541 #define MIN_TX_GAIN_IDX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */
542
543 /**
544 * 2.4 GHz gain table
545 *
546 * Index Dsp gain Radio gain
547 * 0 110 0x3f (highest gain)
548 * 1 104 0x3f
549 * 2 98 0x3f
550 * 3 110 0x3e
551 * 4 104 0x3e
552 * 5 98 0x3e
553 * 6 110 0x3d
554 * 7 104 0x3d
555 * 8 98 0x3d
556 * 9 110 0x3c
557 * 10 104 0x3c
558 * 11 98 0x3c
559 * 12 110 0x3b
560 * 13 104 0x3b
561 * 14 98 0x3b
562 * 15 110 0x3a
563 * 16 104 0x3a
564 * 17 98 0x3a
565 * 18 110 0x39
566 * 19 104 0x39
567 * 20 98 0x39
568 * 21 110 0x38
569 * 22 104 0x38
570 * 23 98 0x38
571 * 24 110 0x37
572 * 25 104 0x37
573 * 26 98 0x37
574 * 27 110 0x36
575 * 28 104 0x36
576 * 29 98 0x36
577 * 30 110 0x35
578 * 31 104 0x35
579 * 32 98 0x35
580 * 33 110 0x34
581 * 34 104 0x34
582 * 35 98 0x34
583 * 36 110 0x33
584 * 37 104 0x33
585 * 38 98 0x33
586 * 39 110 0x32
587 * 40 104 0x32
588 * 41 98 0x32
589 * 42 110 0x31
590 * 43 104 0x31
591 * 44 98 0x31
592 * 45 110 0x30
593 * 46 104 0x30
594 * 47 98 0x30
595 * 48 110 0x6
596 * 49 104 0x6
597 * 50 98 0x6
598 * 51 110 0x5
599 * 52 104 0x5
600 * 53 98 0x5
601 * 54 110 0x4
602 * 55 104 0x4
603 * 56 98 0x4
604 * 57 110 0x3
605 * 58 104 0x3
606 * 59 98 0x3
607 * 60 110 0x2
608 * 61 104 0x2
609 * 62 98 0x2
610 * 63 110 0x1
611 * 64 104 0x1
612 * 65 98 0x1
613 * 66 110 0x0
614 * 67 104 0x0
615 * 68 98 0x0
616 * 69 97 0
617 * 70 96 0
618 * 71 95 0
619 * 72 94 0
620 * 73 93 0
621 * 74 92 0
622 * 75 91 0
623 * 76 90 0
624 * 77 89 0
625 * 78 88 0
626 * 79 87 0
627 * 80 86 0
628 * 81 85 0
629 * 82 84 0
630 * 83 83 0
631 * 84 82 0
632 * 85 81 0
633 * 86 80 0
634 * 87 79 0
635 * 88 78 0
636 * 89 77 0
637 * 90 76 0
638 * 91 75 0
639 * 92 74 0
640 * 93 73 0
641 * 94 72 0
642 * 95 71 0
643 * 96 70 0
644 * 97 69 0
645 * 98 68 0
646 */
647
648 /**
649 * 5 GHz gain table
650 *
651 * Index Dsp gain Radio gain
652 * -9 123 0x3F (highest gain)
653 * -8 117 0x3F
654 * -7 110 0x3F
655 * -6 104 0x3F
656 * -5 98 0x3F
657 * -4 110 0x3E
658 * -3 104 0x3E
659 * -2 98 0x3E
660 * -1 110 0x3D
661 * 0 104 0x3D
662 * 1 98 0x3D
663 * 2 110 0x3C
664 * 3 104 0x3C
665 * 4 98 0x3C
666 * 5 110 0x3B
667 * 6 104 0x3B
668 * 7 98 0x3B
669 * 8 110 0x3A
670 * 9 104 0x3A
671 * 10 98 0x3A
672 * 11 110 0x39
673 * 12 104 0x39
674 * 13 98 0x39
675 * 14 110 0x38
676 * 15 104 0x38
677 * 16 98 0x38
678 * 17 110 0x37
679 * 18 104 0x37
680 * 19 98 0x37
681 * 20 110 0x36
682 * 21 104 0x36
683 * 22 98 0x36
684 * 23 110 0x35
685 * 24 104 0x35
686 * 25 98 0x35
687 * 26 110 0x34
688 * 27 104 0x34
689 * 28 98 0x34
690 * 29 110 0x33
691 * 30 104 0x33
692 * 31 98 0x33
693 * 32 110 0x32
694 * 33 104 0x32
695 * 34 98 0x32
696 * 35 110 0x31
697 * 36 104 0x31
698 * 37 98 0x31
699 * 38 110 0x30
700 * 39 104 0x30
701 * 40 98 0x30
702 * 41 110 0x25
703 * 42 104 0x25
704 * 43 98 0x25
705 * 44 110 0x24
706 * 45 104 0x24
707 * 46 98 0x24
708 * 47 110 0x23
709 * 48 104 0x23
710 * 49 98 0x23
711 * 50 110 0x22
712 * 51 104 0x18
713 * 52 98 0x18
714 * 53 110 0x17
715 * 54 104 0x17
716 * 55 98 0x17
717 * 56 110 0x16
718 * 57 104 0x16
719 * 58 98 0x16
720 * 59 110 0x15
721 * 60 104 0x15
722 * 61 98 0x15
723 * 62 110 0x14
724 * 63 104 0x14
725 * 64 98 0x14
726 * 65 110 0x13
727 * 66 104 0x13
728 * 67 98 0x13
729 * 68 110 0x12
730 * 69 104 0x08
731 * 70 98 0x08
732 * 71 110 0x07
733 * 72 104 0x07
734 * 73 98 0x07
735 * 74 110 0x06
736 * 75 104 0x06
737 * 76 98 0x06
738 * 77 110 0x05
739 * 78 104 0x05
740 * 79 98 0x05
741 * 80 110 0x04
742 * 81 104 0x04
743 * 82 98 0x04
744 * 83 110 0x03
745 * 84 104 0x03
746 * 85 98 0x03
747 * 86 110 0x02
748 * 87 104 0x02
749 * 88 98 0x02
750 * 89 110 0x01
751 * 90 104 0x01
752 * 91 98 0x01
753 * 92 110 0x00
754 * 93 104 0x00
755 * 94 98 0x00
756 * 95 93 0x00
757 * 96 88 0x00
758 * 97 83 0x00
759 * 98 78 0x00
760 */
761
762 /**
763 * Sanity checks and default values for EEPROM regulatory levels.
764 * If EEPROM values fall outside MIN/MAX range, use default values.
765 *
766 * Regulatory limits refer to the maximum average txpower allowed by
767 * regulatory agencies in the geographies in which the device is meant
768 * to be operated. These limits are SKU-specific (i.e. geography-specific),
769 * and channel-specific; each channel has an individual regulatory limit
770 * listed in the EEPROM.
771 *
772 * Units are in half-dBm (i.e. "34" means 17 dBm).
773 */
774 #define IL_TX_POWER_DEFAULT_REGULATORY_24 (34)
775 #define IL_TX_POWER_DEFAULT_REGULATORY_52 (34)
776 #define IL_TX_POWER_REGULATORY_MIN (0)
777 #define IL_TX_POWER_REGULATORY_MAX (34)
778
779 /**
780 * Sanity checks and default values for EEPROM saturation levels.
781 * If EEPROM values fall outside MIN/MAX range, use default values.
782 *
783 * Saturation is the highest level that the output power amplifier can produce
784 * without significant clipping distortion. This is a "peak" power level.
785 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
786 * require differing amounts of backoff, relative to their average power output,
787 * in order to avoid clipping distortion.
788 *
789 * Driver must make sure that it is violating neither the saturation limit,
790 * nor the regulatory limit, when calculating Tx power settings for various
791 * rates.
792 *
793 * Units are in half-dBm (i.e. "38" means 19 dBm).
794 */
795 #define IL_TX_POWER_DEFAULT_SATURATION_24 (38)
796 #define IL_TX_POWER_DEFAULT_SATURATION_52 (38)
797 #define IL_TX_POWER_SATURATION_MIN (20)
798 #define IL_TX_POWER_SATURATION_MAX (50)
799
800 /**
801 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
802 * and thermal Txpower calibration.
803 *
804 * When calculating txpower, driver must compensate for current device
805 * temperature; higher temperature requires higher gain. Driver must calculate
806 * current temperature (see "4965 temperature calculation"), then compare vs.
807 * factory calibration temperature in EEPROM; if current temperature is higher
808 * than factory temperature, driver must *increase* gain by proportions shown
809 * in table below. If current temperature is lower than factory, driver must
810 * *decrease* gain.
811 *
812 * Different frequency ranges require different compensation, as shown below.
813 */
814 /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
815 #define CALIB_IL_TX_ATTEN_GR1_FCH 34
816 #define CALIB_IL_TX_ATTEN_GR1_LCH 43
817
818 /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
819 #define CALIB_IL_TX_ATTEN_GR2_FCH 44
820 #define CALIB_IL_TX_ATTEN_GR2_LCH 70
821
822 /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
823 #define CALIB_IL_TX_ATTEN_GR3_FCH 71
824 #define CALIB_IL_TX_ATTEN_GR3_LCH 124
825
826 /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
827 #define CALIB_IL_TX_ATTEN_GR4_FCH 125
828 #define CALIB_IL_TX_ATTEN_GR4_LCH 200
829
830 /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
831 #define CALIB_IL_TX_ATTEN_GR5_FCH 1
832 #define CALIB_IL_TX_ATTEN_GR5_LCH 20
833
834 enum {
835 CALIB_CH_GROUP_1 = 0,
836 CALIB_CH_GROUP_2 = 1,
837 CALIB_CH_GROUP_3 = 2,
838 CALIB_CH_GROUP_4 = 3,
839 CALIB_CH_GROUP_5 = 4,
840 CALIB_CH_GROUP_MAX
841 };
842
843 /********************* END TXPOWER *****************************************/
844
845 /**
846 * Tx/Rx Queues
847 *
848 * Most communication between driver and 4965 is via queues of data buffers.
849 * For example, all commands that the driver issues to device's embedded
850 * controller (uCode) are via the command queue (one of the Tx queues). All
851 * uCode command responses/replies/notifications, including Rx frames, are
852 * conveyed from uCode to driver via the Rx queue.
853 *
854 * Most support for these queues, including handshake support, resides in
855 * structures in host DRAM, shared between the driver and the device. When
856 * allocating this memory, the driver must make sure that data written by
857 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
858 * cache memory), so DRAM and cache are consistent, and the device can
859 * immediately see changes made by the driver.
860 *
861 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
862 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
863 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
864 */
865 #define IL49_NUM_FIFOS 7
866 #define IL49_CMD_FIFO_NUM 4
867 #define IL49_NUM_QUEUES 16
868 #define IL49_NUM_AMPDU_QUEUES 8
869
870 /**
871 * struct il4965_schedq_bc_tbl
872 *
873 * Byte Count table
874 *
875 * Each Tx queue uses a byte-count table containing 320 entries:
876 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
877 * duplicate the first 64 entries (to avoid wrap-around within a Tx win;
878 * max Tx win is 64 TFDs).
879 *
880 * When driver sets up a new TFD, it must also enter the total byte count
881 * of the frame to be transmitted into the corresponding entry in the byte
882 * count table for the chosen Tx queue. If the TFD idx is 0-63, the driver
883 * must duplicate the byte count entry in corresponding idx 256-319.
884 *
885 * padding puts each byte count table on a 1024-byte boundary;
886 * 4965 assumes tables are separated by 1024 bytes.
887 */
888 struct il4965_scd_bc_tbl {
889 __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
890 u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)];
891 } __packed;
892
893 #define IL4965_RTC_INST_LOWER_BOUND (0x000000)
894
895 /* RSSI to dBm */
896 #define IL4965_RSSI_OFFSET 44
897
898 /* PCI registers */
899 #define PCI_CFG_RETRY_TIMEOUT 0x041
900
901 #define IL4965_DEFAULT_TX_RETRY 15
902
903 /* EEPROM */
904 #define IL4965_FIRST_AMPDU_QUEUE 10
905
906 /* Calibration */
907 void il4965_chain_noise_calibration(struct il_priv *il, void *stat_resp);
908 void il4965_sensitivity_calibration(struct il_priv *il, void *resp);
909 void il4965_init_sensitivity(struct il_priv *il);
910 void il4965_reset_run_time_calib(struct il_priv *il);
911
912 /* Debug */
913 #ifdef CONFIG_IWLEGACY_DEBUGFS
914 extern const struct il_debugfs_ops il4965_debugfs_ops;
915 #endif
916
917 /****************************/
918 /* Flow Handler Definitions */
919 /****************************/
920
921 /**
922 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
923 * Addresses are offsets from device's PCI hardware base address.
924 */
925 #define FH49_MEM_LOWER_BOUND (0x1000)
926 #define FH49_MEM_UPPER_BOUND (0x2000)
927
928 /**
929 * Keep-Warm (KW) buffer base address.
930 *
931 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
932 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
933 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
934 * from going into a power-savings mode that would cause higher DRAM latency,
935 * and possible data over/under-runs, before all Tx/Rx is complete.
936 *
937 * Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4)
938 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
939 * automatically invokes keep-warm accesses when normal accesses might not
940 * be sufficient to maintain fast DRAM response.
941 *
942 * Bit fields:
943 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
944 */
945 #define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C)
946
947 /**
948 * TFD Circular Buffers Base (CBBC) addresses
949 *
950 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
951 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
952 * (see struct il_tfd_frame). These 16 pointer registers are offset by 0x04
953 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
954 * aligned (address bits 0-7 must be 0).
955 *
956 * Bit fields in each pointer register:
957 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
958 */
959 #define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
960 #define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10)
961
962 /* Find TFD CB base pointer for given queue (range 0-15). */
963 #define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
964
965 /**
966 * Rx SRAM Control and Status Registers (RSCSR)
967 *
968 * These registers provide handshake between driver and 4965 for the Rx queue
969 * (this queue handles *all* command responses, notifications, Rx data, etc.
970 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
971 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
972 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
973 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
974 * mapping between RBDs and RBs.
975 *
976 * Driver must allocate host DRAM memory for the following, and set the
977 * physical address of each into 4965 registers:
978 *
979 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
980 * entries (although any power of 2, up to 4096, is selectable by driver).
981 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
982 * (typically 4K, although 8K or 16K are also selectable by driver).
983 * Driver sets up RB size and number of RBDs in the CB via Rx config
984 * register FH49_MEM_RCSR_CHNL0_CONFIG_REG.
985 *
986 * Bit fields within one RBD:
987 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
988 *
989 * Driver sets physical address [35:8] of base of RBD circular buffer
990 * into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
991 *
992 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
993 * (RBs) have been filled, via a "write pointer", actually the idx of
994 * the RB's corresponding RBD within the circular buffer. Driver sets
995 * physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
996 *
997 * Bit fields in lower dword of Rx status buffer (upper dword not used
998 * by driver; see struct il4965_shared, val0):
999 * 31-12: Not used by driver
1000 * 11- 0: Index of last filled Rx buffer descriptor
1001 * (4965 writes, driver reads this value)
1002 *
1003 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
1004 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1005 * and update the 4965's "write" idx register,
1006 * FH49_RSCSR_CHNL0_RBDCB_WPTR_REG.
1007 *
1008 * This "write" idx corresponds to the *next* RBD that the driver will make
1009 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1010 * the circular buffer. This value should initially be 0 (before preparing any
1011 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1012 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1013 * "read" idx has advanced past 1! See below).
1014 * NOTE: 4965 EXPECTS THE WRITE IDX TO BE INCREMENTED IN MULTIPLES OF 8.
1015 *
1016 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
1017 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1018 * to tell the driver the idx of the latest filled RBD. The driver must
1019 * read this "read" idx from DRAM after receiving an Rx interrupt from 4965.
1020 *
1021 * The driver must also internally keep track of a third idx, which is the
1022 * next RBD to process. When receiving an Rx interrupt, driver should process
1023 * all filled but unprocessed RBs up to, but not including, the RB
1024 * corresponding to the "read" idx. For example, if "read" idx becomes "1",
1025 * driver may process the RB pointed to by RBD 0. Depending on volume of
1026 * traffic, there may be many RBs to process.
1027 *
1028 * If read idx == write idx, 4965 thinks there is no room to put new data.
1029 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1030 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1031 * and "read" idxes; that is, make sure that there are no more than 254
1032 * buffers waiting to be filled.
1033 */
1034 #define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0)
1035 #define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1036 #define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND)
1037
1038 /**
1039 * Physical base address of 8-byte Rx Status buffer.
1040 * Bit fields:
1041 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1042 */
1043 #define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0)
1044
1045 /**
1046 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1047 * Bit fields:
1048 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1049 */
1050 #define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004)
1051
1052 /**
1053 * Rx write pointer (idx, really!).
1054 * Bit fields:
1055 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1056 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1057 */
1058 #define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008)
1059 #define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG)
1060
1061 /**
1062 * Rx Config/Status Registers (RCSR)
1063 * Rx Config Reg for channel 0 (only channel used)
1064 *
1065 * Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1066 * normal operation (see bit fields).
1067 *
1068 * Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1069 * Driver should poll FH49_MEM_RSSR_RX_STATUS_REG for
1070 * FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1071 *
1072 * Bit fields:
1073 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1074 * '10' operate normally
1075 * 29-24: reserved
1076 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1077 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1078 * 19-18: reserved
1079 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1080 * '10' 12K, '11' 16K.
1081 * 15-14: reserved
1082 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1083 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1084 * typical value 0x10 (about 1/2 msec)
1085 * 3- 0: reserved
1086 */
1087 #define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1088 #define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0)
1089 #define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND)
1090
1091 #define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0)
1092
1093 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1094 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1095 #define FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1096 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1097 #define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1098 #define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31 */
1099
1100 #define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1101 #define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1102 #define RX_RB_TIMEOUT (0x10)
1103
1104 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1105 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1106 #define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1107
1108 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1109 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1110 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1111 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1112
1113 #define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1114 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1115 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1116
1117 /**
1118 * Rx Shared Status Registers (RSSR)
1119 *
1120 * After stopping Rx DMA channel (writing 0 to
1121 * FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1122 * FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1123 *
1124 * Bit fields:
1125 * 24: 1 = Channel 0 is idle
1126 *
1127 * FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1128 * contain default values that should not be altered by the driver.
1129 */
1130 #define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40)
1131 #define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1132
1133 #define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND)
1134 #define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004)
1135 #define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1136 (FH49_MEM_RSSR_LOWER_BOUND + 0x008)
1137
1138 #define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1139
1140 #define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1141
1142 /* TFDB Area - TFDs buffer table */
1143 #define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1144 #define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900)
1145 #define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958)
1146 #define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1147 #define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1148
1149 /**
1150 * Transmit DMA Channel Control/Status Registers (TCSR)
1151 *
1152 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
1153 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1154 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1155 *
1156 * To use a Tx DMA channel, driver must initialize its
1157 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1158 *
1159 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1160 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1161 *
1162 * All other bits should be 0.
1163 *
1164 * Bit fields:
1165 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1166 * '10' operate normally
1167 * 29- 4: Reserved, set to "0"
1168 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1169 * 2- 0: Reserved, set to "0"
1170 */
1171 #define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1172 #define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60)
1173
1174 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1175 #define FH49_TCSR_CHNL_NUM (7)
1176 #define FH50_TCSR_CHNL_NUM (8)
1177
1178 /* TCSR: tx_config register values */
1179 #define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1180 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1181 #define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1182 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1183 #define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1184 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1185
1186 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1187 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1188
1189 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1190 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1191
1192 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1193 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1194 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1195
1196 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1197 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1198 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1199
1200 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1201 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1202 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1203
1204 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1205 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1206 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1207
1208 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1209 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1210
1211 /**
1212 * Tx Shared Status Registers (TSSR)
1213 *
1214 * After stopping Tx DMA channel (writing 0 to
1215 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1216 * FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle
1217 * (channel's buffers empty | no pending requests).
1218 *
1219 * Bit fields:
1220 * 31-24: 1 = Channel buffers empty (channel 7:0)
1221 * 23-16: 1 = No pending requests (channel 7:0)
1222 */
1223 #define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0)
1224 #define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0)
1225
1226 #define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010)
1227
1228 /**
1229 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1230 * 31: Indicates an address error when accessed to internal memory
1231 * uCode/driver must write "1" in order to clear this flag
1232 * 30: Indicates that Host did not send the expected number of dwords to FH
1233 * uCode/driver must write "1" in order to clear this flag
1234 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1235 * command was received from the scheduler while the TRB was already full
1236 * with previous command
1237 * uCode/driver must write "1" in order to clear this flag
1238 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1239 * bit is set, it indicates that the FH has received a full indication
1240 * from the RTC TxFIFO and the current value of the TxCredit counter was
1241 * not equal to zero. This mean that the credit mechanism was not
1242 * synchronized to the TxFIFO status
1243 * uCode/driver must write "1" in order to clear this flag
1244 */
1245 #define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018)
1246
1247 #define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1248
1249 /* Tx service channels */
1250 #define FH49_SRVC_CHNL (9)
1251 #define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8)
1252 #define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
1253 #define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1254 (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1255
1256 #define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98)
1257 /* Instruct FH to increment the retry count of a packet when
1258 * it is brought from the memory to TX-FIFO
1259 */
1260 #define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1261
1262 /* Keep Warm Size */
1263 #define IL_KW_SIZE 0x1000 /* 4k */
1264
1265 #endif /* __il_4965_h__ */