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64 #ifndef __iwl_commands_h__
65 #define __iwl_commands_h__
66
67 #include <linux/ieee80211.h>
68 #include <linux/types.h>
69
70
71 enum {
72 REPLY_ALIVE = 0x1,
73 REPLY_ERROR = 0x2,
74 REPLY_ECHO = 0x3,
75
76
77 REPLY_RXON = 0x10,
78 REPLY_RXON_ASSOC = 0x11,
79 REPLY_QOS_PARAM = 0x13,
80 REPLY_RXON_TIMING = 0x14,
81
82
83 REPLY_ADD_STA = 0x18,
84 REPLY_REMOVE_STA = 0x19,
85 REPLY_REMOVE_ALL_STA = 0x1a,
86 REPLY_TXFIFO_FLUSH = 0x1e,
87
88
89 REPLY_WEPKEY = 0x20,
90
91
92 REPLY_TX = 0x1c,
93 REPLY_LEDS_CMD = 0x48,
94 REPLY_TX_LINK_QUALITY_CMD = 0x4e,
95
96
97 COEX_PRIORITY_TABLE_CMD = 0x5a,
98 COEX_MEDIUM_NOTIFICATION = 0x5b,
99 COEX_EVENT_CMD = 0x5c,
100
101
102 TEMPERATURE_NOTIFICATION = 0x62,
103 CALIBRATION_CFG_CMD = 0x65,
104 CALIBRATION_RES_NOTIFICATION = 0x66,
105 CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
106
107
108 REPLY_QUIET_CMD = 0x71,
109 REPLY_CHANNEL_SWITCH = 0x72,
110 CHANNEL_SWITCH_NOTIFICATION = 0x73,
111 REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74,
112 SPECTRUM_MEASURE_NOTIFICATION = 0x75,
113
114
115 POWER_TABLE_CMD = 0x77,
116 PM_SLEEP_NOTIFICATION = 0x7A,
117 PM_DEBUG_STATISTIC_NOTIFIC = 0x7B,
118
119
120 REPLY_SCAN_CMD = 0x80,
121 REPLY_SCAN_ABORT_CMD = 0x81,
122 SCAN_START_NOTIFICATION = 0x82,
123 SCAN_RESULTS_NOTIFICATION = 0x83,
124 SCAN_COMPLETE_NOTIFICATION = 0x84,
125
126
127 BEACON_NOTIFICATION = 0x90,
128 REPLY_TX_BEACON = 0x91,
129 WHO_IS_AWAKE_NOTIFICATION = 0x94,
130
131
132 REPLY_TX_POWER_DBM_CMD = 0x95,
133 QUIET_NOTIFICATION = 0x96,
134 REPLY_TX_PWR_TABLE_CMD = 0x97,
135 REPLY_TX_POWER_DBM_CMD_V1 = 0x98,
136 TX_ANT_CONFIGURATION_CMD = 0x98,
137 MEASURE_ABORT_NOTIFICATION = 0x99,
138
139
140 REPLY_BT_CONFIG = 0x9b,
141
142
143 REPLY_STATISTICS_CMD = 0x9c,
144 STATISTICS_NOTIFICATION = 0x9d,
145
146
147 REPLY_CARD_STATE_CMD = 0xa0,
148 CARD_STATE_NOTIFICATION = 0xa1,
149
150
151 MISSED_BEACONS_NOTIFICATION = 0xa2,
152
153 REPLY_CT_KILL_CONFIG_CMD = 0xa4,
154 SENSITIVITY_CMD = 0xa8,
155 REPLY_PHY_CALIBRATION_CMD = 0xb0,
156 REPLY_RX_PHY_CMD = 0xc0,
157 REPLY_RX_MPDU_CMD = 0xc1,
158 REPLY_RX = 0xc3,
159 REPLY_COMPRESSED_BA = 0xc5,
160
161
162 REPLY_BT_COEX_PRIO_TABLE = 0xcc,
163 REPLY_BT_COEX_PROT_ENV = 0xcd,
164 REPLY_BT_COEX_PROFILE_NOTIF = 0xce,
165
166
167 REPLY_WIPAN_PARAMS = 0xb2,
168 REPLY_WIPAN_RXON = 0xb3,
169 REPLY_WIPAN_RXON_TIMING = 0xb4,
170 REPLY_WIPAN_RXON_ASSOC = 0xb6,
171 REPLY_WIPAN_QOS_PARAM = 0xb7,
172 REPLY_WIPAN_WEPKEY = 0xb8,
173 REPLY_WIPAN_P2P_CHANNEL_SWITCH = 0xb9,
174 REPLY_WIPAN_NOA_NOTIFICATION = 0xbc,
175 REPLY_WIPAN_DEACTIVATION_COMPLETE = 0xbd,
176
177 REPLY_WOWLAN_PATTERNS = 0xe0,
178 REPLY_WOWLAN_WAKEUP_FILTER = 0xe1,
179 REPLY_WOWLAN_TSC_RSC_PARAMS = 0xe2,
180 REPLY_WOWLAN_TKIP_PARAMS = 0xe3,
181 REPLY_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
182 REPLY_WOWLAN_GET_STATUS = 0xe5,
183 REPLY_D3_CONFIG = 0xd3,
184
185 REPLY_MAX = 0xff
186 };
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195
196
197 #define IWL_MIN_NUM_QUEUES 11
198
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201
202 #define IWL_DEFAULT_CMD_QUEUE_NUM 4
203 #define IWL_IPAN_CMD_QUEUE_NUM 9
204
205 #define IWL_TX_FIFO_BK 0
206 #define IWL_TX_FIFO_BE 1
207 #define IWL_TX_FIFO_VI 2
208 #define IWL_TX_FIFO_VO 3
209 #define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
210 #define IWL_TX_FIFO_BE_IPAN 4
211 #define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
212 #define IWL_TX_FIFO_VO_IPAN 5
213
214 #define IWL_TX_FIFO_AUX 5
215 #define IWL_TX_FIFO_UNUSED 255
216
217 #define IWLAGN_CMD_FIFO_NUM 7
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224 #define IWL_IPAN_MCAST_QUEUE 8
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274 #define RATE_MCS_CODE_MSK 0x7
275 #define RATE_MCS_SPATIAL_POS 3
276 #define RATE_MCS_SPATIAL_MSK 0x18
277 #define RATE_MCS_HT_DUP_POS 5
278 #define RATE_MCS_HT_DUP_MSK 0x20
279
280 #define RATE_MCS_RATE_MSK 0xff
281
282
283 #define RATE_MCS_FLAGS_POS 8
284 #define RATE_MCS_HT_POS 8
285 #define RATE_MCS_HT_MSK 0x100
286
287
288 #define RATE_MCS_CCK_POS 9
289 #define RATE_MCS_CCK_MSK 0x200
290
291
292 #define RATE_MCS_GF_POS 10
293 #define RATE_MCS_GF_MSK 0x400
294
295
296 #define RATE_MCS_HT40_POS 11
297 #define RATE_MCS_HT40_MSK 0x800
298
299
300 #define RATE_MCS_DUP_POS 12
301 #define RATE_MCS_DUP_MSK 0x1000
302
303
304 #define RATE_MCS_SGI_POS 13
305 #define RATE_MCS_SGI_MSK 0x2000
306
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310
311 #define RATE_MCS_ANT_POS 14
312 #define RATE_MCS_ANT_A_MSK 0x04000
313 #define RATE_MCS_ANT_B_MSK 0x08000
314 #define RATE_MCS_ANT_C_MSK 0x10000
315 #define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | RATE_MCS_ANT_B_MSK)
316 #define RATE_MCS_ANT_ABC_MSK (RATE_MCS_ANT_AB_MSK | RATE_MCS_ANT_C_MSK)
317 #define RATE_ANT_NUM 3
318
319 #define POWER_TABLE_NUM_ENTRIES 33
320 #define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32
321 #define POWER_TABLE_CCK_ENTRY 32
322
323 #define IWL_PWR_NUM_HT_OFDM_ENTRIES 24
324 #define IWL_PWR_CCK_ENTRIES 2
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331
332
333 struct tx_power_dual_stream {
334 __le32 dw;
335 } __packed;
336
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339
340
341 #define IWLAGN_TX_POWER_AUTO 0x7f
342 #define IWLAGN_TX_POWER_NO_CLOSED (0x1 << 6)
343
344 struct iwlagn_tx_power_dbm_cmd {
345 s8 global_lmt;
346 u8 flags;
347 s8 srv_chan_lmt;
348 u8 reserved;
349 } __packed;
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356
357 struct iwl_tx_ant_config_cmd {
358 __le32 valid;
359 } __packed;
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366
367 #define UCODE_VALID_OK cpu_to_le32(0x1)
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415 struct iwl_error_event_table {
416 u32 valid;
417 u32 error_id;
418 u32 pc;
419 u32 blink1;
420 u32 blink2;
421 u32 ilink1;
422 u32 ilink2;
423 u32 data1;
424 u32 data2;
425 u32 line;
426 u32 bcon_time;
427 u32 tsf_low;
428 u32 tsf_hi;
429 u32 gp1;
430 u32 gp2;
431 u32 gp3;
432 u32 ucode_ver;
433 u32 hw_ver;
434 u32 brd_ver;
435 u32 log_pc;
436 u32 frame_ptr;
437 u32 stack_ptr;
438 u32 hcmd;
439 u32 isr0;
440
441 u32 isr1;
442
443 u32 isr2;
444
445 u32 isr3;
446
447 u32 isr4;
448
449 u32 isr_pref;
450 u32 wait_event;
451 u32 l2p_control;
452 u32 l2p_duration;
453 u32 l2p_mhvalid;
454 u32 l2p_addr_match;
455 u32 lmpm_pmg_sel;
456
457 u32 u_timestamp;
458
459 u32 flow_handler;
460 } __packed;
461
462 struct iwl_alive_resp {
463 u8 ucode_minor;
464 u8 ucode_major;
465 __le16 reserved1;
466 u8 sw_rev[8];
467 u8 ver_type;
468 u8 ver_subtype;
469 __le16 reserved2;
470 __le32 log_event_table_ptr;
471 __le32 error_event_table_ptr;
472 __le32 timestamp;
473 __le32 is_valid;
474 } __packed;
475
476
477
478
479 struct iwl_error_resp {
480 __le32 error_type;
481 u8 cmd_id;
482 u8 reserved1;
483 __le16 bad_cmd_seq_num;
484 __le32 error_info;
485 __le64 timestamp;
486 } __packed;
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497
498 enum {
499 RXON_DEV_TYPE_AP = 1,
500 RXON_DEV_TYPE_ESS = 3,
501 RXON_DEV_TYPE_IBSS = 4,
502 RXON_DEV_TYPE_SNIFFER = 6,
503 RXON_DEV_TYPE_CP = 7,
504 RXON_DEV_TYPE_2STA = 8,
505 RXON_DEV_TYPE_P2P = 9,
506 };
507
508
509 #define RXON_RX_CHAIN_DRIVER_FORCE_MSK cpu_to_le16(0x1 << 0)
510 #define RXON_RX_CHAIN_DRIVER_FORCE_POS (0)
511 #define RXON_RX_CHAIN_VALID_MSK cpu_to_le16(0x7 << 1)
512 #define RXON_RX_CHAIN_VALID_POS (1)
513 #define RXON_RX_CHAIN_FORCE_SEL_MSK cpu_to_le16(0x7 << 4)
514 #define RXON_RX_CHAIN_FORCE_SEL_POS (4)
515 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK cpu_to_le16(0x7 << 7)
516 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
517 #define RXON_RX_CHAIN_CNT_MSK cpu_to_le16(0x3 << 10)
518 #define RXON_RX_CHAIN_CNT_POS (10)
519 #define RXON_RX_CHAIN_MIMO_CNT_MSK cpu_to_le16(0x3 << 12)
520 #define RXON_RX_CHAIN_MIMO_CNT_POS (12)
521 #define RXON_RX_CHAIN_MIMO_FORCE_MSK cpu_to_le16(0x1 << 14)
522 #define RXON_RX_CHAIN_MIMO_FORCE_POS (14)
523
524
525
526 #define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0)
527 #define RXON_FLG_CCK_MSK cpu_to_le32(1 << 1)
528
529 #define RXON_FLG_AUTO_DETECT_MSK cpu_to_le32(1 << 2)
530
531 #define RXON_FLG_TGG_PROTECT_MSK cpu_to_le32(1 << 3)
532
533 #define RXON_FLG_SHORT_SLOT_MSK cpu_to_le32(1 << 4)
534 #define RXON_FLG_SHORT_PREAMBLE_MSK cpu_to_le32(1 << 5)
535
536 #define RXON_FLG_DIS_DIV_MSK cpu_to_le32(1 << 7)
537 #define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00)
538 #define RXON_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
539 #define RXON_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
540
541 #define RXON_FLG_RADAR_DETECT_MSK cpu_to_le32(1 << 12)
542 #define RXON_FLG_TGJ_NARROW_BAND_MSK cpu_to_le32(1 << 13)
543
544
545 #define RXON_FLG_TSF2HOST_MSK cpu_to_le32(1 << 15)
546
547
548
549 #define RXON_FLG_CTRL_CHANNEL_LOC_POS (22)
550 #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22)
551
552 #define RXON_FLG_HT_OPERATING_MODE_POS (23)
553
554 #define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23)
555 #define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23)
556
557 #define RXON_FLG_CHANNEL_MODE_POS (25)
558 #define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
559
560
561 enum {
562 CHANNEL_MODE_LEGACY = 0,
563 CHANNEL_MODE_PURE_40 = 1,
564 CHANNEL_MODE_MIXED = 2,
565 CHANNEL_MODE_RESERVED = 3,
566 };
567 #define RXON_FLG_CHANNEL_MODE_LEGACY cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
568 #define RXON_FLG_CHANNEL_MODE_PURE_40 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
569 #define RXON_FLG_CHANNEL_MODE_MIXED cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
570
571
572 #define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
573
574
575
576 #define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0)
577
578 #define RXON_FILTER_CTL2HOST_MSK cpu_to_le32(1 << 1)
579
580 #define RXON_FILTER_ACCEPT_GRP_MSK cpu_to_le32(1 << 2)
581
582 #define RXON_FILTER_DIS_DECRYPT_MSK cpu_to_le32(1 << 3)
583
584 #define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
585
586 #define RXON_FILTER_ASSOC_MSK cpu_to_le32(1 << 5)
587
588 #define RXON_FILTER_BCON_AWARE_MSK cpu_to_le32(1 << 6)
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608 struct iwl_rxon_cmd {
609 u8 node_addr[6];
610 __le16 reserved1;
611 u8 bssid_addr[6];
612 __le16 reserved2;
613 u8 wlap_bssid_addr[6];
614 __le16 reserved3;
615 u8 dev_type;
616 u8 air_propagation;
617 __le16 rx_chain;
618 u8 ofdm_basic_rates;
619 u8 cck_basic_rates;
620 __le16 assoc_id;
621 __le32 flags;
622 __le32 filter_flags;
623 __le16 channel;
624 u8 ofdm_ht_single_stream_basic_rates;
625 u8 ofdm_ht_dual_stream_basic_rates;
626 u8 ofdm_ht_triple_stream_basic_rates;
627 u8 reserved5;
628 __le16 acquisition_data;
629 __le16 reserved6;
630 } __packed;
631
632
633
634
635 struct iwl_rxon_assoc_cmd {
636 __le32 flags;
637 __le32 filter_flags;
638 u8 ofdm_basic_rates;
639 u8 cck_basic_rates;
640 __le16 reserved1;
641 u8 ofdm_ht_single_stream_basic_rates;
642 u8 ofdm_ht_dual_stream_basic_rates;
643 u8 ofdm_ht_triple_stream_basic_rates;
644 u8 reserved2;
645 __le16 rx_chain_select_flags;
646 __le16 acquisition_data;
647 __le32 reserved3;
648 } __packed;
649
650 #define IWL_CONN_MAX_LISTEN_INTERVAL 10
651 #define IWL_MAX_UCODE_BEACON_INTERVAL 4
652
653
654
655
656 struct iwl_rxon_time_cmd {
657 __le64 timestamp;
658 __le16 beacon_interval;
659 __le16 atim_window;
660 __le32 beacon_init_val;
661 __le16 listen_interval;
662 u8 dtim_period;
663 u8 delta_cp_bss_tbtts;
664 } __packed;
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680 struct iwl5000_channel_switch_cmd {
681 u8 band;
682 u8 expect_beacon;
683 __le16 channel;
684 __le32 rxon_flags;
685 __le32 rxon_filter_flags;
686 __le32 switch_time;
687 __le32 reserved[2][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
688 } __packed;
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700
701 struct iwl6000_channel_switch_cmd {
702 u8 band;
703 u8 expect_beacon;
704 __le16 channel;
705 __le32 rxon_flags;
706 __le32 rxon_filter_flags;
707 __le32 switch_time;
708 __le32 reserved[3][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
709 } __packed;
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714 struct iwl_csa_notification {
715 __le16 band;
716 __le16 channel;
717 __le32 status;
718 } __packed;
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741
742 struct iwl_ac_qos {
743 __le16 cw_min;
744 __le16 cw_max;
745 u8 aifsn;
746 u8 reserved1;
747 __le16 edca_txop;
748 } __packed;
749
750
751 #define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01)
752 #define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02)
753 #define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10)
754
755
756 #define AC_NUM 4
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764 struct iwl_qosparam_cmd {
765 __le32 qos_flags;
766 struct iwl_ac_qos ac[AC_NUM];
767 } __packed;
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779 #define IWL_AP_ID 0
780 #define IWL_AP_ID_PAN 1
781 #define IWL_STA_ID 2
782 #define IWLAGN_PAN_BCAST_ID 14
783 #define IWLAGN_BROADCAST_ID 15
784 #define IWLAGN_STATION_COUNT 16
785
786 #define IWL_TID_NON_QOS IWL_MAX_TID_COUNT
787
788 #define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
789 #define STA_FLG_PWR_SAVE_MSK cpu_to_le32(1 << 8)
790 #define STA_FLG_PAN_STATION cpu_to_le32(1 << 13)
791 #define STA_FLG_RTS_MIMO_PROT_MSK cpu_to_le32(1 << 17)
792 #define STA_FLG_AGG_MPDU_8US_MSK cpu_to_le32(1 << 18)
793 #define STA_FLG_MAX_AGG_SIZE_POS (19)
794 #define STA_FLG_MAX_AGG_SIZE_MSK cpu_to_le32(3 << 19)
795 #define STA_FLG_HT40_EN_MSK cpu_to_le32(1 << 21)
796 #define STA_FLG_MIMO_DIS_MSK cpu_to_le32(1 << 22)
797 #define STA_FLG_AGG_MPDU_DENSITY_POS (23)
798 #define STA_FLG_AGG_MPDU_DENSITY_MSK cpu_to_le32(7 << 23)
799
800
801 #define STA_CONTROL_MODIFY_MSK 0x01
802
803
804 #define STA_KEY_FLG_ENCRYPT_MSK cpu_to_le16(0x0007)
805 #define STA_KEY_FLG_NO_ENC cpu_to_le16(0x0000)
806 #define STA_KEY_FLG_WEP cpu_to_le16(0x0001)
807 #define STA_KEY_FLG_CCMP cpu_to_le16(0x0002)
808 #define STA_KEY_FLG_TKIP cpu_to_le16(0x0003)
809
810 #define STA_KEY_FLG_KEYID_POS 8
811 #define STA_KEY_FLG_INVALID cpu_to_le16(0x0800)
812
813 #define STA_KEY_FLG_MAP_KEY_MSK cpu_to_le16(0x0008)
814
815
816 #define STA_KEY_FLG_KEY_SIZE_MSK cpu_to_le16(0x1000)
817 #define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000)
818 #define STA_KEY_MAX_NUM 8
819 #define STA_KEY_MAX_NUM_PAN 16
820
821 #define IWLAGN_HW_KEY_DEFAULT 0xfe
822
823
824 #define STA_MODIFY_KEY_MASK 0x01
825 #define STA_MODIFY_TID_DISABLE_TX 0x02
826 #define STA_MODIFY_TX_RATE_MSK 0x04
827 #define STA_MODIFY_ADDBA_TID_MSK 0x08
828 #define STA_MODIFY_DELBA_TID_MSK 0x10
829 #define STA_MODIFY_SLEEP_TX_COUNT_MSK 0x20
830
831
832 struct iwl_keyinfo {
833 __le16 key_flags;
834 u8 tkip_rx_tsc_byte2;
835 u8 reserved1;
836 __le16 tkip_rx_ttak[5];
837 u8 key_offset;
838 u8 reserved2;
839 u8 key[16];
840 __le64 tx_secur_seq_cnt;
841 __le64 hw_tkip_mic_rx_key;
842 __le64 hw_tkip_mic_tx_key;
843 } __packed;
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857 struct sta_id_modify {
858 u8 addr[ETH_ALEN];
859 __le16 reserved1;
860 u8 sta_id;
861 u8 modify_mask;
862 __le16 reserved2;
863 } __packed;
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872
873
874
875
876
877
878
879
880
881
882
883
884
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886
887
888
889
890
891 struct iwl_addsta_cmd {
892 u8 mode;
893 u8 reserved[3];
894 struct sta_id_modify sta;
895 struct iwl_keyinfo key;
896 __le32 station_flags;
897 __le32 station_flags_msk;
898
899
900
901
902 __le16 tid_disable_tx;
903 __le16 legacy_reserved;
904
905
906
907 u8 add_immediate_ba_tid;
908
909
910
911 u8 remove_immediate_ba_tid;
912
913
914
915 __le16 add_immediate_ba_ssn;
916
917
918
919
920
921
922 __le16 sleep_tx_count;
923
924 __le16 reserved2;
925 } __packed;
926
927
928 #define ADD_STA_SUCCESS_MSK 0x1
929 #define ADD_STA_NO_ROOM_IN_TABLE 0x2
930 #define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4
931 #define ADD_STA_MODIFY_NON_EXIST_STA 0x8
932
933
934
935 struct iwl_add_sta_resp {
936 u8 status;
937 } __packed;
938
939 #define REM_STA_SUCCESS_MSK 0x1
940
941
942
943 struct iwl_rem_sta_resp {
944 u8 status;
945 } __packed;
946
947
948
949
950 struct iwl_rem_sta_cmd {
951 u8 num_sta;
952 u8 reserved[3];
953 u8 addr[ETH_ALEN];
954 u8 reserved2[2];
955 } __packed;
956
957
958
959 #define IWL_SCD_BK_MSK BIT(0)
960 #define IWL_SCD_BE_MSK BIT(1)
961 #define IWL_SCD_VI_MSK BIT(2)
962 #define IWL_SCD_VO_MSK BIT(3)
963 #define IWL_SCD_MGMT_MSK BIT(3)
964
965
966 #define IWL_PAN_SCD_BK_MSK BIT(4)
967 #define IWL_PAN_SCD_BE_MSK BIT(5)
968 #define IWL_PAN_SCD_VI_MSK BIT(6)
969 #define IWL_PAN_SCD_VO_MSK BIT(7)
970 #define IWL_PAN_SCD_MGMT_MSK BIT(7)
971 #define IWL_PAN_SCD_MULTICAST_MSK BIT(8)
972
973 #define IWL_AGG_TX_QUEUE_MSK 0xffc00
974
975 #define IWL_DROP_ALL BIT(1)
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
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992
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994
995
996
997
998 struct iwl_txfifo_flush_cmd_v3 {
999 __le32 queue_control;
1000 __le16 flush_control;
1001 __le16 reserved;
1002 } __packed;
1003
1004 struct iwl_txfifo_flush_cmd_v2 {
1005 __le16 queue_control;
1006 __le16 flush_control;
1007 } __packed;
1008
1009
1010
1011
1012 struct iwl_wep_key {
1013 u8 key_index;
1014 u8 key_offset;
1015 u8 reserved1[2];
1016 u8 key_size;
1017 u8 reserved2[3];
1018 u8 key[16];
1019 } __packed;
1020
1021 struct iwl_wep_cmd {
1022 u8 num_keys;
1023 u8 global_key_type;
1024 u8 flags;
1025 u8 reserved;
1026 struct iwl_wep_key key[0];
1027 } __packed;
1028
1029 #define WEP_KEY_WEP_TYPE 1
1030 #define WEP_KEYS_MAX 4
1031 #define WEP_INVALID_OFFSET 0xff
1032 #define WEP_KEY_LEN_64 5
1033 #define WEP_KEY_LEN_128 13
1034
1035
1036
1037
1038
1039
1040
1041 #define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0)
1042 #define RX_RES_STATUS_NO_RXE_OVERFLOW cpu_to_le32(1 << 1)
1043
1044 #define RX_RES_PHY_FLAGS_BAND_24_MSK cpu_to_le16(1 << 0)
1045 #define RX_RES_PHY_FLAGS_MOD_CCK_MSK cpu_to_le16(1 << 1)
1046 #define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK cpu_to_le16(1 << 2)
1047 #define RX_RES_PHY_FLAGS_NARROW_BAND_MSK cpu_to_le16(1 << 3)
1048 #define RX_RES_PHY_FLAGS_ANTENNA_MSK 0x70
1049 #define RX_RES_PHY_FLAGS_ANTENNA_POS 4
1050 #define RX_RES_PHY_FLAGS_AGG_MSK cpu_to_le16(1 << 7)
1051
1052 #define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
1053 #define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
1054 #define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
1055 #define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
1056 #define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
1057 #define RX_RES_STATUS_SEC_TYPE_ERR (0x7 << 8)
1058
1059 #define RX_RES_STATUS_STATION_FOUND (1<<6)
1060 #define RX_RES_STATUS_NO_STATION_INFO_MISMATCH (1<<7)
1061
1062 #define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
1063 #define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
1064 #define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
1065 #define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
1066 #define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
1067
1068 #define RX_MPDU_RES_STATUS_ICV_OK (0x20)
1069 #define RX_MPDU_RES_STATUS_MIC_OK (0x40)
1070 #define RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
1071 #define RX_MPDU_RES_STATUS_DEC_DONE_MSK (0x800)
1072
1073
1074 #define IWLAGN_RX_RES_PHY_CNT 8
1075 #define IWLAGN_RX_RES_AGC_IDX 1
1076 #define IWLAGN_RX_RES_RSSI_AB_IDX 2
1077 #define IWLAGN_RX_RES_RSSI_C_IDX 3
1078 #define IWLAGN_OFDM_AGC_MSK 0xfe00
1079 #define IWLAGN_OFDM_AGC_BIT_POS 9
1080 #define IWLAGN_OFDM_RSSI_INBAND_A_BITMSK 0x00ff
1081 #define IWLAGN_OFDM_RSSI_ALLBAND_A_BITMSK 0xff00
1082 #define IWLAGN_OFDM_RSSI_A_BIT_POS 0
1083 #define IWLAGN_OFDM_RSSI_INBAND_B_BITMSK 0xff0000
1084 #define IWLAGN_OFDM_RSSI_ALLBAND_B_BITMSK 0xff000000
1085 #define IWLAGN_OFDM_RSSI_B_BIT_POS 16
1086 #define IWLAGN_OFDM_RSSI_INBAND_C_BITMSK 0x00ff
1087 #define IWLAGN_OFDM_RSSI_ALLBAND_C_BITMSK 0xff00
1088 #define IWLAGN_OFDM_RSSI_C_BIT_POS 0
1089
1090 struct iwlagn_non_cfg_phy {
1091 __le32 non_cfg_phy[IWLAGN_RX_RES_PHY_CNT];
1092 } __packed;
1093
1094
1095
1096
1097
1098
1099 struct iwl_rx_phy_res {
1100 u8 non_cfg_phy_cnt;
1101 u8 cfg_phy_cnt;
1102 u8 stat_id;
1103 u8 reserved1;
1104 __le64 timestamp;
1105 __le32 beacon_time_stamp;
1106 __le16 phy_flags;
1107 __le16 channel;
1108 u8 non_cfg_phy_buf[32];
1109 __le32 rate_n_flags;
1110 __le16 byte_count;
1111 __le16 frame_time;
1112 } __packed;
1113
1114 struct iwl_rx_mpdu_res_start {
1115 __le16 byte_count;
1116 __le16 reserved;
1117 } __packed;
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
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1143
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1147
1148
1149
1150
1151 #define TX_CMD_FLG_PROT_REQUIRE_MSK cpu_to_le32(1 << 0)
1152
1153
1154
1155
1156 #define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
1157
1158
1159
1160
1161
1162
1163
1164 #define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
1165
1166
1167
1168 #define TX_CMD_FLG_IMM_BA_RSP_MASK cpu_to_le32(1 << 6)
1169
1170
1171 #define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1172
1173
1174
1175 #define TX_CMD_FLG_IGNORE_BT cpu_to_le32(1 << 12)
1176
1177
1178
1179
1180
1181 #define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
1182
1183
1184
1185 #define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
1186
1187
1188
1189
1190 #define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
1191
1192
1193
1194
1195
1196
1197
1198 #define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
1199
1200
1201
1202 #define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
1203
1204
1205 #define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
1206
1207
1208
1209
1210
1211 #define TX_CMD_SEC_WEP 0x01
1212 #define TX_CMD_SEC_CCM 0x02
1213 #define TX_CMD_SEC_TKIP 0x03
1214 #define TX_CMD_SEC_MSK 0x03
1215 #define TX_CMD_SEC_SHIFT 6
1216 #define TX_CMD_SEC_KEY128 0x08
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226 struct iwl_dram_scratch {
1227 u8 try_cnt;
1228 u8 bt_kill_cnt;
1229 __le16 reserved;
1230 } __packed;
1231
1232 struct iwl_tx_cmd {
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243 __le16 len;
1244
1245
1246
1247
1248
1249
1250 __le16 next_frame_len;
1251
1252 __le32 tx_flags;
1253
1254
1255
1256 struct iwl_dram_scratch scratch;
1257
1258
1259 __le32 rate_n_flags;
1260
1261
1262 u8 sta_id;
1263
1264
1265 u8 sec_ctl;
1266
1267
1268
1269
1270
1271
1272
1273
1274 u8 initial_rate_index;
1275 u8 reserved;
1276 u8 key[16];
1277 __le16 next_frame_flags;
1278 __le16 reserved2;
1279 union {
1280 __le32 life_time;
1281 __le32 attempt;
1282 } stop_time;
1283
1284
1285
1286 __le32 dram_lsb_ptr;
1287 u8 dram_msb_ptr;
1288
1289 u8 rts_retry_limit;
1290 u8 data_retry_limit;
1291 u8 tid_tspec;
1292 union {
1293 __le16 pm_frame_timeout;
1294 __le16 attempt_duration;
1295 } timeout;
1296
1297
1298
1299
1300
1301 __le16 driver_txop;
1302
1303
1304
1305
1306
1307 u8 payload[0];
1308 struct ieee80211_hdr hdr[0];
1309 } __packed;
1310
1311
1312
1313
1314
1315
1316
1317
1318 enum {
1319 TX_STATUS_SUCCESS = 0x01,
1320 TX_STATUS_DIRECT_DONE = 0x02,
1321
1322 TX_STATUS_POSTPONE_DELAY = 0x40,
1323 TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
1324 TX_STATUS_POSTPONE_BT_PRIO = 0x42,
1325 TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
1326 TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
1327
1328 TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
1329 TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
1330 TX_STATUS_FAIL_LONG_LIMIT = 0x83,
1331 TX_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
1332 TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
1333 TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
1334 TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
1335 TX_STATUS_FAIL_DEST_PS = 0x88,
1336 TX_STATUS_FAIL_HOST_ABORTED = 0x89,
1337 TX_STATUS_FAIL_BT_RETRY = 0x8a,
1338 TX_STATUS_FAIL_STA_INVALID = 0x8b,
1339 TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
1340 TX_STATUS_FAIL_TID_DISABLE = 0x8d,
1341 TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
1342 TX_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
1343 TX_STATUS_FAIL_PASSIVE_NO_RX = 0x90,
1344 TX_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
1345 };
1346
1347 #define TX_PACKET_MODE_REGULAR 0x0000
1348 #define TX_PACKET_MODE_BURST_SEQ 0x0100
1349 #define TX_PACKET_MODE_BURST_FIRST 0x0200
1350
1351 enum {
1352 TX_POWER_PA_NOT_ACTIVE = 0x0,
1353 };
1354
1355 enum {
1356 TX_STATUS_MSK = 0x000000ff,
1357 TX_STATUS_DELAY_MSK = 0x00000040,
1358 TX_STATUS_ABORT_MSK = 0x00000080,
1359 TX_PACKET_MODE_MSK = 0x0000ff00,
1360 TX_FIFO_NUMBER_MSK = 0x00070000,
1361 TX_RESERVED = 0x00780000,
1362 TX_POWER_PA_DETECT_MSK = 0x7f800000,
1363 TX_ABORT_REQUIRED_MSK = 0x80000000,
1364 };
1365
1366
1367
1368
1369
1370 enum {
1371 AGG_TX_STATE_TRANSMITTED = 0x00,
1372 AGG_TX_STATE_UNDERRUN_MSK = 0x01,
1373 AGG_TX_STATE_BT_PRIO_MSK = 0x02,
1374 AGG_TX_STATE_FEW_BYTES_MSK = 0x04,
1375 AGG_TX_STATE_ABORT_MSK = 0x08,
1376 AGG_TX_STATE_LAST_SENT_TTL_MSK = 0x10,
1377 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK = 0x20,
1378 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK = 0x40,
1379 AGG_TX_STATE_SCD_QUERY_MSK = 0x80,
1380 AGG_TX_STATE_TEST_BAD_CRC32_MSK = 0x100,
1381 AGG_TX_STATE_RESPONSE_MSK = 0x1ff,
1382 AGG_TX_STATE_DUMP_TX_MSK = 0x200,
1383 AGG_TX_STATE_DELAY_TX_MSK = 0x400
1384 };
1385
1386 #define AGG_TX_STATUS_MSK 0x00000fff
1387 #define AGG_TX_TRY_MSK 0x0000f000
1388 #define AGG_TX_TRY_POS 12
1389
1390 #define AGG_TX_STATE_LAST_SENT_MSK (AGG_TX_STATE_LAST_SENT_TTL_MSK | \
1391 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK | \
1392 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK)
1393
1394
1395 #define AGG_TX_STATE_TRY_CNT_POS 12
1396 #define AGG_TX_STATE_TRY_CNT_MSK 0xf000
1397
1398
1399 #define AGG_TX_STATE_SEQ_NUM_POS 16
1400 #define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1401
1402
1403
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1416
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1418
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1420
1421
1422
1423
1424 struct agg_tx_status {
1425 __le16 status;
1426 __le16 sequence;
1427 } __packed;
1428
1429
1430 #define IWLAGN_TX_RES_TID_POS 0
1431 #define IWLAGN_TX_RES_TID_MSK 0x0f
1432 #define IWLAGN_TX_RES_RA_POS 4
1433 #define IWLAGN_TX_RES_RA_MSK 0xf0
1434
1435 struct iwlagn_tx_resp {
1436 u8 frame_count;
1437 u8 bt_kill_count;
1438 u8 failure_rts;
1439 u8 failure_frame;
1440
1441
1442
1443 __le32 rate_n_flags;
1444
1445
1446
1447 __le16 wireless_media_time;
1448
1449 u8 pa_status;
1450 u8 pa_integ_res_a[3];
1451 u8 pa_integ_res_b[3];
1452 u8 pa_integ_res_C[3];
1453
1454 __le32 tfd_info;
1455 __le16 seq_ctl;
1456 __le16 byte_cnt;
1457 u8 tlc_info;
1458 u8 ra_tid;
1459 __le16 frame_ctrl;
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473 struct agg_tx_status status;
1474
1475 } __packed;
1476
1477
1478
1479
1480
1481 struct iwl_compressed_ba_resp {
1482 __le32 sta_addr_lo32;
1483 __le16 sta_addr_hi16;
1484 __le16 reserved;
1485
1486
1487 u8 sta_id;
1488 u8 tid;
1489 __le16 seq_ctl;
1490 __le64 bitmap;
1491 __le16 scd_flow;
1492 __le16 scd_ssn;
1493 u8 txed;
1494 u8 txed_2_done;
1495 __le16 reserved1;
1496 } __packed;
1497
1498
1499
1500
1501
1502
1503
1504 #define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1 << 0)
1505
1506
1507 #define LINK_QUAL_AC_NUM AC_NUM
1508
1509
1510 #define LINK_QUAL_MAX_RETRY_NUM 16
1511
1512
1513 #define LINK_QUAL_ANT_A_MSK (1 << 0)
1514 #define LINK_QUAL_ANT_B_MSK (1 << 1)
1515 #define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK)
1516
1517
1518
1519
1520
1521
1522
1523 struct iwl_link_qual_general_params {
1524 u8 flags;
1525
1526
1527 u8 mimo_delimiter;
1528
1529
1530 u8 single_stream_ant_msk;
1531
1532
1533 u8 dual_stream_ant_msk;
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546 u8 start_rate_index[LINK_QUAL_AC_NUM];
1547 } __packed;
1548
1549 #define LINK_QUAL_AGG_TIME_LIMIT_DEF (4000)
1550 #define LINK_QUAL_AGG_TIME_LIMIT_MAX (8000)
1551 #define LINK_QUAL_AGG_TIME_LIMIT_MIN (100)
1552
1553 #define LINK_QUAL_AGG_DISABLE_START_DEF (3)
1554 #define LINK_QUAL_AGG_DISABLE_START_MAX (255)
1555 #define LINK_QUAL_AGG_DISABLE_START_MIN (0)
1556
1557 #define LINK_QUAL_AGG_FRAME_LIMIT_DEF (63)
1558 #define LINK_QUAL_AGG_FRAME_LIMIT_MAX (63)
1559 #define LINK_QUAL_AGG_FRAME_LIMIT_MIN (0)
1560
1561
1562
1563
1564
1565
1566 struct iwl_link_qual_agg_params {
1567
1568
1569
1570
1571
1572 __le16 agg_time_limit;
1573
1574
1575
1576
1577
1578
1579
1580 u8 agg_dis_start_th;
1581
1582
1583
1584
1585
1586
1587 u8 agg_frame_cnt_limit;
1588
1589 __le32 reserved;
1590 } __packed;
1591
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1776
1777
1778
1779
1780 struct iwl_link_quality_cmd {
1781
1782
1783 u8 sta_id;
1784 u8 reserved1;
1785 __le16 control;
1786 struct iwl_link_qual_general_params general_params;
1787 struct iwl_link_qual_agg_params agg_params;
1788
1789
1790
1791
1792
1793
1794 struct {
1795 __le32 rate_n_flags;
1796 } rs_table[LINK_QUAL_MAX_RETRY_NUM];
1797 __le32 reserved2;
1798 } __packed;
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809 #define BT_COEX_DISABLE (0x0)
1810 #define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0)
1811 #define BT_ENABLE_PRIORITY BIT(1)
1812 #define BT_ENABLE_2_WIRE BIT(2)
1813
1814 #define BT_COEX_DISABLE (0x0)
1815 #define BT_COEX_ENABLE (BT_ENABLE_CHANNEL_ANNOUNCE | BT_ENABLE_PRIORITY)
1816
1817 #define BT_LEAD_TIME_MIN (0x0)
1818 #define BT_LEAD_TIME_DEF (0x1E)
1819 #define BT_LEAD_TIME_MAX (0xFF)
1820
1821 #define BT_MAX_KILL_MIN (0x1)
1822 #define BT_MAX_KILL_DEF (0x5)
1823 #define BT_MAX_KILL_MAX (0xFF)
1824
1825 #define BT_DURATION_LIMIT_DEF 625
1826 #define BT_DURATION_LIMIT_MAX 1250
1827 #define BT_DURATION_LIMIT_MIN 625
1828
1829 #define BT_ON_THRESHOLD_DEF 4
1830 #define BT_ON_THRESHOLD_MAX 1000
1831 #define BT_ON_THRESHOLD_MIN 1
1832
1833 #define BT_FRAG_THRESHOLD_DEF 0
1834 #define BT_FRAG_THRESHOLD_MAX 0
1835 #define BT_FRAG_THRESHOLD_MIN 0
1836
1837 #define BT_AGG_THRESHOLD_DEF 1200
1838 #define BT_AGG_THRESHOLD_MAX 8000
1839 #define BT_AGG_THRESHOLD_MIN 400
1840
1841
1842
1843
1844
1845
1846
1847
1848 struct iwl_bt_cmd {
1849 u8 flags;
1850 u8 lead_time;
1851 u8 max_kill;
1852 u8 reserved;
1853 __le32 kill_ack_mask;
1854 __le32 kill_cts_mask;
1855 } __packed;
1856
1857 #define IWLAGN_BT_FLAG_CHANNEL_INHIBITION BIT(0)
1858
1859 #define IWLAGN_BT_FLAG_COEX_MODE_MASK (BIT(3)|BIT(4)|BIT(5))
1860 #define IWLAGN_BT_FLAG_COEX_MODE_SHIFT 3
1861 #define IWLAGN_BT_FLAG_COEX_MODE_DISABLED 0
1862 #define IWLAGN_BT_FLAG_COEX_MODE_LEGACY_2W 1
1863 #define IWLAGN_BT_FLAG_COEX_MODE_3W 2
1864 #define IWLAGN_BT_FLAG_COEX_MODE_4W 3
1865
1866 #define IWLAGN_BT_FLAG_UCODE_DEFAULT BIT(6)
1867
1868 #define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE BIT(7)
1869
1870 #define IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD -75
1871 #define IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD -65
1872
1873 #define IWLAGN_BT_PRIO_BOOST_MAX 0xFF
1874 #define IWLAGN_BT_PRIO_BOOST_MIN 0x00
1875 #define IWLAGN_BT_PRIO_BOOST_DEFAULT 0xF0
1876 #define IWLAGN_BT_PRIO_BOOST_DEFAULT32 0xF0F0F0F0
1877
1878 #define IWLAGN_BT_MAX_KILL_DEFAULT 5
1879
1880 #define IWLAGN_BT3_T7_DEFAULT 1
1881
1882 enum iwl_bt_kill_idx {
1883 IWL_BT_KILL_DEFAULT = 0,
1884 IWL_BT_KILL_OVERRIDE = 1,
1885 IWL_BT_KILL_REDUCE = 2,
1886 };
1887
1888 #define IWLAGN_BT_KILL_ACK_MASK_DEFAULT cpu_to_le32(0xffff0000)
1889 #define IWLAGN_BT_KILL_CTS_MASK_DEFAULT cpu_to_le32(0xffff0000)
1890 #define IWLAGN_BT_KILL_ACK_CTS_MASK_SCO cpu_to_le32(0xffffffff)
1891 #define IWLAGN_BT_KILL_ACK_CTS_MASK_REDUCE cpu_to_le32(0)
1892
1893 #define IWLAGN_BT3_PRIO_SAMPLE_DEFAULT 2
1894
1895 #define IWLAGN_BT3_T2_DEFAULT 0xc
1896
1897 #define IWLAGN_BT_VALID_ENABLE_FLAGS cpu_to_le16(BIT(0))
1898 #define IWLAGN_BT_VALID_BOOST cpu_to_le16(BIT(1))
1899 #define IWLAGN_BT_VALID_MAX_KILL cpu_to_le16(BIT(2))
1900 #define IWLAGN_BT_VALID_3W_TIMERS cpu_to_le16(BIT(3))
1901 #define IWLAGN_BT_VALID_KILL_ACK_MASK cpu_to_le16(BIT(4))
1902 #define IWLAGN_BT_VALID_KILL_CTS_MASK cpu_to_le16(BIT(5))
1903 #define IWLAGN_BT_VALID_REDUCED_TX_PWR cpu_to_le16(BIT(6))
1904 #define IWLAGN_BT_VALID_3W_LUT cpu_to_le16(BIT(7))
1905
1906 #define IWLAGN_BT_ALL_VALID_MSK (IWLAGN_BT_VALID_ENABLE_FLAGS | \
1907 IWLAGN_BT_VALID_BOOST | \
1908 IWLAGN_BT_VALID_MAX_KILL | \
1909 IWLAGN_BT_VALID_3W_TIMERS | \
1910 IWLAGN_BT_VALID_KILL_ACK_MASK | \
1911 IWLAGN_BT_VALID_KILL_CTS_MASK | \
1912 IWLAGN_BT_VALID_REDUCED_TX_PWR | \
1913 IWLAGN_BT_VALID_3W_LUT)
1914
1915 #define IWLAGN_BT_REDUCED_TX_PWR BIT(0)
1916
1917 #define IWLAGN_BT_DECISION_LUT_SIZE 12
1918
1919 struct iwl_basic_bt_cmd {
1920 u8 flags;
1921 u8 ledtime;
1922 u8 max_kill;
1923 u8 bt3_timer_t7_value;
1924 __le32 kill_ack_mask;
1925 __le32 kill_cts_mask;
1926 u8 bt3_prio_sample_time;
1927 u8 bt3_timer_t2_value;
1928 __le16 bt4_reaction_time;
1929 __le32 bt3_lookup_table[IWLAGN_BT_DECISION_LUT_SIZE];
1930
1931
1932
1933
1934 u8 reduce_txpower;
1935 u8 reserved;
1936 __le16 valid;
1937 };
1938
1939 struct iwl_bt_cmd_v1 {
1940 struct iwl_basic_bt_cmd basic;
1941 u8 prio_boost;
1942
1943
1944
1945
1946 u8 tx_prio_boost;
1947 __le16 rx_prio_boost;
1948 };
1949
1950 struct iwl_bt_cmd_v2 {
1951 struct iwl_basic_bt_cmd basic;
1952 __le32 prio_boost;
1953
1954
1955
1956
1957 u8 reserved;
1958 u8 tx_prio_boost;
1959 __le16 rx_prio_boost;
1960 };
1961
1962 #define IWLAGN_BT_SCO_ACTIVE cpu_to_le32(BIT(0))
1963
1964 struct iwlagn_bt_sco_cmd {
1965 __le32 flags;
1966 };
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977 #define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK | \
1978 RXON_FILTER_CTL2HOST_MSK | \
1979 RXON_FILTER_ACCEPT_GRP_MSK | \
1980 RXON_FILTER_DIS_DECRYPT_MSK | \
1981 RXON_FILTER_DIS_GRP_DECRYPT_MSK | \
1982 RXON_FILTER_ASSOC_MSK | \
1983 RXON_FILTER_BCON_AWARE_MSK)
1984
1985 struct iwl_measure_channel {
1986 __le32 duration;
1987
1988 u8 channel;
1989 u8 type;
1990 __le16 reserved;
1991 } __packed;
1992
1993
1994
1995
1996 struct iwl_spectrum_cmd {
1997 __le16 len;
1998 u8 token;
1999 u8 id;
2000 u8 origin;
2001 u8 periodic;
2002 __le16 path_loss_timeout;
2003 __le32 start_time;
2004 __le32 reserved2;
2005 __le32 flags;
2006 __le32 filter_flags;
2007 __le16 channel_count;
2008 __le16 reserved3;
2009 struct iwl_measure_channel channels[10];
2010 } __packed;
2011
2012
2013
2014
2015 struct iwl_spectrum_resp {
2016 u8 token;
2017 u8 id;
2018 __le16 status;
2019
2020
2021 } __packed;
2022
2023 enum iwl_measurement_state {
2024 IWL_MEASUREMENT_START = 0,
2025 IWL_MEASUREMENT_STOP = 1,
2026 };
2027
2028 enum iwl_measurement_status {
2029 IWL_MEASUREMENT_OK = 0,
2030 IWL_MEASUREMENT_CONCURRENT = 1,
2031 IWL_MEASUREMENT_CSA_CONFLICT = 2,
2032 IWL_MEASUREMENT_TGH_CONFLICT = 3,
2033
2034 IWL_MEASUREMENT_STOPPED = 6,
2035 IWL_MEASUREMENT_TIMEOUT = 7,
2036 IWL_MEASUREMENT_PERIODIC_FAILED = 8,
2037 };
2038
2039 #define NUM_ELEMENTS_IN_HISTOGRAM 8
2040
2041 struct iwl_measurement_histogram {
2042 __le32 ofdm[NUM_ELEMENTS_IN_HISTOGRAM];
2043 __le32 cck[NUM_ELEMENTS_IN_HISTOGRAM];
2044 } __packed;
2045
2046
2047 struct iwl_measurement_cca_counters {
2048 __le32 ofdm;
2049 __le32 cck;
2050 } __packed;
2051
2052 enum iwl_measure_type {
2053 IWL_MEASURE_BASIC = (1 << 0),
2054 IWL_MEASURE_CHANNEL_LOAD = (1 << 1),
2055 IWL_MEASURE_HISTOGRAM_RPI = (1 << 2),
2056 IWL_MEASURE_HISTOGRAM_NOISE = (1 << 3),
2057 IWL_MEASURE_FRAME = (1 << 4),
2058
2059 IWL_MEASURE_IDLE = (1 << 7),
2060 };
2061
2062
2063
2064
2065 struct iwl_spectrum_notification {
2066 u8 id;
2067 u8 token;
2068 u8 channel_index;
2069 u8 state;
2070 __le32 start_time;
2071 u8 band;
2072 u8 channel;
2073 u8 type;
2074 u8 reserved1;
2075
2076
2077 __le32 cca_ofdm;
2078 __le32 cca_cck;
2079 __le32 cca_time;
2080 u8 basic_type;
2081
2082 u8 reserved2[3];
2083 struct iwl_measurement_histogram histogram;
2084 __le32 stop_time;
2085 __le32 status;
2086 } __packed;
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129 #define IWL_POWER_VEC_SIZE 5
2130
2131 #define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0))
2132 #define IWL_POWER_POWER_SAVE_ENA_MSK cpu_to_le16(BIT(0))
2133 #define IWL_POWER_POWER_MANAGEMENT_ENA_MSK cpu_to_le16(BIT(1))
2134 #define IWL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2))
2135 #define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3))
2136 #define IWL_POWER_FAST_PD cpu_to_le16(BIT(4))
2137 #define IWL_POWER_BEACON_FILTERING cpu_to_le16(BIT(5))
2138 #define IWL_POWER_SHADOW_REG_ENA cpu_to_le16(BIT(6))
2139 #define IWL_POWER_CT_KILL_SET cpu_to_le16(BIT(7))
2140 #define IWL_POWER_BT_SCO_ENA cpu_to_le16(BIT(8))
2141 #define IWL_POWER_ADVANCE_PM_ENA_MSK cpu_to_le16(BIT(9))
2142
2143 struct iwl_powertable_cmd {
2144 __le16 flags;
2145 u8 keep_alive_seconds;
2146 u8 debug_flags;
2147 __le32 rx_data_timeout;
2148 __le32 tx_data_timeout;
2149 __le32 sleep_interval[IWL_POWER_VEC_SIZE];
2150 __le32 keep_alive_beacons;
2151 } __packed;
2152
2153
2154
2155
2156
2157 struct iwl_sleep_notification {
2158 u8 pm_sleep_mode;
2159 u8 pm_wakeup_src;
2160 __le16 reserved;
2161 __le32 sleep_time;
2162 __le32 tsf_low;
2163 __le32 bcon_timer;
2164 } __packed;
2165
2166
2167 enum {
2168 IWL_PM_NO_SLEEP = 0,
2169 IWL_PM_SLP_MAC = 1,
2170 IWL_PM_SLP_FULL_MAC_UNASSOCIATE = 2,
2171 IWL_PM_SLP_FULL_MAC_CARD_STATE = 3,
2172 IWL_PM_SLP_PHY = 4,
2173 IWL_PM_SLP_REPENT = 5,
2174 IWL_PM_WAKEUP_BY_TIMER = 6,
2175 IWL_PM_WAKEUP_BY_DRIVER = 7,
2176 IWL_PM_WAKEUP_BY_RFKILL = 8,
2177
2178 IWL_PM_NUM_OF_MODES = 12,
2179 };
2180
2181
2182
2183
2184 #define CARD_STATE_CMD_DISABLE 0x00
2185 #define CARD_STATE_CMD_ENABLE 0x01
2186 #define CARD_STATE_CMD_HALT 0x02
2187 struct iwl_card_state_cmd {
2188 __le32 status;
2189 } __packed;
2190
2191
2192
2193
2194 struct iwl_card_state_notif {
2195 __le32 flags;
2196 } __packed;
2197
2198 #define HW_CARD_DISABLED 0x01
2199 #define SW_CARD_DISABLED 0x02
2200 #define CT_CARD_DISABLED 0x04
2201 #define RXON_CARD_DISABLED 0x10
2202
2203 struct iwl_ct_kill_config {
2204 __le32 reserved;
2205 __le32 critical_temperature_M;
2206 __le32 critical_temperature_R;
2207 } __packed;
2208
2209
2210 struct iwl_ct_kill_throttling_config {
2211 __le32 critical_temperature_exit;
2212 __le32 reserved;
2213 __le32 critical_temperature_enter;
2214 } __packed;
2215
2216
2217
2218
2219
2220
2221
2222 #define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2223 #define SCAN_CHANNEL_TYPE_ACTIVE cpu_to_le32(1)
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245 struct iwl_scan_channel {
2246
2247
2248
2249
2250
2251
2252
2253 __le32 type;
2254 __le16 channel;
2255 u8 tx_gain;
2256 u8 dsp_atten;
2257 __le16 active_dwell;
2258 __le16 passive_dwell;
2259 } __packed;
2260
2261
2262 #define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272 struct iwl_ssid_ie {
2273 u8 id;
2274 u8 len;
2275 u8 ssid[32];
2276 } __packed;
2277
2278 #define PROBE_OPTION_MAX 20
2279 #define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF)
2280 #define IWL_GOOD_CRC_TH_DISABLED 0
2281 #define IWL_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
2282 #define IWL_GOOD_CRC_TH_NEVER cpu_to_le16(0xffff)
2283 #define IWL_MAX_CMD_SIZE 4096
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338 enum iwl_scan_flags {
2339
2340 IWL_SCAN_FLAGS_ACTION_FRAME_TX = BIT(1),
2341
2342 };
2343
2344 struct iwl_scan_cmd {
2345 __le16 len;
2346 u8 scan_flags;
2347 u8 channel_count;
2348 __le16 quiet_time;
2349
2350 __le16 quiet_plcp_th;
2351 __le16 good_CRC_th;
2352 __le16 rx_chain;
2353 __le32 max_out_time;
2354
2355 __le32 suspend_time;
2356
2357
2358 __le32 flags;
2359 __le32 filter_flags;
2360
2361
2362
2363 struct iwl_tx_cmd tx_cmd;
2364
2365
2366 struct iwl_ssid_ie direct_scan[PROBE_OPTION_MAX];
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383 u8 data[0];
2384 } __packed;
2385
2386
2387 #define CAN_ABORT_STATUS cpu_to_le32(0x1)
2388
2389 #define ABORT_STATUS 0x2
2390
2391
2392
2393
2394 struct iwl_scanreq_notification {
2395 __le32 status;
2396 } __packed;
2397
2398
2399
2400
2401 struct iwl_scanstart_notification {
2402 __le32 tsf_low;
2403 __le32 tsf_high;
2404 __le32 beacon_timer;
2405 u8 channel;
2406 u8 band;
2407 u8 reserved[2];
2408 __le32 status;
2409 } __packed;
2410
2411 #define SCAN_OWNER_STATUS 0x1
2412 #define MEASURE_OWNER_STATUS 0x2
2413
2414 #define IWL_PROBE_STATUS_OK 0
2415 #define IWL_PROBE_STATUS_TX_FAILED BIT(0)
2416
2417 #define IWL_PROBE_STATUS_FAIL_TTL BIT(1)
2418 #define IWL_PROBE_STATUS_FAIL_BT BIT(2)
2419
2420 #define NUMBER_OF_STATISTICS 1
2421
2422
2423
2424 struct iwl_scanresults_notification {
2425 u8 channel;
2426 u8 band;
2427 u8 probe_status;
2428 u8 num_probe_not_sent;
2429 __le32 tsf_low;
2430 __le32 tsf_high;
2431 __le32 statistics[NUMBER_OF_STATISTICS];
2432 } __packed;
2433
2434
2435
2436
2437 struct iwl_scancomplete_notification {
2438 u8 scanned_channels;
2439 u8 status;
2440 u8 bt_status;
2441 u8 last_channel;
2442 __le32 tsf_low;
2443 __le32 tsf_high;
2444 } __packed;
2445
2446
2447
2448
2449
2450
2451
2452
2453 enum iwl_ibss_manager {
2454 IWL_NOT_IBSS_MANAGER = 0,
2455 IWL_IBSS_MANAGER = 1,
2456 };
2457
2458
2459
2460
2461
2462 struct iwlagn_beacon_notif {
2463 struct iwlagn_tx_resp beacon_notify_hdr;
2464 __le32 low_tsf;
2465 __le32 high_tsf;
2466 __le32 ibss_mgr_status;
2467 } __packed;
2468
2469
2470
2471
2472
2473 struct iwl_tx_beacon_cmd {
2474 struct iwl_tx_cmd tx;
2475 __le16 tim_idx;
2476 u8 tim_size;
2477 u8 reserved1;
2478 struct ieee80211_hdr frame[0];
2479 } __packed;
2480
2481
2482
2483
2484
2485
2486
2487 #define IWL_TEMP_CONVERT 260
2488
2489 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8
2490 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4
2491 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12
2492
2493
2494 struct rate_histogram {
2495 union {
2496 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2497 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2498 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2499 } success;
2500 union {
2501 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2502 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2503 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2504 } failed;
2505 } __packed;
2506
2507
2508
2509 struct statistics_dbg {
2510 __le32 burst_check;
2511 __le32 burst_count;
2512 __le32 wait_for_silence_timeout_cnt;
2513 __le32 reserved[3];
2514 } __packed;
2515
2516 struct statistics_rx_phy {
2517 __le32 ina_cnt;
2518 __le32 fina_cnt;
2519 __le32 plcp_err;
2520 __le32 crc32_err;
2521 __le32 overrun_err;
2522 __le32 early_overrun_err;
2523 __le32 crc32_good;
2524 __le32 false_alarm_cnt;
2525 __le32 fina_sync_err_cnt;
2526 __le32 sfd_timeout;
2527 __le32 fina_timeout;
2528 __le32 unresponded_rts;
2529 __le32 rxe_frame_limit_overrun;
2530 __le32 sent_ack_cnt;
2531 __le32 sent_cts_cnt;
2532 __le32 sent_ba_rsp_cnt;
2533 __le32 dsp_self_kill;
2534 __le32 mh_format_err;
2535 __le32 re_acq_main_rssi_sum;
2536 __le32 reserved3;
2537 } __packed;
2538
2539 struct statistics_rx_ht_phy {
2540 __le32 plcp_err;
2541 __le32 overrun_err;
2542 __le32 early_overrun_err;
2543 __le32 crc32_good;
2544 __le32 crc32_err;
2545 __le32 mh_format_err;
2546 __le32 agg_crc32_good;
2547 __le32 agg_mpdu_cnt;
2548 __le32 agg_cnt;
2549 __le32 unsupport_mcs;
2550 } __packed;
2551
2552 #define INTERFERENCE_DATA_AVAILABLE cpu_to_le32(1)
2553
2554 struct statistics_rx_non_phy {
2555 __le32 bogus_cts;
2556 __le32 bogus_ack;
2557 __le32 non_bssid_frames;
2558
2559 __le32 filtered_frames;
2560
2561 __le32 non_channel_beacons;
2562
2563 __le32 channel_beacons;
2564
2565 __le32 num_missed_bcon;
2566 __le32 adc_rx_saturation_time;
2567
2568 __le32 ina_detection_search_time;
2569
2570 __le32 beacon_silence_rssi_a;
2571 __le32 beacon_silence_rssi_b;
2572 __le32 beacon_silence_rssi_c;
2573 __le32 interference_data_flag;
2574
2575
2576 __le32 channel_load;
2577 __le32 dsp_false_alarms;
2578
2579 __le32 beacon_rssi_a;
2580 __le32 beacon_rssi_b;
2581 __le32 beacon_rssi_c;
2582 __le32 beacon_energy_a;
2583 __le32 beacon_energy_b;
2584 __le32 beacon_energy_c;
2585 } __packed;
2586
2587 struct statistics_rx_non_phy_bt {
2588 struct statistics_rx_non_phy common;
2589
2590 __le32 num_bt_kills;
2591 __le32 reserved[2];
2592 } __packed;
2593
2594 struct statistics_rx {
2595 struct statistics_rx_phy ofdm;
2596 struct statistics_rx_phy cck;
2597 struct statistics_rx_non_phy general;
2598 struct statistics_rx_ht_phy ofdm_ht;
2599 } __packed;
2600
2601 struct statistics_rx_bt {
2602 struct statistics_rx_phy ofdm;
2603 struct statistics_rx_phy cck;
2604 struct statistics_rx_non_phy_bt general;
2605 struct statistics_rx_ht_phy ofdm_ht;
2606 } __packed;
2607
2608
2609
2610
2611
2612
2613
2614
2615 struct statistics_tx_power {
2616 u8 ant_a;
2617 u8 ant_b;
2618 u8 ant_c;
2619 u8 reserved;
2620 } __packed;
2621
2622 struct statistics_tx_non_phy_agg {
2623 __le32 ba_timeout;
2624 __le32 ba_reschedule_frames;
2625 __le32 scd_query_agg_frame_cnt;
2626 __le32 scd_query_no_agg;
2627 __le32 scd_query_agg;
2628 __le32 scd_query_mismatch;
2629 __le32 frame_not_ready;
2630 __le32 underrun;
2631 __le32 bt_prio_kill;
2632 __le32 rx_ba_rsp_cnt;
2633 } __packed;
2634
2635 struct statistics_tx {
2636 __le32 preamble_cnt;
2637 __le32 rx_detected_cnt;
2638 __le32 bt_prio_defer_cnt;
2639 __le32 bt_prio_kill_cnt;
2640 __le32 few_bytes_cnt;
2641 __le32 cts_timeout;
2642 __le32 ack_timeout;
2643 __le32 expected_ack_cnt;
2644 __le32 actual_ack_cnt;
2645 __le32 dump_msdu_cnt;
2646 __le32 burst_abort_next_frame_mismatch_cnt;
2647 __le32 burst_abort_missing_next_frame_cnt;
2648 __le32 cts_timeout_collision;
2649 __le32 ack_or_ba_timeout_collision;
2650 struct statistics_tx_non_phy_agg agg;
2651
2652
2653
2654
2655
2656 struct statistics_tx_power tx_power;
2657 __le32 reserved1;
2658 } __packed;
2659
2660
2661 struct statistics_div {
2662 __le32 tx_on_a;
2663 __le32 tx_on_b;
2664 __le32 exec_time;
2665 __le32 probe_time;
2666 __le32 reserved1;
2667 __le32 reserved2;
2668 } __packed;
2669
2670 struct statistics_general_common {
2671 __le32 temperature;
2672 __le32 temperature_m;
2673 struct statistics_dbg dbg;
2674 __le32 sleep_time;
2675 __le32 slots_out;
2676 __le32 slots_idle;
2677 __le32 ttl_timestamp;
2678 struct statistics_div div;
2679 __le32 rx_enable_counter;
2680
2681
2682
2683
2684
2685 __le32 num_of_sos_states;
2686 } __packed;
2687
2688 struct statistics_bt_activity {
2689
2690 __le32 hi_priority_tx_req_cnt;
2691 __le32 hi_priority_tx_denied_cnt;
2692 __le32 lo_priority_tx_req_cnt;
2693 __le32 lo_priority_tx_denied_cnt;
2694
2695 __le32 hi_priority_rx_req_cnt;
2696 __le32 hi_priority_rx_denied_cnt;
2697 __le32 lo_priority_rx_req_cnt;
2698 __le32 lo_priority_rx_denied_cnt;
2699 } __packed;
2700
2701 struct statistics_general {
2702 struct statistics_general_common common;
2703 __le32 reserved2;
2704 __le32 reserved3;
2705 } __packed;
2706
2707 struct statistics_general_bt {
2708 struct statistics_general_common common;
2709 struct statistics_bt_activity activity;
2710 __le32 reserved2;
2711 __le32 reserved3;
2712 } __packed;
2713
2714 #define UCODE_STATISTICS_CLEAR_MSK (0x1 << 0)
2715 #define UCODE_STATISTICS_FREQUENCY_MSK (0x1 << 1)
2716 #define UCODE_STATISTICS_NARROW_BAND_MSK (0x1 << 2)
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733 #define IWL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1)
2734 #define IWL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)
2735 struct iwl_statistics_cmd {
2736 __le32 configuration_flags;
2737 } __packed;
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754 #define STATISTICS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
2755 #define STATISTICS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)
2756
2757 struct iwl_notif_statistics {
2758 __le32 flag;
2759 struct statistics_rx rx;
2760 struct statistics_tx tx;
2761 struct statistics_general general;
2762 } __packed;
2763
2764 struct iwl_bt_notif_statistics {
2765 __le32 flag;
2766 struct statistics_rx_bt rx;
2767 struct statistics_tx tx;
2768 struct statistics_general_bt general;
2769 } __packed;
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791 #define IWL_MISSED_BEACON_THRESHOLD_MIN (1)
2792 #define IWL_MISSED_BEACON_THRESHOLD_DEF (5)
2793 #define IWL_MISSED_BEACON_THRESHOLD_MAX IWL_MISSED_BEACON_THRESHOLD_DEF
2794
2795 struct iwl_missed_beacon_notif {
2796 __le32 consecutive_missed_beacons;
2797 __le32 total_missed_becons;
2798 __le32 num_expected_beacons;
2799 __le32 num_recvd_beacons;
2800 } __packed;
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
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2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975 #define HD_TABLE_SIZE (11)
2976 #define HD_MIN_ENERGY_CCK_DET_INDEX (0)
2977 #define HD_MIN_ENERGY_OFDM_DET_INDEX (1)
2978 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2)
2979 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3)
2980 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4)
2981 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5)
2982 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6)
2983 #define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7)
2984 #define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8)
2985 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9)
2986 #define HD_OFDM_ENERGY_TH_IN_INDEX (10)
2987
2988
2989
2990
2991 #define HD_INA_NON_SQUARE_DET_OFDM_INDEX (11)
2992 #define HD_INA_NON_SQUARE_DET_CCK_INDEX (12)
2993 #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_INDEX (13)
2994 #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_INDEX (14)
2995 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (15)
2996 #define HD_OFDM_NON_SQUARE_DET_SLOPE_INDEX (16)
2997 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_INDEX (17)
2998 #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_INDEX (18)
2999 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (19)
3000 #define HD_CCK_NON_SQUARE_DET_SLOPE_INDEX (20)
3001 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_INDEX (21)
3002 #define HD_RESERVED (22)
3003
3004
3005 #define ENHANCE_HD_TABLE_SIZE (23)
3006
3007
3008 #define ENHANCE_HD_TABLE_ENTRIES (ENHANCE_HD_TABLE_SIZE - HD_TABLE_SIZE)
3009
3010 #define HD_INA_NON_SQUARE_DET_OFDM_DATA_V1 cpu_to_le16(0)
3011 #define HD_INA_NON_SQUARE_DET_CCK_DATA_V1 cpu_to_le16(0)
3012 #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V1 cpu_to_le16(0)
3013 #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(668)
3014 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3015 #define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(486)
3016 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(37)
3017 #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(853)
3018 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3019 #define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(476)
3020 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(99)
3021
3022 #define HD_INA_NON_SQUARE_DET_OFDM_DATA_V2 cpu_to_le16(1)
3023 #define HD_INA_NON_SQUARE_DET_CCK_DATA_V2 cpu_to_le16(1)
3024 #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V2 cpu_to_le16(1)
3025 #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(600)
3026 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(40)
3027 #define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(486)
3028 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(45)
3029 #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(853)
3030 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(60)
3031 #define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(476)
3032 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(99)
3033
3034
3035
3036 #define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE cpu_to_le16(0)
3037 #define SENSITIVITY_CMD_CONTROL_WORK_TABLE cpu_to_le16(1)
3038
3039
3040
3041
3042
3043
3044
3045
3046 struct iwl_sensitivity_cmd {
3047 __le16 control;
3048 __le16 table[HD_TABLE_SIZE];
3049 } __packed;
3050
3051
3052
3053
3054 struct iwl_enhance_sensitivity_cmd {
3055 __le16 control;
3056 __le16 enhance_table[ENHANCE_HD_TABLE_SIZE];
3057 } __packed;
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116 enum {
3117 IWL_PHY_CALIBRATE_DC_CMD = 8,
3118 IWL_PHY_CALIBRATE_LO_CMD = 9,
3119 IWL_PHY_CALIBRATE_TX_IQ_CMD = 11,
3120 IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD = 15,
3121 IWL_PHY_CALIBRATE_BASE_BAND_CMD = 16,
3122 IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD = 17,
3123 IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD = 18,
3124 };
3125
3126
3127
3128
3129 enum iwl_ucode_calib_cfg {
3130 IWL_CALIB_CFG_RX_BB_IDX = BIT(0),
3131 IWL_CALIB_CFG_DC_IDX = BIT(1),
3132 IWL_CALIB_CFG_LO_IDX = BIT(2),
3133 IWL_CALIB_CFG_TX_IQ_IDX = BIT(3),
3134 IWL_CALIB_CFG_RX_IQ_IDX = BIT(4),
3135 IWL_CALIB_CFG_NOISE_IDX = BIT(5),
3136 IWL_CALIB_CFG_CRYSTAL_IDX = BIT(6),
3137 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(7),
3138 IWL_CALIB_CFG_PAPD_IDX = BIT(8),
3139 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(9),
3140 IWL_CALIB_CFG_TX_PWR_IDX = BIT(10),
3141 };
3142
3143 #define IWL_CALIB_INIT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3144 IWL_CALIB_CFG_DC_IDX | \
3145 IWL_CALIB_CFG_LO_IDX | \
3146 IWL_CALIB_CFG_TX_IQ_IDX | \
3147 IWL_CALIB_CFG_RX_IQ_IDX | \
3148 IWL_CALIB_CFG_CRYSTAL_IDX)
3149
3150 #define IWL_CALIB_RT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3151 IWL_CALIB_CFG_DC_IDX | \
3152 IWL_CALIB_CFG_LO_IDX | \
3153 IWL_CALIB_CFG_TX_IQ_IDX | \
3154 IWL_CALIB_CFG_RX_IQ_IDX | \
3155 IWL_CALIB_CFG_TEMPERATURE_IDX | \
3156 IWL_CALIB_CFG_PAPD_IDX | \
3157 IWL_CALIB_CFG_TX_PWR_IDX | \
3158 IWL_CALIB_CFG_CRYSTAL_IDX)
3159
3160 #define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0))
3161
3162 struct iwl_calib_cfg_elmnt_s {
3163 __le32 is_enable;
3164 __le32 start;
3165 __le32 send_res;
3166 __le32 apply_res;
3167 __le32 reserved;
3168 } __packed;
3169
3170 struct iwl_calib_cfg_status_s {
3171 struct iwl_calib_cfg_elmnt_s once;
3172 struct iwl_calib_cfg_elmnt_s perd;
3173 __le32 flags;
3174 } __packed;
3175
3176 struct iwl_calib_cfg_cmd {
3177 struct iwl_calib_cfg_status_s ucd_calib_cfg;
3178 struct iwl_calib_cfg_status_s drv_calib_cfg;
3179 __le32 reserved1;
3180 } __packed;
3181
3182 struct iwl_calib_hdr {
3183 u8 op_code;
3184 u8 first_group;
3185 u8 groups_num;
3186 u8 data_valid;
3187 } __packed;
3188
3189 struct iwl_calib_cmd {
3190 struct iwl_calib_hdr hdr;
3191 u8 data[0];
3192 } __packed;
3193
3194 struct iwl_calib_xtal_freq_cmd {
3195 struct iwl_calib_hdr hdr;
3196 u8 cap_pin1;
3197 u8 cap_pin2;
3198 u8 pad[2];
3199 } __packed;
3200
3201 #define DEFAULT_RADIO_SENSOR_OFFSET cpu_to_le16(2700)
3202 struct iwl_calib_temperature_offset_cmd {
3203 struct iwl_calib_hdr hdr;
3204 __le16 radio_sensor_offset;
3205 __le16 reserved;
3206 } __packed;
3207
3208 struct iwl_calib_temperature_offset_v2_cmd {
3209 struct iwl_calib_hdr hdr;
3210 __le16 radio_sensor_offset_high;
3211 __le16 radio_sensor_offset_low;
3212 __le16 burntVoltageRef;
3213 __le16 reserved;
3214 } __packed;
3215
3216
3217 struct iwl_calib_chain_noise_reset_cmd {
3218 struct iwl_calib_hdr hdr;
3219 u8 data[0];
3220 };
3221
3222
3223 struct iwl_calib_chain_noise_gain_cmd {
3224 struct iwl_calib_hdr hdr;
3225 u8 delta_gain_1;
3226 u8 delta_gain_2;
3227 u8 pad[2];
3228 } __packed;
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243 struct iwl_led_cmd {
3244 __le32 interval;
3245 u8 id;
3246 u8 off;
3247
3248 u8 on;
3249
3250 u8 reserved;
3251 } __packed;
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264 #define COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG (0x1)
3265 #define COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG (0x2)
3266 #define COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG (0x4)
3267
3268 #define COEX_CU_UNASSOC_IDLE_RP 4
3269 #define COEX_CU_UNASSOC_MANUAL_SCAN_RP 4
3270 #define COEX_CU_UNASSOC_AUTO_SCAN_RP 4
3271 #define COEX_CU_CALIBRATION_RP 4
3272 #define COEX_CU_PERIODIC_CALIBRATION_RP 4
3273 #define COEX_CU_CONNECTION_ESTAB_RP 4
3274 #define COEX_CU_ASSOCIATED_IDLE_RP 4
3275 #define COEX_CU_ASSOC_MANUAL_SCAN_RP 4
3276 #define COEX_CU_ASSOC_AUTO_SCAN_RP 4
3277 #define COEX_CU_ASSOC_ACTIVE_LEVEL_RP 4
3278 #define COEX_CU_RF_ON_RP 6
3279 #define COEX_CU_RF_OFF_RP 4
3280 #define COEX_CU_STAND_ALONE_DEBUG_RP 6
3281 #define COEX_CU_IPAN_ASSOC_LEVEL_RP 4
3282 #define COEX_CU_RSRVD1_RP 4
3283 #define COEX_CU_RSRVD2_RP 4
3284
3285 #define COEX_CU_UNASSOC_IDLE_WP 3
3286 #define COEX_CU_UNASSOC_MANUAL_SCAN_WP 3
3287 #define COEX_CU_UNASSOC_AUTO_SCAN_WP 3
3288 #define COEX_CU_CALIBRATION_WP 3
3289 #define COEX_CU_PERIODIC_CALIBRATION_WP 3
3290 #define COEX_CU_CONNECTION_ESTAB_WP 3
3291 #define COEX_CU_ASSOCIATED_IDLE_WP 3
3292 #define COEX_CU_ASSOC_MANUAL_SCAN_WP 3
3293 #define COEX_CU_ASSOC_AUTO_SCAN_WP 3
3294 #define COEX_CU_ASSOC_ACTIVE_LEVEL_WP 3
3295 #define COEX_CU_RF_ON_WP 3
3296 #define COEX_CU_RF_OFF_WP 3
3297 #define COEX_CU_STAND_ALONE_DEBUG_WP 6
3298 #define COEX_CU_IPAN_ASSOC_LEVEL_WP 3
3299 #define COEX_CU_RSRVD1_WP 3
3300 #define COEX_CU_RSRVD2_WP 3
3301
3302 #define COEX_UNASSOC_IDLE_FLAGS 0
3303 #define COEX_UNASSOC_MANUAL_SCAN_FLAGS \
3304 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3305 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3306 #define COEX_UNASSOC_AUTO_SCAN_FLAGS \
3307 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3308 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3309 #define COEX_CALIBRATION_FLAGS \
3310 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3311 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3312 #define COEX_PERIODIC_CALIBRATION_FLAGS 0
3313
3314
3315
3316
3317 #define COEX_CONNECTION_ESTAB_FLAGS \
3318 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3319 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3320 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3321 #define COEX_ASSOCIATED_IDLE_FLAGS 0
3322 #define COEX_ASSOC_MANUAL_SCAN_FLAGS \
3323 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3324 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3325 #define COEX_ASSOC_AUTO_SCAN_FLAGS \
3326 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3327 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3328 #define COEX_ASSOC_ACTIVE_LEVEL_FLAGS 0
3329 #define COEX_RF_ON_FLAGS 0
3330 #define COEX_RF_OFF_FLAGS 0
3331 #define COEX_STAND_ALONE_DEBUG_FLAGS \
3332 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3333 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3334 #define COEX_IPAN_ASSOC_LEVEL_FLAGS \
3335 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3336 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3337 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3338 #define COEX_RSRVD1_FLAGS 0
3339 #define COEX_RSRVD2_FLAGS 0
3340
3341
3342
3343
3344 #define COEX_CU_RF_ON_FLAGS \
3345 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3346 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3347 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3348
3349
3350 enum {
3351
3352 COEX_UNASSOC_IDLE = 0,
3353 COEX_UNASSOC_MANUAL_SCAN = 1,
3354 COEX_UNASSOC_AUTO_SCAN = 2,
3355
3356 COEX_CALIBRATION = 3,
3357 COEX_PERIODIC_CALIBRATION = 4,
3358
3359 COEX_CONNECTION_ESTAB = 5,
3360
3361 COEX_ASSOCIATED_IDLE = 6,
3362 COEX_ASSOC_MANUAL_SCAN = 7,
3363 COEX_ASSOC_AUTO_SCAN = 8,
3364 COEX_ASSOC_ACTIVE_LEVEL = 9,
3365
3366 COEX_RF_ON = 10,
3367 COEX_RF_OFF = 11,
3368 COEX_STAND_ALONE_DEBUG = 12,
3369
3370 COEX_IPAN_ASSOC_LEVEL = 13,
3371
3372 COEX_RSRVD1 = 14,
3373 COEX_RSRVD2 = 15,
3374 COEX_NUM_OF_EVENTS = 16
3375 };
3376
3377
3378
3379
3380
3381
3382 struct iwl_wimax_coex_event_entry {
3383 u8 request_prio;
3384 u8 win_medium_prio;
3385 u8 reserved;
3386 u8 flags;
3387 } __packed;
3388
3389
3390
3391
3392 #define COEX_FLAGS_STA_TABLE_VALID_MSK (0x1)
3393
3394 #define COEX_FLAGS_UNASSOC_WA_UNMASK_MSK (0x4)
3395
3396 #define COEX_FLAGS_ASSOC_WA_UNMASK_MSK (0x8)
3397
3398 #define COEX_FLAGS_COEX_ENABLE_MSK (0x80)
3399
3400 struct iwl_wimax_coex_cmd {
3401 u8 flags;
3402 u8 reserved[3];
3403 struct iwl_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS];
3404 } __packed;
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420 #define COEX_MEDIUM_BUSY (0x0)
3421 #define COEX_MEDIUM_ACTIVE (0x1)
3422 #define COEX_MEDIUM_PRE_RELEASE (0x2)
3423 #define COEX_MEDIUM_MSK (0x7)
3424
3425
3426 #define COEX_MEDIUM_CHANGED (0x8)
3427 #define COEX_MEDIUM_CHANGED_MSK (0x8)
3428 #define COEX_MEDIUM_SHIFT (3)
3429
3430 struct iwl_coex_medium_notification {
3431 __le32 status;
3432 __le32 events;
3433 } __packed;
3434
3435
3436
3437
3438
3439
3440
3441
3442 #define COEX_EVENT_REQUEST_MSK (0x1)
3443
3444 struct iwl_coex_event_cmd {
3445 u8 flags;
3446 u8 event;
3447 __le16 reserved;
3448 } __packed;
3449
3450 struct iwl_coex_event_resp {
3451 __le32 status;
3452 } __packed;
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464 enum iwl_bt_coex_profile_traffic_load {
3465 IWL_BT_COEX_TRAFFIC_LOAD_NONE = 0,
3466 IWL_BT_COEX_TRAFFIC_LOAD_LOW = 1,
3467 IWL_BT_COEX_TRAFFIC_LOAD_HIGH = 2,
3468 IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS = 3,
3469
3470
3471
3472
3473 };
3474
3475 #define BT_SESSION_ACTIVITY_1_UART_MSG 0x1
3476 #define BT_SESSION_ACTIVITY_2_UART_MSG 0x2
3477
3478
3479 #define BT_UART_MSG_FRAME1MSGTYPE_POS (0)
3480 #define BT_UART_MSG_FRAME1MSGTYPE_MSK \
3481 (0x7 << BT_UART_MSG_FRAME1MSGTYPE_POS)
3482 #define BT_UART_MSG_FRAME1SSN_POS (3)
3483 #define BT_UART_MSG_FRAME1SSN_MSK \
3484 (0x3 << BT_UART_MSG_FRAME1SSN_POS)
3485 #define BT_UART_MSG_FRAME1UPDATEREQ_POS (5)
3486 #define BT_UART_MSG_FRAME1UPDATEREQ_MSK \
3487 (0x1 << BT_UART_MSG_FRAME1UPDATEREQ_POS)
3488 #define BT_UART_MSG_FRAME1RESERVED_POS (6)
3489 #define BT_UART_MSG_FRAME1RESERVED_MSK \
3490 (0x3 << BT_UART_MSG_FRAME1RESERVED_POS)
3491
3492 #define BT_UART_MSG_FRAME2OPENCONNECTIONS_POS (0)
3493 #define BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK \
3494 (0x3 << BT_UART_MSG_FRAME2OPENCONNECTIONS_POS)
3495 #define BT_UART_MSG_FRAME2TRAFFICLOAD_POS (2)
3496 #define BT_UART_MSG_FRAME2TRAFFICLOAD_MSK \
3497 (0x3 << BT_UART_MSG_FRAME2TRAFFICLOAD_POS)
3498 #define BT_UART_MSG_FRAME2CHLSEQN_POS (4)
3499 #define BT_UART_MSG_FRAME2CHLSEQN_MSK \
3500 (0x1 << BT_UART_MSG_FRAME2CHLSEQN_POS)
3501 #define BT_UART_MSG_FRAME2INBAND_POS (5)
3502 #define BT_UART_MSG_FRAME2INBAND_MSK \
3503 (0x1 << BT_UART_MSG_FRAME2INBAND_POS)
3504 #define BT_UART_MSG_FRAME2RESERVED_POS (6)
3505 #define BT_UART_MSG_FRAME2RESERVED_MSK \
3506 (0x3 << BT_UART_MSG_FRAME2RESERVED_POS)
3507
3508 #define BT_UART_MSG_FRAME3SCOESCO_POS (0)
3509 #define BT_UART_MSG_FRAME3SCOESCO_MSK \
3510 (0x1 << BT_UART_MSG_FRAME3SCOESCO_POS)
3511 #define BT_UART_MSG_FRAME3SNIFF_POS (1)
3512 #define BT_UART_MSG_FRAME3SNIFF_MSK \
3513 (0x1 << BT_UART_MSG_FRAME3SNIFF_POS)
3514 #define BT_UART_MSG_FRAME3A2DP_POS (2)
3515 #define BT_UART_MSG_FRAME3A2DP_MSK \
3516 (0x1 << BT_UART_MSG_FRAME3A2DP_POS)
3517 #define BT_UART_MSG_FRAME3ACL_POS (3)
3518 #define BT_UART_MSG_FRAME3ACL_MSK \
3519 (0x1 << BT_UART_MSG_FRAME3ACL_POS)
3520 #define BT_UART_MSG_FRAME3MASTER_POS (4)
3521 #define BT_UART_MSG_FRAME3MASTER_MSK \
3522 (0x1 << BT_UART_MSG_FRAME3MASTER_POS)
3523 #define BT_UART_MSG_FRAME3OBEX_POS (5)
3524 #define BT_UART_MSG_FRAME3OBEX_MSK \
3525 (0x1 << BT_UART_MSG_FRAME3OBEX_POS)
3526 #define BT_UART_MSG_FRAME3RESERVED_POS (6)
3527 #define BT_UART_MSG_FRAME3RESERVED_MSK \
3528 (0x3 << BT_UART_MSG_FRAME3RESERVED_POS)
3529
3530 #define BT_UART_MSG_FRAME4IDLEDURATION_POS (0)
3531 #define BT_UART_MSG_FRAME4IDLEDURATION_MSK \
3532 (0x3F << BT_UART_MSG_FRAME4IDLEDURATION_POS)
3533 #define BT_UART_MSG_FRAME4RESERVED_POS (6)
3534 #define BT_UART_MSG_FRAME4RESERVED_MSK \
3535 (0x3 << BT_UART_MSG_FRAME4RESERVED_POS)
3536
3537 #define BT_UART_MSG_FRAME5TXACTIVITY_POS (0)
3538 #define BT_UART_MSG_FRAME5TXACTIVITY_MSK \
3539 (0x3 << BT_UART_MSG_FRAME5TXACTIVITY_POS)
3540 #define BT_UART_MSG_FRAME5RXACTIVITY_POS (2)
3541 #define BT_UART_MSG_FRAME5RXACTIVITY_MSK \
3542 (0x3 << BT_UART_MSG_FRAME5RXACTIVITY_POS)
3543 #define BT_UART_MSG_FRAME5ESCORETRANSMIT_POS (4)
3544 #define BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK \
3545 (0x3 << BT_UART_MSG_FRAME5ESCORETRANSMIT_POS)
3546 #define BT_UART_MSG_FRAME5RESERVED_POS (6)
3547 #define BT_UART_MSG_FRAME5RESERVED_MSK \
3548 (0x3 << BT_UART_MSG_FRAME5RESERVED_POS)
3549
3550 #define BT_UART_MSG_FRAME6SNIFFINTERVAL_POS (0)
3551 #define BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK \
3552 (0x1F << BT_UART_MSG_FRAME6SNIFFINTERVAL_POS)
3553 #define BT_UART_MSG_FRAME6DISCOVERABLE_POS (5)
3554 #define BT_UART_MSG_FRAME6DISCOVERABLE_MSK \
3555 (0x1 << BT_UART_MSG_FRAME6DISCOVERABLE_POS)
3556 #define BT_UART_MSG_FRAME6RESERVED_POS (6)
3557 #define BT_UART_MSG_FRAME6RESERVED_MSK \
3558 (0x3 << BT_UART_MSG_FRAME6RESERVED_POS)
3559
3560 #define BT_UART_MSG_FRAME7SNIFFACTIVITY_POS (0)
3561 #define BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK \
3562 (0x7 << BT_UART_MSG_FRAME7SNIFFACTIVITY_POS)
3563 #define BT_UART_MSG_FRAME7PAGE_POS (3)
3564 #define BT_UART_MSG_FRAME7PAGE_MSK \
3565 (0x1 << BT_UART_MSG_FRAME7PAGE_POS)
3566 #define BT_UART_MSG_FRAME7INQUIRY_POS (4)
3567 #define BT_UART_MSG_FRAME7INQUIRY_MSK \
3568 (0x1 << BT_UART_MSG_FRAME7INQUIRY_POS)
3569 #define BT_UART_MSG_FRAME7CONNECTABLE_POS (5)
3570 #define BT_UART_MSG_FRAME7CONNECTABLE_MSK \
3571 (0x1 << BT_UART_MSG_FRAME7CONNECTABLE_POS)
3572 #define BT_UART_MSG_FRAME7RESERVED_POS (6)
3573 #define BT_UART_MSG_FRAME7RESERVED_MSK \
3574 (0x3 << BT_UART_MSG_FRAME7RESERVED_POS)
3575
3576
3577 #define BT_UART_MSG_2_FRAME1RESERVED1_POS (5)
3578 #define BT_UART_MSG_2_FRAME1RESERVED1_MSK \
3579 (0x1<<BT_UART_MSG_2_FRAME1RESERVED1_POS)
3580 #define BT_UART_MSG_2_FRAME1RESERVED2_POS (6)
3581 #define BT_UART_MSG_2_FRAME1RESERVED2_MSK \
3582 (0x3<<BT_UART_MSG_2_FRAME1RESERVED2_POS)
3583
3584 #define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS (0)
3585 #define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_MSK \
3586 (0x3F<<BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS)
3587 #define BT_UART_MSG_2_FRAME2RESERVED_POS (6)
3588 #define BT_UART_MSG_2_FRAME2RESERVED_MSK \
3589 (0x3<<BT_UART_MSG_2_FRAME2RESERVED_POS)
3590
3591 #define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS (0)
3592 #define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_MSK \
3593 (0xF<<BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS)
3594 #define BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS (4)
3595 #define BT_UART_MSG_2_FRAME3INQPAGESRMODE_MSK \
3596 (0x1<<BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS)
3597 #define BT_UART_MSG_2_FRAME3LEMASTER_POS (5)
3598 #define BT_UART_MSG_2_FRAME3LEMASTER_MSK \
3599 (0x1<<BT_UART_MSG_2_FRAME3LEMASTER_POS)
3600 #define BT_UART_MSG_2_FRAME3RESERVED_POS (6)
3601 #define BT_UART_MSG_2_FRAME3RESERVED_MSK \
3602 (0x3<<BT_UART_MSG_2_FRAME3RESERVED_POS)
3603
3604 #define BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS (0)
3605 #define BT_UART_MSG_2_FRAME4LELASTTXPOWER_MSK \
3606 (0xF<<BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS)
3607 #define BT_UART_MSG_2_FRAME4NUMLECONN_POS (4)
3608 #define BT_UART_MSG_2_FRAME4NUMLECONN_MSK \
3609 (0x3<<BT_UART_MSG_2_FRAME4NUMLECONN_POS)
3610 #define BT_UART_MSG_2_FRAME4RESERVED_POS (6)
3611 #define BT_UART_MSG_2_FRAME4RESERVED_MSK \
3612 (0x3<<BT_UART_MSG_2_FRAME4RESERVED_POS)
3613
3614 #define BT_UART_MSG_2_FRAME5BTMINRSSI_POS (0)
3615 #define BT_UART_MSG_2_FRAME5BTMINRSSI_MSK \
3616 (0xF<<BT_UART_MSG_2_FRAME5BTMINRSSI_POS)
3617 #define BT_UART_MSG_2_FRAME5LESCANINITMODE_POS (4)
3618 #define BT_UART_MSG_2_FRAME5LESCANINITMODE_MSK \
3619 (0x1<<BT_UART_MSG_2_FRAME5LESCANINITMODE_POS)
3620 #define BT_UART_MSG_2_FRAME5LEADVERMODE_POS (5)
3621 #define BT_UART_MSG_2_FRAME5LEADVERMODE_MSK \
3622 (0x1<<BT_UART_MSG_2_FRAME5LEADVERMODE_POS)
3623 #define BT_UART_MSG_2_FRAME5RESERVED_POS (6)
3624 #define BT_UART_MSG_2_FRAME5RESERVED_MSK \
3625 (0x3<<BT_UART_MSG_2_FRAME5RESERVED_POS)
3626
3627 #define BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS (0)
3628 #define BT_UART_MSG_2_FRAME6LECONNINTERVAL_MSK \
3629 (0x1F<<BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS)
3630 #define BT_UART_MSG_2_FRAME6RFU_POS (5)
3631 #define BT_UART_MSG_2_FRAME6RFU_MSK \
3632 (0x1<<BT_UART_MSG_2_FRAME6RFU_POS)
3633 #define BT_UART_MSG_2_FRAME6RESERVED_POS (6)
3634 #define BT_UART_MSG_2_FRAME6RESERVED_MSK \
3635 (0x3<<BT_UART_MSG_2_FRAME6RESERVED_POS)
3636
3637 #define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS (0)
3638 #define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_MSK \
3639 (0x7<<BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS)
3640 #define BT_UART_MSG_2_FRAME7LEPROFILE1_POS (3)
3641 #define BT_UART_MSG_2_FRAME7LEPROFILE1_MSK \
3642 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE1_POS)
3643 #define BT_UART_MSG_2_FRAME7LEPROFILE2_POS (4)
3644 #define BT_UART_MSG_2_FRAME7LEPROFILE2_MSK \
3645 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE2_POS)
3646 #define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS (5)
3647 #define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_MSK \
3648 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS)
3649 #define BT_UART_MSG_2_FRAME7RESERVED_POS (6)
3650 #define BT_UART_MSG_2_FRAME7RESERVED_MSK \
3651 (0x3<<BT_UART_MSG_2_FRAME7RESERVED_POS)
3652
3653
3654 #define BT_ENABLE_REDUCED_TXPOWER_THRESHOLD (-62)
3655 #define BT_DISABLE_REDUCED_TXPOWER_THRESHOLD (-65)
3656
3657 struct iwl_bt_uart_msg {
3658 u8 header;
3659 u8 frame1;
3660 u8 frame2;
3661 u8 frame3;
3662 u8 frame4;
3663 u8 frame5;
3664 u8 frame6;
3665 u8 frame7;
3666 } __packed;
3667
3668 struct iwl_bt_coex_profile_notif {
3669 struct iwl_bt_uart_msg last_bt_uart_msg;
3670 u8 bt_status;
3671 u8 bt_traffic_load;
3672 u8 bt_ci_compliance;
3673 u8 reserved;
3674 } __packed;
3675
3676 #define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS 0
3677 #define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_MSK 0x1
3678 #define IWL_BT_COEX_PRIO_TBL_PRIO_POS 1
3679 #define IWL_BT_COEX_PRIO_TBL_PRIO_MASK 0x0e
3680 #define IWL_BT_COEX_PRIO_TBL_RESERVED_POS 4
3681 #define IWL_BT_COEX_PRIO_TBL_RESERVED_MASK 0xf0
3682 #define IWL_BT_COEX_PRIO_TBL_PRIO_SHIFT 1
3683
3684
3685
3686
3687
3688 enum bt_coex_prio_table_events {
3689 BT_COEX_PRIO_TBL_EVT_INIT_CALIB1 = 0,
3690 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2 = 1,
3691 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW1 = 2,
3692 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW2 = 3,
3693 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH1 = 4,
3694 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH2 = 5,
3695 BT_COEX_PRIO_TBL_EVT_DTIM = 6,
3696 BT_COEX_PRIO_TBL_EVT_SCAN52 = 7,
3697 BT_COEX_PRIO_TBL_EVT_SCAN24 = 8,
3698 BT_COEX_PRIO_TBL_EVT_RESERVED0 = 9,
3699 BT_COEX_PRIO_TBL_EVT_RESERVED1 = 10,
3700 BT_COEX_PRIO_TBL_EVT_RESERVED2 = 11,
3701 BT_COEX_PRIO_TBL_EVT_RESERVED3 = 12,
3702 BT_COEX_PRIO_TBL_EVT_RESERVED4 = 13,
3703 BT_COEX_PRIO_TBL_EVT_RESERVED5 = 14,
3704 BT_COEX_PRIO_TBL_EVT_RESERVED6 = 15,
3705
3706 BT_COEX_PRIO_TBL_EVT_MAX,
3707 };
3708
3709 enum bt_coex_prio_table_priorities {
3710 BT_COEX_PRIO_TBL_DISABLED = 0,
3711 BT_COEX_PRIO_TBL_PRIO_LOW = 1,
3712 BT_COEX_PRIO_TBL_PRIO_HIGH = 2,
3713 BT_COEX_PRIO_TBL_PRIO_BYPASS = 3,
3714 BT_COEX_PRIO_TBL_PRIO_COEX_OFF = 4,
3715 BT_COEX_PRIO_TBL_PRIO_COEX_ON = 5,
3716 BT_COEX_PRIO_TBL_PRIO_RSRVD1 = 6,
3717 BT_COEX_PRIO_TBL_PRIO_RSRVD2 = 7,
3718 BT_COEX_PRIO_TBL_MAX,
3719 };
3720
3721 struct iwl_bt_coex_prio_table_cmd {
3722 u8 prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX];
3723 } __packed;
3724
3725 #define IWL_BT_COEX_ENV_CLOSE 0
3726 #define IWL_BT_COEX_ENV_OPEN 1
3727
3728
3729
3730
3731 struct iwl_bt_coex_prot_env_cmd {
3732 u8 action;
3733 u8 type;
3734 u8 reserved[2];
3735 } __packed;
3736
3737
3738
3739
3740 enum iwlagn_d3_wakeup_filters {
3741 IWLAGN_D3_WAKEUP_RFKILL = BIT(0),
3742 IWLAGN_D3_WAKEUP_SYSASSERT = BIT(1),
3743 };
3744
3745 struct iwlagn_d3_config_cmd {
3746 __le32 min_sleep_time;
3747 __le32 wakeup_flags;
3748 } __packed;
3749
3750
3751
3752
3753 #define IWLAGN_WOWLAN_MIN_PATTERN_LEN 16
3754 #define IWLAGN_WOWLAN_MAX_PATTERN_LEN 128
3755
3756 struct iwlagn_wowlan_pattern {
3757 u8 mask[IWLAGN_WOWLAN_MAX_PATTERN_LEN / 8];
3758 u8 pattern[IWLAGN_WOWLAN_MAX_PATTERN_LEN];
3759 u8 mask_size;
3760 u8 pattern_size;
3761 __le16 reserved;
3762 } __packed;
3763
3764 #define IWLAGN_WOWLAN_MAX_PATTERNS 20
3765
3766 struct iwlagn_wowlan_patterns_cmd {
3767 __le32 n_patterns;
3768 struct iwlagn_wowlan_pattern patterns[];
3769 } __packed;
3770
3771
3772
3773
3774 enum iwlagn_wowlan_wakeup_filters {
3775 IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET = BIT(0),
3776 IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH = BIT(1),
3777 IWLAGN_WOWLAN_WAKEUP_BEACON_MISS = BIT(2),
3778 IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE = BIT(3),
3779 IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL = BIT(4),
3780 IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ = BIT(5),
3781 IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE = BIT(6),
3782 IWLAGN_WOWLAN_WAKEUP_ALWAYS = BIT(7),
3783 IWLAGN_WOWLAN_WAKEUP_ENABLE_NET_DETECT = BIT(8),
3784 };
3785
3786 struct iwlagn_wowlan_wakeup_filter_cmd {
3787 __le32 enabled;
3788 __le16 non_qos_seq;
3789 __le16 reserved;
3790 __le16 qos_seq[8];
3791 };
3792
3793
3794
3795
3796 #define IWLAGN_NUM_RSC 16
3797
3798 struct tkip_sc {
3799 __le16 iv16;
3800 __le16 pad;
3801 __le32 iv32;
3802 } __packed;
3803
3804 struct iwlagn_tkip_rsc_tsc {
3805 struct tkip_sc unicast_rsc[IWLAGN_NUM_RSC];
3806 struct tkip_sc multicast_rsc[IWLAGN_NUM_RSC];
3807 struct tkip_sc tsc;
3808 } __packed;
3809
3810 struct aes_sc {
3811 __le64 pn;
3812 } __packed;
3813
3814 struct iwlagn_aes_rsc_tsc {
3815 struct aes_sc unicast_rsc[IWLAGN_NUM_RSC];
3816 struct aes_sc multicast_rsc[IWLAGN_NUM_RSC];
3817 struct aes_sc tsc;
3818 } __packed;
3819
3820 union iwlagn_all_tsc_rsc {
3821 struct iwlagn_tkip_rsc_tsc tkip;
3822 struct iwlagn_aes_rsc_tsc aes;
3823 };
3824
3825 struct iwlagn_wowlan_rsc_tsc_params_cmd {
3826 union iwlagn_all_tsc_rsc all_tsc_rsc;
3827 } __packed;
3828
3829
3830
3831
3832 #define IWLAGN_MIC_KEY_SIZE 8
3833 #define IWLAGN_P1K_SIZE 5
3834 struct iwlagn_mic_keys {
3835 u8 tx[IWLAGN_MIC_KEY_SIZE];
3836 u8 rx_unicast[IWLAGN_MIC_KEY_SIZE];
3837 u8 rx_mcast[IWLAGN_MIC_KEY_SIZE];
3838 } __packed;
3839
3840 struct iwlagn_p1k_cache {
3841 __le16 p1k[IWLAGN_P1K_SIZE];
3842 } __packed;
3843
3844 #define IWLAGN_NUM_RX_P1K_CACHE 2
3845
3846 struct iwlagn_wowlan_tkip_params_cmd {
3847 struct iwlagn_mic_keys mic_keys;
3848 struct iwlagn_p1k_cache tx;
3849 struct iwlagn_p1k_cache rx_uni[IWLAGN_NUM_RX_P1K_CACHE];
3850 struct iwlagn_p1k_cache rx_multi[IWLAGN_NUM_RX_P1K_CACHE];
3851 } __packed;
3852
3853
3854
3855
3856
3857 #define IWLAGN_KCK_MAX_SIZE 32
3858 #define IWLAGN_KEK_MAX_SIZE 32
3859
3860 struct iwlagn_wowlan_kek_kck_material_cmd {
3861 u8 kck[IWLAGN_KCK_MAX_SIZE];
3862 u8 kek[IWLAGN_KEK_MAX_SIZE];
3863 __le16 kck_len;
3864 __le16 kek_len;
3865 __le64 replay_ctr;
3866 } __packed;
3867
3868 #define RF_KILL_INDICATOR_FOR_WOWLAN 0x87
3869
3870
3871
3872
3873 struct iwlagn_wowlan_status {
3874 __le64 replay_ctr;
3875 __le32 rekey_status;
3876 __le32 wakeup_reason;
3877 u8 pattern_number;
3878 u8 reserved1;
3879 __le16 qos_seq_ctr[8];
3880 __le16 non_qos_seq_ctr;
3881 __le16 reserved2;
3882 union iwlagn_all_tsc_rsc tsc_rsc;
3883 __le16 reserved3;
3884 } __packed;
3885
3886
3887
3888
3889
3890
3891
3892
3893 #define IWL_MIN_SLOT_TIME 20
3894
3895
3896
3897
3898
3899
3900
3901
3902 struct iwl_wipan_slot {
3903 __le16 width;
3904 u8 type;
3905 u8 reserved;
3906 } __packed;
3907
3908 #define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_CTS BIT(1)
3909 #define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_QUIET BIT(2)
3910 #define IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE BIT(3)
3911 #define IWL_WIPAN_PARAMS_FLG_FILTER_BEACON_NOTIF BIT(4)
3912 #define IWL_WIPAN_PARAMS_FLG_FULL_SLOTTED_MODE BIT(5)
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929 struct iwl_wipan_params_cmd {
3930 __le16 flags;
3931 u8 reserved;
3932 u8 num_slots;
3933 struct iwl_wipan_slot slots[10];
3934 } __packed;
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944 struct iwl_wipan_p2p_channel_switch_cmd {
3945 __le16 channel;
3946 __le16 reserved;
3947 };
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960 struct iwl_wipan_noa_descriptor {
3961 u8 count;
3962 __le32 duration;
3963 __le32 interval;
3964 __le32 starttime;
3965 } __packed;
3966
3967 struct iwl_wipan_noa_attribute {
3968 u8 id;
3969 __le16 length;
3970 u8 index;
3971 u8 ct_window;
3972 struct iwl_wipan_noa_descriptor descr0, descr1;
3973 u8 reserved;
3974 } __packed;
3975
3976 struct iwl_wipan_noa_notification {
3977 u32 noa_active;
3978 struct iwl_wipan_noa_attribute noa_attribute;
3979 } __packed;
3980
3981 #endif