This source file includes following definitions.
- iwl_pcie_gen2_tx_stop
- iwl_pcie_gen2_update_byte_tbl
- iwl_pcie_gen2_txq_inc_wr_ptr
- iwl_pcie_gen2_get_num_tbs
- iwl_pcie_gen2_tfd_unmap
- iwl_pcie_gen2_free_tfd
- iwl_pcie_gen2_set_tb
- iwl_pcie_gen2_build_amsdu
- iwl_pcie_gen2_build_tx_amsdu
- iwl_pcie_gen2_tx_add_frags
- iwl_pcie_gen2_build_tx
- iwl_pcie_gen2_build_tfd
- iwl_trans_pcie_gen2_tx
- iwl_pcie_gen2_enqueue_hcmd
- iwl_pcie_gen2_send_hcmd_sync
- iwl_trans_pcie_gen2_send_hcmd
- iwl_pcie_gen2_txq_unmap
- iwl_pcie_gen2_txq_free_memory
- iwl_pcie_gen2_txq_free
- iwl_trans_pcie_dyn_txq_alloc_dma
- iwl_trans_pcie_txq_alloc_response
- iwl_trans_pcie_dyn_txq_alloc
- iwl_trans_pcie_dyn_txq_free
- iwl_pcie_gen2_tx_free
- iwl_pcie_gen2_tx_init
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52
53 #include <net/tso.h>
54 #include <linux/tcp.h>
55
56 #include "iwl-debug.h"
57 #include "iwl-csr.h"
58 #include "iwl-io.h"
59 #include "internal.h"
60 #include "fw/api/tx.h"
61
62
63
64
65 void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans)
66 {
67 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
68 int txq_id;
69
70
71
72
73
74
75 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
76 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
77
78
79 for (txq_id = 0; txq_id < ARRAY_SIZE(trans_pcie->txq); txq_id++) {
80 if (!trans_pcie->txq[txq_id])
81 continue;
82 iwl_pcie_gen2_txq_unmap(trans, txq_id);
83 }
84 }
85
86
87
88
89 void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans_pcie *trans_pcie,
90 struct iwl_txq *txq, u16 byte_cnt,
91 int num_tbs)
92 {
93 struct iwlagn_scd_bc_tbl *scd_bc_tbl = txq->bc_tbl.addr;
94 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
95 struct iwl_gen3_bc_tbl *scd_bc_tbl_gen3 = txq->bc_tbl.addr;
96 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
97 u8 filled_tfd_size, num_fetch_chunks;
98 u16 len = byte_cnt;
99 __le16 bc_ent;
100
101 if (WARN(idx >= txq->n_window, "%d >= %d\n", idx, txq->n_window))
102 return;
103
104 filled_tfd_size = offsetof(struct iwl_tfh_tfd, tbs) +
105 num_tbs * sizeof(struct iwl_tfh_tb);
106
107
108
109
110
111
112
113
114 num_fetch_chunks = DIV_ROUND_UP(filled_tfd_size, 64) - 1;
115
116 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22560) {
117
118 WARN_ON(trans_pcie->bc_table_dword);
119 WARN_ON(len > 0x3FFF);
120 bc_ent = cpu_to_le16(len | (num_fetch_chunks << 14));
121 scd_bc_tbl_gen3->tfd_offset[idx] = bc_ent;
122 } else {
123
124 WARN_ON(!trans_pcie->bc_table_dword);
125 len = DIV_ROUND_UP(len, 4);
126 WARN_ON(len > 0xFFF);
127 bc_ent = cpu_to_le16(len | (num_fetch_chunks << 12));
128 scd_bc_tbl->tfd_offset[idx] = bc_ent;
129 }
130 }
131
132
133
134
135 void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans,
136 struct iwl_txq *txq)
137 {
138 lockdep_assert_held(&txq->lock);
139
140 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq->id, txq->write_ptr);
141
142
143
144
145
146 iwl_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr | (txq->id << 16));
147 }
148
149 static u8 iwl_pcie_gen2_get_num_tbs(struct iwl_trans *trans,
150 struct iwl_tfh_tfd *tfd)
151 {
152 return le16_to_cpu(tfd->num_tbs) & 0x1f;
153 }
154
155 static void iwl_pcie_gen2_tfd_unmap(struct iwl_trans *trans,
156 struct iwl_cmd_meta *meta,
157 struct iwl_tfh_tfd *tfd)
158 {
159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
160 int i, num_tbs;
161
162
163 num_tbs = iwl_pcie_gen2_get_num_tbs(trans, tfd);
164
165 if (num_tbs > trans_pcie->max_tbs) {
166 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
167 return;
168 }
169
170
171 for (i = 1; i < num_tbs; i++) {
172 if (meta->tbs & BIT(i))
173 dma_unmap_page(trans->dev,
174 le64_to_cpu(tfd->tbs[i].addr),
175 le16_to_cpu(tfd->tbs[i].tb_len),
176 DMA_TO_DEVICE);
177 else
178 dma_unmap_single(trans->dev,
179 le64_to_cpu(tfd->tbs[i].addr),
180 le16_to_cpu(tfd->tbs[i].tb_len),
181 DMA_TO_DEVICE);
182 }
183
184 tfd->num_tbs = 0;
185 }
186
187 static void iwl_pcie_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
188 {
189
190
191
192 int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
193
194 lockdep_assert_held(&txq->lock);
195
196 iwl_pcie_gen2_tfd_unmap(trans, &txq->entries[idx].meta,
197 iwl_pcie_get_tfd(trans, txq, idx));
198
199
200 if (txq->entries) {
201 struct sk_buff *skb;
202
203 skb = txq->entries[idx].skb;
204
205
206
207
208
209 if (skb) {
210 iwl_op_mode_free_skb(trans->op_mode, skb);
211 txq->entries[idx].skb = NULL;
212 }
213 }
214 }
215
216 static int iwl_pcie_gen2_set_tb(struct iwl_trans *trans,
217 struct iwl_tfh_tfd *tfd, dma_addr_t addr,
218 u16 len)
219 {
220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
221 int idx = iwl_pcie_gen2_get_num_tbs(trans, tfd);
222 struct iwl_tfh_tb *tb;
223
224 if (WARN_ON(idx >= IWL_TFH_NUM_TBS))
225 return -EINVAL;
226 tb = &tfd->tbs[idx];
227
228
229 if (le16_to_cpu(tfd->num_tbs) >= trans_pcie->max_tbs) {
230 IWL_ERR(trans, "Error can not send more than %d chunks\n",
231 trans_pcie->max_tbs);
232 return -EINVAL;
233 }
234
235 put_unaligned_le64(addr, &tb->addr);
236 tb->tb_len = cpu_to_le16(len);
237
238 tfd->num_tbs = cpu_to_le16(idx + 1);
239
240 return idx;
241 }
242
243 static int iwl_pcie_gen2_build_amsdu(struct iwl_trans *trans,
244 struct sk_buff *skb,
245 struct iwl_tfh_tfd *tfd, int start_len,
246 u8 hdr_len,
247 struct iwl_device_tx_cmd *dev_cmd)
248 {
249 #ifdef CONFIG_INET
250 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
251 struct iwl_tx_cmd_gen2 *tx_cmd = (void *)dev_cmd->payload;
252 struct ieee80211_hdr *hdr = (void *)skb->data;
253 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
254 unsigned int mss = skb_shinfo(skb)->gso_size;
255 u16 length, amsdu_pad;
256 u8 *start_hdr;
257 struct iwl_tso_hdr_page *hdr_page;
258 struct page **page_ptr;
259 struct tso_t tso;
260
261 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd),
262 &dev_cmd->hdr, start_len, 0);
263
264 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
265 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
266 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len;
267 amsdu_pad = 0;
268
269
270 hdr_room = DIV_ROUND_UP(total_len, mss) *
271 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr));
272
273
274 hdr_page = get_page_hdr(trans, hdr_room);
275 if (!hdr_page)
276 return -ENOMEM;
277
278 get_page(hdr_page->page);
279 start_hdr = hdr_page->pos;
280 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
281 *page_ptr = hdr_page->page;
282
283
284
285
286
287 skb_pull(skb, hdr_len);
288
289
290
291
292
293
294 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
295
296 tso_start(skb, &tso);
297
298 while (total_len) {
299
300 unsigned int data_left = min_t(unsigned int, mss, total_len);
301 struct sk_buff *csum_skb = NULL;
302 unsigned int tb_len;
303 dma_addr_t tb_phys;
304 u8 *subf_hdrs_start = hdr_page->pos;
305
306 total_len -= data_left;
307
308 memset(hdr_page->pos, 0, amsdu_pad);
309 hdr_page->pos += amsdu_pad;
310 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
311 data_left)) & 0x3;
312 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
313 hdr_page->pos += ETH_ALEN;
314 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
315 hdr_page->pos += ETH_ALEN;
316
317 length = snap_ip_tcp_hdrlen + data_left;
318 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
319 hdr_page->pos += sizeof(length);
320
321
322
323
324
325 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
326
327 hdr_page->pos += snap_ip_tcp_hdrlen;
328
329 tb_len = hdr_page->pos - start_hdr;
330 tb_phys = dma_map_single(trans->dev, start_hdr,
331 tb_len, DMA_TO_DEVICE);
332 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
333 dev_kfree_skb(csum_skb);
334 goto out_err;
335 }
336 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb_len);
337 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr, tb_len);
338
339 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
340
341
342 start_hdr = hdr_page->pos;
343
344
345 while (data_left) {
346 tb_len = min_t(unsigned int, tso.size, data_left);
347 tb_phys = dma_map_single(trans->dev, tso.data,
348 tb_len, DMA_TO_DEVICE);
349 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
350 dev_kfree_skb(csum_skb);
351 goto out_err;
352 }
353 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb_len);
354 trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data,
355 tb_len);
356
357 data_left -= tb_len;
358 tso_build_data(skb, &tso, tb_len);
359 }
360 }
361
362
363 skb_push(skb, hdr_len);
364
365 return 0;
366
367 out_err:
368 #endif
369 return -EINVAL;
370 }
371
372 static struct
373 iwl_tfh_tfd *iwl_pcie_gen2_build_tx_amsdu(struct iwl_trans *trans,
374 struct iwl_txq *txq,
375 struct iwl_device_tx_cmd *dev_cmd,
376 struct sk_buff *skb,
377 struct iwl_cmd_meta *out_meta,
378 int hdr_len,
379 int tx_cmd_len)
380 {
381 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
382 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx);
383 dma_addr_t tb_phys;
384 int len;
385 void *tb1_addr;
386
387 tb_phys = iwl_pcie_get_first_tb_dma(txq, idx);
388
389 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE);
390
391
392
393
394
395
396
397 len = tx_cmd_len + sizeof(struct iwl_cmd_header) + hdr_len -
398 IWL_FIRST_TB_SIZE;
399
400
401
402
403 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
404 tb_phys = dma_map_single(trans->dev, tb1_addr, len, DMA_TO_DEVICE);
405 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
406 goto out_err;
407
408
409
410
411 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, len);
412
413 if (iwl_pcie_gen2_build_amsdu(trans, skb, tfd,
414 len + IWL_FIRST_TB_SIZE,
415 hdr_len, dev_cmd))
416 goto out_err;
417
418
419 memcpy(&txq->first_tb_bufs[idx], dev_cmd, IWL_FIRST_TB_SIZE);
420 return tfd;
421
422 out_err:
423 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
424 return NULL;
425 }
426
427 static int iwl_pcie_gen2_tx_add_frags(struct iwl_trans *trans,
428 struct sk_buff *skb,
429 struct iwl_tfh_tfd *tfd,
430 struct iwl_cmd_meta *out_meta)
431 {
432 int i;
433
434 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
435 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
436 dma_addr_t tb_phys;
437 int tb_idx;
438
439 if (!skb_frag_size(frag))
440 continue;
441
442 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
443 skb_frag_size(frag), DMA_TO_DEVICE);
444
445 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
446 return -ENOMEM;
447 tb_idx = iwl_pcie_gen2_set_tb(trans, tfd, tb_phys,
448 skb_frag_size(frag));
449 trace_iwlwifi_dev_tx_tb(trans->dev, skb,
450 skb_frag_address(frag),
451 skb_frag_size(frag));
452 if (tb_idx < 0)
453 return tb_idx;
454
455 out_meta->tbs |= BIT(tb_idx);
456 }
457
458 return 0;
459 }
460
461 static struct
462 iwl_tfh_tfd *iwl_pcie_gen2_build_tx(struct iwl_trans *trans,
463 struct iwl_txq *txq,
464 struct iwl_device_tx_cmd *dev_cmd,
465 struct sk_buff *skb,
466 struct iwl_cmd_meta *out_meta,
467 int hdr_len,
468 int tx_cmd_len,
469 bool pad)
470 {
471 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
472 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx);
473 dma_addr_t tb_phys;
474 int len, tb1_len, tb2_len;
475 void *tb1_addr;
476 struct sk_buff *frag;
477
478 tb_phys = iwl_pcie_get_first_tb_dma(txq, idx);
479
480
481 memcpy(&txq->first_tb_bufs[idx], dev_cmd, IWL_FIRST_TB_SIZE);
482
483 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE);
484
485
486
487
488
489
490
491 len = tx_cmd_len + sizeof(struct iwl_cmd_header) + hdr_len -
492 IWL_FIRST_TB_SIZE;
493
494 if (pad)
495 tb1_len = ALIGN(len, 4);
496 else
497 tb1_len = len;
498
499
500 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
501 tb_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
502 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
503 goto out_err;
504
505
506
507
508 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb1_len);
509 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd), &dev_cmd->hdr,
510 IWL_FIRST_TB_SIZE + tb1_len, hdr_len);
511
512
513 tb2_len = skb_headlen(skb) - hdr_len;
514
515 if (tb2_len > 0) {
516 tb_phys = dma_map_single(trans->dev, skb->data + hdr_len,
517 tb2_len, DMA_TO_DEVICE);
518 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
519 goto out_err;
520 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb2_len);
521 trace_iwlwifi_dev_tx_tb(trans->dev, skb,
522 skb->data + hdr_len,
523 tb2_len);
524 }
525
526 if (iwl_pcie_gen2_tx_add_frags(trans, skb, tfd, out_meta))
527 goto out_err;
528
529 skb_walk_frags(skb, frag) {
530 tb_phys = dma_map_single(trans->dev, frag->data,
531 skb_headlen(frag), DMA_TO_DEVICE);
532 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
533 goto out_err;
534 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, skb_headlen(frag));
535 trace_iwlwifi_dev_tx_tb(trans->dev, skb,
536 frag->data,
537 skb_headlen(frag));
538 if (iwl_pcie_gen2_tx_add_frags(trans, frag, tfd, out_meta))
539 goto out_err;
540 }
541
542 return tfd;
543
544 out_err:
545 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
546 return NULL;
547 }
548
549 static
550 struct iwl_tfh_tfd *iwl_pcie_gen2_build_tfd(struct iwl_trans *trans,
551 struct iwl_txq *txq,
552 struct iwl_device_tx_cmd *dev_cmd,
553 struct sk_buff *skb,
554 struct iwl_cmd_meta *out_meta)
555 {
556 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
557 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
558 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx);
559 int len, hdr_len;
560 bool amsdu;
561
562
563 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd_gen2) < IWL_FIRST_TB_SIZE);
564
565 memset(tfd, 0, sizeof(*tfd));
566
567 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_22560)
568 len = sizeof(struct iwl_tx_cmd_gen2);
569 else
570 len = sizeof(struct iwl_tx_cmd_gen3);
571
572 amsdu = ieee80211_is_data_qos(hdr->frame_control) &&
573 (*ieee80211_get_qos_ctl(hdr) &
574 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
575
576 hdr_len = ieee80211_hdrlen(hdr->frame_control);
577
578
579
580
581
582
583 if (amsdu && skb_shinfo(skb)->gso_size)
584 return iwl_pcie_gen2_build_tx_amsdu(trans, txq, dev_cmd, skb,
585 out_meta, hdr_len, len);
586
587 return iwl_pcie_gen2_build_tx(trans, txq, dev_cmd, skb, out_meta,
588 hdr_len, len, !amsdu);
589 }
590
591 int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
592 struct iwl_device_tx_cmd *dev_cmd, int txq_id)
593 {
594 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
595 struct iwl_cmd_meta *out_meta;
596 struct iwl_txq *txq = trans_pcie->txq[txq_id];
597 u16 cmd_len;
598 int idx;
599 void *tfd;
600
601 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
602 "TX on unused queue %d\n", txq_id))
603 return -EINVAL;
604
605 if (skb_is_nonlinear(skb) &&
606 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
607 __skb_linearize(skb))
608 return -ENOMEM;
609
610 spin_lock(&txq->lock);
611
612 if (iwl_queue_space(trans, txq) < txq->high_mark) {
613 iwl_stop_queue(trans, txq);
614
615
616 if (unlikely(iwl_queue_space(trans, txq) < 3)) {
617 struct iwl_device_tx_cmd **dev_cmd_ptr;
618
619 dev_cmd_ptr = (void *)((u8 *)skb->cb +
620 trans_pcie->dev_cmd_offs);
621
622 *dev_cmd_ptr = dev_cmd;
623 __skb_queue_tail(&txq->overflow_q, skb);
624 spin_unlock(&txq->lock);
625 return 0;
626 }
627 }
628
629 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
630
631
632 txq->entries[idx].skb = skb;
633 txq->entries[idx].cmd = dev_cmd;
634
635 dev_cmd->hdr.sequence =
636 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
637 INDEX_TO_SEQ(idx)));
638
639
640 out_meta = &txq->entries[idx].meta;
641 out_meta->flags = 0;
642
643 tfd = iwl_pcie_gen2_build_tfd(trans, txq, dev_cmd, skb, out_meta);
644 if (!tfd) {
645 spin_unlock(&txq->lock);
646 return -1;
647 }
648
649 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22560) {
650 struct iwl_tx_cmd_gen3 *tx_cmd_gen3 =
651 (void *)dev_cmd->payload;
652
653 cmd_len = le16_to_cpu(tx_cmd_gen3->len);
654 } else {
655 struct iwl_tx_cmd_gen2 *tx_cmd_gen2 =
656 (void *)dev_cmd->payload;
657
658 cmd_len = le16_to_cpu(tx_cmd_gen2->len);
659 }
660
661
662 iwl_pcie_gen2_update_byte_tbl(trans_pcie, txq, cmd_len,
663 iwl_pcie_gen2_get_num_tbs(trans, tfd));
664
665
666 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
667 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
668
669
670 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
671 iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq);
672
673
674
675
676 spin_unlock(&txq->lock);
677 return 0;
678 }
679
680
681
682
683
684
685
686
687
688
689
690
691 static int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
692 struct iwl_host_cmd *cmd)
693 {
694 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
695 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
696 struct iwl_device_cmd *out_cmd;
697 struct iwl_cmd_meta *out_meta;
698 unsigned long flags;
699 void *dup_buf = NULL;
700 dma_addr_t phys_addr;
701 int i, cmd_pos, idx;
702 u16 copy_size, cmd_size, tb0_size;
703 bool had_nocopy = false;
704 u8 group_id = iwl_cmd_groupid(cmd->id);
705 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
706 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
707 struct iwl_tfh_tfd *tfd;
708
709 copy_size = sizeof(struct iwl_cmd_header_wide);
710 cmd_size = sizeof(struct iwl_cmd_header_wide);
711
712 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
713 cmddata[i] = cmd->data[i];
714 cmdlen[i] = cmd->len[i];
715
716 if (!cmd->len[i])
717 continue;
718
719
720 if (copy_size < IWL_FIRST_TB_SIZE) {
721 int copy = IWL_FIRST_TB_SIZE - copy_size;
722
723 if (copy > cmdlen[i])
724 copy = cmdlen[i];
725 cmdlen[i] -= copy;
726 cmddata[i] += copy;
727 copy_size += copy;
728 }
729
730 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
731 had_nocopy = true;
732 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
733 idx = -EINVAL;
734 goto free_dup_buf;
735 }
736 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
737
738
739
740
741 had_nocopy = true;
742
743
744 if (WARN_ON(dup_buf)) {
745 idx = -EINVAL;
746 goto free_dup_buf;
747 }
748
749 dup_buf = kmemdup(cmddata[i], cmdlen[i],
750 GFP_ATOMIC);
751 if (!dup_buf)
752 return -ENOMEM;
753 } else {
754
755 if (WARN_ON(had_nocopy)) {
756 idx = -EINVAL;
757 goto free_dup_buf;
758 }
759 copy_size += cmdlen[i];
760 }
761 cmd_size += cmd->len[i];
762 }
763
764
765
766
767
768
769 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
770 "Command %s (%#x) is too large (%d bytes)\n",
771 iwl_get_cmd_string(trans, cmd->id), cmd->id, copy_size)) {
772 idx = -EINVAL;
773 goto free_dup_buf;
774 }
775
776 spin_lock_bh(&txq->lock);
777
778 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
779 tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr);
780 memset(tfd, 0, sizeof(*tfd));
781
782 if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
783 spin_unlock_bh(&txq->lock);
784
785 IWL_ERR(trans, "No space in command queue\n");
786 iwl_op_mode_cmd_queue_full(trans->op_mode);
787 idx = -ENOSPC;
788 goto free_dup_buf;
789 }
790
791 out_cmd = txq->entries[idx].cmd;
792 out_meta = &txq->entries[idx].meta;
793
794
795 memset(out_meta, 0, sizeof(*out_meta));
796 if (cmd->flags & CMD_WANT_SKB)
797 out_meta->source = cmd;
798
799
800 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
801 out_cmd->hdr_wide.group_id = group_id;
802 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
803 out_cmd->hdr_wide.length =
804 cpu_to_le16(cmd_size - sizeof(struct iwl_cmd_header_wide));
805 out_cmd->hdr_wide.reserved = 0;
806 out_cmd->hdr_wide.sequence =
807 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
808 INDEX_TO_SEQ(txq->write_ptr));
809
810 cmd_pos = sizeof(struct iwl_cmd_header_wide);
811 copy_size = sizeof(struct iwl_cmd_header_wide);
812
813
814 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
815 int copy;
816
817 if (!cmd->len[i])
818 continue;
819
820
821 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
822 IWL_HCMD_DFL_DUP))) {
823 copy = cmd->len[i];
824
825 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
826 cmd_pos += copy;
827 copy_size += copy;
828 continue;
829 }
830
831
832
833
834
835
836 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
837
838 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
839 cmd_pos += copy;
840
841
842 if (copy_size < IWL_FIRST_TB_SIZE) {
843 copy = IWL_FIRST_TB_SIZE - copy_size;
844
845 if (copy > cmd->len[i])
846 copy = cmd->len[i];
847 copy_size += copy;
848 }
849 }
850
851 IWL_DEBUG_HC(trans,
852 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
853 iwl_get_cmd_string(trans, cmd->id), group_id,
854 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
855 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
856
857
858 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
859 memcpy(&txq->first_tb_bufs[idx], out_cmd, tb0_size);
860 iwl_pcie_gen2_set_tb(trans, tfd, iwl_pcie_get_first_tb_dma(txq, idx),
861 tb0_size);
862
863
864 if (copy_size > tb0_size) {
865 phys_addr = dma_map_single(trans->dev,
866 (u8 *)out_cmd + tb0_size,
867 copy_size - tb0_size,
868 DMA_TO_DEVICE);
869 if (dma_mapping_error(trans->dev, phys_addr)) {
870 idx = -ENOMEM;
871 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
872 goto out;
873 }
874 iwl_pcie_gen2_set_tb(trans, tfd, phys_addr,
875 copy_size - tb0_size);
876 }
877
878
879 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
880 const void *data = cmddata[i];
881
882 if (!cmdlen[i])
883 continue;
884 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
885 IWL_HCMD_DFL_DUP)))
886 continue;
887 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
888 data = dup_buf;
889 phys_addr = dma_map_single(trans->dev, (void *)data,
890 cmdlen[i], DMA_TO_DEVICE);
891 if (dma_mapping_error(trans->dev, phys_addr)) {
892 idx = -ENOMEM;
893 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
894 goto out;
895 }
896 iwl_pcie_gen2_set_tb(trans, tfd, phys_addr, cmdlen[i]);
897 }
898
899 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
900 out_meta->flags = cmd->flags;
901 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
902 kzfree(txq->entries[idx].free_buf);
903 txq->entries[idx].free_buf = dup_buf;
904
905 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
906
907
908 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
909 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
910
911 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
912
913 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
914 iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq);
915 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
916
917 out:
918 spin_unlock_bh(&txq->lock);
919 free_dup_buf:
920 if (idx < 0)
921 kfree(dup_buf);
922 return idx;
923 }
924
925 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
926
927 static int iwl_pcie_gen2_send_hcmd_sync(struct iwl_trans *trans,
928 struct iwl_host_cmd *cmd)
929 {
930 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
931 const char *cmd_str = iwl_get_cmd_string(trans, cmd->id);
932 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
933 int cmd_idx;
934 int ret;
935
936 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", cmd_str);
937
938 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
939 &trans->status),
940 "Command %s: a command is already active!\n", cmd_str))
941 return -EIO;
942
943 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", cmd_str);
944
945 cmd_idx = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
946 if (cmd_idx < 0) {
947 ret = cmd_idx;
948 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
949 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
950 cmd_str, ret);
951 return ret;
952 }
953
954 ret = wait_event_timeout(trans_pcie->wait_command_queue,
955 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
956 &trans->status),
957 HOST_COMPLETE_TIMEOUT);
958 if (!ret) {
959 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
960 cmd_str, jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
961
962 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
963 txq->read_ptr, txq->write_ptr);
964
965 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
966 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
967 cmd_str);
968 ret = -ETIMEDOUT;
969
970 iwl_trans_pcie_sync_nmi(trans);
971 goto cancel;
972 }
973
974 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
975 IWL_ERR(trans, "FW error in SYNC CMD %s\n", cmd_str);
976 dump_stack();
977 ret = -EIO;
978 goto cancel;
979 }
980
981 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
982 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
983 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
984 ret = -ERFKILL;
985 goto cancel;
986 }
987
988 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
989 IWL_ERR(trans, "Error: Response NULL in '%s'\n", cmd_str);
990 ret = -EIO;
991 goto cancel;
992 }
993
994 return 0;
995
996 cancel:
997 if (cmd->flags & CMD_WANT_SKB) {
998
999
1000
1001
1002
1003
1004 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1005 }
1006
1007 if (cmd->resp_pkt) {
1008 iwl_free_resp(cmd);
1009 cmd->resp_pkt = NULL;
1010 }
1011
1012 return ret;
1013 }
1014
1015 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
1016 struct iwl_host_cmd *cmd)
1017 {
1018 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1019 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1020 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1021 cmd->id);
1022 return -ERFKILL;
1023 }
1024
1025 if (cmd->flags & CMD_ASYNC) {
1026 int ret;
1027
1028
1029 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1030 return -EINVAL;
1031
1032 ret = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
1033 if (ret < 0) {
1034 IWL_ERR(trans,
1035 "Error sending %s: enqueue_hcmd failed: %d\n",
1036 iwl_get_cmd_string(trans, cmd->id), ret);
1037 return ret;
1038 }
1039 return 0;
1040 }
1041
1042 return iwl_pcie_gen2_send_hcmd_sync(trans, cmd);
1043 }
1044
1045
1046
1047
1048 void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id)
1049 {
1050 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1051 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1052
1053 spin_lock_bh(&txq->lock);
1054 while (txq->write_ptr != txq->read_ptr) {
1055 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
1056 txq_id, txq->read_ptr);
1057
1058 if (txq_id != trans_pcie->cmd_queue) {
1059 int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1060 struct sk_buff *skb = txq->entries[idx].skb;
1061
1062 if (WARN_ON_ONCE(!skb))
1063 continue;
1064
1065 iwl_pcie_free_tso_page(trans_pcie, skb);
1066 }
1067 iwl_pcie_gen2_free_tfd(trans, txq);
1068 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
1069 }
1070
1071 while (!skb_queue_empty(&txq->overflow_q)) {
1072 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
1073
1074 iwl_op_mode_free_skb(trans->op_mode, skb);
1075 }
1076
1077 spin_unlock_bh(&txq->lock);
1078
1079
1080 iwl_wake_queue(trans, txq);
1081 }
1082
1083 void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans,
1084 struct iwl_txq *txq)
1085 {
1086 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1087 struct device *dev = trans->dev;
1088
1089
1090 if (txq->tfds) {
1091 dma_free_coherent(dev,
1092 trans_pcie->tfd_size * txq->n_window,
1093 txq->tfds, txq->dma_addr);
1094 dma_free_coherent(dev,
1095 sizeof(*txq->first_tb_bufs) * txq->n_window,
1096 txq->first_tb_bufs, txq->first_tb_dma);
1097 }
1098
1099 kfree(txq->entries);
1100 iwl_pcie_free_dma_ptr(trans, &txq->bc_tbl);
1101 kfree(txq);
1102 }
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112 static void iwl_pcie_gen2_txq_free(struct iwl_trans *trans, int txq_id)
1113 {
1114 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1115 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1116 int i;
1117
1118 if (WARN_ON(!txq))
1119 return;
1120
1121 iwl_pcie_gen2_txq_unmap(trans, txq_id);
1122
1123
1124 if (txq_id == trans_pcie->cmd_queue)
1125 for (i = 0; i < txq->n_window; i++) {
1126 kzfree(txq->entries[i].cmd);
1127 kzfree(txq->entries[i].free_buf);
1128 }
1129 del_timer_sync(&txq->stuck_timer);
1130
1131 iwl_pcie_gen2_txq_free_memory(trans, txq);
1132
1133 trans_pcie->txq[txq_id] = NULL;
1134
1135 clear_bit(txq_id, trans_pcie->queue_used);
1136 }
1137
1138 int iwl_trans_pcie_dyn_txq_alloc_dma(struct iwl_trans *trans,
1139 struct iwl_txq **intxq, int size,
1140 unsigned int timeout)
1141 {
1142 int ret;
1143
1144 struct iwl_txq *txq;
1145 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
1146 if (!txq)
1147 return -ENOMEM;
1148 ret = iwl_pcie_alloc_dma_ptr(trans, &txq->bc_tbl,
1149 (trans->trans_cfg->device_family >=
1150 IWL_DEVICE_FAMILY_22560) ?
1151 sizeof(struct iwl_gen3_bc_tbl) :
1152 sizeof(struct iwlagn_scd_bc_tbl));
1153 if (ret) {
1154 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
1155 kfree(txq);
1156 return -ENOMEM;
1157 }
1158
1159 ret = iwl_pcie_txq_alloc(trans, txq, size, false);
1160 if (ret) {
1161 IWL_ERR(trans, "Tx queue alloc failed\n");
1162 goto error;
1163 }
1164 ret = iwl_pcie_txq_init(trans, txq, size, false);
1165 if (ret) {
1166 IWL_ERR(trans, "Tx queue init failed\n");
1167 goto error;
1168 }
1169
1170 txq->wd_timeout = msecs_to_jiffies(timeout);
1171
1172 *intxq = txq;
1173 return 0;
1174
1175 error:
1176 iwl_pcie_gen2_txq_free_memory(trans, txq);
1177 return ret;
1178 }
1179
1180 int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans,
1181 struct iwl_txq *txq,
1182 struct iwl_host_cmd *hcmd)
1183 {
1184 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1185 struct iwl_tx_queue_cfg_rsp *rsp;
1186 int ret, qid;
1187 u32 wr_ptr;
1188
1189 if (WARN_ON(iwl_rx_packet_payload_len(hcmd->resp_pkt) !=
1190 sizeof(*rsp))) {
1191 ret = -EINVAL;
1192 goto error_free_resp;
1193 }
1194
1195 rsp = (void *)hcmd->resp_pkt->data;
1196 qid = le16_to_cpu(rsp->queue_number);
1197 wr_ptr = le16_to_cpu(rsp->write_pointer);
1198
1199 if (qid >= ARRAY_SIZE(trans_pcie->txq)) {
1200 WARN_ONCE(1, "queue index %d unsupported", qid);
1201 ret = -EIO;
1202 goto error_free_resp;
1203 }
1204
1205 if (test_and_set_bit(qid, trans_pcie->queue_used)) {
1206 WARN_ONCE(1, "queue %d already used", qid);
1207 ret = -EIO;
1208 goto error_free_resp;
1209 }
1210
1211 txq->id = qid;
1212 trans_pcie->txq[qid] = txq;
1213 wr_ptr &= (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
1214
1215
1216 txq->read_ptr = wr_ptr;
1217 txq->write_ptr = wr_ptr;
1218
1219 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d\n", qid);
1220
1221 iwl_free_resp(hcmd);
1222 return qid;
1223
1224 error_free_resp:
1225 iwl_free_resp(hcmd);
1226 iwl_pcie_gen2_txq_free_memory(trans, txq);
1227 return ret;
1228 }
1229
1230 int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans,
1231 __le16 flags, u8 sta_id, u8 tid,
1232 int cmd_id, int size,
1233 unsigned int timeout)
1234 {
1235 struct iwl_txq *txq = NULL;
1236 struct iwl_tx_queue_cfg_cmd cmd = {
1237 .flags = flags,
1238 .sta_id = sta_id,
1239 .tid = tid,
1240 };
1241 struct iwl_host_cmd hcmd = {
1242 .id = cmd_id,
1243 .len = { sizeof(cmd) },
1244 .data = { &cmd, },
1245 .flags = CMD_WANT_SKB,
1246 };
1247 int ret;
1248
1249 ret = iwl_trans_pcie_dyn_txq_alloc_dma(trans, &txq, size, timeout);
1250 if (ret)
1251 return ret;
1252
1253 cmd.tfdq_addr = cpu_to_le64(txq->dma_addr);
1254 cmd.byte_cnt_addr = cpu_to_le64(txq->bc_tbl.dma);
1255 cmd.cb_size = cpu_to_le32(TFD_QUEUE_CB_SIZE(size));
1256
1257 ret = iwl_trans_send_cmd(trans, &hcmd);
1258 if (ret)
1259 goto error;
1260
1261 return iwl_trans_pcie_txq_alloc_response(trans, txq, &hcmd);
1262
1263 error:
1264 iwl_pcie_gen2_txq_free_memory(trans, txq);
1265 return ret;
1266 }
1267
1268 void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue)
1269 {
1270 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1271
1272
1273
1274
1275
1276
1277
1278 if (!test_and_clear_bit(queue, trans_pcie->queue_used)) {
1279 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1280 "queue %d not used", queue);
1281 return;
1282 }
1283
1284 iwl_pcie_gen2_txq_unmap(trans, queue);
1285
1286 iwl_pcie_gen2_txq_free_memory(trans, trans_pcie->txq[queue]);
1287 trans_pcie->txq[queue] = NULL;
1288
1289 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", queue);
1290 }
1291
1292 void iwl_pcie_gen2_tx_free(struct iwl_trans *trans)
1293 {
1294 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1295 int i;
1296
1297 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1298
1299
1300 for (i = 0; i < ARRAY_SIZE(trans_pcie->txq); i++) {
1301 if (!trans_pcie->txq[i])
1302 continue;
1303
1304 iwl_pcie_gen2_txq_free(trans, i);
1305 }
1306 }
1307
1308 int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id, int queue_size)
1309 {
1310 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1311 struct iwl_txq *queue;
1312 int ret;
1313
1314
1315 if (!trans_pcie->txq[txq_id]) {
1316 queue = kzalloc(sizeof(*queue), GFP_KERNEL);
1317 if (!queue) {
1318 IWL_ERR(trans, "Not enough memory for tx queue\n");
1319 return -ENOMEM;
1320 }
1321 trans_pcie->txq[txq_id] = queue;
1322 ret = iwl_pcie_txq_alloc(trans, queue, queue_size, true);
1323 if (ret) {
1324 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1325 goto error;
1326 }
1327 } else {
1328 queue = trans_pcie->txq[txq_id];
1329 }
1330
1331 ret = iwl_pcie_txq_init(trans, queue, queue_size,
1332 (txq_id == trans_pcie->cmd_queue));
1333 if (ret) {
1334 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
1335 goto error;
1336 }
1337 trans_pcie->txq[txq_id]->id = txq_id;
1338 set_bit(txq_id, trans_pcie->queue_used);
1339
1340 return 0;
1341
1342 error:
1343 iwl_pcie_gen2_tx_free(trans);
1344 return ret;
1345 }
1346