drivers/net/wireless/intel/iwlwifi/pcie/trans.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
iwl_trans_pcie_dump_regs
iwl_trans_pcie_sw_reset
iwl_pcie_free_fw_monitor
iwl_pcie_alloc_fw_monitor_block
iwl_pcie_alloc_fw_monitor
iwl_trans_pcie_read_shr
iwl_trans_pcie_write_shr
iwl_pcie_set_pwr
iwl_pcie_apm_config
iwl_pcie_apm_init
iwl_pcie_apm_lp_xtal_enable
iwl_pcie_apm_stop_master
iwl_pcie_apm_stop
iwl_pcie_nic_init
iwl_pcie_set_hw_ready
iwl_pcie_prepare_card_hw
iwl_pcie_load_firmware_chunk_fh
iwl_pcie_load_firmware_chunk
iwl_pcie_load_section
iwl_pcie_load_cpu_sections_8000
iwl_pcie_load_cpu_sections
iwl_pcie_apply_destination
iwl_pcie_load_given_ucode
iwl_pcie_load_given_ucode_8000
iwl_pcie_check_hw_rf_kill
iwl_pcie_map_non_rx_causes
iwl_pcie_map_rx_causes
iwl_pcie_conf_msix_hw
iwl_pcie_init_msix
_iwl_trans_pcie_stop_device
iwl_pcie_synchronize_irqs
iwl_trans_pcie_start_fw
iwl_trans_pcie_fw_alive
iwl_trans_pcie_handle_stop_rfkill
iwl_trans_pcie_stop_device
iwl_trans_pcie_rf_kill
iwl_pcie_d3_complete_suspend
iwl_trans_pcie_d3_suspend
iwl_trans_pcie_d3_resume
iwl_pcie_set_interrupt_capa
iwl_pcie_irq_set_affinity
iwl_pcie_init_msix_handler
iwl_trans_pcie_clear_persistence_bit
iwl_pcie_gen2_force_power_gating
_iwl_trans_pcie_start_hw
iwl_trans_pcie_start_hw
iwl_trans_pcie_op_mode_leave
iwl_trans_pcie_write8
iwl_trans_pcie_write32
iwl_trans_pcie_read32
iwl_trans_pcie_prph_msk
iwl_trans_pcie_read_prph
iwl_trans_pcie_write_prph
iwl_trans_pcie_configure
iwl_trans_pcie_free
iwl_trans_pcie_set_pmi
iwl_trans_pcie_removal_wk
iwl_trans_pcie_grab_nic_access
iwl_trans_pcie_release_nic_access
iwl_trans_pcie_read_mem
iwl_trans_pcie_write_mem
iwl_trans_pcie_freeze_txq_timer
iwl_trans_pcie_block_txq_ptrs
iwl_trans_pcie_log_scd_error
iwl_trans_pcie_rxq_dma_data
iwl_trans_pcie_wait_txq_empty
iwl_trans_pcie_wait_txqs_empty
iwl_trans_pcie_set_bits_mask
get_csr_string
iwl_pcie_dump_csr
iwl_dbgfs_tx_queue_read
iwl_dbgfs_rx_queue_read
iwl_dbgfs_interrupt_read
iwl_dbgfs_interrupt_write
iwl_dbgfs_csr_write
iwl_dbgfs_fh_reg_read
iwl_dbgfs_rfkill_read
iwl_dbgfs_rfkill_write
iwl_dbgfs_monitor_data_open
iwl_dbgfs_monitor_data_release
iwl_write_to_user_buf
iwl_dbgfs_monitor_data_read
iwl_trans_pcie_dbgfs_register
iwl_trans_pcie_debugfs_cleanup
iwl_trans_pcie_get_cmdlen
iwl_trans_pcie_dump_rbs
iwl_trans_pcie_dump_csr
iwl_trans_pcie_fh_regs_dump
iwl_trans_pci_dump_marbh_monitor
iwl_trans_pcie_dump_pointers
iwl_trans_pcie_dump_monitor
iwl_trans_get_fw_monitor_len
iwl_trans_pcie_dump_data
iwl_trans_pcie_suspend
iwl_trans_pcie_resume
iwl_trans_pcie_alloc
iwl_trans_pcie_sync_nmi
   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  * Copyright(c) 2018 - 2019 Intel Corporation
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of version 2 of the GNU General Public License as
  15  * published by the Free Software Foundation.
  16  *
  17  * This program is distributed in the hope that it will be useful, but
  18  * WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20  * General Public License for more details.
  21  *
  22  * The full GNU General Public License is included in this distribution
  23  * in the file called COPYING.
  24  *
  25  * Contact Information:
  26  *  Intel Linux Wireless <linuxwifi@intel.com>
  27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  28  *
  29  * BSD LICENSE
  30  *
  31  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  32  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  33  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  34  * Copyright(c) 2018 - 2019 Intel Corporation
  35  * All rights reserved.
  36  *
  37  * Redistribution and use in source and binary forms, with or without
  38  * modification, are permitted provided that the following conditions
  39  * are met:
  40  *
  41  *  * Redistributions of source code must retain the above copyright
  42  *    notice, this list of conditions and the following disclaimer.
  43  *  * Redistributions in binary form must reproduce the above copyright
  44  *    notice, this list of conditions and the following disclaimer in
  45  *    the documentation and/or other materials provided with the
  46  *    distribution.
  47  *  * Neither the name Intel Corporation nor the names of its
  48  *    contributors may be used to endorse or promote products derived
  49  *    from this software without specific prior written permission.
  50  *
  51  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  52  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  53  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  54  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  55  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  56  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  57  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  58  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  59  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  60  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  61  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  62  *
  63  *****************************************************************************/
  64 #include <linux/pci.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70 #include <linux/vmalloc.h>
  71 #include <linux/module.h>
  72 #include <linux/wait.h>
  73 
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-scd.h"
  79 #include "iwl-agn-hw.h"
  80 #include "fw/error-dump.h"
  81 #include "fw/dbg.h"
  82 #include "fw/api/tx.h"
  83 #include "internal.h"
  84 #include "iwl-fh.h"
  85 
  86 /* extended range in FW SRAM */
  87 #define IWL_FW_MEM_EXTENDED_START       0x40000
  88 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  89 
  90 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
  91 {
  92 #define PCI_DUMP_SIZE           352
  93 #define PCI_MEM_DUMP_SIZE       64
  94 #define PCI_PARENT_DUMP_SIZE    524
  95 #define PREFIX_LEN              32
  96         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  97         struct pci_dev *pdev = trans_pcie->pci_dev;
  98         u32 i, pos, alloc_size, *ptr, *buf;
  99         char *prefix;
 100 
 101         if (trans_pcie->pcie_dbg_dumped_once)
 102                 return;
 103 
 104         /* Should be a multiple of 4 */
 105         BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
 106         BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
 107         BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
 108 
 109         /* Alloc a max size buffer */
 110         alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
 111         alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
 112         alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
 113         alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
 114 
 115         buf = kmalloc(alloc_size, GFP_ATOMIC);
 116         if (!buf)
 117                 return;
 118         prefix = (char *)buf + alloc_size - PREFIX_LEN;
 119 
 120         IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
 121 
 122         /* Print wifi device registers */
 123         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 124         IWL_ERR(trans, "iwlwifi device config registers:\n");
 125         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 126                 if (pci_read_config_dword(pdev, i, ptr))
 127                         goto err_read;
 128         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 129 
 130         IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
 131         for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
 132                 *ptr = iwl_read32(trans, i);
 133         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 134 
 135         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 136         if (pos) {
 137                 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
 138                 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
 139                         if (pci_read_config_dword(pdev, pos + i, ptr))
 140                                 goto err_read;
 141                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
 142                                32, 4, buf, i, 0);
 143         }
 144 
 145         /* Print parent device registers next */
 146         if (!pdev->bus->self)
 147                 goto out;
 148 
 149         pdev = pdev->bus->self;
 150         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 151 
 152         IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
 153                 pci_name(pdev));
 154         for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
 155                 if (pci_read_config_dword(pdev, i, ptr))
 156                         goto err_read;
 157         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 158 
 159         /* Print root port AER registers */
 160         pos = 0;
 161         pdev = pcie_find_root_port(pdev);
 162         if (pdev)
 163                 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 164         if (pos) {
 165                 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
 166                         pci_name(pdev));
 167                 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 168                 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
 169                         if (pci_read_config_dword(pdev, pos + i, ptr))
 170                                 goto err_read;
 171                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
 172                                4, buf, i, 0);
 173         }
 174         goto out;
 175 
 176 err_read:
 177         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 178         IWL_ERR(trans, "Read failed at 0x%X\n", i);
 179 out:
 180         trans_pcie->pcie_dbg_dumped_once = 1;
 181         kfree(buf);
 182 }
 183 
 184 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
 185 {
 186         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 187         iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
 188                     BIT(trans->trans_cfg->csr->flag_sw_reset));
 189         usleep_range(5000, 6000);
 190 }
 191 
 192 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
 193 {
 194         int i;
 195 
 196         for (i = 0; i < trans->dbg.num_blocks; i++) {
 197                 dma_free_coherent(trans->dev, trans->dbg.fw_mon[i].size,
 198                                   trans->dbg.fw_mon[i].block,
 199                                   trans->dbg.fw_mon[i].physical);
 200                 trans->dbg.fw_mon[i].block = NULL;
 201                 trans->dbg.fw_mon[i].physical = 0;
 202                 trans->dbg.fw_mon[i].size = 0;
 203                 trans->dbg.num_blocks--;
 204         }
 205 }
 206 
 207 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
 208                                             u8 max_power, u8 min_power)
 209 {
 210         void *cpu_addr = NULL;
 211         dma_addr_t phys = 0;
 212         u32 size = 0;
 213         u8 power;
 214 
 215         for (power = max_power; power >= min_power; power--) {
 216                 size = BIT(power);
 217                 cpu_addr = dma_alloc_coherent(trans->dev, size, &phys,
 218                                               GFP_KERNEL | __GFP_NOWARN);
 219                 if (!cpu_addr)
 220                         continue;
 221 
 222                 IWL_INFO(trans,
 223                          "Allocated 0x%08x bytes for firmware monitor.\n",
 224                          size);
 225                 break;
 226         }
 227 
 228         if (WARN_ON_ONCE(!cpu_addr))
 229                 return;
 230 
 231         if (power != max_power)
 232                 IWL_ERR(trans,
 233                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 234                         (unsigned long)BIT(power - 10),
 235                         (unsigned long)BIT(max_power - 10));
 236 
 237         trans->dbg.fw_mon[trans->dbg.num_blocks].block = cpu_addr;
 238         trans->dbg.fw_mon[trans->dbg.num_blocks].physical = phys;
 239         trans->dbg.fw_mon[trans->dbg.num_blocks].size = size;
 240         trans->dbg.num_blocks++;
 241 }
 242 
 243 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 244 {
 245         if (!max_power) {
 246                 /* default max_power is maximum */
 247                 max_power = 26;
 248         } else {
 249                 max_power += 11;
 250         }
 251 
 252         if (WARN(max_power > 26,
 253                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 254                  max_power))
 255                 return;
 256 
 257         /*
 258          * This function allocats the default fw monitor.
 259          * The optional additional ones will be allocated in runtime
 260          */
 261         if (trans->dbg.num_blocks)
 262                 return;
 263 
 264         iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
 265 }
 266 
 267 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 268 {
 269         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 270                     ((reg & 0x0000ffff) | (2 << 28)));
 271         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 272 }
 273 
 274 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 275 {
 276         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 277         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 278                     ((reg & 0x0000ffff) | (3 << 28)));
 279 }
 280 
 281 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 282 {
 283         if (trans->cfg->apmg_not_supported)
 284                 return;
 285 
 286         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 287                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 288                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 289                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 290         else
 291                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 292                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 293                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 294 }
 295 
 296 /* PCI registers */
 297 #define PCI_CFG_RETRY_TIMEOUT   0x041
 298 
 299 void iwl_pcie_apm_config(struct iwl_trans *trans)
 300 {
 301         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 302         u16 lctl;
 303         u16 cap;
 304 
 305         /*
 306          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 307          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 308          * If so (likely), disable L0S, so device moves directly L0->L1;
 309          *    costs negligible amount of power savings.
 310          * If not (unlikely), enable L0S, so there is at least some
 311          *    power savings, even without L1.
 312          */
 313         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 314         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 315                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 316         else
 317                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 318         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 319 
 320         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 321         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 322         IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
 323                         (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 324                         trans->ltr_enabled ? "En" : "Dis");
 325 }
 326 
 327 /*
 328  * Start up NIC's basic functionality after it has been reset
 329  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 330  * NOTE:  This does not load uCode nor start the embedded processor
 331  */
 332 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 333 {
 334         int ret;
 335 
 336         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 337 
 338         /*
 339          * Use "set_bit" below rather than "write", to preserve any hardware
 340          * bits already set by default after reset.
 341          */
 342 
 343         /* Disable L0S exit timer (platform NMI Work/Around) */
 344         if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
 345                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 346                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 347 
 348         /*
 349          * Disable L0s without affecting L1;
 350          *  don't wait for ICH L0s (ICH bug W/A)
 351          */
 352         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 353                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 354 
 355         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 356         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 357 
 358         /*
 359          * Enable HAP INTA (interrupt from management bus) to
 360          * wake device's PCI Express link L1a -> L0s
 361          */
 362         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 363                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 364 
 365         iwl_pcie_apm_config(trans);
 366 
 367         /* Configure analog phase-lock-loop before activating to D0A */
 368         if (trans->trans_cfg->base_params->pll_cfg)
 369                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 370 
 371         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
 372         if (ret)
 373                 return ret;
 374 
 375         if (trans->cfg->host_interrupt_operation_mode) {
 376                 /*
 377                  * This is a bit of an abuse - This is needed for 7260 / 3160
 378                  * only check host_interrupt_operation_mode even if this is
 379                  * not related to host_interrupt_operation_mode.
 380                  *
 381                  * Enable the oscillator to count wake up time for L1 exit. This
 382                  * consumes slightly more power (100uA) - but allows to be sure
 383                  * that we wake up from L1 on time.
 384                  *
 385                  * This looks weird: read twice the same register, discard the
 386                  * value, set a bit, and yet again, read that same register
 387                  * just to discard the value. But that's the way the hardware
 388                  * seems to like it.
 389                  */
 390                 iwl_read_prph(trans, OSC_CLK);
 391                 iwl_read_prph(trans, OSC_CLK);
 392                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 393                 iwl_read_prph(trans, OSC_CLK);
 394                 iwl_read_prph(trans, OSC_CLK);
 395         }
 396 
 397         /*
 398          * Enable DMA clock and wait for it to stabilize.
 399          *
 400          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 401          * bits do not disable clocks.  This preserves any hardware
 402          * bits already set by default in "CLK_CTRL_REG" after reset.
 403          */
 404         if (!trans->cfg->apmg_not_supported) {
 405                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 406                                APMG_CLK_VAL_DMA_CLK_RQT);
 407                 udelay(20);
 408 
 409                 /* Disable L1-Active */
 410                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 411                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 412 
 413                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 414                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 415                                APMG_RTC_INT_STT_RFKILL);
 416         }
 417 
 418         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 419 
 420         return 0;
 421 }
 422 
 423 /*
 424  * Enable LP XTAL to avoid HW bug where device may consume much power if
 425  * FW is not loaded after device reset. LP XTAL is disabled by default
 426  * after device HW reset. Do it only if XTAL is fed by internal source.
 427  * Configure device's "persistence" mode to avoid resetting XTAL again when
 428  * SHRD_HW_RST occurs in S3.
 429  */
 430 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 431 {
 432         int ret;
 433         u32 apmg_gp1_reg;
 434         u32 apmg_xtal_cfg_reg;
 435         u32 dl_cfg_reg;
 436 
 437         /* Force XTAL ON */
 438         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 439                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 440 
 441         iwl_trans_pcie_sw_reset(trans);
 442 
 443         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
 444         if (WARN_ON(ret)) {
 445                 /* Release XTAL ON request */
 446                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 447                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 448                 return;
 449         }
 450 
 451         /*
 452          * Clear "disable persistence" to avoid LP XTAL resetting when
 453          * SHRD_HW_RST is applied in S3.
 454          */
 455         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 456                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 457 
 458         /*
 459          * Force APMG XTAL to be active to prevent its disabling by HW
 460          * caused by APMG idle state.
 461          */
 462         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 463                                                     SHR_APMG_XTAL_CFG_REG);
 464         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 465                                  apmg_xtal_cfg_reg |
 466                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 467 
 468         iwl_trans_pcie_sw_reset(trans);
 469 
 470         /* Enable LP XTAL by indirect access through CSR */
 471         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 472         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 473                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 474                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 475 
 476         /* Clear delay line clock power up */
 477         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 478         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 479                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 480 
 481         /*
 482          * Enable persistence mode to avoid LP XTAL resetting when
 483          * SHRD_HW_RST is applied in S3.
 484          */
 485         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 486                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 487 
 488         /*
 489          * Clear "initialization complete" bit to move adapter from
 490          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 491          */
 492         iwl_clear_bit(trans, CSR_GP_CNTRL,
 493                       BIT(trans->trans_cfg->csr->flag_init_done));
 494 
 495         /* Activates XTAL resources monitor */
 496         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 497                                  CSR_MONITOR_XTAL_RESOURCES);
 498 
 499         /* Release XTAL ON request */
 500         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 501                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 502         udelay(10);
 503 
 504         /* Release APMG XTAL */
 505         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 506                                  apmg_xtal_cfg_reg &
 507                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 508 }
 509 
 510 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 511 {
 512         int ret;
 513 
 514         /* stop device's busmaster DMA activity */
 515         iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
 516                     BIT(trans->trans_cfg->csr->flag_stop_master));
 517 
 518         ret = iwl_poll_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
 519                            BIT(trans->trans_cfg->csr->flag_master_dis),
 520                            BIT(trans->trans_cfg->csr->flag_master_dis), 100);
 521         if (ret < 0)
 522                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 523 
 524         IWL_DEBUG_INFO(trans, "stop master\n");
 525 }
 526 
 527 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 528 {
 529         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 530 
 531         if (op_mode_leave) {
 532                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 533                         iwl_pcie_apm_init(trans);
 534 
 535                 /* inform ME that we are leaving */
 536                 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
 537                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 538                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 539                 else if (trans->trans_cfg->device_family >=
 540                          IWL_DEVICE_FAMILY_8000) {
 541                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 542                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 543                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 544                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 545                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 546                         mdelay(1);
 547                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 548                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 549                 }
 550                 mdelay(5);
 551         }
 552 
 553         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 554 
 555         /* Stop device's DMA activity */
 556         iwl_pcie_apm_stop_master(trans);
 557 
 558         if (trans->cfg->lp_xtal_workaround) {
 559                 iwl_pcie_apm_lp_xtal_enable(trans);
 560                 return;
 561         }
 562 
 563         iwl_trans_pcie_sw_reset(trans);
 564 
 565         /*
 566          * Clear "initialization complete" bit to move adapter from
 567          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 568          */
 569         iwl_clear_bit(trans, CSR_GP_CNTRL,
 570                       BIT(trans->trans_cfg->csr->flag_init_done));
 571 }
 572 
 573 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 574 {
 575         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 576         int ret;
 577 
 578         /* nic_init */
 579         spin_lock(&trans_pcie->irq_lock);
 580         ret = iwl_pcie_apm_init(trans);
 581         spin_unlock(&trans_pcie->irq_lock);
 582 
 583         if (ret)
 584                 return ret;
 585 
 586         iwl_pcie_set_pwr(trans, false);
 587 
 588         iwl_op_mode_nic_config(trans->op_mode);
 589 
 590         /* Allocate the RX queue, or reset if it is already allocated */
 591         iwl_pcie_rx_init(trans);
 592 
 593         /* Allocate or reset and init all Tx and Command queues */
 594         if (iwl_pcie_tx_init(trans))
 595                 return -ENOMEM;
 596 
 597         if (trans->trans_cfg->base_params->shadow_reg_enable) {
 598                 /* enable shadow regs in HW */
 599                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 600                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 601         }
 602 
 603         return 0;
 604 }
 605 
 606 #define HW_READY_TIMEOUT (50)
 607 
 608 /* Note: returns poll_bit return value, which is >= 0 if success */
 609 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 610 {
 611         int ret;
 612 
 613         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 614                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 615 
 616         /* See if we got it */
 617         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 618                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 619                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 620                            HW_READY_TIMEOUT);
 621 
 622         if (ret >= 0)
 623                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 624 
 625         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 626         return ret;
 627 }
 628 
 629 /* Note: returns standard 0/-ERROR code */
 630 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 631 {
 632         int ret;
 633         int t = 0;
 634         int iter;
 635 
 636         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 637 
 638         ret = iwl_pcie_set_hw_ready(trans);
 639         /* If the card is ready, exit 0 */
 640         if (ret >= 0)
 641                 return 0;
 642 
 643         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 644                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 645         usleep_range(1000, 2000);
 646 
 647         for (iter = 0; iter < 10; iter++) {
 648                 /* If HW is not ready, prepare the conditions to check again */
 649                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 650                             CSR_HW_IF_CONFIG_REG_PREPARE);
 651 
 652                 do {
 653                         ret = iwl_pcie_set_hw_ready(trans);
 654                         if (ret >= 0)
 655                                 return 0;
 656 
 657                         usleep_range(200, 1000);
 658                         t += 200;
 659                 } while (t < 150000);
 660                 msleep(25);
 661         }
 662 
 663         IWL_ERR(trans, "Couldn't prepare the card\n");
 664 
 665         return ret;
 666 }
 667 
 668 /*
 669  * ucode
 670  */
 671 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 672                                             u32 dst_addr, dma_addr_t phy_addr,
 673                                             u32 byte_cnt)
 674 {
 675         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 676                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 677 
 678         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 679                     dst_addr);
 680 
 681         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 682                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 683 
 684         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 685                     (iwl_get_dma_hi_addr(phy_addr)
 686                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 687 
 688         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 689                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 690                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 691                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 692 
 693         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 694                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 695                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 696                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 697 }
 698 
 699 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
 700                                         u32 dst_addr, dma_addr_t phy_addr,
 701                                         u32 byte_cnt)
 702 {
 703         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 704         unsigned long flags;
 705         int ret;
 706 
 707         trans_pcie->ucode_write_complete = false;
 708 
 709         if (!iwl_trans_grab_nic_access(trans, &flags))
 710                 return -EIO;
 711 
 712         iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
 713                                         byte_cnt);
 714         iwl_trans_release_nic_access(trans, &flags);
 715 
 716         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 717                                  trans_pcie->ucode_write_complete, 5 * HZ);
 718         if (!ret) {
 719                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 720                 iwl_trans_pcie_dump_regs(trans);
 721                 return -ETIMEDOUT;
 722         }
 723 
 724         return 0;
 725 }
 726 
 727 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 728                             const struct fw_desc *section)
 729 {
 730         u8 *v_addr;
 731         dma_addr_t p_addr;
 732         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 733         int ret = 0;
 734 
 735         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 736                      section_num);
 737 
 738         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 739                                     GFP_KERNEL | __GFP_NOWARN);
 740         if (!v_addr) {
 741                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 742                 chunk_sz = PAGE_SIZE;
 743                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 744                                             &p_addr, GFP_KERNEL);
 745                 if (!v_addr)
 746                         return -ENOMEM;
 747         }
 748 
 749         for (offset = 0; offset < section->len; offset += chunk_sz) {
 750                 u32 copy_size, dst_addr;
 751                 bool extended_addr = false;
 752 
 753                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 754                 dst_addr = section->offset + offset;
 755 
 756                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 757                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 758                         extended_addr = true;
 759 
 760                 if (extended_addr)
 761                         iwl_set_bits_prph(trans, LMPM_CHICK,
 762                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 763 
 764                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 765                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 766                                                    copy_size);
 767 
 768                 if (extended_addr)
 769                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 770                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 771 
 772                 if (ret) {
 773                         IWL_ERR(trans,
 774                                 "Could not load the [%d] uCode section\n",
 775                                 section_num);
 776                         break;
 777                 }
 778         }
 779 
 780         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 781         return ret;
 782 }
 783 
 784 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 785                                            const struct fw_img *image,
 786                                            int cpu,
 787                                            int *first_ucode_section)
 788 {
 789         int shift_param;
 790         int i, ret = 0, sec_num = 0x1;
 791         u32 val, last_read_idx = 0;
 792 
 793         if (cpu == 1) {
 794                 shift_param = 0;
 795                 *first_ucode_section = 0;
 796         } else {
 797                 shift_param = 16;
 798                 (*first_ucode_section)++;
 799         }
 800 
 801         for (i = *first_ucode_section; i < image->num_sec; i++) {
 802                 last_read_idx = i;
 803 
 804                 /*
 805                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 806                  * CPU1 to CPU2.
 807                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 808                  * CPU2 non paged to CPU2 paging sec.
 809                  */
 810                 if (!image->sec[i].data ||
 811                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 812                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 813                         IWL_DEBUG_FW(trans,
 814                                      "Break since Data not valid or Empty section, sec = %d\n",
 815                                      i);
 816                         break;
 817                 }
 818 
 819                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 820                 if (ret)
 821                         return ret;
 822 
 823                 /* Notify ucode of loaded section number and status */
 824                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 825                 val = val | (sec_num << shift_param);
 826                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 827 
 828                 sec_num = (sec_num << 1) | 0x1;
 829         }
 830 
 831         *first_ucode_section = last_read_idx;
 832 
 833         iwl_enable_interrupts(trans);
 834 
 835         if (trans->trans_cfg->use_tfh) {
 836                 if (cpu == 1)
 837                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 838                                        0xFFFF);
 839                 else
 840                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 841                                        0xFFFFFFFF);
 842         } else {
 843                 if (cpu == 1)
 844                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 845                                            0xFFFF);
 846                 else
 847                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 848                                            0xFFFFFFFF);
 849         }
 850 
 851         return 0;
 852 }
 853 
 854 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 855                                       const struct fw_img *image,
 856                                       int cpu,
 857                                       int *first_ucode_section)
 858 {
 859         int i, ret = 0;
 860         u32 last_read_idx = 0;
 861 
 862         if (cpu == 1)
 863                 *first_ucode_section = 0;
 864         else
 865                 (*first_ucode_section)++;
 866 
 867         for (i = *first_ucode_section; i < image->num_sec; i++) {
 868                 last_read_idx = i;
 869 
 870                 /*
 871                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 872                  * CPU1 to CPU2.
 873                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 874                  * CPU2 non paged to CPU2 paging sec.
 875                  */
 876                 if (!image->sec[i].data ||
 877                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 878                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 879                         IWL_DEBUG_FW(trans,
 880                                      "Break since Data not valid or Empty section, sec = %d\n",
 881                                      i);
 882                         break;
 883                 }
 884 
 885                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 886                 if (ret)
 887                         return ret;
 888         }
 889 
 890         *first_ucode_section = last_read_idx;
 891 
 892         return 0;
 893 }
 894 
 895 void iwl_pcie_apply_destination(struct iwl_trans *trans)
 896 {
 897         const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
 898         int i;
 899 
 900         if (iwl_trans_dbg_ini_valid(trans)) {
 901                 if (!trans->dbg.num_blocks)
 902                         return;
 903 
 904                 IWL_DEBUG_FW(trans,
 905                              "WRT: Applying DRAM buffer[0] destination\n");
 906                 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
 907                                     trans->dbg.fw_mon[0].physical >>
 908                                     MON_BUFF_SHIFT_VER2);
 909                 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
 910                                     (trans->dbg.fw_mon[0].physical +
 911                                      trans->dbg.fw_mon[0].size - 256) >>
 912                                     MON_BUFF_SHIFT_VER2);
 913                 return;
 914         }
 915 
 916         IWL_INFO(trans, "Applying debug destination %s\n",
 917                  get_fw_dbg_mode_string(dest->monitor_mode));
 918 
 919         if (dest->monitor_mode == EXTERNAL_MODE)
 920                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 921         else
 922                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 923 
 924         for (i = 0; i < trans->dbg.n_dest_reg; i++) {
 925                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 926                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 927 
 928                 switch (dest->reg_ops[i].op) {
 929                 case CSR_ASSIGN:
 930                         iwl_write32(trans, addr, val);
 931                         break;
 932                 case CSR_SETBIT:
 933                         iwl_set_bit(trans, addr, BIT(val));
 934                         break;
 935                 case CSR_CLEARBIT:
 936                         iwl_clear_bit(trans, addr, BIT(val));
 937                         break;
 938                 case PRPH_ASSIGN:
 939                         iwl_write_prph(trans, addr, val);
 940                         break;
 941                 case PRPH_SETBIT:
 942                         iwl_set_bits_prph(trans, addr, BIT(val));
 943                         break;
 944                 case PRPH_CLEARBIT:
 945                         iwl_clear_bits_prph(trans, addr, BIT(val));
 946                         break;
 947                 case PRPH_BLOCKBIT:
 948                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 949                                 IWL_ERR(trans,
 950                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 951                                         val, addr);
 952                                 goto monitor;
 953                         }
 954                         break;
 955                 default:
 956                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 957                                 dest->reg_ops[i].op);
 958                         break;
 959                 }
 960         }
 961 
 962 monitor:
 963         if (dest->monitor_mode == EXTERNAL_MODE && trans->dbg.fw_mon[0].size) {
 964                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 965                                trans->dbg.fw_mon[0].physical >>
 966                                dest->base_shift);
 967                 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
 968                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 969                                        (trans->dbg.fw_mon[0].physical +
 970                                         trans->dbg.fw_mon[0].size - 256) >>
 971                                                 dest->end_shift);
 972                 else
 973                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 974                                        (trans->dbg.fw_mon[0].physical +
 975                                         trans->dbg.fw_mon[0].size) >>
 976                                                 dest->end_shift);
 977         }
 978 }
 979 
 980 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 981                                 const struct fw_img *image)
 982 {
 983         int ret = 0;
 984         int first_ucode_section;
 985 
 986         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 987                      image->is_dual_cpus ? "Dual" : "Single");
 988 
 989         /* load to FW the binary non secured sections of CPU1 */
 990         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 991         if (ret)
 992                 return ret;
 993 
 994         if (image->is_dual_cpus) {
 995                 /* set CPU2 header address */
 996                 iwl_write_prph(trans,
 997                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 998                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 999 
1000                 /* load to FW the binary sections of CPU2 */
1001                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1002                                                  &first_ucode_section);
1003                 if (ret)
1004                         return ret;
1005         }
1006 
1007         /* supported for 7000 only for the moment */
1008         if (iwlwifi_mod_params.fw_monitor &&
1009             trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1010                 iwl_pcie_alloc_fw_monitor(trans, 0);
1011 
1012                 if (trans->dbg.fw_mon[0].size) {
1013                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1014                                        trans->dbg.fw_mon[0].physical >> 4);
1015                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
1016                                        (trans->dbg.fw_mon[0].physical +
1017                                         trans->dbg.fw_mon[0].size) >> 4);
1018                 }
1019         } else if (iwl_pcie_dbg_on(trans)) {
1020                 iwl_pcie_apply_destination(trans);
1021         }
1022 
1023         iwl_enable_interrupts(trans);
1024 
1025         /* release CPU reset */
1026         iwl_write32(trans, CSR_RESET, 0);
1027 
1028         return 0;
1029 }
1030 
1031 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1032                                           const struct fw_img *image)
1033 {
1034         int ret = 0;
1035         int first_ucode_section;
1036 
1037         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1038                      image->is_dual_cpus ? "Dual" : "Single");
1039 
1040         if (iwl_pcie_dbg_on(trans))
1041                 iwl_pcie_apply_destination(trans);
1042 
1043         IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1044                         iwl_read_prph(trans, WFPM_GP2));
1045 
1046         /*
1047          * Set default value. On resume reading the values that were
1048          * zeored can provide debug data on the resume flow.
1049          * This is for debugging only and has no functional impact.
1050          */
1051         iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1052 
1053         /* configure the ucode to be ready to get the secured image */
1054         /* release CPU reset */
1055         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1056 
1057         /* load to FW the binary Secured sections of CPU1 */
1058         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1059                                               &first_ucode_section);
1060         if (ret)
1061                 return ret;
1062 
1063         /* load to FW the binary sections of CPU2 */
1064         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1065                                                &first_ucode_section);
1066 }
1067 
1068 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1069 {
1070         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1071         bool hw_rfkill = iwl_is_rfkill_set(trans);
1072         bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1073         bool report;
1074 
1075         if (hw_rfkill) {
1076                 set_bit(STATUS_RFKILL_HW, &trans->status);
1077                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1078         } else {
1079                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1080                 if (trans_pcie->opmode_down)
1081                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1082         }
1083 
1084         report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1085 
1086         if (prev != report)
1087                 iwl_trans_pcie_rf_kill(trans, report);
1088 
1089         return hw_rfkill;
1090 }
1091 
1092 struct iwl_causes_list {
1093         u32 cause_num;
1094         u32 mask_reg;
1095         u8 addr;
1096 };
1097 
1098 static struct iwl_causes_list causes_list[] = {
1099         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1100         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1101         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1102         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1103         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1104         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1105         {MSIX_HW_INT_CAUSES_REG_IML,            CSR_MSIX_HW_INT_MASK_AD, 0x12},
1106         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1107         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1108         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1109         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1110         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1111         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1112         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1113         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1114 };
1115 
1116 static struct iwl_causes_list causes_list_v2[] = {
1117         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1118         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1119         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1120         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1121         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1122         {MSIX_HW_INT_CAUSES_REG_IPC,            CSR_MSIX_HW_INT_MASK_AD, 0x11},
1123         {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2,      CSR_MSIX_HW_INT_MASK_AD, 0x15},
1124         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1125         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1126         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1127         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1128         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1129         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1130         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1131 };
1132 
1133 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1134 {
1135         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1136         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1137         int i, arr_size =
1138                 (trans->trans_cfg->device_family != IWL_DEVICE_FAMILY_22560) ?
1139                 ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2);
1140 
1141         /*
1142          * Access all non RX causes and map them to the default irq.
1143          * In case we are missing at least one interrupt vector,
1144          * the first interrupt vector will serve non-RX and FBQ causes.
1145          */
1146         for (i = 0; i < arr_size; i++) {
1147                 struct iwl_causes_list *causes =
1148                         (trans->trans_cfg->device_family !=
1149                          IWL_DEVICE_FAMILY_22560) ?
1150                         causes_list : causes_list_v2;
1151 
1152                 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1153                 iwl_clear_bit(trans, causes[i].mask_reg,
1154                               causes[i].cause_num);
1155         }
1156 }
1157 
1158 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1159 {
1160         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1161         u32 offset =
1162                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1163         u32 val, idx;
1164 
1165         /*
1166          * The first RX queue - fallback queue, which is designated for
1167          * management frame, command responses etc, is always mapped to the
1168          * first interrupt vector. The other RX queues are mapped to
1169          * the other (N - 2) interrupt vectors.
1170          */
1171         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1172         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1173                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1174                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1175                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1176         }
1177         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1178 
1179         val = MSIX_FH_INT_CAUSES_Q(0);
1180         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1181                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1182         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1183 
1184         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1185                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1186 }
1187 
1188 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1189 {
1190         struct iwl_trans *trans = trans_pcie->trans;
1191 
1192         if (!trans_pcie->msix_enabled) {
1193                 if (trans->trans_cfg->mq_rx_supported &&
1194                     test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1195                         iwl_write_umac_prph(trans, UREG_CHICK,
1196                                             UREG_CHICK_MSI_ENABLE);
1197                 return;
1198         }
1199         /*
1200          * The IVAR table needs to be configured again after reset,
1201          * but if the device is disabled, we can't write to
1202          * prph.
1203          */
1204         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1205                 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1206 
1207         /*
1208          * Each cause from the causes list above and the RX causes is
1209          * represented as a byte in the IVAR table. The first nibble
1210          * represents the bound interrupt vector of the cause, the second
1211          * represents no auto clear for this cause. This will be set if its
1212          * interrupt vector is bound to serve other causes.
1213          */
1214         iwl_pcie_map_rx_causes(trans);
1215 
1216         iwl_pcie_map_non_rx_causes(trans);
1217 }
1218 
1219 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1220 {
1221         struct iwl_trans *trans = trans_pcie->trans;
1222 
1223         iwl_pcie_conf_msix_hw(trans_pcie);
1224 
1225         if (!trans_pcie->msix_enabled)
1226                 return;
1227 
1228         trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1229         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1230         trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1231         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1232 }
1233 
1234 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1235 {
1236         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1237 
1238         lockdep_assert_held(&trans_pcie->mutex);
1239 
1240         if (trans_pcie->is_down)
1241                 return;
1242 
1243         trans_pcie->is_down = true;
1244 
1245         /* tell the device to stop sending interrupts */
1246         iwl_disable_interrupts(trans);
1247 
1248         /* device going down, Stop using ICT table */
1249         iwl_pcie_disable_ict(trans);
1250 
1251         /*
1252          * If a HW restart happens during firmware loading,
1253          * then the firmware loading might call this function
1254          * and later it might be called again due to the
1255          * restart. So don't process again if the device is
1256          * already dead.
1257          */
1258         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1259                 IWL_DEBUG_INFO(trans,
1260                                "DEVICE_ENABLED bit was set and is now cleared\n");
1261                 iwl_pcie_tx_stop(trans);
1262                 iwl_pcie_rx_stop(trans);
1263 
1264                 /* Power-down device's busmaster DMA clocks */
1265                 if (!trans->cfg->apmg_not_supported) {
1266                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1267                                        APMG_CLK_VAL_DMA_CLK_RQT);
1268                         udelay(5);
1269                 }
1270         }
1271 
1272         /* Make sure (redundant) we've released our request to stay awake */
1273         iwl_clear_bit(trans, CSR_GP_CNTRL,
1274                       BIT(trans->trans_cfg->csr->flag_mac_access_req));
1275 
1276         /* Stop the device, and put it in low power state */
1277         iwl_pcie_apm_stop(trans, false);
1278 
1279         iwl_trans_pcie_sw_reset(trans);
1280 
1281         /*
1282          * Upon stop, the IVAR table gets erased, so msi-x won't
1283          * work. This causes a bug in RF-KILL flows, since the interrupt
1284          * that enables radio won't fire on the correct irq, and the
1285          * driver won't be able to handle the interrupt.
1286          * Configure the IVAR table again after reset.
1287          */
1288         iwl_pcie_conf_msix_hw(trans_pcie);
1289 
1290         /*
1291          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1292          * This is a bug in certain verions of the hardware.
1293          * Certain devices also keep sending HW RF kill interrupt all
1294          * the time, unless the interrupt is ACKed even if the interrupt
1295          * should be masked. Re-ACK all the interrupts here.
1296          */
1297         iwl_disable_interrupts(trans);
1298 
1299         /* clear all status bits */
1300         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1301         clear_bit(STATUS_INT_ENABLED, &trans->status);
1302         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1303 
1304         /*
1305          * Even if we stop the HW, we still want the RF kill
1306          * interrupt
1307          */
1308         iwl_enable_rfkill_int(trans);
1309 
1310         /* re-take ownership to prevent other users from stealing the device */
1311         iwl_pcie_prepare_card_hw(trans);
1312 }
1313 
1314 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1315 {
1316         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1317 
1318         if (trans_pcie->msix_enabled) {
1319                 int i;
1320 
1321                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1322                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1323         } else {
1324                 synchronize_irq(trans_pcie->pci_dev->irq);
1325         }
1326 }
1327 
1328 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1329                                    const struct fw_img *fw, bool run_in_rfkill)
1330 {
1331         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1332         bool hw_rfkill;
1333         int ret;
1334 
1335         /* This may fail if AMT took ownership of the device */
1336         if (iwl_pcie_prepare_card_hw(trans)) {
1337                 IWL_WARN(trans, "Exit HW not ready\n");
1338                 ret = -EIO;
1339                 goto out;
1340         }
1341 
1342         iwl_enable_rfkill_int(trans);
1343 
1344         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1345 
1346         /*
1347          * We enabled the RF-Kill interrupt and the handler may very
1348          * well be running. Disable the interrupts to make sure no other
1349          * interrupt can be fired.
1350          */
1351         iwl_disable_interrupts(trans);
1352 
1353         /* Make sure it finished running */
1354         iwl_pcie_synchronize_irqs(trans);
1355 
1356         mutex_lock(&trans_pcie->mutex);
1357 
1358         /* If platform's RF_KILL switch is NOT set to KILL */
1359         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1360         if (hw_rfkill && !run_in_rfkill) {
1361                 ret = -ERFKILL;
1362                 goto out;
1363         }
1364 
1365         /* Someone called stop_device, don't try to start_fw */
1366         if (trans_pcie->is_down) {
1367                 IWL_WARN(trans,
1368                          "Can't start_fw since the HW hasn't been started\n");
1369                 ret = -EIO;
1370                 goto out;
1371         }
1372 
1373         /* make sure rfkill handshake bits are cleared */
1374         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1375         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1376                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1377 
1378         /* clear (again), then enable host interrupts */
1379         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1380 
1381         ret = iwl_pcie_nic_init(trans);
1382         if (ret) {
1383                 IWL_ERR(trans, "Unable to init nic\n");
1384                 goto out;
1385         }
1386 
1387         /*
1388          * Now, we load the firmware and don't want to be interrupted, even
1389          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1390          * FH_TX interrupt which is needed to load the firmware). If the
1391          * RF-Kill switch is toggled, we will find out after having loaded
1392          * the firmware and return the proper value to the caller.
1393          */
1394         iwl_enable_fw_load_int(trans);
1395 
1396         /* really make sure rfkill handshake bits are cleared */
1397         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1398         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1399 
1400         /* Load the given image to the HW */
1401         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1402                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1403         else
1404                 ret = iwl_pcie_load_given_ucode(trans, fw);
1405 
1406         /* re-check RF-Kill state since we may have missed the interrupt */
1407         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1408         if (hw_rfkill && !run_in_rfkill)
1409                 ret = -ERFKILL;
1410 
1411 out:
1412         mutex_unlock(&trans_pcie->mutex);
1413         return ret;
1414 }
1415 
1416 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1417 {
1418         iwl_pcie_reset_ict(trans);
1419         iwl_pcie_tx_start(trans, scd_addr);
1420 }
1421 
1422 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1423                                        bool was_in_rfkill)
1424 {
1425         bool hw_rfkill;
1426 
1427         /*
1428          * Check again since the RF kill state may have changed while
1429          * all the interrupts were disabled, in this case we couldn't
1430          * receive the RF kill interrupt and update the state in the
1431          * op_mode.
1432          * Don't call the op_mode if the rkfill state hasn't changed.
1433          * This allows the op_mode to call stop_device from the rfkill
1434          * notification without endless recursion. Under very rare
1435          * circumstances, we might have a small recursion if the rfkill
1436          * state changed exactly now while we were called from stop_device.
1437          * This is very unlikely but can happen and is supported.
1438          */
1439         hw_rfkill = iwl_is_rfkill_set(trans);
1440         if (hw_rfkill) {
1441                 set_bit(STATUS_RFKILL_HW, &trans->status);
1442                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1443         } else {
1444                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1445                 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1446         }
1447         if (hw_rfkill != was_in_rfkill)
1448                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1449 }
1450 
1451 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1452 {
1453         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1454         bool was_in_rfkill;
1455 
1456         mutex_lock(&trans_pcie->mutex);
1457         trans_pcie->opmode_down = true;
1458         was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1459         _iwl_trans_pcie_stop_device(trans);
1460         iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1461         mutex_unlock(&trans_pcie->mutex);
1462 }
1463 
1464 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1465 {
1466         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1467                 IWL_TRANS_GET_PCIE_TRANS(trans);
1468 
1469         lockdep_assert_held(&trans_pcie->mutex);
1470 
1471         IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1472                  state ? "disabled" : "enabled");
1473         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1474                 if (trans->trans_cfg->gen2)
1475                         _iwl_trans_pcie_gen2_stop_device(trans);
1476                 else
1477                         _iwl_trans_pcie_stop_device(trans);
1478         }
1479 }
1480 
1481 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1482                                   bool test, bool reset)
1483 {
1484         iwl_disable_interrupts(trans);
1485 
1486         /*
1487          * in testing mode, the host stays awake and the
1488          * hardware won't be reset (not even partially)
1489          */
1490         if (test)
1491                 return;
1492 
1493         iwl_pcie_disable_ict(trans);
1494 
1495         iwl_pcie_synchronize_irqs(trans);
1496 
1497         iwl_clear_bit(trans, CSR_GP_CNTRL,
1498                       BIT(trans->trans_cfg->csr->flag_mac_access_req));
1499         iwl_clear_bit(trans, CSR_GP_CNTRL,
1500                       BIT(trans->trans_cfg->csr->flag_init_done));
1501 
1502         if (reset) {
1503                 /*
1504                  * reset TX queues -- some of their registers reset during S3
1505                  * so if we don't reset everything here the D3 image would try
1506                  * to execute some invalid memory upon resume
1507                  */
1508                 iwl_trans_pcie_tx_reset(trans);
1509         }
1510 
1511         iwl_pcie_set_pwr(trans, true);
1512 }
1513 
1514 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1515                                      bool reset)
1516 {
1517         int ret;
1518         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1519 
1520         /*
1521          * Family IWL_DEVICE_FAMILY_AX210 and above persist mode is set by FW.
1522          */
1523         if (!reset && trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
1524                 /* Enable persistence mode to avoid reset */
1525                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1526                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1527         }
1528 
1529         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1530                 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1531                                     UREG_DOORBELL_TO_ISR6_SUSPEND);
1532 
1533                 ret = wait_event_timeout(trans_pcie->sx_waitq,
1534                                          trans_pcie->sx_complete, 2 * HZ);
1535                 /*
1536                  * Invalidate it toward resume.
1537                  */
1538                 trans_pcie->sx_complete = false;
1539 
1540                 if (!ret) {
1541                         IWL_ERR(trans, "Timeout entering D3\n");
1542                         return -ETIMEDOUT;
1543                 }
1544         }
1545         iwl_pcie_d3_complete_suspend(trans, test, reset);
1546 
1547         return 0;
1548 }
1549 
1550 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1551                                     enum iwl_d3_status *status,
1552                                     bool test,  bool reset)
1553 {
1554         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1555         u32 val;
1556         int ret;
1557 
1558         if (test) {
1559                 iwl_enable_interrupts(trans);
1560                 *status = IWL_D3_STATUS_ALIVE;
1561                 goto out;
1562         }
1563 
1564         iwl_set_bit(trans, CSR_GP_CNTRL,
1565                     BIT(trans->trans_cfg->csr->flag_mac_access_req));
1566 
1567         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1568         if (ret)
1569                 return ret;
1570 
1571         /*
1572          * Reconfigure IVAR table in case of MSIX or reset ict table in
1573          * MSI mode since HW reset erased it.
1574          * Also enables interrupts - none will happen as
1575          * the device doesn't know we're waking it up, only when
1576          * the opmode actually tells it after this call.
1577          */
1578         iwl_pcie_conf_msix_hw(trans_pcie);
1579         if (!trans_pcie->msix_enabled)
1580                 iwl_pcie_reset_ict(trans);
1581         iwl_enable_interrupts(trans);
1582 
1583         iwl_pcie_set_pwr(trans, false);
1584 
1585         if (!reset) {
1586                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1587                               BIT(trans->trans_cfg->csr->flag_mac_access_req));
1588         } else {
1589                 iwl_trans_pcie_tx_reset(trans);
1590 
1591                 ret = iwl_pcie_rx_init(trans);
1592                 if (ret) {
1593                         IWL_ERR(trans,
1594                                 "Failed to resume the device (RX reset)\n");
1595                         return ret;
1596                 }
1597         }
1598 
1599         IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1600                         iwl_read_umac_prph(trans, WFPM_GP2));
1601 
1602         val = iwl_read32(trans, CSR_RESET);
1603         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1604                 *status = IWL_D3_STATUS_RESET;
1605         else
1606                 *status = IWL_D3_STATUS_ALIVE;
1607 
1608 out:
1609         if (*status == IWL_D3_STATUS_ALIVE &&
1610             trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1611                 trans_pcie->sx_complete = false;
1612                 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1613                                     UREG_DOORBELL_TO_ISR6_RESUME);
1614 
1615                 ret = wait_event_timeout(trans_pcie->sx_waitq,
1616                                          trans_pcie->sx_complete, 2 * HZ);
1617                 /*
1618                  * Invalidate it toward next suspend.
1619                  */
1620                 trans_pcie->sx_complete = false;
1621 
1622                 if (!ret) {
1623                         IWL_ERR(trans, "Timeout exiting D3\n");
1624                         return -ETIMEDOUT;
1625                 }
1626         }
1627         return 0;
1628 }
1629 
1630 static void
1631 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1632                             struct iwl_trans *trans,
1633                             const struct iwl_cfg_trans_params *cfg_trans)
1634 {
1635         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1636         int max_irqs, num_irqs, i, ret;
1637         u16 pci_cmd;
1638 
1639         if (!cfg_trans->mq_rx_supported)
1640                 goto enable_msi;
1641 
1642         max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
1643         for (i = 0; i < max_irqs; i++)
1644                 trans_pcie->msix_entries[i].entry = i;
1645 
1646         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1647                                          MSIX_MIN_INTERRUPT_VECTORS,
1648                                          max_irqs);
1649         if (num_irqs < 0) {
1650                 IWL_DEBUG_INFO(trans,
1651                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1652                                num_irqs);
1653                 goto enable_msi;
1654         }
1655         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1656 
1657         IWL_DEBUG_INFO(trans,
1658                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1659                        num_irqs);
1660 
1661         /*
1662          * In case the OS provides fewer interrupts than requested, different
1663          * causes will share the same interrupt vector as follows:
1664          * One interrupt less: non rx causes shared with FBQ.
1665          * Two interrupts less: non rx causes shared with FBQ and RSS.
1666          * More than two interrupts: we will use fewer RSS queues.
1667          */
1668         if (num_irqs <= max_irqs - 2) {
1669                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1670                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1671                         IWL_SHARED_IRQ_FIRST_RSS;
1672         } else if (num_irqs == max_irqs - 1) {
1673                 trans_pcie->trans->num_rx_queues = num_irqs;
1674                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1675         } else {
1676                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1677         }
1678         WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1679 
1680         trans_pcie->alloc_vecs = num_irqs;
1681         trans_pcie->msix_enabled = true;
1682         return;
1683 
1684 enable_msi:
1685         ret = pci_enable_msi(pdev);
1686         if (ret) {
1687                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1688                 /* enable rfkill interrupt: hw bug w/a */
1689                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1690                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1691                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1692                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1693                 }
1694         }
1695 }
1696 
1697 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1698 {
1699         int iter_rx_q, i, ret, cpu, offset;
1700         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1701 
1702         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1703         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1704         offset = 1 + i;
1705         for (; i < iter_rx_q ; i++) {
1706                 /*
1707                  * Get the cpu prior to the place to search
1708                  * (i.e. return will be > i - 1).
1709                  */
1710                 cpu = cpumask_next(i - offset, cpu_online_mask);
1711                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1712                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1713                                             &trans_pcie->affinity_mask[i]);
1714                 if (ret)
1715                         IWL_ERR(trans_pcie->trans,
1716                                 "Failed to set affinity mask for IRQ %d\n",
1717                                 i);
1718         }
1719 }
1720 
1721 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1722                                       struct iwl_trans_pcie *trans_pcie)
1723 {
1724         int i;
1725 
1726         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1727                 int ret;
1728                 struct msix_entry *msix_entry;
1729                 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1730 
1731                 if (!qname)
1732                         return -ENOMEM;
1733 
1734                 msix_entry = &trans_pcie->msix_entries[i];
1735                 ret = devm_request_threaded_irq(&pdev->dev,
1736                                                 msix_entry->vector,
1737                                                 iwl_pcie_msix_isr,
1738                                                 (i == trans_pcie->def_irq) ?
1739                                                 iwl_pcie_irq_msix_handler :
1740                                                 iwl_pcie_irq_rx_msix_handler,
1741                                                 IRQF_SHARED,
1742                                                 qname,
1743                                                 msix_entry);
1744                 if (ret) {
1745                         IWL_ERR(trans_pcie->trans,
1746                                 "Error allocating IRQ %d\n", i);
1747 
1748                         return ret;
1749                 }
1750         }
1751         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1752 
1753         return 0;
1754 }
1755 
1756 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
1757 {
1758         u32 hpm, wprot;
1759 
1760         switch (trans->trans_cfg->device_family) {
1761         case IWL_DEVICE_FAMILY_9000:
1762                 wprot = PREG_PRPH_WPROT_9000;
1763                 break;
1764         case IWL_DEVICE_FAMILY_22000:
1765                 wprot = PREG_PRPH_WPROT_22000;
1766                 break;
1767         default:
1768                 return 0;
1769         }
1770 
1771         hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1772         if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
1773                 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1774 
1775                 if (wprot_val & PREG_WFPM_ACCESS) {
1776                         IWL_ERR(trans,
1777                                 "Error, can not clear persistence bit\n");
1778                         return -EPERM;
1779                 }
1780                 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1781                                             hpm & ~PERSISTENCE_BIT);
1782         }
1783 
1784         return 0;
1785 }
1786 
1787 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1788 {
1789         int ret;
1790 
1791         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1792         if (ret < 0)
1793                 return ret;
1794 
1795         iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1796                           HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1797         udelay(20);
1798         iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1799                           HPM_HIPM_GEN_CFG_CR_PG_EN |
1800                           HPM_HIPM_GEN_CFG_CR_SLP_EN);
1801         udelay(20);
1802         iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1803                             HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1804 
1805         iwl_trans_pcie_sw_reset(trans);
1806 
1807         return 0;
1808 }
1809 
1810 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1811 {
1812         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1813         int err;
1814 
1815         lockdep_assert_held(&trans_pcie->mutex);
1816 
1817         err = iwl_pcie_prepare_card_hw(trans);
1818         if (err) {
1819                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1820                 return err;
1821         }
1822 
1823         err = iwl_trans_pcie_clear_persistence_bit(trans);
1824         if (err)
1825                 return err;
1826 
1827         iwl_trans_pcie_sw_reset(trans);
1828 
1829         if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1830             trans->cfg->integrated) {
1831                 err = iwl_pcie_gen2_force_power_gating(trans);
1832                 if (err)
1833                         return err;
1834         }
1835 
1836         err = iwl_pcie_apm_init(trans);
1837         if (err)
1838                 return err;
1839 
1840         iwl_pcie_init_msix(trans_pcie);
1841 
1842         /* From now on, the op_mode will be kept updated about RF kill state */
1843         iwl_enable_rfkill_int(trans);
1844 
1845         trans_pcie->opmode_down = false;
1846 
1847         /* Set is_down to false here so that...*/
1848         trans_pcie->is_down = false;
1849 
1850         /* ...rfkill can call stop_device and set it false if needed */
1851         iwl_pcie_check_hw_rf_kill(trans);
1852 
1853         return 0;
1854 }
1855 
1856 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1857 {
1858         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1859         int ret;
1860 
1861         mutex_lock(&trans_pcie->mutex);
1862         ret = _iwl_trans_pcie_start_hw(trans);
1863         mutex_unlock(&trans_pcie->mutex);
1864 
1865         return ret;
1866 }
1867 
1868 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1869 {
1870         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1871 
1872         mutex_lock(&trans_pcie->mutex);
1873 
1874         /* disable interrupts - don't enable HW RF kill interrupt */
1875         iwl_disable_interrupts(trans);
1876 
1877         iwl_pcie_apm_stop(trans, true);
1878 
1879         iwl_disable_interrupts(trans);
1880 
1881         iwl_pcie_disable_ict(trans);
1882 
1883         mutex_unlock(&trans_pcie->mutex);
1884 
1885         iwl_pcie_synchronize_irqs(trans);
1886 }
1887 
1888 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1889 {
1890         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1891 }
1892 
1893 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1894 {
1895         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1896 }
1897 
1898 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1899 {
1900         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1901 }
1902 
1903 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1904 {
1905         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1906                 return 0x00FFFFFF;
1907         else
1908                 return 0x000FFFFF;
1909 }
1910 
1911 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1912 {
1913         u32 mask = iwl_trans_pcie_prph_msk(trans);
1914 
1915         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1916                                ((reg & mask) | (3 << 24)));
1917         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1918 }
1919 
1920 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1921                                       u32 val)
1922 {
1923         u32 mask = iwl_trans_pcie_prph_msk(trans);
1924 
1925         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1926                                ((addr & mask) | (3 << 24)));
1927         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1928 }
1929 
1930 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1931                                      const struct iwl_trans_config *trans_cfg)
1932 {
1933         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1934 
1935         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1936         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1937         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1938         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1939                 trans_pcie->n_no_reclaim_cmds = 0;
1940         else
1941                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1942         if (trans_pcie->n_no_reclaim_cmds)
1943                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1944                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1945 
1946         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1947         trans_pcie->rx_page_order =
1948                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1949 
1950         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1951         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1952         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1953 
1954         trans_pcie->page_offs = trans_cfg->cb_data_offs;
1955         trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1956 
1957         trans->command_groups = trans_cfg->command_groups;
1958         trans->command_groups_size = trans_cfg->command_groups_size;
1959 
1960         /* Initialize NAPI here - it should be before registering to mac80211
1961          * in the opmode but after the HW struct is allocated.
1962          * As this function may be called again in some corner cases don't
1963          * do anything if NAPI was already initialized.
1964          */
1965         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1966                 init_dummy_netdev(&trans_pcie->napi_dev);
1967 }
1968 
1969 void iwl_trans_pcie_free(struct iwl_trans *trans)
1970 {
1971         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1972         int i;
1973 
1974         iwl_pcie_synchronize_irqs(trans);
1975 
1976         if (trans->trans_cfg->gen2)
1977                 iwl_pcie_gen2_tx_free(trans);
1978         else
1979                 iwl_pcie_tx_free(trans);
1980         iwl_pcie_rx_free(trans);
1981 
1982         if (trans_pcie->rba.alloc_wq) {
1983                 destroy_workqueue(trans_pcie->rba.alloc_wq);
1984                 trans_pcie->rba.alloc_wq = NULL;
1985         }
1986 
1987         if (trans_pcie->msix_enabled) {
1988                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1989                         irq_set_affinity_hint(
1990                                 trans_pcie->msix_entries[i].vector,
1991                                 NULL);
1992                 }
1993 
1994                 trans_pcie->msix_enabled = false;
1995         } else {
1996                 iwl_pcie_free_ict(trans);
1997         }
1998 
1999         iwl_pcie_free_fw_monitor(trans);
2000 
2001         for_each_possible_cpu(i) {
2002                 struct iwl_tso_hdr_page *p =
2003                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
2004 
2005                 if (p->page)
2006                         __free_page(p->page);
2007         }
2008 
2009         free_percpu(trans_pcie->tso_hdr_page);
2010         mutex_destroy(&trans_pcie->mutex);
2011         iwl_trans_free(trans);
2012 }
2013 
2014 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2015 {
2016         if (state)
2017                 set_bit(STATUS_TPOWER_PMI, &trans->status);
2018         else
2019                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
2020 }
2021 
2022 struct iwl_trans_pcie_removal {
2023         struct pci_dev *pdev;
2024         struct work_struct work;
2025 };
2026 
2027 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2028 {
2029         struct iwl_trans_pcie_removal *removal =
2030                 container_of(wk, struct iwl_trans_pcie_removal, work);
2031         struct pci_dev *pdev = removal->pdev;
2032         static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
2033 
2034         dev_err(&pdev->dev, "Device gone - attempting removal\n");
2035         kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2036         pci_lock_rescan_remove();
2037         pci_dev_put(pdev);
2038         pci_stop_and_remove_bus_device(pdev);
2039         pci_unlock_rescan_remove();
2040 
2041         kfree(removal);
2042         module_put(THIS_MODULE);
2043 }
2044 
2045 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
2046                                            unsigned long *flags)
2047 {
2048         int ret;
2049         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2050 
2051         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
2052 
2053         if (trans_pcie->cmd_hold_nic_awake)
2054                 goto out;
2055 
2056         /* this bit wakes up the NIC */
2057         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
2058                                  BIT(trans->trans_cfg->csr->flag_mac_access_req));
2059         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2060                 udelay(2);
2061 
2062         /*
2063          * These bits say the device is running, and should keep running for
2064          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2065          * but they do not indicate that embedded SRAM is restored yet;
2066          * HW with volatile SRAM must save/restore contents to/from
2067          * host DRAM when sleeping/waking for power-saving.
2068          * Each direction takes approximately 1/4 millisecond; with this
2069          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2070          * series of register accesses are expected (e.g. reading Event Log),
2071          * to keep device from sleeping.
2072          *
2073          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2074          * SRAM is okay/restored.  We don't check that here because this call
2075          * is just for hardware register access; but GP1 MAC_SLEEP
2076          * check is a good idea before accessing the SRAM of HW with
2077          * volatile SRAM (e.g. reading Event Log).
2078          *
2079          * 5000 series and later (including 1000 series) have non-volatile SRAM,
2080          * and do not save/restore SRAM when power cycling.
2081          */
2082         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2083                            BIT(trans->trans_cfg->csr->flag_val_mac_access_en),
2084                            (BIT(trans->trans_cfg->csr->flag_mac_clock_ready) |
2085                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2086         if (unlikely(ret < 0)) {
2087                 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2088 
2089                 WARN_ONCE(1,
2090                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2091                           cntrl);
2092 
2093                 iwl_trans_pcie_dump_regs(trans);
2094 
2095                 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2096                         struct iwl_trans_pcie_removal *removal;
2097 
2098                         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2099                                 goto err;
2100 
2101                         IWL_ERR(trans, "Device gone - scheduling removal!\n");
2102 
2103                         /*
2104                          * get a module reference to avoid doing this
2105                          * while unloading anyway and to avoid
2106                          * scheduling a work with code that's being
2107                          * removed.
2108                          */
2109                         if (!try_module_get(THIS_MODULE)) {
2110                                 IWL_ERR(trans,
2111                                         "Module is being unloaded - abort\n");
2112                                 goto err;
2113                         }
2114 
2115                         removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2116                         if (!removal) {
2117                                 module_put(THIS_MODULE);
2118                                 goto err;
2119                         }
2120                         /*
2121                          * we don't need to clear this flag, because
2122                          * the trans will be freed and reallocated.
2123                         */
2124                         set_bit(STATUS_TRANS_DEAD, &trans->status);
2125 
2126                         removal->pdev = to_pci_dev(trans->dev);
2127                         INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2128                         pci_dev_get(removal->pdev);
2129                         schedule_work(&removal->work);
2130                 } else {
2131                         iwl_write32(trans, CSR_RESET,
2132                                     CSR_RESET_REG_FLAG_FORCE_NMI);
2133                 }
2134 
2135 err:
2136                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2137                 return false;
2138         }
2139 
2140 out:
2141         /*
2142          * Fool sparse by faking we release the lock - sparse will
2143          * track nic_access anyway.
2144          */
2145         __release(&trans_pcie->reg_lock);
2146         return true;
2147 }
2148 
2149 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2150                                               unsigned long *flags)
2151 {
2152         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2153 
2154         lockdep_assert_held(&trans_pcie->reg_lock);
2155 
2156         /*
2157          * Fool sparse by faking we acquiring the lock - sparse will
2158          * track nic_access anyway.
2159          */
2160         __acquire(&trans_pcie->reg_lock);
2161 
2162         if (trans_pcie->cmd_hold_nic_awake)
2163                 goto out;
2164 
2165         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2166                                    BIT(trans->trans_cfg->csr->flag_mac_access_req));
2167         /*
2168          * Above we read the CSR_GP_CNTRL register, which will flush
2169          * any previous writes, but we need the write that clears the
2170          * MAC_ACCESS_REQ bit to be performed before any other writes
2171          * scheduled on different CPUs (after we drop reg_lock).
2172          */
2173 out:
2174         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2175 }
2176 
2177 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2178                                    void *buf, int dwords)
2179 {
2180         unsigned long flags;
2181         int offs, ret = 0;
2182         u32 *vals = buf;
2183 
2184         if (iwl_trans_grab_nic_access(trans, &flags)) {
2185                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2186                 for (offs = 0; offs < dwords; offs++)
2187                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
2188                 iwl_trans_release_nic_access(trans, &flags);
2189         } else {
2190                 ret = -EBUSY;
2191         }
2192         return ret;
2193 }
2194 
2195 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2196                                     const void *buf, int dwords)
2197 {
2198         unsigned long flags;
2199         int offs, ret = 0;
2200         const u32 *vals = buf;
2201 
2202         if (iwl_trans_grab_nic_access(trans, &flags)) {
2203                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2204                 for (offs = 0; offs < dwords; offs++)
2205                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2206                                     vals ? vals[offs] : 0);
2207                 iwl_trans_release_nic_access(trans, &flags);
2208         } else {
2209                 ret = -EBUSY;
2210         }
2211         return ret;
2212 }
2213 
2214 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2215                                             unsigned long txqs,
2216                                             bool freeze)
2217 {
2218         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2219         int queue;
2220 
2221         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2222                 struct iwl_txq *txq = trans_pcie->txq[queue];
2223                 unsigned long now;
2224 
2225                 spin_lock_bh(&txq->lock);
2226 
2227                 now = jiffies;
2228 
2229                 if (txq->frozen == freeze)
2230                         goto next_queue;
2231 
2232                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2233                                     freeze ? "Freezing" : "Waking", queue);
2234 
2235                 txq->frozen = freeze;
2236 
2237                 if (txq->read_ptr == txq->write_ptr)
2238                         goto next_queue;
2239 
2240                 if (freeze) {
2241                         if (unlikely(time_after(now,
2242                                                 txq->stuck_timer.expires))) {
2243                                 /*
2244                                  * The timer should have fired, maybe it is
2245                                  * spinning right now on the lock.
2246                                  */
2247                                 goto next_queue;
2248                         }
2249                         /* remember how long until the timer fires */
2250                         txq->frozen_expiry_remainder =
2251                                 txq->stuck_timer.expires - now;
2252                         del_timer(&txq->stuck_timer);
2253                         goto next_queue;
2254                 }
2255 
2256                 /*
2257                  * Wake a non-empty queue -> arm timer with the
2258                  * remainder before it froze
2259                  */
2260                 mod_timer(&txq->stuck_timer,
2261                           now + txq->frozen_expiry_remainder);
2262 
2263 next_queue:
2264                 spin_unlock_bh(&txq->lock);
2265         }
2266 }
2267 
2268 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2269 {
2270         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2271         int i;
2272 
2273         for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
2274                 struct iwl_txq *txq = trans_pcie->txq[i];
2275 
2276                 if (i == trans_pcie->cmd_queue)
2277                         continue;
2278 
2279                 spin_lock_bh(&txq->lock);
2280 
2281                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2282                         txq->block--;
2283                         if (!txq->block) {
2284                                 iwl_write32(trans, HBUS_TARG_WRPTR,
2285                                             txq->write_ptr | (i << 8));
2286                         }
2287                 } else if (block) {
2288                         txq->block++;
2289                 }
2290 
2291                 spin_unlock_bh(&txq->lock);
2292         }
2293 }
2294 
2295 #define IWL_FLUSH_WAIT_MS       2000
2296 
2297 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2298 {
2299         u32 txq_id = txq->id;
2300         u32 status;
2301         bool active;
2302         u8 fifo;
2303 
2304         if (trans->trans_cfg->use_tfh) {
2305                 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2306                         txq->read_ptr, txq->write_ptr);
2307                 /* TODO: access new SCD registers and dump them */
2308                 return;
2309         }
2310 
2311         status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2312         fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2313         active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2314 
2315         IWL_ERR(trans,
2316                 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2317                 txq_id, active ? "" : "in", fifo,
2318                 jiffies_to_msecs(txq->wd_timeout),
2319                 txq->read_ptr, txq->write_ptr,
2320                 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2321                         (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2322                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2323                         (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2324                         iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2325 }
2326 
2327 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2328                                        struct iwl_trans_rxq_dma_data *data)
2329 {
2330         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2331 
2332         if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2333                 return -EINVAL;
2334 
2335         data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2336         data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2337         data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2338         data->fr_bd_wid = 0;
2339 
2340         return 0;
2341 }
2342 
2343 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2344 {
2345         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2346         struct iwl_txq *txq;
2347         unsigned long now = jiffies;
2348         bool overflow_tx;
2349         u8 wr_ptr;
2350 
2351         /* Make sure the NIC is still alive in the bus */
2352         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2353                 return -ENODEV;
2354 
2355         if (!test_bit(txq_idx, trans_pcie->queue_used))
2356                 return -EINVAL;
2357 
2358         IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2359         txq = trans_pcie->txq[txq_idx];
2360 
2361         spin_lock_bh(&txq->lock);
2362         overflow_tx = txq->overflow_tx ||
2363                       !skb_queue_empty(&txq->overflow_q);
2364         spin_unlock_bh(&txq->lock);
2365 
2366         wr_ptr = READ_ONCE(txq->write_ptr);
2367 
2368         while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2369                 overflow_tx) &&
2370                !time_after(jiffies,
2371                            now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2372                 u8 write_ptr = READ_ONCE(txq->write_ptr);
2373 
2374                 /*
2375                  * If write pointer moved during the wait, warn only
2376                  * if the TX came from op mode. In case TX came from
2377                  * trans layer (overflow TX) don't warn.
2378                  */
2379                 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
2380                               "WR pointer moved while flushing %d -> %d\n",
2381                               wr_ptr, write_ptr))
2382                         return -ETIMEDOUT;
2383                 wr_ptr = write_ptr;
2384 
2385                 usleep_range(1000, 2000);
2386 
2387                 spin_lock_bh(&txq->lock);
2388                 overflow_tx = txq->overflow_tx ||
2389                               !skb_queue_empty(&txq->overflow_q);
2390                 spin_unlock_bh(&txq->lock);
2391         }
2392 
2393         if (txq->read_ptr != txq->write_ptr) {
2394                 IWL_ERR(trans,
2395                         "fail to flush all tx fifo queues Q %d\n", txq_idx);
2396                 iwl_trans_pcie_log_scd_error(trans, txq);
2397                 return -ETIMEDOUT;
2398         }
2399 
2400         IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2401 
2402         return 0;
2403 }
2404 
2405 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2406 {
2407         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2408         int cnt;
2409         int ret = 0;
2410 
2411         /* waiting for all the tx frames complete might take a while */
2412         for (cnt = 0;
2413              cnt < trans->trans_cfg->base_params->num_of_queues;
2414              cnt++) {
2415 
2416                 if (cnt == trans_pcie->cmd_queue)
2417                         continue;
2418                 if (!test_bit(cnt, trans_pcie->queue_used))
2419                         continue;
2420                 if (!(BIT(cnt) & txq_bm))
2421                         continue;
2422 
2423                 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2424                 if (ret)
2425                         break;
2426         }
2427 
2428         return ret;
2429 }
2430 
2431 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2432                                          u32 mask, u32 value)
2433 {
2434         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2435         unsigned long flags;
2436 
2437         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2438         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2439         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2440 }
2441 
2442 static const char *get_csr_string(int cmd)
2443 {
2444 #define IWL_CMD(x) case x: return #x
2445         switch (cmd) {
2446         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2447         IWL_CMD(CSR_INT_COALESCING);
2448         IWL_CMD(CSR_INT);
2449         IWL_CMD(CSR_INT_MASK);
2450         IWL_CMD(CSR_FH_INT_STATUS);
2451         IWL_CMD(CSR_GPIO_IN);
2452         IWL_CMD(CSR_RESET);
2453         IWL_CMD(CSR_GP_CNTRL);
2454         IWL_CMD(CSR_HW_REV);
2455         IWL_CMD(CSR_EEPROM_REG);
2456         IWL_CMD(CSR_EEPROM_GP);
2457         IWL_CMD(CSR_OTP_GP_REG);
2458         IWL_CMD(CSR_GIO_REG);
2459         IWL_CMD(CSR_GP_UCODE_REG);
2460         IWL_CMD(CSR_GP_DRIVER_REG);
2461         IWL_CMD(CSR_UCODE_DRV_GP1);
2462         IWL_CMD(CSR_UCODE_DRV_GP2);
2463         IWL_CMD(CSR_LED_REG);
2464         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2465         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2466         IWL_CMD(CSR_ANA_PLL_CFG);
2467         IWL_CMD(CSR_HW_REV_WA_REG);
2468         IWL_CMD(CSR_MONITOR_STATUS_REG);
2469         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2470         default:
2471                 return "UNKNOWN";
2472         }
2473 #undef IWL_CMD
2474 }
2475 
2476 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2477 {
2478         int i;
2479         static const u32 csr_tbl[] = {
2480                 CSR_HW_IF_CONFIG_REG,
2481                 CSR_INT_COALESCING,
2482                 CSR_INT,
2483                 CSR_INT_MASK,
2484                 CSR_FH_INT_STATUS,
2485                 CSR_GPIO_IN,
2486                 CSR_RESET,
2487                 CSR_GP_CNTRL,
2488                 CSR_HW_REV,
2489                 CSR_EEPROM_REG,
2490                 CSR_EEPROM_GP,
2491                 CSR_OTP_GP_REG,
2492                 CSR_GIO_REG,
2493                 CSR_GP_UCODE_REG,
2494                 CSR_GP_DRIVER_REG,
2495                 CSR_UCODE_DRV_GP1,
2496                 CSR_UCODE_DRV_GP2,
2497                 CSR_LED_REG,
2498                 CSR_DRAM_INT_TBL_REG,
2499                 CSR_GIO_CHICKEN_BITS,
2500                 CSR_ANA_PLL_CFG,
2501                 CSR_MONITOR_STATUS_REG,
2502                 CSR_HW_REV_WA_REG,
2503                 CSR_DBG_HPET_MEM_REG
2504         };
2505         IWL_ERR(trans, "CSR values:\n");
2506         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2507                 "CSR_INT_PERIODIC_REG)\n");
2508         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2509                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2510                         get_csr_string(csr_tbl[i]),
2511                         iwl_read32(trans, csr_tbl[i]));
2512         }
2513 }
2514 
2515 #ifdef CONFIG_IWLWIFI_DEBUGFS
2516 /* create and remove of files */
2517 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2518         debugfs_create_file(#name, mode, parent, trans,                 \
2519                             &iwl_dbgfs_##name##_ops);                   \
2520 } while (0)
2521 
2522 /* file operation */
2523 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2524 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2525         .read = iwl_dbgfs_##name##_read,                                \
2526         .open = simple_open,                                            \
2527         .llseek = generic_file_llseek,                                  \
2528 };
2529 
2530 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2531 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2532         .write = iwl_dbgfs_##name##_write,                              \
2533         .open = simple_open,                                            \
2534         .llseek = generic_file_llseek,                                  \
2535 };
2536 
2537 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2538 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2539         .write = iwl_dbgfs_##name##_write,                              \
2540         .read = iwl_dbgfs_##name##_read,                                \
2541         .open = simple_open,                                            \
2542         .llseek = generic_file_llseek,                                  \
2543 };
2544 
2545 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2546                                        char __user *user_buf,
2547                                        size_t count, loff_t *ppos)
2548 {
2549         struct iwl_trans *trans = file->private_data;
2550         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2551         struct iwl_txq *txq;
2552         char *buf;
2553         int pos = 0;
2554         int cnt;
2555         int ret;
2556         size_t bufsz;
2557 
2558         bufsz = sizeof(char) * 75 *
2559                 trans->trans_cfg->base_params->num_of_queues;
2560 
2561         if (!trans_pcie->txq_memory)
2562                 return -EAGAIN;
2563 
2564         buf = kzalloc(bufsz, GFP_KERNEL);
2565         if (!buf)
2566                 return -ENOMEM;
2567 
2568         for (cnt = 0;
2569              cnt < trans->trans_cfg->base_params->num_of_queues;
2570              cnt++) {
2571                 txq = trans_pcie->txq[cnt];
2572                 pos += scnprintf(buf + pos, bufsz - pos,
2573                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2574                                 cnt, txq->read_ptr, txq->write_ptr,
2575                                 !!test_bit(cnt, trans_pcie->queue_used),
2576                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2577                                  txq->need_update, txq->frozen,
2578                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2579         }
2580         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2581         kfree(buf);
2582         return ret;
2583 }
2584 
2585 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2586                                        char __user *user_buf,
2587                                        size_t count, loff_t *ppos)
2588 {
2589         struct iwl_trans *trans = file->private_data;
2590         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2591         char *buf;
2592         int pos = 0, i, ret;
2593         size_t bufsz = sizeof(buf);
2594 
2595         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2596 
2597         if (!trans_pcie->rxq)
2598                 return -EAGAIN;
2599 
2600         buf = kzalloc(bufsz, GFP_KERNEL);
2601         if (!buf)
2602                 return -ENOMEM;
2603 
2604         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2605                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2606 
2607                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2608                                  i);
2609                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2610                                  rxq->read);
2611                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2612                                  rxq->write);
2613                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2614                                  rxq->write_actual);
2615                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2616                                  rxq->need_update);
2617                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2618                                  rxq->free_count);
2619                 if (rxq->rb_stts) {
2620                         u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2621                                                                      rxq));
2622                         pos += scnprintf(buf + pos, bufsz - pos,
2623                                          "\tclosed_rb_num: %u\n",
2624                                          r & 0x0FFF);
2625                 } else {
2626                         pos += scnprintf(buf + pos, bufsz - pos,
2627                                          "\tclosed_rb_num: Not Allocated\n");
2628                 }
2629         }
2630         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2631         kfree(buf);
2632 
2633         return ret;
2634 }
2635 
2636 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2637                                         char __user *user_buf,
2638                                         size_t count, loff_t *ppos)
2639 {
2640         struct iwl_trans *trans = file->private_data;
2641         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2642         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2643 
2644         int pos = 0;
2645         char *buf;
2646         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2647         ssize_t ret;
2648 
2649         buf = kzalloc(bufsz, GFP_KERNEL);
2650         if (!buf)
2651                 return -ENOMEM;
2652 
2653         pos += scnprintf(buf + pos, bufsz - pos,
2654                         "Interrupt Statistics Report:\n");
2655 
2656         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2657                 isr_stats->hw);
2658         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2659                 isr_stats->sw);
2660         if (isr_stats->sw || isr_stats->hw) {
2661                 pos += scnprintf(buf + pos, bufsz - pos,
2662                         "\tLast Restarting Code:  0x%X\n",
2663                         isr_stats->err_code);
2664         }
2665 #ifdef CONFIG_IWLWIFI_DEBUG
2666         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2667                 isr_stats->sch);
2668         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2669                 isr_stats->alive);
2670 #endif
2671         pos += scnprintf(buf + pos, bufsz - pos,
2672                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2673 
2674         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2675                 isr_stats->ctkill);
2676 
2677         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2678                 isr_stats->wakeup);
2679 
2680         pos += scnprintf(buf + pos, bufsz - pos,
2681                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2682 
2683         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2684                 isr_stats->tx);
2685 
2686         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2687                 isr_stats->unhandled);
2688 
2689         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2690         kfree(buf);
2691         return ret;
2692 }
2693 
2694 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2695                                          const char __user *user_buf,
2696                                          size_t count, loff_t *ppos)
2697 {
2698         struct iwl_trans *trans = file->private_data;
2699         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2700         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2701         u32 reset_flag;
2702         int ret;
2703 
2704         ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2705         if (ret)
2706                 return ret;
2707         if (reset_flag == 0)
2708                 memset(isr_stats, 0, sizeof(*isr_stats));
2709 
2710         return count;
2711 }
2712 
2713 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2714                                    const char __user *user_buf,
2715                                    size_t count, loff_t *ppos)
2716 {
2717         struct iwl_trans *trans = file->private_data;
2718 
2719         iwl_pcie_dump_csr(trans);
2720 
2721         return count;
2722 }
2723 
2724 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2725                                      char __user *user_buf,
2726                                      size_t count, loff_t *ppos)
2727 {
2728         struct iwl_trans *trans = file->private_data;
2729         char *buf = NULL;
2730         ssize_t ret;
2731 
2732         ret = iwl_dump_fh(trans, &buf);
2733         if (ret < 0)
2734                 return ret;
2735         if (!buf)
2736                 return -EINVAL;
2737         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2738         kfree(buf);
2739         return ret;
2740 }
2741 
2742 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2743                                      char __user *user_buf,
2744                                      size_t count, loff_t *ppos)
2745 {
2746         struct iwl_trans *trans = file->private_data;
2747         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2748         char buf[100];
2749         int pos;
2750 
2751         pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2752                         trans_pcie->debug_rfkill,
2753                         !(iwl_read32(trans, CSR_GP_CNTRL) &
2754                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2755 
2756         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2757 }
2758 
2759 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2760                                       const char __user *user_buf,
2761                                       size_t count, loff_t *ppos)
2762 {
2763         struct iwl_trans *trans = file->private_data;
2764         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2765         bool new_value;
2766         int ret;
2767 
2768         ret = kstrtobool_from_user(user_buf, count, &new_value);
2769         if (ret)
2770                 return ret;
2771         if (new_value == trans_pcie->debug_rfkill)
2772                 return count;
2773         IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2774                  trans_pcie->debug_rfkill, new_value);
2775         trans_pcie->debug_rfkill = new_value;
2776         iwl_pcie_handle_rfkill_irq(trans);
2777 
2778         return count;
2779 }
2780 
2781 static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2782                                        struct file *file)
2783 {
2784         struct iwl_trans *trans = inode->i_private;
2785         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2786 
2787         if (!trans->dbg.dest_tlv ||
2788             trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
2789                 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2790                 return -ENOENT;
2791         }
2792 
2793         if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2794                 return -EBUSY;
2795 
2796         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2797         return simple_open(inode, file);
2798 }
2799 
2800 static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2801                                           struct file *file)
2802 {
2803         struct iwl_trans_pcie *trans_pcie =
2804                 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2805 
2806         if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2807                 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2808         return 0;
2809 }
2810 
2811 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2812                                   void *buf, ssize_t *size,
2813                                   ssize_t *bytes_copied)
2814 {
2815         int buf_size_left = count - *bytes_copied;
2816 
2817         buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2818         if (*size > buf_size_left)
2819                 *size = buf_size_left;
2820 
2821         *size -= copy_to_user(user_buf, buf, *size);
2822         *bytes_copied += *size;
2823 
2824         if (buf_size_left == *size)
2825                 return true;
2826         return false;
2827 }
2828 
2829 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2830                                            char __user *user_buf,
2831                                            size_t count, loff_t *ppos)
2832 {
2833         struct iwl_trans *trans = file->private_data;
2834         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2835         void *cpu_addr = (void *)trans->dbg.fw_mon[0].block, *curr_buf;
2836         struct cont_rec *data = &trans_pcie->fw_mon_data;
2837         u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2838         ssize_t size, bytes_copied = 0;
2839         bool b_full;
2840 
2841         if (trans->dbg.dest_tlv) {
2842                 write_ptr_addr =
2843                         le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2844                 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
2845         } else {
2846                 write_ptr_addr = MON_BUFF_WRPTR;
2847                 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2848         }
2849 
2850         if (unlikely(!trans->dbg.rec_on))
2851                 return 0;
2852 
2853         mutex_lock(&data->mutex);
2854         if (data->state ==
2855             IWL_FW_MON_DBGFS_STATE_DISABLED) {
2856                 mutex_unlock(&data->mutex);
2857                 return 0;
2858         }
2859 
2860         /* write_ptr position in bytes rather then DW */
2861         write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2862         wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2863 
2864         if (data->prev_wrap_cnt == wrap_cnt) {
2865                 size = write_ptr - data->prev_wr_ptr;
2866                 curr_buf = cpu_addr + data->prev_wr_ptr;
2867                 b_full = iwl_write_to_user_buf(user_buf, count,
2868                                                curr_buf, &size,
2869                                                &bytes_copied);
2870                 data->prev_wr_ptr += size;
2871 
2872         } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2873                    write_ptr < data->prev_wr_ptr) {
2874                 size = trans->dbg.fw_mon[0].size - data->prev_wr_ptr;
2875                 curr_buf = cpu_addr + data->prev_wr_ptr;
2876                 b_full = iwl_write_to_user_buf(user_buf, count,
2877                                                curr_buf, &size,
2878                                                &bytes_copied);
2879                 data->prev_wr_ptr += size;
2880 
2881                 if (!b_full) {
2882                         size = write_ptr;
2883                         b_full = iwl_write_to_user_buf(user_buf, count,
2884                                                        cpu_addr, &size,
2885                                                        &bytes_copied);
2886                         data->prev_wr_ptr = size;
2887                         data->prev_wrap_cnt++;
2888                 }
2889         } else {
2890                 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2891                     write_ptr > data->prev_wr_ptr)
2892                         IWL_WARN(trans,
2893                                  "write pointer passed previous write pointer, start copying from the beginning\n");
2894                 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2895                                    data->prev_wr_ptr == 0))
2896                         IWL_WARN(trans,
2897                                  "monitor data is out of sync, start copying from the beginning\n");
2898 
2899                 size = write_ptr;
2900                 b_full = iwl_write_to_user_buf(user_buf, count,
2901                                                cpu_addr, &size,
2902                                                &bytes_copied);
2903                 data->prev_wr_ptr = size;
2904                 data->prev_wrap_cnt = wrap_cnt;
2905         }
2906 
2907         mutex_unlock(&data->mutex);
2908 
2909         return bytes_copied;
2910 }
2911 
2912 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2913 DEBUGFS_READ_FILE_OPS(fh_reg);
2914 DEBUGFS_READ_FILE_OPS(rx_queue);
2915 DEBUGFS_READ_FILE_OPS(tx_queue);
2916 DEBUGFS_WRITE_FILE_OPS(csr);
2917 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2918 
2919 static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2920         .read = iwl_dbgfs_monitor_data_read,
2921         .open = iwl_dbgfs_monitor_data_open,
2922         .release = iwl_dbgfs_monitor_data_release,
2923 };
2924 
2925 /* Create the debugfs files and directories */
2926 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2927 {
2928         struct dentry *dir = trans->dbgfs_dir;
2929 
2930         DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2931         DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2932         DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2933         DEBUGFS_ADD_FILE(csr, dir, 0200);
2934         DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2935         DEBUGFS_ADD_FILE(rfkill, dir, 0600);
2936         DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
2937 }
2938 
2939 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2940 {
2941         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2942         struct cont_rec *data = &trans_pcie->fw_mon_data;
2943 
2944         mutex_lock(&data->mutex);
2945         data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2946         mutex_unlock(&data->mutex);
2947 }
2948 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2949 
2950 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2951 {
2952         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2953         u32 cmdlen = 0;
2954         int i;
2955 
2956         for (i = 0; i < trans_pcie->max_tbs; i++)
2957                 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2958 
2959         return cmdlen;
2960 }
2961 
2962 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2963                                    struct iwl_fw_error_dump_data **data,
2964                                    int allocated_rb_nums)
2965 {
2966         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2967         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2968         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2969         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2970         u32 i, r, j, rb_len = 0;
2971 
2972         spin_lock(&rxq->lock);
2973 
2974         r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
2975 
2976         for (i = rxq->read, j = 0;
2977              i != r && j < allocated_rb_nums;
2978              i = (i + 1) & RX_QUEUE_MASK, j++) {
2979                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2980                 struct iwl_fw_error_dump_rb *rb;
2981 
2982                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2983                                DMA_FROM_DEVICE);
2984 
2985                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2986 
2987                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2988                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2989                 rb = (void *)(*data)->data;
2990                 rb->index = cpu_to_le32(i);
2991                 memcpy(rb->data, page_address(rxb->page), max_len);
2992                 /* remap the page for the free benefit */
2993                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2994                                                      max_len,
2995                                                      DMA_FROM_DEVICE);
2996 
2997                 *data = iwl_fw_error_next_data(*data);
2998         }
2999 
3000         spin_unlock(&rxq->lock);
3001 
3002         return rb_len;
3003 }
3004 #define IWL_CSR_TO_DUMP (0x250)
3005 
3006 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3007                                    struct iwl_fw_error_dump_data **data)
3008 {
3009         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3010         __le32 *val;
3011         int i;
3012 
3013         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3014         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3015         val = (void *)(*data)->data;
3016 
3017         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3018                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3019 
3020         *data = iwl_fw_error_next_data(*data);
3021 
3022         return csr_len;
3023 }
3024 
3025 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3026                                        struct iwl_fw_error_dump_data **data)
3027 {
3028         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3029         unsigned long flags;
3030         __le32 *val;
3031         int i;
3032 
3033         if (!iwl_trans_grab_nic_access(trans, &flags))
3034                 return 0;
3035 
3036         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3037         (*data)->len = cpu_to_le32(fh_regs_len);
3038         val = (void *)(*data)->data;
3039 
3040         if (!trans->trans_cfg->gen2)
3041                 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3042                      i += sizeof(u32))
3043                         *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3044         else
3045                 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3046                      i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
3047                      i += sizeof(u32))
3048                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3049                                                                       i));
3050 
3051         iwl_trans_release_nic_access(trans, &flags);
3052 
3053         *data = iwl_fw_error_next_data(*data);
3054 
3055         return sizeof(**data) + fh_regs_len;
3056 }
3057 
3058 static u32
3059 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3060                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3061                                  u32 monitor_len)
3062 {
3063         u32 buf_size_in_dwords = (monitor_len >> 2);
3064         u32 *buffer = (u32 *)fw_mon_data->data;
3065         unsigned long flags;
3066         u32 i;
3067 
3068         if (!iwl_trans_grab_nic_access(trans, &flags))
3069                 return 0;
3070 
3071         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3072         for (i = 0; i < buf_size_in_dwords; i++)
3073                 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3074                                                        MON_DMARB_RD_DATA_ADDR);
3075         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3076 
3077         iwl_trans_release_nic_access(trans, &flags);
3078 
3079         return monitor_len;
3080 }
3081 
3082 static void
3083 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3084                              struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3085 {
3086         u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
3087 
3088         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3089                 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3090                 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3091                 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3092                 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
3093         } else if (trans->dbg.dest_tlv) {
3094                 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3095                 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3096                 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3097         } else {
3098                 base = MON_BUFF_BASE_ADDR;
3099                 write_ptr = MON_BUFF_WRPTR;
3100                 wrap_cnt = MON_BUFF_CYCLE_CNT;
3101         }
3102 
3103         write_ptr_val = iwl_read_prph(trans, write_ptr);
3104         fw_mon_data->fw_mon_cycle_cnt =
3105                 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3106         fw_mon_data->fw_mon_base_ptr =
3107                 cpu_to_le32(iwl_read_prph(trans, base));
3108         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3109                 fw_mon_data->fw_mon_base_high_ptr =
3110                         cpu_to_le32(iwl_read_prph(trans, base_high));
3111                 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3112         }
3113         fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
3114 }
3115 
3116 static u32
3117 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3118                             struct iwl_fw_error_dump_data **data,
3119                             u32 monitor_len)
3120 {
3121         u32 len = 0;
3122 
3123         if (trans->dbg.dest_tlv ||
3124             (trans->dbg.num_blocks &&
3125              (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3126               trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
3127                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
3128 
3129                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3130                 fw_mon_data = (void *)(*data)->data;
3131 
3132                 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3133 
3134                 len += sizeof(**data) + sizeof(*fw_mon_data);
3135                 if (trans->dbg.num_blocks) {
3136                         memcpy(fw_mon_data->data,
3137                                trans->dbg.fw_mon[0].block,
3138                                trans->dbg.fw_mon[0].size);
3139 
3140                         monitor_len = trans->dbg.fw_mon[0].size;
3141                 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
3142                         u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
3143                         /*
3144                          * Update pointers to reflect actual values after
3145                          * shifting
3146                          */
3147                         if (trans->dbg.dest_tlv->version) {
3148                                 base = (iwl_read_prph(trans, base) &
3149                                         IWL_LDBG_M2S_BUF_BA_MSK) <<
3150                                        trans->dbg.dest_tlv->base_shift;
3151                                 base *= IWL_M2S_UNIT_SIZE;
3152                                 base += trans->cfg->smem_offset;
3153                         } else {
3154                                 base = iwl_read_prph(trans, base) <<
3155                                        trans->dbg.dest_tlv->base_shift;
3156                         }
3157 
3158                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
3159                                            monitor_len / sizeof(u32));
3160                 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
3161                         monitor_len =
3162                                 iwl_trans_pci_dump_marbh_monitor(trans,
3163                                                                  fw_mon_data,
3164                                                                  monitor_len);
3165                 } else {
3166                         /* Didn't match anything - output no monitor data */
3167                         monitor_len = 0;
3168                 }
3169 
3170                 len += monitor_len;
3171                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3172         }
3173 
3174         return len;
3175 }
3176 
3177 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
3178 {
3179         if (trans->dbg.num_blocks) {
3180                 *len += sizeof(struct iwl_fw_error_dump_data) +
3181                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3182                         trans->dbg.fw_mon[0].size;
3183                 return trans->dbg.fw_mon[0].size;
3184         } else if (trans->dbg.dest_tlv) {
3185                 u32 base, end, cfg_reg, monitor_len;
3186 
3187                 if (trans->dbg.dest_tlv->version == 1) {
3188                         cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3189                         cfg_reg = iwl_read_prph(trans, cfg_reg);
3190                         base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3191                                 trans->dbg.dest_tlv->base_shift;
3192                         base *= IWL_M2S_UNIT_SIZE;
3193                         base += trans->cfg->smem_offset;
3194 
3195                         monitor_len =
3196                                 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3197                                 trans->dbg.dest_tlv->end_shift;
3198                         monitor_len *= IWL_M2S_UNIT_SIZE;
3199                 } else {
3200                         base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3201                         end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3202 
3203                         base = iwl_read_prph(trans, base) <<
3204                                trans->dbg.dest_tlv->base_shift;
3205                         end = iwl_read_prph(trans, end) <<
3206                               trans->dbg.dest_tlv->end_shift;
3207 
3208                         /* Make "end" point to the actual end */
3209                         if (trans->trans_cfg->device_family >=
3210                             IWL_DEVICE_FAMILY_8000 ||
3211                             trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3212                                 end += (1 << trans->dbg.dest_tlv->end_shift);
3213                         monitor_len = end - base;
3214                 }
3215                 *len += sizeof(struct iwl_fw_error_dump_data) +
3216                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3217                         monitor_len;
3218                 return monitor_len;
3219         }
3220         return 0;
3221 }
3222 
3223 static struct iwl_trans_dump_data
3224 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
3225                           u32 dump_mask)
3226 {
3227         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3228         struct iwl_fw_error_dump_data *data;
3229         struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
3230         struct iwl_fw_error_dump_txcmd *txcmd;
3231         struct iwl_trans_dump_data *dump_data;
3232         u32 len, num_rbs = 0, monitor_len = 0;
3233         int i, ptr;
3234         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3235                         !trans->trans_cfg->mq_rx_supported &&
3236                         dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3237 
3238         if (!dump_mask)
3239                 return NULL;
3240 
3241         /* transport dump header */
3242         len = sizeof(*dump_data);
3243 
3244         /* host commands */
3245         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
3246                 len += sizeof(*data) +
3247                         cmdq->n_window * (sizeof(*txcmd) +
3248                                           TFD_MAX_PAYLOAD_SIZE);
3249 
3250         /* FW monitor */
3251         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3252                 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3253 
3254         /* CSR registers */
3255         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3256                 len += sizeof(*data) + IWL_CSR_TO_DUMP;
3257 
3258         /* FH registers */
3259         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3260                 if (trans->trans_cfg->gen2)
3261                         len += sizeof(*data) +
3262                                (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3263                                 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3264                 else
3265                         len += sizeof(*data) +
3266                                (FH_MEM_UPPER_BOUND -
3267                                 FH_MEM_LOWER_BOUND);
3268         }
3269 
3270         if (dump_rbs) {
3271                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3272                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3273                 /* RBs */
3274                 num_rbs =
3275                         le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3276                         & 0x0FFF;
3277                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3278                 len += num_rbs * (sizeof(*data) +
3279                                   sizeof(struct iwl_fw_error_dump_rb) +
3280                                   (PAGE_SIZE << trans_pcie->rx_page_order));
3281         }
3282 
3283         /* Paged memory for gen2 HW */
3284         if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3285                 for (i = 0; i < trans->init_dram.paging_cnt; i++)
3286                         len += sizeof(*data) +
3287                                sizeof(struct iwl_fw_error_dump_paging) +
3288                                trans->init_dram.paging[i].size;
3289 
3290         dump_data = vzalloc(len);
3291         if (!dump_data)
3292                 return NULL;
3293 
3294         len = 0;
3295         data = (void *)dump_data->data;
3296 
3297         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
3298                 u16 tfd_size = trans_pcie->tfd_size;
3299 
3300                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3301                 txcmd = (void *)data->data;
3302                 spin_lock_bh(&cmdq->lock);
3303                 ptr = cmdq->write_ptr;
3304                 for (i = 0; i < cmdq->n_window; i++) {
3305                         u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
3306                         u8 tfdidx;
3307                         u32 caplen, cmdlen;
3308 
3309                         if (trans->trans_cfg->use_tfh)
3310                                 tfdidx = idx;
3311                         else
3312                                 tfdidx = ptr;
3313 
3314                         cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3315                                                            (u8 *)cmdq->tfds +
3316                                                            tfd_size * tfdidx);
3317                         caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3318 
3319                         if (cmdlen) {
3320                                 len += sizeof(*txcmd) + caplen;
3321                                 txcmd->cmdlen = cpu_to_le32(cmdlen);
3322                                 txcmd->caplen = cpu_to_le32(caplen);
3323                                 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3324                                        caplen);
3325                                 txcmd = (void *)((u8 *)txcmd->data + caplen);
3326                         }
3327 
3328                         ptr = iwl_queue_dec_wrap(trans, ptr);
3329                 }
3330                 spin_unlock_bh(&cmdq->lock);
3331 
3332                 data->len = cpu_to_le32(len);
3333                 len += sizeof(*data);
3334                 data = iwl_fw_error_next_data(data);
3335         }
3336 
3337         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3338                 len += iwl_trans_pcie_dump_csr(trans, &data);
3339         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3340                 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3341         if (dump_rbs)
3342                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3343 
3344         /* Paged memory for gen2 HW */
3345         if (trans->trans_cfg->gen2 &&
3346             dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3347                 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3348                         struct iwl_fw_error_dump_paging *paging;
3349                         u32 page_len = trans->init_dram.paging[i].size;
3350 
3351                         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3352                         data->len = cpu_to_le32(sizeof(*paging) + page_len);
3353                         paging = (void *)data->data;
3354                         paging->index = cpu_to_le32(i);
3355                         memcpy(paging->data,
3356                                trans->init_dram.paging[i].block, page_len);
3357                         data = iwl_fw_error_next_data(data);
3358 
3359                         len += sizeof(*data) + sizeof(*paging) + page_len;
3360                 }
3361         }
3362         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3363                 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3364 
3365         dump_data->len = len;
3366 
3367         return dump_data;
3368 }
3369 
3370 #ifdef CONFIG_PM_SLEEP
3371 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3372 {
3373         return 0;
3374 }
3375 
3376 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3377 {
3378 }
3379 #endif /* CONFIG_PM_SLEEP */
3380 
3381 #define IWL_TRANS_COMMON_OPS                                            \
3382         .op_mode_leave = iwl_trans_pcie_op_mode_leave,                  \
3383         .write8 = iwl_trans_pcie_write8,                                \
3384         .write32 = iwl_trans_pcie_write32,                              \
3385         .read32 = iwl_trans_pcie_read32,                                \
3386         .read_prph = iwl_trans_pcie_read_prph,                          \
3387         .write_prph = iwl_trans_pcie_write_prph,                        \
3388         .read_mem = iwl_trans_pcie_read_mem,                            \
3389         .write_mem = iwl_trans_pcie_write_mem,                          \
3390         .configure = iwl_trans_pcie_configure,                          \
3391         .set_pmi = iwl_trans_pcie_set_pmi,                              \
3392         .sw_reset = iwl_trans_pcie_sw_reset,                            \
3393         .grab_nic_access = iwl_trans_pcie_grab_nic_access,              \
3394         .release_nic_access = iwl_trans_pcie_release_nic_access,        \
3395         .set_bits_mask = iwl_trans_pcie_set_bits_mask,                  \
3396         .dump_data = iwl_trans_pcie_dump_data,                          \
3397         .d3_suspend = iwl_trans_pcie_d3_suspend,                        \
3398         .d3_resume = iwl_trans_pcie_d3_resume,                          \
3399         .sync_nmi = iwl_trans_pcie_sync_nmi
3400 
3401 #ifdef CONFIG_PM_SLEEP
3402 #define IWL_TRANS_PM_OPS                                                \
3403         .suspend = iwl_trans_pcie_suspend,                              \
3404         .resume = iwl_trans_pcie_resume,
3405 #else
3406 #define IWL_TRANS_PM_OPS
3407 #endif /* CONFIG_PM_SLEEP */
3408 
3409 static const struct iwl_trans_ops trans_ops_pcie = {
3410         IWL_TRANS_COMMON_OPS,
3411         IWL_TRANS_PM_OPS
3412         .start_hw = iwl_trans_pcie_start_hw,
3413         .fw_alive = iwl_trans_pcie_fw_alive,
3414         .start_fw = iwl_trans_pcie_start_fw,
3415         .stop_device = iwl_trans_pcie_stop_device,
3416 
3417         .send_cmd = iwl_trans_pcie_send_hcmd,
3418 
3419         .tx = iwl_trans_pcie_tx,
3420         .reclaim = iwl_trans_pcie_reclaim,
3421 
3422         .txq_disable = iwl_trans_pcie_txq_disable,
3423         .txq_enable = iwl_trans_pcie_txq_enable,
3424 
3425         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3426 
3427         .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3428 
3429         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3430         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3431 #ifdef CONFIG_IWLWIFI_DEBUGFS
3432         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3433 #endif
3434 };
3435 
3436 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3437         IWL_TRANS_COMMON_OPS,
3438         IWL_TRANS_PM_OPS
3439         .start_hw = iwl_trans_pcie_start_hw,
3440         .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3441         .start_fw = iwl_trans_pcie_gen2_start_fw,
3442         .stop_device = iwl_trans_pcie_gen2_stop_device,
3443 
3444         .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
3445 
3446         .tx = iwl_trans_pcie_gen2_tx,
3447         .reclaim = iwl_trans_pcie_reclaim,
3448 
3449         .set_q_ptrs = iwl_trans_pcie_set_q_ptrs,
3450 
3451         .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3452         .txq_free = iwl_trans_pcie_dyn_txq_free,
3453         .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3454         .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3455 #ifdef CONFIG_IWLWIFI_DEBUGFS
3456         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3457 #endif
3458 };
3459 
3460 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3461                                const struct pci_device_id *ent,
3462                                const struct iwl_cfg_trans_params *cfg_trans)
3463 {
3464         struct iwl_trans_pcie *trans_pcie;
3465         struct iwl_trans *trans;
3466         int ret, addr_size, txcmd_size, txcmd_align;
3467         const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3468 
3469         if (!cfg_trans->gen2) {
3470                 ops = &trans_ops_pcie;
3471                 txcmd_size = sizeof(struct iwl_tx_cmd);
3472                 txcmd_align = sizeof(void *);
3473         } else if (cfg_trans->device_family < IWL_DEVICE_FAMILY_AX210) {
3474                 txcmd_size = sizeof(struct iwl_tx_cmd_gen2);
3475                 txcmd_align = 64;
3476         } else {
3477                 txcmd_size = sizeof(struct iwl_tx_cmd_gen3);
3478                 txcmd_align = 128;
3479         }
3480 
3481         txcmd_size += sizeof(struct iwl_cmd_header);
3482         txcmd_size += 36; /* biggest possible 802.11 header */
3483 
3484         /* Ensure device TX cmd cannot reach/cross a page boundary in gen2 */
3485         if (WARN_ON(cfg_trans->gen2 && txcmd_size >= txcmd_align))
3486                 return ERR_PTR(-EINVAL);
3487 
3488         ret = pcim_enable_device(pdev);
3489         if (ret)
3490                 return ERR_PTR(ret);
3491 
3492         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
3493                                 txcmd_size, txcmd_align);
3494         if (!trans)
3495                 return ERR_PTR(-ENOMEM);
3496 
3497         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3498 
3499         trans_pcie->trans = trans;
3500         trans_pcie->opmode_down = true;
3501         spin_lock_init(&trans_pcie->irq_lock);
3502         spin_lock_init(&trans_pcie->reg_lock);
3503         mutex_init(&trans_pcie->mutex);
3504         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3505 
3506         trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3507                                                    WQ_HIGHPRI | WQ_UNBOUND, 1);
3508         if (!trans_pcie->rba.alloc_wq) {
3509                 ret = -ENOMEM;
3510                 goto out_free_trans;
3511         }
3512         INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3513 
3514         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3515         if (!trans_pcie->tso_hdr_page) {
3516                 ret = -ENOMEM;
3517                 goto out_no_pci;
3518         }
3519         trans_pcie->debug_rfkill = -1;
3520 
3521         if (!cfg_trans->base_params->pcie_l1_allowed) {
3522                 /*
3523                  * W/A - seems to solve weird behavior. We need to remove this
3524                  * if we don't want to stay in L1 all the time. This wastes a
3525                  * lot of power.
3526                  */
3527                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3528                                        PCIE_LINK_STATE_L1 |
3529                                        PCIE_LINK_STATE_CLKPM);
3530         }
3531 
3532         trans_pcie->def_rx_queue = 0;
3533 
3534         if (cfg_trans->use_tfh) {
3535                 addr_size = 64;
3536                 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
3537                 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
3538         } else {
3539                 addr_size = 36;
3540                 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
3541                 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3542         }
3543         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3544 
3545         pci_set_master(pdev);
3546 
3547         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
3548         if (!ret)
3549                 ret = pci_set_consistent_dma_mask(pdev,
3550                                                   DMA_BIT_MASK(addr_size));
3551         if (ret) {
3552                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3553                 if (!ret)
3554                         ret = pci_set_consistent_dma_mask(pdev,
3555                                                           DMA_BIT_MASK(32));
3556                 /* both attempts failed: */
3557                 if (ret) {
3558                         dev_err(&pdev->dev, "No suitable DMA available\n");
3559                         goto out_no_pci;
3560                 }
3561         }
3562 
3563         ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3564         if (ret) {
3565                 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3566                 goto out_no_pci;
3567         }
3568 
3569         trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
3570         if (!trans_pcie->hw_base) {
3571                 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3572                 ret = -ENODEV;
3573                 goto out_no_pci;
3574         }
3575 
3576         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3577          * PCI Tx retries from interfering with C3 CPU state */
3578         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3579 
3580         trans_pcie->pci_dev = pdev;
3581         iwl_disable_interrupts(trans);
3582 
3583         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3584         if (trans->hw_rev == 0xffffffff) {
3585                 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3586                 ret = -EIO;
3587                 goto out_no_pci;
3588         }
3589 
3590         /*
3591          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3592          * changed, and now the revision step also includes bit 0-1 (no more
3593          * "dash" value). To keep hw_rev backwards compatible - we'll store it
3594          * in the old format.
3595          */
3596         if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) {
3597                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3598                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3599 
3600                 ret = iwl_pcie_prepare_card_hw(trans);
3601                 if (ret) {
3602                         IWL_WARN(trans, "Exit HW not ready\n");
3603                         goto out_no_pci;
3604                 }
3605 
3606                 /*
3607                  * in-order to recognize C step driver should read chip version
3608                  * id located at the AUX bus MISC address space.
3609                  */
3610                 ret = iwl_finish_nic_init(trans, cfg_trans);
3611                 if (ret)
3612                         goto out_no_pci;
3613 
3614         }
3615 
3616         IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3617 
3618         iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
3619         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3620         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3621                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3622 
3623         /* Initialize the wait queue for commands */
3624         init_waitqueue_head(&trans_pcie->wait_command_queue);
3625 
3626         init_waitqueue_head(&trans_pcie->sx_waitq);
3627 
3628         if (trans_pcie->msix_enabled) {
3629                 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3630                 if (ret)
3631                         goto out_no_pci;
3632          } else {
3633                 ret = iwl_pcie_alloc_ict(trans);
3634                 if (ret)
3635                         goto out_no_pci;
3636 
3637                 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3638                                                 iwl_pcie_isr,
3639                                                 iwl_pcie_irq_handler,
3640                                                 IRQF_SHARED, DRV_NAME, trans);
3641                 if (ret) {
3642                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3643                         goto out_free_ict;
3644                 }
3645                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3646          }
3647 
3648 #ifdef CONFIG_IWLWIFI_DEBUGFS
3649         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3650         mutex_init(&trans_pcie->fw_mon_data.mutex);
3651 #endif
3652 
3653         return trans;
3654 
3655 out_free_ict:
3656         iwl_pcie_free_ict(trans);
3657 out_no_pci:
3658         free_percpu(trans_pcie->tso_hdr_page);
3659         destroy_workqueue(trans_pcie->rba.alloc_wq);
3660 out_free_trans:
3661         iwl_trans_free(trans);
3662         return ERR_PTR(ret);
3663 }
3664 
3665 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
3666 {
3667         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3668         unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
3669         bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
3670         u32 inta_addr, sw_err_bit;
3671 
3672         if (trans_pcie->msix_enabled) {
3673                 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3674                 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3675         } else {
3676                 inta_addr = CSR_INT;
3677                 sw_err_bit = CSR_INT_BIT_SW_ERR;
3678         }
3679 
3680         /* if the interrupts were already disabled, there is no point in
3681          * calling iwl_disable_interrupts
3682          */
3683         if (interrupts_enabled)
3684                 iwl_disable_interrupts(trans);
3685 
3686         iwl_force_nmi(trans);
3687         while (time_after(timeout, jiffies)) {
3688                 u32 inta_hw = iwl_read32(trans, inta_addr);
3689 
3690                 /* Error detected by uCode */
3691                 if (inta_hw & sw_err_bit) {
3692                         /* Clear causes register */
3693                         iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
3694                         break;
3695                 }
3696 
3697                 mdelay(1);
3698         }
3699 
3700         /* enable interrupts only if there were already enabled before this
3701          * function to avoid a case were the driver enable interrupts before
3702          * proper configurations were made
3703          */
3704         if (interrupts_enabled)
3705                 iwl_enable_interrupts(trans);
3706 
3707         iwl_trans_fw_error(trans);
3708 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/wireless/intel/iwlwifi/pcie/trans.c

DEFINITIONS
