1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2018 - 2019 Intel Corporation
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called COPYING.
22 *
23 * Contact Information:
24 * Intel Linux Wireless <linuxwifi@intel.com>
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *
27 * BSD LICENSE
28 *
29 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
30 * Copyright(c) 2018 - 2019 Intel Corporation
31 * All rights reserved.
32 *
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
35 * are met:
36 *
37 * * Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * * Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in
41 * the documentation and/or other materials provided with the
42 * distribution.
43 * * Neither the name Intel Corporation nor the names of its
44 * contributors may be used to endorse or promote products derived
45 * from this software without specific prior written permission.
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
48 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
49 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
50 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
51 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
53 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
57 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58 *****************************************************************************/
59 #include <linux/types.h>
60 #include <linux/slab.h>
61 #include <linux/export.h>
62
63 #include "iwl-drv.h"
64 #include "iwl-debug.h"
65 #include "iwl-eeprom-read.h"
66 #include "iwl-io.h"
67 #include "iwl-prph.h"
68 #include "iwl-csr.h"
69
70 /*
71 * EEPROM access time values:
72 *
73 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
74 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
75 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
76 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
77 */
78 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
79
80 #define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
81 #define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
82
83
84 /*
85 * The device's EEPROM semaphore prevents conflicts between driver and uCode
86 * when accessing the EEPROM; each access is a series of pulses to/from the
87 * EEPROM chip, not a single event, so even reads could conflict if they
88 * weren't arbitrated by the semaphore.
89 */
90
91 #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
92 #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
93
94 static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
95 {
96 u16 count;
97 int ret;
98
99 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
100 /* Request semaphore */
101 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
102 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
103
104 /* See if we got it */
105 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
106 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
107 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
108 EEPROM_SEM_TIMEOUT);
109 if (ret >= 0) {
110 IWL_DEBUG_EEPROM(trans->dev,
111 "Acquired semaphore after %d tries.\n",
112 count+1);
113 return ret;
114 }
115 }
116
117 return ret;
118 }
119
120 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
121 {
122 iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
123 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
124 }
125
126 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
127 {
128 u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
129
130 IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp);
131
132 switch (gp) {
133 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
134 if (!nvm_is_otp) {
135 IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n",
136 gp);
137 return -ENOENT;
138 }
139 return 0;
140 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
141 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
142 if (nvm_is_otp) {
143 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);
144 return -ENOENT;
145 }
146 return 0;
147 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
148 default:
149 IWL_ERR(trans,
150 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n",
151 nvm_is_otp ? "OTP" : "EEPROM", gp);
152 return -ENOENT;
153 }
154 }
155
156 /******************************************************************************
157 *
158 * OTP related functions
159 *
160 ******************************************************************************/
161
162 static void iwl_set_otp_access_absolute(struct iwl_trans *trans)
163 {
164 iwl_read32(trans, CSR_OTP_GP_REG);
165
166 iwl_clear_bit(trans, CSR_OTP_GP_REG,
167 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
168 }
169
170 static int iwl_nvm_is_otp(struct iwl_trans *trans)
171 {
172 u32 otpgp;
173
174 /* OTP only valid for CP/PP and after */
175 switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) {
176 case CSR_HW_REV_TYPE_NONE:
177 IWL_ERR(trans, "Unknown hardware type\n");
178 return -EIO;
179 case CSR_HW_REV_TYPE_5300:
180 case CSR_HW_REV_TYPE_5350:
181 case CSR_HW_REV_TYPE_5100:
182 case CSR_HW_REV_TYPE_5150:
183 return 0;
184 default:
185 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
186 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
187 return 1;
188 return 0;
189 }
190 }
191
192 static int iwl_init_otp_access(struct iwl_trans *trans)
193 {
194 int ret;
195
196 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
197 if (ret)
198 return ret;
199
200 iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
201 APMG_PS_CTRL_VAL_RESET_REQ);
202 udelay(5);
203 iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
204 APMG_PS_CTRL_VAL_RESET_REQ);
205
206 /*
207 * CSR auto clock gate disable bit -
208 * this is only applicable for HW with OTP shadow RAM
209 */
210 if (trans->trans_cfg->base_params->shadow_ram_support)
211 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
212 CSR_RESET_LINK_PWR_MGMT_DISABLED);
213
214 return 0;
215 }
216
217 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
218 __le16 *eeprom_data)
219 {
220 int ret = 0;
221 u32 r;
222 u32 otpgp;
223
224 iwl_write32(trans, CSR_EEPROM_REG,
225 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
226 ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
227 CSR_EEPROM_REG_READ_VALID_MSK,
228 CSR_EEPROM_REG_READ_VALID_MSK,
229 IWL_EEPROM_ACCESS_TIMEOUT);
230 if (ret < 0) {
231 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
232 return ret;
233 }
234 r = iwl_read32(trans, CSR_EEPROM_REG);
235 /* check for ECC errors: */
236 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
237 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
238 /* stop in this case */
239 /* set the uncorrectable OTP ECC bit for acknowledgment */
240 iwl_set_bit(trans, CSR_OTP_GP_REG,
241 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
242 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
243 return -EINVAL;
244 }
245 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
246 /* continue in this case */
247 /* set the correctable OTP ECC bit for acknowledgment */
248 iwl_set_bit(trans, CSR_OTP_GP_REG,
249 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
250 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
251 }
252 *eeprom_data = cpu_to_le16(r >> 16);
253 return 0;
254 }
255
256 /*
257 * iwl_is_otp_empty: check for empty OTP
258 */
259 static bool iwl_is_otp_empty(struct iwl_trans *trans)
260 {
261 u16 next_link_addr = 0;
262 __le16 link_value;
263 bool is_empty = false;
264
265 /* locate the beginning of OTP link list */
266 if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) {
267 if (!link_value) {
268 IWL_ERR(trans, "OTP is empty\n");
269 is_empty = true;
270 }
271 } else {
272 IWL_ERR(trans, "Unable to read first block of OTP list.\n");
273 is_empty = true;
274 }
275
276 return is_empty;
277 }
278
279
280 /*
281 * iwl_find_otp_image: find EEPROM image in OTP
282 * finding the OTP block that contains the EEPROM image.
283 * the last valid block on the link list (the block _before_ the last block)
284 * is the block we should read and used to configure the device.
285 * If all the available OTP blocks are full, the last block will be the block
286 * we should read and used to configure the device.
287 * only perform this operation if shadow RAM is disabled
288 */
289 static int iwl_find_otp_image(struct iwl_trans *trans,
290 u16 *validblockaddr)
291 {
292 u16 next_link_addr = 0, valid_addr;
293 __le16 link_value = 0;
294 int usedblocks = 0;
295
296 /* set addressing mode to absolute to traverse the link list */
297 iwl_set_otp_access_absolute(trans);
298
299 /* checking for empty OTP or error */
300 if (iwl_is_otp_empty(trans))
301 return -EINVAL;
302
303 /*
304 * start traverse link list
305 * until reach the max number of OTP blocks
306 * different devices have different number of OTP blocks
307 */
308 do {
309 /* save current valid block address
310 * check for more block on the link list
311 */
312 valid_addr = next_link_addr;
313 next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
314 IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n",
315 usedblocks, next_link_addr);
316 if (iwl_read_otp_word(trans, next_link_addr, &link_value))
317 return -EINVAL;
318 if (!link_value) {
319 /*
320 * reach the end of link list, return success and
321 * set address point to the starting address
322 * of the image
323 */
324 *validblockaddr = valid_addr;
325 /* skip first 2 bytes (link list pointer) */
326 *validblockaddr += 2;
327 return 0;
328 }
329 /* more in the link list, continue */
330 usedblocks++;
331 } while (usedblocks <= trans->trans_cfg->base_params->max_ll_items);
332
333 /* OTP has no valid blocks */
334 IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n");
335 return -EINVAL;
336 }
337
338 /**
339 * iwl_read_eeprom - read EEPROM contents
340 *
341 * Load the EEPROM contents from adapter and return it
342 * and its size.
343 *
344 * NOTE: This routine uses the non-debug IO access functions.
345 */
346 int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
347 {
348 __le16 *e;
349 u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
350 int sz;
351 int ret;
352 u16 addr;
353 u16 validblockaddr = 0;
354 u16 cache_addr = 0;
355 int nvm_is_otp;
356
357 if (!eeprom || !eeprom_size)
358 return -EINVAL;
359
360 nvm_is_otp = iwl_nvm_is_otp(trans);
361 if (nvm_is_otp < 0)
362 return nvm_is_otp;
363
364 sz = trans->trans_cfg->base_params->eeprom_size;
365 IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz);
366
367 e = kmalloc(sz, GFP_KERNEL);
368 if (!e)
369 return -ENOMEM;
370
371 ret = iwl_eeprom_verify_signature(trans, nvm_is_otp);
372 if (ret < 0) {
373 IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
374 goto err_free;
375 }
376
377 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
378 ret = iwl_eeprom_acquire_semaphore(trans);
379 if (ret < 0) {
380 IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n");
381 goto err_free;
382 }
383
384 if (nvm_is_otp) {
385 ret = iwl_init_otp_access(trans);
386 if (ret) {
387 IWL_ERR(trans, "Failed to initialize OTP access.\n");
388 goto err_unlock;
389 }
390
391 iwl_write32(trans, CSR_EEPROM_GP,
392 iwl_read32(trans, CSR_EEPROM_GP) &
393 ~CSR_EEPROM_GP_IF_OWNER_MSK);
394
395 iwl_set_bit(trans, CSR_OTP_GP_REG,
396 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
397 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
398 /* traversing the linked list if no shadow ram supported */
399 if (!trans->trans_cfg->base_params->shadow_ram_support) {
400 ret = iwl_find_otp_image(trans, &validblockaddr);
401 if (ret)
402 goto err_unlock;
403 }
404 for (addr = validblockaddr; addr < validblockaddr + sz;
405 addr += sizeof(u16)) {
406 __le16 eeprom_data;
407
408 ret = iwl_read_otp_word(trans, addr, &eeprom_data);
409 if (ret)
410 goto err_unlock;
411 e[cache_addr / 2] = eeprom_data;
412 cache_addr += sizeof(u16);
413 }
414 } else {
415 /* eeprom is an array of 16bit values */
416 for (addr = 0; addr < sz; addr += sizeof(u16)) {
417 u32 r;
418
419 iwl_write32(trans, CSR_EEPROM_REG,
420 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
421
422 ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
423 CSR_EEPROM_REG_READ_VALID_MSK,
424 CSR_EEPROM_REG_READ_VALID_MSK,
425 IWL_EEPROM_ACCESS_TIMEOUT);
426 if (ret < 0) {
427 IWL_ERR(trans,
428 "Time out reading EEPROM[%d]\n", addr);
429 goto err_unlock;
430 }
431 r = iwl_read32(trans, CSR_EEPROM_REG);
432 e[addr / 2] = cpu_to_le16(r >> 16);
433 }
434 }
435
436 IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n",
437 nvm_is_otp ? "OTP" : "EEPROM");
438
439 iwl_eeprom_release_semaphore(trans);
440
441 *eeprom_size = sz;
442 *eeprom = (u8 *)e;
443 return 0;
444
445 err_unlock:
446 iwl_eeprom_release_semaphore(trans);
447 err_free:
448 kfree(e);
449
450 return ret;
451 }
452 IWL_EXPORT_SYMBOL(iwl_read_eeprom);