1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright (C) 2018 - 2019 Intel Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright (C) 2018 - 2019 Intel Corporation
35 * All rights reserved.
36 *
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45 * the documentation and/or other materials provided with the
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50 *
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63 *****************************************************************************/
64 #ifndef __iwl_fw_api_debug_h__
65 #define __iwl_fw_api_debug_h__
66
67 /**
68 * enum iwl_debug_cmds - debug commands
69 */
70 enum iwl_debug_cmds {
71 /**
72 * @LMAC_RD_WR:
73 * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
74 * &struct iwl_dbg_mem_access_rsp
75 */
76 LMAC_RD_WR = 0x0,
77 /**
78 * @UMAC_RD_WR:
79 * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
80 * &struct iwl_dbg_mem_access_rsp
81 */
82 UMAC_RD_WR = 0x1,
83 /**
84 * @DBGC_SUSPEND_RESUME:
85 * DBGC suspend/resume commad. Uses a single dword as data:
86 * 0 - resume DBGC recording
87 * 1 - suspend DBGC recording
88 */
89 DBGC_SUSPEND_RESUME = 0x7,
90 /**
91 * @BUFFER_ALLOCATION:
92 * passes DRAM buffers to a DBGC
93 * &struct iwl_buf_alloc_cmd
94 */
95 BUFFER_ALLOCATION = 0x8,
96 /**
97 * @MFU_ASSERT_DUMP_NTF:
98 * &struct iwl_mfu_assert_dump_notif
99 */
100 MFU_ASSERT_DUMP_NTF = 0xFE,
101 };
102
103 /* Error response/notification */
104 enum {
105 FW_ERR_UNKNOWN_CMD = 0x0,
106 FW_ERR_INVALID_CMD_PARAM = 0x1,
107 FW_ERR_SERVICE = 0x2,
108 FW_ERR_ARC_MEMORY = 0x3,
109 FW_ERR_ARC_CODE = 0x4,
110 FW_ERR_WATCH_DOG = 0x5,
111 FW_ERR_WEP_GRP_KEY_INDX = 0x10,
112 FW_ERR_WEP_KEY_SIZE = 0x11,
113 FW_ERR_OBSOLETE_FUNC = 0x12,
114 FW_ERR_UNEXPECTED = 0xFE,
115 FW_ERR_FATAL = 0xFF
116 };
117
118 /** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations
119 * dbgc suspend resume command operations
120 * @DBGC_RESUME_CMD: resume dbgc recording
121 * @DBGC_SUSPEND_CMD: stop dbgc recording
122 */
123 enum iwl_dbg_suspend_resume_cmds {
124 DBGC_RESUME_CMD,
125 DBGC_SUSPEND_CMD,
126 };
127
128 /**
129 * struct iwl_error_resp - FW error indication
130 * ( REPLY_ERROR = 0x2 )
131 * @error_type: one of FW_ERR_*
132 * @cmd_id: the command ID for which the error occurred
133 * @reserved1: reserved
134 * @bad_cmd_seq_num: sequence number of the erroneous command
135 * @error_service: which service created the error, applicable only if
136 * error_type = 2, otherwise 0
137 * @timestamp: TSF in usecs.
138 */
139 struct iwl_error_resp {
140 __le32 error_type;
141 u8 cmd_id;
142 u8 reserved1;
143 __le16 bad_cmd_seq_num;
144 __le32 error_service;
145 __le64 timestamp;
146 } __packed;
147
148 #define TX_FIFO_MAX_NUM_9000 8
149 #define TX_FIFO_MAX_NUM 15
150 #define RX_FIFO_MAX_NUM 2
151 #define TX_FIFO_INTERNAL_MAX_NUM 6
152
153 /**
154 * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information
155 *
156 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not
157 * accessible)
158 * @shared_mem_size: shared memory size
159 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to
160 * 0x0 as accessible only via DBGM RDAT)
161 * @sample_buff_size: internal sample buff size
162 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre
163 * 8000 HW set to 0x0 as not accessible)
164 * @txfifo_size: size of TXF0 ... TXF7
165 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0
166 * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
167 * when paging is not supported this should be 0
168 * @page_buff_size: size of %page_buff_addr
169 * @rxfifo_addr: Start address of rxFifo
170 * @internal_txfifo_addr: start address of internalFifo
171 * @internal_txfifo_size: internal fifos' size
172 *
173 * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
174 * set, the last 3 members don't exist.
175 */
176 struct iwl_shared_mem_cfg_v2 {
177 __le32 shared_mem_addr;
178 __le32 shared_mem_size;
179 __le32 sample_buff_addr;
180 __le32 sample_buff_size;
181 __le32 txfifo_addr;
182 __le32 txfifo_size[TX_FIFO_MAX_NUM_9000];
183 __le32 rxfifo_size[RX_FIFO_MAX_NUM];
184 __le32 page_buff_addr;
185 __le32 page_buff_size;
186 __le32 rxfifo_addr;
187 __le32 internal_txfifo_addr;
188 __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM];
189 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */
190
191 /**
192 * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration
193 *
194 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB)
195 * @txfifo_size: size of TX FIFOs
196 * @rxfifo1_addr: RXF1 addr
197 * @rxfifo1_size: RXF1 size
198 */
199 struct iwl_shared_mem_lmac_cfg {
200 __le32 txfifo_addr;
201 __le32 txfifo_size[TX_FIFO_MAX_NUM];
202 __le32 rxfifo1_addr;
203 __le32 rxfifo1_size;
204
205 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */
206
207 /**
208 * struct iwl_shared_mem_cfg - Shared memory configuration information
209 *
210 * @shared_mem_addr: shared memory address
211 * @shared_mem_size: shared memory size
212 * @sample_buff_addr: internal sample (mon/adc) buff addr
213 * @sample_buff_size: internal sample buff size
214 * @rxfifo2_addr: start addr of RXF2
215 * @rxfifo2_size: size of RXF2
216 * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
217 * when paging is not supported this should be 0
218 * @page_buff_size: size of %page_buff_addr
219 * @lmac_num: number of LMACs (1 or 2)
220 * @lmac_smem: per - LMAC smem data
221 */
222 struct iwl_shared_mem_cfg {
223 __le32 shared_mem_addr;
224 __le32 shared_mem_size;
225 __le32 sample_buff_addr;
226 __le32 sample_buff_size;
227 __le32 rxfifo2_addr;
228 __le32 rxfifo2_size;
229 __le32 page_buff_addr;
230 __le32 page_buff_size;
231 __le32 lmac_num;
232 struct iwl_shared_mem_lmac_cfg lmac_smem[2];
233 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_3 */
234
235 /**
236 * struct iwl_mfuart_load_notif - mfuart image version & status
237 * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
238 * @installed_ver: installed image version
239 * @external_ver: external image version
240 * @status: MFUART loading status
241 * @duration: MFUART loading time
242 * @image_size: MFUART image size in bytes
243 */
244 struct iwl_mfuart_load_notif {
245 __le32 installed_ver;
246 __le32 external_ver;
247 __le32 status;
248 __le32 duration;
249 /* image size valid only in v2 of the command */
250 __le32 image_size;
251 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */
252
253 /**
254 * struct iwl_mfu_assert_dump_notif - mfuart dump logs
255 * ( MFU_ASSERT_DUMP_NTF = 0xfe )
256 * @assert_id: mfuart assert id that cause the notif
257 * @curr_reset_num: number of asserts since uptime
258 * @index_num: current chunk id
259 * @parts_num: total number of chunks
260 * @data_size: number of data bytes sent
261 * @data: data buffer
262 */
263 struct iwl_mfu_assert_dump_notif {
264 __le32 assert_id;
265 __le32 curr_reset_num;
266 __le16 index_num;
267 __le16 parts_num;
268 __le32 data_size;
269 __le32 data[0];
270 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */
271
272 /**
273 * enum iwl_mvm_marker_id - marker ids
274 *
275 * The ids for different type of markers to insert into the usniffer logs
276 *
277 * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker
278 * @MARKER_ID_SYNC_CLOCK: sync FW time and systime
279 */
280 enum iwl_mvm_marker_id {
281 MARKER_ID_TX_FRAME_LATENCY = 1,
282 MARKER_ID_SYNC_CLOCK = 2,
283 }; /* MARKER_ID_API_E_VER_2 */
284
285 /**
286 * struct iwl_mvm_marker - mark info into the usniffer logs
287 *
288 * (MARKER_CMD = 0xcb)
289 *
290 * Mark the UTC time stamp into the usniffer logs together with additional
291 * metadata, so the usniffer output can be parsed.
292 * In the command response the ucode will return the GP2 time.
293 *
294 * @dw_len: The amount of dwords following this byte including this byte.
295 * @marker_id: A unique marker id (iwl_mvm_marker_id).
296 * @reserved: reserved.
297 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC
298 * @metadata: additional meta data that will be written to the unsiffer log
299 */
300 struct iwl_mvm_marker {
301 u8 dw_len;
302 u8 marker_id;
303 __le16 reserved;
304 __le64 timestamp;
305 __le32 metadata[0];
306 } __packed; /* MARKER_API_S_VER_1 */
307
308 /**
309 * struct iwl_mvm_marker_rsp - Response to marker cmd
310 *
311 * @gp2: The gp2 clock value in the FW
312 */
313 struct iwl_mvm_marker_rsp {
314 __le32 gp2;
315 } __packed;
316
317 /* Operation types for the debug mem access */
318 enum {
319 DEBUG_MEM_OP_READ = 0,
320 DEBUG_MEM_OP_WRITE = 1,
321 DEBUG_MEM_OP_WRITE_BYTES = 2,
322 };
323
324 #define DEBUG_MEM_MAX_SIZE_DWORDS 32
325
326 /**
327 * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory
328 * @op: DEBUG_MEM_OP_*
329 * @addr: address to read/write from/to
330 * @len: in dwords, to read/write
331 * @data: for write opeations, contains the source buffer
332 */
333 struct iwl_dbg_mem_access_cmd {
334 __le32 op;
335 __le32 addr;
336 __le32 len;
337 __le32 data[];
338 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */
339
340 /* Status responses for the debug mem access */
341 enum {
342 DEBUG_MEM_STATUS_SUCCESS = 0x0,
343 DEBUG_MEM_STATUS_FAILED = 0x1,
344 DEBUG_MEM_STATUS_LOCKED = 0x2,
345 DEBUG_MEM_STATUS_HIDDEN = 0x3,
346 DEBUG_MEM_STATUS_LENGTH = 0x4,
347 };
348
349 /**
350 * struct iwl_dbg_mem_access_rsp - Response to debug mem commands
351 * @status: DEBUG_MEM_STATUS_*
352 * @len: read dwords (0 for write operations)
353 * @data: contains the read DWs
354 */
355 struct iwl_dbg_mem_access_rsp {
356 __le32 status;
357 __le32 len;
358 __le32 data[];
359 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */
360
361 /**
362 * struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command
363 * @operation: suspend or resume operation, uses
364 * &enum iwl_dbg_suspend_resume_cmds
365 */
366 struct iwl_dbg_suspend_resume_cmd {
367 __le32 operation;
368 } __packed;
369
370 #define BUF_ALLOC_MAX_NUM_FRAGS 16
371
372 /**
373 * struct iwl_buf_alloc_frag - a DBGC fragment
374 * @addr: base address of the fragment
375 * @size: size of the fragment
376 */
377 struct iwl_buf_alloc_frag {
378 __le64 addr;
379 __le32 size;
380 } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */
381
382 /**
383 * struct iwl_buf_alloc_cmd - buffer allocation command
384 * @alloc_id: &enum iwl_fw_ini_allocation_id
385 * @buf_location: &enum iwl_fw_ini_buffer_location
386 * @num_frags: number of fragments
387 * @frags: fragments array
388 */
389 struct iwl_buf_alloc_cmd {
390 __le32 alloc_id;
391 __le32 buf_location;
392 __le32 num_frags;
393 struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS];
394 } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */
395
396 #endif /* __iwl_fw_api_debug_h__ */