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64 #ifndef __iwl_fw_api_txq_h__
65 #define __iwl_fw_api_txq_h__
66
67 /*
68 * DQA queue numbers
69 *
70 * @IWL_MVM_DQA_CMD_QUEUE: a queue reserved for sending HCMDs to the FW
71 * @IWL_MVM_DQA_AUX_QUEUE: a queue reserved for aux frames
72 * @IWL_MVM_DQA_P2P_DEVICE_QUEUE: a queue reserved for P2P device frames
73 * @IWL_MVM_DQA_INJECT_MONITOR_QUEUE: a queue reserved for injection using
74 * monitor mode. Note this queue is the same as the queue for P2P device
75 * but we can't have active monitor mode along with P2P device anyway.
76 * @IWL_MVM_DQA_GCAST_QUEUE: a queue reserved for P2P GO/SoftAP GCAST frames
77 * @IWL_MVM_DQA_BSS_CLIENT_QUEUE: a queue reserved for BSS activity, to ensure
78 * that we are never left without the possibility to connect to an AP.
79 * @IWL_MVM_DQA_MIN_MGMT_QUEUE: first TXQ in pool for MGMT and non-QOS frames.
80 * Each MGMT queue is mapped to a single STA
81 * MGMT frames are frames that return true on ieee80211_is_mgmt()
82 * @IWL_MVM_DQA_MAX_MGMT_QUEUE: last TXQ in pool for MGMT frames
83 * @IWL_MVM_DQA_AP_PROBE_RESP_QUEUE: a queue reserved for P2P GO/SoftAP probe
84 * responses
85 * @IWL_MVM_DQA_MIN_DATA_QUEUE: first TXQ in pool for DATA frames.
86 * DATA frames are intended for !ieee80211_is_mgmt() frames, but if
87 * the MGMT TXQ pool is exhausted, mgmt frames can be sent on DATA queues
88 * as well
89 * @IWL_MVM_DQA_MAX_DATA_QUEUE: last TXQ in pool for DATA frames
90 */
91 enum iwl_mvm_dqa_txq {
92 IWL_MVM_DQA_CMD_QUEUE = 0,
93 IWL_MVM_DQA_AUX_QUEUE = 1,
94 IWL_MVM_DQA_P2P_DEVICE_QUEUE = 2,
95 IWL_MVM_DQA_INJECT_MONITOR_QUEUE = 2,
96 IWL_MVM_DQA_GCAST_QUEUE = 3,
97 IWL_MVM_DQA_BSS_CLIENT_QUEUE = 4,
98 IWL_MVM_DQA_MIN_MGMT_QUEUE = 5,
99 IWL_MVM_DQA_MAX_MGMT_QUEUE = 8,
100 IWL_MVM_DQA_AP_PROBE_RESP_QUEUE = 9,
101 IWL_MVM_DQA_MIN_DATA_QUEUE = 10,
102 IWL_MVM_DQA_MAX_DATA_QUEUE = 30,
103 };
104
105 enum iwl_mvm_tx_fifo {
106 IWL_MVM_TX_FIFO_BK = 0,
107 IWL_MVM_TX_FIFO_BE,
108 IWL_MVM_TX_FIFO_VI,
109 IWL_MVM_TX_FIFO_VO,
110 IWL_MVM_TX_FIFO_MCAST = 5,
111 IWL_MVM_TX_FIFO_CMD = 7,
112 };
113
114 enum iwl_gen2_tx_fifo {
115 IWL_GEN2_TX_FIFO_CMD = 0,
116 IWL_GEN2_EDCA_TX_FIFO_BK,
117 IWL_GEN2_EDCA_TX_FIFO_BE,
118 IWL_GEN2_EDCA_TX_FIFO_VI,
119 IWL_GEN2_EDCA_TX_FIFO_VO,
120 IWL_GEN2_TRIG_TX_FIFO_BK,
121 IWL_GEN2_TRIG_TX_FIFO_BE,
122 IWL_GEN2_TRIG_TX_FIFO_VI,
123 IWL_GEN2_TRIG_TX_FIFO_VO,
124 };
125
126 /**
127 * enum iwl_tx_queue_cfg_actions - TXQ config options
128 * @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue
129 * @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format
130 */
131 enum iwl_tx_queue_cfg_actions {
132 TX_QUEUE_CFG_ENABLE_QUEUE = BIT(0),
133 TX_QUEUE_CFG_TFD_SHORT_FORMAT = BIT(1),
134 };
135
136 #define IWL_DEFAULT_QUEUE_SIZE 256
137 #define IWL_MGMT_QUEUE_SIZE 16
138 #define IWL_CMD_QUEUE_SIZE 32
139 /**
140 * struct iwl_tx_queue_cfg_cmd - txq hw scheduler config command
141 * @sta_id: station id
142 * @tid: tid of the queue
143 * @flags: see &enum iwl_tx_queue_cfg_actions
144 * @cb_size: size of TFD cyclic buffer. Value is exponent - 3.
145 * Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs)
146 * @byte_cnt_addr: address of byte count table
147 * @tfdq_addr: address of TFD circular buffer
148 */
149 struct iwl_tx_queue_cfg_cmd {
150 u8 sta_id;
151 u8 tid;
152 __le16 flags;
153 __le32 cb_size;
154 __le64 byte_cnt_addr;
155 __le64 tfdq_addr;
156 } __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */
157
158 /**
159 * struct iwl_tx_queue_cfg_rsp - response to txq hw scheduler config
160 * @queue_number: queue number assigned to this RA -TID
161 * @flags: set on failure
162 * @write_pointer: initial value for write pointer
163 * @reserved: reserved
164 */
165 struct iwl_tx_queue_cfg_rsp {
166 __le16 queue_number;
167 __le16 flags;
168 __le16 write_pointer;
169 __le16 reserved;
170 } __packed; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */
171
172 #endif /* __iwl_fw_api_txq_h__ */