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12 #ifndef _IPW2100_H
13 #define _IPW2100_H
14
15 #include <linux/sched.h>
16 #include <linux/interrupt.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/list.h>
20 #include <linux/delay.h>
21 #include <linux/skbuff.h>
22 #include <asm/io.h>
23 #include <linux/socket.h>
24 #include <linux/if_arp.h>
25 #include <linux/wireless.h>
26 #include <net/iw_handler.h>
27
28 #ifdef CONFIG_IPW2100_MONITOR
29 #include <net/ieee80211_radiotap.h>
30 #endif
31
32 #include <linux/workqueue.h>
33 #include <linux/mutex.h>
34
35 #include "libipw.h"
36
37 struct ipw2100_priv;
38 struct ipw2100_tx_packet;
39 struct ipw2100_rx_packet;
40
41 #define IPW_DL_UNINIT 0x80000000
42 #define IPW_DL_NONE 0x00000000
43 #define IPW_DL_ALL 0x7FFFFFFF
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71 #define IPW_DL_ERROR (1<<0)
72 #define IPW_DL_WARNING (1<<1)
73 #define IPW_DL_INFO (1<<2)
74 #define IPW_DL_WX (1<<3)
75 #define IPW_DL_HC (1<<5)
76 #define IPW_DL_STATE (1<<6)
77
78 #define IPW_DL_NOTIF (1<<10)
79 #define IPW_DL_SCAN (1<<11)
80 #define IPW_DL_ASSOC (1<<12)
81 #define IPW_DL_DROP (1<<13)
82
83 #define IPW_DL_IOCTL (1<<14)
84 #define IPW_DL_RF_KILL (1<<17)
85
86 #define IPW_DL_MANAGE (1<<15)
87 #define IPW_DL_FW (1<<16)
88
89 #define IPW_DL_FRAG (1<<21)
90 #define IPW_DL_WEP (1<<22)
91 #define IPW_DL_TX (1<<23)
92 #define IPW_DL_RX (1<<24)
93 #define IPW_DL_ISR (1<<25)
94 #define IPW_DL_IO (1<<26)
95 #define IPW_DL_TRACE (1<<28)
96
97 #define IPW_DEBUG_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
98 #define IPW_DEBUG_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
99 #define IPW_DEBUG_INFO(f...) IPW_DEBUG(IPW_DL_INFO, ## f)
100 #define IPW_DEBUG_WX(f...) IPW_DEBUG(IPW_DL_WX, ## f)
101 #define IPW_DEBUG_SCAN(f...) IPW_DEBUG(IPW_DL_SCAN, ## f)
102 #define IPW_DEBUG_NOTIF(f...) IPW_DEBUG(IPW_DL_NOTIF, ## f)
103 #define IPW_DEBUG_TRACE(f...) IPW_DEBUG(IPW_DL_TRACE, ## f)
104 #define IPW_DEBUG_RX(f...) IPW_DEBUG(IPW_DL_RX, ## f)
105 #define IPW_DEBUG_TX(f...) IPW_DEBUG(IPW_DL_TX, ## f)
106 #define IPW_DEBUG_ISR(f...) IPW_DEBUG(IPW_DL_ISR, ## f)
107 #define IPW_DEBUG_MANAGEMENT(f...) IPW_DEBUG(IPW_DL_MANAGE, ## f)
108 #define IPW_DEBUG_WEP(f...) IPW_DEBUG(IPW_DL_WEP, ## f)
109 #define IPW_DEBUG_HC(f...) IPW_DEBUG(IPW_DL_HC, ## f)
110 #define IPW_DEBUG_FRAG(f...) IPW_DEBUG(IPW_DL_FRAG, ## f)
111 #define IPW_DEBUG_FW(f...) IPW_DEBUG(IPW_DL_FW, ## f)
112 #define IPW_DEBUG_RF_KILL(f...) IPW_DEBUG(IPW_DL_RF_KILL, ## f)
113 #define IPW_DEBUG_DROP(f...) IPW_DEBUG(IPW_DL_DROP, ## f)
114 #define IPW_DEBUG_IO(f...) IPW_DEBUG(IPW_DL_IO, ## f)
115 #define IPW_DEBUG_IOCTL(f...) IPW_DEBUG(IPW_DL_IOCTL, ## f)
116 #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
117 #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
118
119 enum {
120 IPW_HW_STATE_DISABLED = 1,
121 IPW_HW_STATE_ENABLED = 0
122 };
123
124 extern const char *port_type_str[];
125 extern const char *band_str[];
126
127 #define NUMBER_OF_BD_PER_COMMAND_PACKET 1
128 #define NUMBER_OF_BD_PER_DATA_PACKET 2
129
130 #define IPW_MAX_BDS 6
131 #define NUMBER_OF_OVERHEAD_BDS_PER_PACKETR 2
132 #define NUMBER_OF_BDS_TO_LEAVE_FOR_COMMANDS 1
133
134 #define REQUIRED_SPACE_IN_RING_FOR_COMMAND_PACKET \
135 (IPW_BD_QUEUE_W_R_MIN_SPARE + NUMBER_OF_BD_PER_COMMAND_PACKET)
136
137 struct bd_status {
138 union {
139 struct {
140 u8 nlf:1, txType:2, intEnabled:1, reserved:4;
141 } fields;
142 u8 field;
143 } info;
144 } __packed;
145
146 struct ipw2100_bd {
147 u32 host_addr;
148 u32 buf_length;
149 struct bd_status status;
150
151
152 u8 num_fragments;
153 u8 reserved[6];
154 } __packed;
155
156 #define IPW_BD_QUEUE_LENGTH(n) (1<<n)
157 #define IPW_BD_ALIGNMENT(L) (L*sizeof(struct ipw2100_bd))
158
159 #define IPW_BD_STATUS_TX_FRAME_802_3 0x00
160 #define IPW_BD_STATUS_TX_FRAME_NOT_LAST_FRAGMENT 0x01
161 #define IPW_BD_STATUS_TX_FRAME_COMMAND 0x02
162 #define IPW_BD_STATUS_TX_FRAME_802_11 0x04
163 #define IPW_BD_STATUS_TX_INTERRUPT_ENABLE 0x08
164
165 struct ipw2100_bd_queue {
166
167 struct ipw2100_bd *drv;
168
169
170 dma_addr_t nic;
171
172
173 u32 size;
174
175
176 u32 entries;
177
178
179 u32 available;
180
181
182
183 u32 oldest;
184
185
186 u32 next;
187 };
188
189 #define RX_QUEUE_LENGTH 256
190 #define TX_QUEUE_LENGTH 256
191 #define HW_QUEUE_LENGTH 256
192
193 #define TX_PENDED_QUEUE_LENGTH (TX_QUEUE_LENGTH / NUMBER_OF_BD_PER_DATA_PACKET)
194
195 #define STATUS_TYPE_MASK 0x0000000f
196 #define COMMAND_STATUS_VAL 0
197 #define STATUS_CHANGE_VAL 1
198 #define P80211_DATA_VAL 2
199 #define P8023_DATA_VAL 3
200 #define HOST_NOTIFICATION_VAL 4
201
202 #define IPW2100_RSSI_TO_DBM (-98)
203
204 struct ipw2100_status {
205 u32 frame_size;
206 u16 status_fields;
207 u8 flags;
208 #define IPW_STATUS_FLAG_DECRYPTED (1<<0)
209 #define IPW_STATUS_FLAG_WEP_ENCRYPTED (1<<1)
210 #define IPW_STATUS_FLAG_CRC_ERROR (1<<2)
211 u8 rssi;
212 } __packed;
213
214 struct ipw2100_status_queue {
215
216 struct ipw2100_status *drv;
217
218
219 dma_addr_t nic;
220
221
222 u32 size;
223 };
224
225 #define HOST_COMMAND_PARAMS_REG_LEN 100
226 #define CMD_STATUS_PARAMS_REG_LEN 3
227
228 #define IPW_WPA_CAPABILITIES 0x1
229 #define IPW_WPA_LISTENINTERVAL 0x2
230 #define IPW_WPA_AP_ADDRESS 0x4
231
232 #define IPW_MAX_VAR_IE_LEN ((HOST_COMMAND_PARAMS_REG_LEN - 4) * sizeof(u32))
233
234 struct ipw2100_wpa_assoc_frame {
235 u16 fixed_ie_mask;
236 struct {
237 u16 capab_info;
238 u16 listen_interval;
239 u8 current_ap[ETH_ALEN];
240 } fixed_ies;
241 u32 var_ie_len;
242 u8 var_ie[IPW_MAX_VAR_IE_LEN];
243 };
244
245 #define IPW_BSS 1
246 #define IPW_MONITOR 2
247 #define IPW_IBSS 3
248
249
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251
252
253 struct ipw2100_cmd_header {
254 u32 host_command_reg;
255 u32 host_command_reg1;
256 u32 sequence;
257 u32 host_command_len_reg;
258 u32 host_command_params_reg[HOST_COMMAND_PARAMS_REG_LEN];
259 u32 cmd_status_reg;
260 u32 cmd_status_params_reg[CMD_STATUS_PARAMS_REG_LEN];
261 u32 rxq_base_ptr;
262 u32 rxq_next_ptr;
263 u32 rxq_host_ptr;
264 u32 txq_base_ptr;
265 u32 txq_next_ptr;
266 u32 txq_host_ptr;
267 u32 tx_status_reg;
268 u32 reserved;
269 u32 status_change_reg;
270 u32 reserved1[3];
271 u32 *ordinal1_ptr;
272 u32 *ordinal2_ptr;
273 } __packed;
274
275 struct ipw2100_data_header {
276 u32 host_command_reg;
277 u32 host_command_reg1;
278 u8 encrypted;
279 u8 needs_encryption;
280 u8 wep_index;
281 u8 key_size;
282 u8 key[16];
283 u8 reserved[10];
284 u8 src_addr[ETH_ALEN];
285 u8 dst_addr[ETH_ALEN];
286 u16 fragment_size;
287 } __packed;
288
289
290 struct host_command {
291 u32 host_command;
292 u32 host_command1;
293 u32 host_command_sequence;
294 u32 host_command_length;
295 u32 host_command_parameters[HOST_COMMAND_PARAMS_REG_LEN];
296 } __packed;
297
298 typedef enum {
299 POWER_ON_RESET,
300 EXIT_POWER_DOWN_RESET,
301 SW_RESET,
302 EEPROM_RW,
303 SW_RE_INIT
304 } ipw2100_reset_event;
305
306 enum {
307 COMMAND = 0xCAFE,
308 DATA,
309 RX
310 };
311
312 struct ipw2100_tx_packet {
313 int type;
314 int index;
315 union {
316 struct {
317 struct ipw2100_cmd_header *cmd;
318 dma_addr_t cmd_phys;
319 } c_struct;
320 struct {
321 struct ipw2100_data_header *data;
322 dma_addr_t data_phys;
323 struct libipw_txb *txb;
324 } d_struct;
325 } info;
326 int jiffy_start;
327
328 struct list_head list;
329 };
330
331 struct ipw2100_rx_packet {
332 struct ipw2100_rx *rxp;
333 dma_addr_t dma_addr;
334 int jiffy_start;
335 struct sk_buff *skb;
336 struct list_head list;
337 };
338
339 #define FRAG_DISABLED (1<<31)
340 #define RTS_DISABLED (1<<31)
341 #define MAX_RTS_THRESHOLD 2304U
342 #define MIN_RTS_THRESHOLD 1U
343 #define DEFAULT_RTS_THRESHOLD 1000U
344
345 #define DEFAULT_BEACON_INTERVAL 100U
346 #define DEFAULT_SHORT_RETRY_LIMIT 7U
347 #define DEFAULT_LONG_RETRY_LIMIT 4U
348
349 struct ipw2100_ordinals {
350 u32 table1_addr;
351 u32 table2_addr;
352 u32 table1_size;
353 u32 table2_size;
354 };
355
356
357 struct ipw2100_notification {
358 u32 hnhdr_subtype;
359 u32 hnhdr_size;
360
361
362 } __packed;
363
364 #define MAX_KEY_SIZE 16
365 #define MAX_KEYS 8
366
367 #define IPW2100_WEP_ENABLE (1<<1)
368 #define IPW2100_WEP_DROP_CLEAR (1<<2)
369
370 #define IPW_NONE_CIPHER (1<<0)
371 #define IPW_WEP40_CIPHER (1<<1)
372 #define IPW_TKIP_CIPHER (1<<2)
373 #define IPW_CCMP_CIPHER (1<<4)
374 #define IPW_WEP104_CIPHER (1<<5)
375 #define IPW_CKIP_CIPHER (1<<6)
376
377 #define IPW_AUTH_OPEN 0
378 #define IPW_AUTH_SHARED 1
379 #define IPW_AUTH_LEAP 2
380 #define IPW_AUTH_LEAP_CISCO_ID 0x80
381
382 struct statistic {
383 int value;
384 int hi;
385 int lo;
386 };
387
388 #define INIT_STAT(x) do { \
389 (x)->value = (x)->hi = 0; \
390 (x)->lo = 0x7fffffff; \
391 } while (0)
392 #define SET_STAT(x,y) do { \
393 (x)->value = y; \
394 if ((x)->value > (x)->hi) (x)->hi = (x)->value; \
395 if ((x)->value < (x)->lo) (x)->lo = (x)->value; \
396 } while (0)
397 #define INC_STAT(x) do { if (++(x)->value > (x)->hi) (x)->hi = (x)->value; } \
398 while (0)
399 #define DEC_STAT(x) do { if (--(x)->value < (x)->lo) (x)->lo = (x)->value; } \
400 while (0)
401
402 #define IPW2100_ERROR_QUEUE 5
403
404
405 enum {
406 #ifdef CONFIG_PM
407 IPW2100_PM_DISABLED = 0,
408 PM_STATE_SIZE = 16,
409 #else
410 IPW2100_PM_DISABLED = 1,
411 PM_STATE_SIZE = 0,
412 #endif
413 };
414
415 #define STATUS_POWERED (1<<0)
416 #define STATUS_CMD_ACTIVE (1<<1)
417 #define STATUS_RUNNING (1<<2)
418 #define STATUS_ENABLED (1<<3)
419 #define STATUS_STOPPING (1<<4)
420 #define STATUS_INITIALIZED (1<<5)
421 #define STATUS_ASSOCIATING (1<<9)
422 #define STATUS_ASSOCIATED (1<<10)
423 #define STATUS_INT_ENABLED (1<<11)
424 #define STATUS_RF_KILL_HW (1<<12)
425 #define STATUS_RF_KILL_SW (1<<13)
426 #define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
427 #define STATUS_EXIT_PENDING (1<<14)
428
429 #define STATUS_SCAN_PENDING (1<<23)
430 #define STATUS_SCANNING (1<<24)
431 #define STATUS_SCAN_ABORTING (1<<25)
432 #define STATUS_SCAN_COMPLETE (1<<26)
433 #define STATUS_WX_EVENT_PENDING (1<<27)
434 #define STATUS_RESET_PENDING (1<<29)
435 #define STATUS_SECURITY_UPDATED (1<<30)
436
437
438 #define IPW_STATE_INITIALIZED (1<<0)
439 #define IPW_STATE_COUNTRY_FOUND (1<<1)
440 #define IPW_STATE_ASSOCIATED (1<<2)
441 #define IPW_STATE_ASSN_LOST (1<<3)
442 #define IPW_STATE_ASSN_CHANGED (1<<4)
443 #define IPW_STATE_SCAN_COMPLETE (1<<5)
444 #define IPW_STATE_ENTERED_PSP (1<<6)
445 #define IPW_STATE_LEFT_PSP (1<<7)
446 #define IPW_STATE_RF_KILL (1<<8)
447 #define IPW_STATE_DISABLED (1<<9)
448 #define IPW_STATE_POWER_DOWN (1<<10)
449 #define IPW_STATE_SCANNING (1<<11)
450
451 #define CFG_STATIC_CHANNEL (1<<0)
452 #define CFG_STATIC_ESSID (1<<1)
453 #define CFG_STATIC_BSSID (1<<2)
454 #define CFG_CUSTOM_MAC (1<<3)
455 #define CFG_LONG_PREAMBLE (1<<4)
456 #define CFG_ASSOCIATE (1<<6)
457 #define CFG_FIXED_RATE (1<<7)
458 #define CFG_ADHOC_CREATE (1<<8)
459 #define CFG_PASSIVE_SCAN (1<<10)
460 #ifdef CONFIG_IPW2100_MONITOR
461 #define CFG_CRC_CHECK (1<<11)
462 #endif
463
464 #define CAP_SHARED_KEY (1<<0)
465 #define CAP_PRIVACY_ON (1<<1)
466
467 struct ipw2100_priv {
468 void __iomem *ioaddr;
469
470 int stop_hang_check;
471 int stop_rf_kill;
472
473 struct libipw_device *ieee;
474 unsigned long status;
475 unsigned long config;
476 unsigned long capability;
477
478
479 int resets;
480 time64_t reset_backoff;
481
482
483 u8 essid[IW_ESSID_MAX_SIZE];
484 u8 essid_len;
485 u8 bssid[ETH_ALEN];
486 u8 channel;
487 int last_mode;
488
489 time64_t connect_start;
490 time64_t last_reset;
491
492 u32 channel_mask;
493 u32 fatal_error;
494 u32 fatal_errors[IPW2100_ERROR_QUEUE];
495 u32 fatal_index;
496 int eeprom_version;
497 int firmware_version;
498 unsigned long hw_features;
499 int hangs;
500 u32 last_rtc;
501 int dump_raw;
502 u8 *snapshot[0x30];
503
504 u8 mandatory_bssid_mac[ETH_ALEN];
505 u8 mac_addr[ETH_ALEN];
506
507 int power_mode;
508
509 int messages_sent;
510
511 int short_retry_limit;
512 int long_retry_limit;
513
514 u32 rts_threshold;
515 u32 frag_threshold;
516
517 int in_isr;
518
519 u32 tx_rates;
520 int tx_power;
521 u32 beacon_interval;
522
523 char nick[IW_ESSID_MAX_SIZE + 1];
524
525 struct ipw2100_status_queue status_queue;
526
527 struct statistic txq_stat;
528 struct statistic rxq_stat;
529 struct ipw2100_bd_queue rx_queue;
530 struct ipw2100_bd_queue tx_queue;
531 struct ipw2100_rx_packet *rx_buffers;
532
533 struct statistic fw_pend_stat;
534 struct list_head fw_pend_list;
535
536 struct statistic msg_free_stat;
537 struct statistic msg_pend_stat;
538 struct list_head msg_free_list;
539 struct list_head msg_pend_list;
540 struct ipw2100_tx_packet *msg_buffers;
541
542 struct statistic tx_free_stat;
543 struct statistic tx_pend_stat;
544 struct list_head tx_free_list;
545 struct list_head tx_pend_list;
546 struct ipw2100_tx_packet *tx_buffers;
547
548 struct ipw2100_ordinals ordinals;
549
550 struct pci_dev *pci_dev;
551
552 struct proc_dir_entry *dir_dev;
553
554 struct net_device *net_dev;
555 struct iw_statistics wstats;
556
557 struct iw_public_data wireless_data;
558
559 struct tasklet_struct irq_tasklet;
560
561 struct delayed_work reset_work;
562 struct delayed_work security_work;
563 struct delayed_work wx_event_work;
564 struct delayed_work hang_check;
565 struct delayed_work rf_kill;
566 struct delayed_work scan_event;
567
568 int user_requested_scan;
569
570
571 time64_t suspend_at;
572 time64_t suspend_time;
573
574 u32 interrupts;
575 int tx_interrupts;
576 int rx_interrupts;
577 int inta_other;
578
579 spinlock_t low_lock;
580 struct mutex action_mutex;
581 struct mutex adapter_mutex;
582
583 wait_queue_head_t wait_command_queue;
584 };
585
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592
593 #define HOST_COMPLETE 2
594 #define SYSTEM_CONFIG 6
595 #define SSID 8
596 #define MANDATORY_BSSID 9
597 #define AUTHENTICATION_TYPE 10
598 #define ADAPTER_ADDRESS 11
599 #define PORT_TYPE 12
600 #define INTERNATIONAL_MODE 13
601 #define CHANNEL 14
602 #define RTS_THRESHOLD 15
603 #define FRAG_THRESHOLD 16
604 #define POWER_MODE 17
605 #define TX_RATES 18
606 #define BASIC_TX_RATES 19
607 #define WEP_KEY_INFO 20
608 #define WEP_KEY_INDEX 25
609 #define WEP_FLAGS 26
610 #define ADD_MULTICAST 27
611 #define CLEAR_ALL_MULTICAST 28
612 #define BEACON_INTERVAL 29
613 #define ATIM_WINDOW 30
614 #define CLEAR_STATISTICS 31
615 #define SEND 33
616 #define TX_POWER_INDEX 36
617 #define BROADCAST_SCAN 43
618 #define CARD_DISABLE 44
619 #define PREFERRED_BSSID 45
620 #define SET_SCAN_OPTIONS 46
621 #define SCAN_DWELL_TIME 47
622 #define SWEEP_TABLE 48
623 #define AP_OR_STATION_TABLE 49
624 #define GROUP_ORDINALS 50
625 #define SHORT_RETRY_LIMIT 51
626 #define LONG_RETRY_LIMIT 52
627
628 #define HOST_PRE_POWER_DOWN 58
629 #define CARD_DISABLE_PHY_OFF 61
630 #define MSDU_TX_RATES 62
631
632
633 #define SET_STATION_STAT_BITS 64
634 #define CLEAR_STATIONS_STAT_BITS 65
635 #define LEAP_ROGUE_MODE 66
636 #define SET_SECURITY_INFORMATION 67
637 #define DISASSOCIATION_BSSID 68
638 #define SET_WPA_IE 69
639
640
641 #define IPW_CFG_MONITOR 0x00004
642 #define IPW_CFG_PREAMBLE_AUTO 0x00010
643 #define IPW_CFG_IBSS_AUTO_START 0x00020
644 #define IPW_CFG_LOOPBACK 0x00100
645 #define IPW_CFG_ANSWER_BCSSID_PROBE 0x00800
646 #define IPW_CFG_BT_SIDEBAND_SIGNAL 0x02000
647 #define IPW_CFG_802_1x_ENABLE 0x04000
648 #define IPW_CFG_BSS_MASK 0x08000
649 #define IPW_CFG_IBSS_MASK 0x10000
650
651 #define IPW_SCAN_NOASSOCIATE (1<<0)
652 #define IPW_SCAN_MIXED_CELL (1<<1)
653
654 #define IPW_SCAN_PASSIVE (1<<3)
655
656 #define IPW_NIC_FATAL_ERROR 0x2A7F0
657 #define IPW_ERROR_ADDR(x) (x & 0x3FFFF)
658 #define IPW_ERROR_CODE(x) ((x & 0xFF000000) >> 24)
659 #define IPW2100_ERR_C3_CORRUPTION (0x10 << 24)
660 #define IPW2100_ERR_MSG_TIMEOUT (0x11 << 24)
661 #define IPW2100_ERR_FW_LOAD (0x12 << 24)
662
663 #define IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND 0x200
664 #define IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x0D80
665
666 #define IPW_MEM_HOST_SHARED_RX_BD_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x40)
667 #define IPW_MEM_HOST_SHARED_RX_STATUS_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x44)
668 #define IPW_MEM_HOST_SHARED_RX_BD_SIZE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x48)
669 #define IPW_MEM_HOST_SHARED_RX_READ_INDEX (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0xa0)
670
671 #define IPW_MEM_HOST_SHARED_TX_QUEUE_BD_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x00)
672 #define IPW_MEM_HOST_SHARED_TX_QUEUE_BD_SIZE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x04)
673 #define IPW_MEM_HOST_SHARED_TX_QUEUE_READ_INDEX (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x80)
674
675 #define IPW_MEM_HOST_SHARED_RX_WRITE_INDEX \
676 (IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND + 0x20)
677
678 #define IPW_MEM_HOST_SHARED_TX_QUEUE_WRITE_INDEX \
679 (IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND)
680
681 #define IPW_MEM_HOST_SHARED_ORDINALS_TABLE_1 (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x180)
682 #define IPW_MEM_HOST_SHARED_ORDINALS_TABLE_2 (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x184)
683
684 #define IPW2100_INTA_TX_TRANSFER (0x00000001)
685 #define IPW2100_INTA_RX_TRANSFER (0x00000002)
686 #define IPW2100_INTA_TX_COMPLETE (0x00000004)
687 #define IPW2100_INTA_EVENT_INTERRUPT (0x00000008)
688 #define IPW2100_INTA_STATUS_CHANGE (0x00000010)
689 #define IPW2100_INTA_BEACON_PERIOD_EXPIRED (0x00000020)
690 #define IPW2100_INTA_SLAVE_MODE_HOST_COMMAND_DONE (0x00010000)
691 #define IPW2100_INTA_FW_INIT_DONE (0x01000000)
692 #define IPW2100_INTA_FW_CALIBRATION_CALC (0x02000000)
693 #define IPW2100_INTA_FATAL_ERROR (0x40000000)
694 #define IPW2100_INTA_PARITY_ERROR (0x80000000)
695
696 #define IPW_AUX_HOST_RESET_REG_PRINCETON_RESET (0x00000001)
697 #define IPW_AUX_HOST_RESET_REG_FORCE_NMI (0x00000002)
698 #define IPW_AUX_HOST_RESET_REG_PCI_HOST_CLUSTER_FATAL_NMI (0x00000004)
699 #define IPW_AUX_HOST_RESET_REG_CORE_FATAL_NMI (0x00000008)
700 #define IPW_AUX_HOST_RESET_REG_SW_RESET (0x00000080)
701 #define IPW_AUX_HOST_RESET_REG_MASTER_DISABLED (0x00000100)
702 #define IPW_AUX_HOST_RESET_REG_STOP_MASTER (0x00000200)
703
704 #define IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY (0x00000001)
705 #define IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY (0x00000002)
706 #define IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE (0x00000004)
707 #define IPW_AUX_HOST_GP_CNTRL_BITS_SYS_CONFIG (0x000007c0)
708 #define IPW_AUX_HOST_GP_CNTRL_BIT_BUS_TYPE (0x00000200)
709 #define IPW_AUX_HOST_GP_CNTRL_BIT_BAR0_BLOCK_SIZE (0x00000400)
710 #define IPW_AUX_HOST_GP_CNTRL_BIT_USB_MODE (0x20000000)
711 #define IPW_AUX_HOST_GP_CNTRL_BIT_HOST_FORCES_SYS_CLK (0x40000000)
712 #define IPW_AUX_HOST_GP_CNTRL_BIT_FW_FORCES_SYS_CLK (0x80000000)
713
714 #define IPW_BIT_GPIO_GPIO1_MASK 0x0000000C
715 #define IPW_BIT_GPIO_GPIO3_MASK 0x000000C0
716 #define IPW_BIT_GPIO_GPIO1_ENABLE 0x00000008
717 #define IPW_BIT_GPIO_RF_KILL 0x00010000
718
719 #define IPW_BIT_GPIO_LED_OFF 0x00002000
720
721 #define IPW_REG_DOMAIN_0_OFFSET 0x0000
722 #define IPW_REG_DOMAIN_1_OFFSET IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND
723
724 #define IPW_REG_INTA IPW_REG_DOMAIN_0_OFFSET + 0x0008
725 #define IPW_REG_INTA_MASK IPW_REG_DOMAIN_0_OFFSET + 0x000C
726 #define IPW_REG_INDIRECT_ACCESS_ADDRESS IPW_REG_DOMAIN_0_OFFSET + 0x0010
727 #define IPW_REG_INDIRECT_ACCESS_DATA IPW_REG_DOMAIN_0_OFFSET + 0x0014
728 #define IPW_REG_AUTOINCREMENT_ADDRESS IPW_REG_DOMAIN_0_OFFSET + 0x0018
729 #define IPW_REG_AUTOINCREMENT_DATA IPW_REG_DOMAIN_0_OFFSET + 0x001C
730 #define IPW_REG_RESET_REG IPW_REG_DOMAIN_0_OFFSET + 0x0020
731 #define IPW_REG_GP_CNTRL IPW_REG_DOMAIN_0_OFFSET + 0x0024
732 #define IPW_REG_GPIO IPW_REG_DOMAIN_0_OFFSET + 0x0030
733 #define IPW_REG_FW_TYPE IPW_REG_DOMAIN_1_OFFSET + 0x0188
734 #define IPW_REG_FW_VERSION IPW_REG_DOMAIN_1_OFFSET + 0x018C
735 #define IPW_REG_FW_COMPATIBILITY_VERSION IPW_REG_DOMAIN_1_OFFSET + 0x0190
736
737 #define IPW_REG_INDIRECT_ADDR_MASK 0x00FFFFFC
738
739 #define IPW_INTERRUPT_MASK 0xC1010013
740
741 #define IPW2100_CONTROL_REG 0x220000
742 #define IPW2100_CONTROL_PHY_OFF 0x8
743
744 #define IPW2100_COMMAND 0x00300004
745 #define IPW2100_COMMAND_PHY_ON 0x0
746 #define IPW2100_COMMAND_PHY_OFF 0x1
747
748
749 #define IPW_REG_DOA_DEBUG_AREA_START IPW_REG_DOMAIN_0_OFFSET + 0x0090
750 #define IPW_REG_DOA_DEBUG_AREA_END IPW_REG_DOMAIN_0_OFFSET + 0x00FF
751 #define IPW_DATA_DOA_DEBUG_VALUE 0xd55555d5
752
753 #define IPW_INTERNAL_REGISTER_HALT_AND_RESET 0x003000e0
754
755 #define IPW_WAIT_CLOCK_STABILIZATION_DELAY 50
756 #define IPW_WAIT_RESET_ARC_COMPLETE_DELAY 10
757 #define IPW_WAIT_RESET_MASTER_ASSERT_COMPLETE_DELAY 10
758
759
760 #define IPW_BD_QUEUE_W_R_MIN_SPARE 2
761
762 #define IPW_CACHE_LINE_LENGTH_DEFAULT 0x80
763
764 #define IPW_CARD_DISABLE_PHY_OFF_COMPLETE_WAIT 100
765 #define IPW_PREPARE_POWER_DOWN_COMPLETE_WAIT 100
766
767 #define IPW_HEADER_802_11_SIZE sizeof(struct libipw_hdr_3addr)
768 #define IPW_MAX_80211_PAYLOAD_SIZE 2304U
769 #define IPW_MAX_802_11_PAYLOAD_LENGTH 2312
770 #define IPW_MAX_ACCEPTABLE_TX_FRAME_LENGTH 1536
771 #define IPW_MIN_ACCEPTABLE_RX_FRAME_LENGTH 60
772 #define IPW_MAX_ACCEPTABLE_RX_FRAME_LENGTH \
773 (IPW_MAX_ACCEPTABLE_TX_FRAME_LENGTH + IPW_HEADER_802_11_SIZE - \
774 sizeof(struct ethhdr))
775
776 #define IPW_802_11_FCS_LENGTH 4
777 #define IPW_RX_NIC_BUFFER_LENGTH \
778 (IPW_MAX_802_11_PAYLOAD_LENGTH + IPW_HEADER_802_11_SIZE + \
779 IPW_802_11_FCS_LENGTH)
780
781 #define IPW_802_11_PAYLOAD_OFFSET \
782 (sizeof(struct libipw_hdr_3addr) + \
783 sizeof(struct libipw_snap_hdr))
784
785 struct ipw2100_rx {
786 union {
787 unsigned char payload[IPW_RX_NIC_BUFFER_LENGTH];
788 struct libipw_hdr_4addr header;
789 u32 status;
790 struct ipw2100_notification notification;
791 struct ipw2100_cmd_header command;
792 } rx_data;
793 } __packed;
794
795
796 #define TX_RATE_1_MBIT 0x0001
797 #define TX_RATE_2_MBIT 0x0002
798 #define TX_RATE_5_5_MBIT 0x0004
799 #define TX_RATE_11_MBIT 0x0008
800 #define TX_RATE_MASK 0x000F
801 #define DEFAULT_TX_RATES 0x000F
802
803 #define IPW_POWER_MODE_CAM 0x00
804 #define IPW_POWER_INDEX_1 0x01
805 #define IPW_POWER_INDEX_2 0x02
806 #define IPW_POWER_INDEX_3 0x03
807 #define IPW_POWER_INDEX_4 0x04
808 #define IPW_POWER_INDEX_5 0x05
809 #define IPW_POWER_AUTO 0x06
810 #define IPW_POWER_MASK 0x0F
811 #define IPW_POWER_ENABLED 0x10
812 #define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
813
814 #define IPW_TX_POWER_AUTO 0
815 #define IPW_TX_POWER_ENHANCED 1
816
817 #define IPW_TX_POWER_DEFAULT 32
818 #define IPW_TX_POWER_MIN 0
819 #define IPW_TX_POWER_MAX 16
820 #define IPW_TX_POWER_MIN_DBM (-12)
821 #define IPW_TX_POWER_MAX_DBM 16
822
823 #define FW_SCAN_DONOT_ASSOCIATE 0x0001
824 #define FW_SCAN_PASSIVE 0x0008
825
826 #define REG_MIN_CHANNEL 0
827 #define REG_MAX_CHANNEL 14
828
829 #define REG_CHANNEL_MASK 0x00003FFF
830 #define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
831
832 #define DIVERSITY_EITHER 0
833 #define DIVERSITY_ANTENNA_A 1
834 #define DIVERSITY_ANTENNA_B 2
835
836 #define HOST_COMMAND_WAIT 0
837 #define HOST_COMMAND_NO_WAIT 1
838
839 #define LOCK_NONE 0
840 #define LOCK_DRIVER 1
841 #define LOCK_FW 2
842
843 #define TYPE_SWEEP_ORD 0x000D
844 #define TYPE_IBSS_STTN_ORD 0x000E
845 #define TYPE_BSS_AP_ORD 0x000F
846 #define TYPE_RAW_BEACON_ENTRY 0x0010
847 #define TYPE_CALIBRATION_DATA 0x0011
848 #define TYPE_ROGUE_AP_DATA 0x0012
849 #define TYPE_ASSOCIATION_REQUEST 0x0013
850 #define TYPE_REASSOCIATION_REQUEST 0x0014
851
852 #define HW_FEATURE_RFKILL 0x0001
853 #define RF_KILLSWITCH_OFF 1
854 #define RF_KILLSWITCH_ON 0
855
856 #define IPW_COMMAND_POOL_SIZE 40
857
858 #define IPW_START_ORD_TAB_1 1
859 #define IPW_START_ORD_TAB_2 1000
860
861 #define IPW_ORD_TAB_1_ENTRY_SIZE sizeof(u32)
862
863 #define IS_ORDINAL_TABLE_ONE(mgr,id) \
864 ((id >= IPW_START_ORD_TAB_1) && (id < mgr->table1_size))
865 #define IS_ORDINAL_TABLE_TWO(mgr,id) \
866 ((id >= IPW_START_ORD_TAB_2) && (id < (mgr->table2_size + IPW_START_ORD_TAB_2)))
867
868 #define BSS_ID_LENGTH 6
869
870
871 typedef enum _ORDINAL_TABLE_1 {
872
873 IPW_ORD_STAT_TX_HOST_REQUESTS = 1,
874 IPW_ORD_STAT_TX_HOST_COMPLETE,
875 IPW_ORD_STAT_TX_DIR_DATA,
876
877 IPW_ORD_STAT_TX_DIR_DATA1 = 4,
878 IPW_ORD_STAT_TX_DIR_DATA2,
879 IPW_ORD_STAT_TX_DIR_DATA5_5,
880 IPW_ORD_STAT_TX_DIR_DATA11,
881 IPW_ORD_STAT_TX_DIR_DATA22,
882
883 IPW_ORD_STAT_TX_NODIR_DATA1 = 13,
884 IPW_ORD_STAT_TX_NODIR_DATA2,
885 IPW_ORD_STAT_TX_NODIR_DATA5_5,
886 IPW_ORD_STAT_TX_NODIR_DATA11,
887
888 IPW_ORD_STAT_NULL_DATA = 21,
889 IPW_ORD_STAT_TX_RTS,
890 IPW_ORD_STAT_TX_CTS,
891 IPW_ORD_STAT_TX_ACK,
892 IPW_ORD_STAT_TX_ASSN,
893 IPW_ORD_STAT_TX_ASSN_RESP,
894 IPW_ORD_STAT_TX_REASSN,
895 IPW_ORD_STAT_TX_REASSN_RESP,
896 IPW_ORD_STAT_TX_PROBE,
897 IPW_ORD_STAT_TX_PROBE_RESP,
898 IPW_ORD_STAT_TX_BEACON,
899 IPW_ORD_STAT_TX_ATIM,
900 IPW_ORD_STAT_TX_DISASSN,
901 IPW_ORD_STAT_TX_AUTH,
902 IPW_ORD_STAT_TX_DEAUTH,
903
904 IPW_ORD_STAT_TX_TOTAL_BYTES = 41,
905 IPW_ORD_STAT_TX_RETRIES,
906 IPW_ORD_STAT_TX_RETRY1,
907 IPW_ORD_STAT_TX_RETRY2,
908 IPW_ORD_STAT_TX_RETRY5_5,
909 IPW_ORD_STAT_TX_RETRY11,
910
911 IPW_ORD_STAT_TX_FAILURES = 51,
912 IPW_ORD_STAT_TX_ABORT_AT_HOP,
913 IPW_ORD_STAT_TX_MAX_TRIES_IN_HOP,
914 IPW_ORD_STAT_TX_ABORT_LATE_DMA,
915 IPW_ORD_STAT_TX_ABORT_STX,
916 IPW_ORD_STAT_TX_DISASSN_FAIL,
917 IPW_ORD_STAT_TX_ERR_CTS,
918 IPW_ORD_STAT_TX_BPDU,
919 IPW_ORD_STAT_TX_ERR_ACK,
920
921
922 IPW_ORD_STAT_RX_HOST = 61,
923 IPW_ORD_STAT_RX_DIR_DATA,
924 IPW_ORD_STAT_RX_DIR_DATA1,
925 IPW_ORD_STAT_RX_DIR_DATA2,
926 IPW_ORD_STAT_RX_DIR_DATA5_5,
927 IPW_ORD_STAT_RX_DIR_DATA11,
928 IPW_ORD_STAT_RX_DIR_DATA22,
929
930 IPW_ORD_STAT_RX_NODIR_DATA = 71,
931 IPW_ORD_STAT_RX_NODIR_DATA1,
932 IPW_ORD_STAT_RX_NODIR_DATA2,
933 IPW_ORD_STAT_RX_NODIR_DATA5_5,
934 IPW_ORD_STAT_RX_NODIR_DATA11,
935
936 IPW_ORD_STAT_RX_NULL_DATA = 80,
937 IPW_ORD_STAT_RX_POLL,
938 IPW_ORD_STAT_RX_RTS,
939 IPW_ORD_STAT_RX_CTS,
940 IPW_ORD_STAT_RX_ACK,
941 IPW_ORD_STAT_RX_CFEND,
942 IPW_ORD_STAT_RX_CFEND_ACK,
943 IPW_ORD_STAT_RX_ASSN,
944 IPW_ORD_STAT_RX_ASSN_RESP,
945 IPW_ORD_STAT_RX_REASSN,
946 IPW_ORD_STAT_RX_REASSN_RESP,
947 IPW_ORD_STAT_RX_PROBE,
948 IPW_ORD_STAT_RX_PROBE_RESP,
949 IPW_ORD_STAT_RX_BEACON,
950 IPW_ORD_STAT_RX_ATIM,
951 IPW_ORD_STAT_RX_DISASSN,
952 IPW_ORD_STAT_RX_AUTH,
953 IPW_ORD_STAT_RX_DEAUTH,
954
955 IPW_ORD_STAT_RX_TOTAL_BYTES = 101,
956 IPW_ORD_STAT_RX_ERR_CRC,
957 IPW_ORD_STAT_RX_ERR_CRC1,
958 IPW_ORD_STAT_RX_ERR_CRC2,
959 IPW_ORD_STAT_RX_ERR_CRC5_5,
960 IPW_ORD_STAT_RX_ERR_CRC11,
961
962 IPW_ORD_STAT_RX_DUPLICATE1 = 112,
963 IPW_ORD_STAT_RX_DUPLICATE2,
964 IPW_ORD_STAT_RX_DUPLICATE5_5,
965 IPW_ORD_STAT_RX_DUPLICATE11,
966 IPW_ORD_STAT_RX_DUPLICATE = 119,
967
968 IPW_ORD_PERS_DB_LOCK = 120,
969 IPW_ORD_PERS_DB_SIZE,
970 IPW_ORD_PERS_DB_ADDR,
971 IPW_ORD_STAT_RX_INVALID_PROTOCOL,
972 IPW_ORD_SYS_BOOT_TIME,
973 IPW_ORD_STAT_RX_NO_BUFFER,
974 IPW_ORD_STAT_RX_ABORT_LATE_DMA,
975 IPW_ORD_STAT_RX_ABORT_AT_HOP,
976 IPW_ORD_STAT_RX_MISSING_FRAG,
977 IPW_ORD_STAT_RX_ORPHAN_FRAG,
978 IPW_ORD_STAT_RX_ORPHAN_FRAME,
979 IPW_ORD_STAT_RX_FRAG_AGEOUT,
980 IPW_ORD_STAT_RX_BAD_SSID,
981 IPW_ORD_STAT_RX_ICV_ERRORS,
982
983
984 IPW_ORD_STAT_PSP_SUSPENSION = 137,
985 IPW_ORD_STAT_PSP_BCN_TIMEOUT,
986 IPW_ORD_STAT_PSP_POLL_TIMEOUT,
987 IPW_ORD_STAT_PSP_NONDIR_TIMEOUT,
988 IPW_ORD_STAT_PSP_RX_DTIMS,
989 IPW_ORD_STAT_PSP_RX_TIMS,
990 IPW_ORD_STAT_PSP_STATION_ID,
991
992
993 IPW_ORD_LAST_ASSN_TIME = 147,
994 IPW_ORD_STAT_PERCENT_MISSED_BCNS,
995 IPW_ORD_STAT_PERCENT_RETRIES,
996 IPW_ORD_ASSOCIATED_AP_PTR,
997
998 IPW_ORD_AVAILABLE_AP_CNT,
999 IPW_ORD_AP_LIST_PTR,
1000 IPW_ORD_STAT_AP_ASSNS,
1001 IPW_ORD_STAT_ASSN_FAIL,
1002 IPW_ORD_STAT_ASSN_RESP_FAIL,
1003 IPW_ORD_STAT_FULL_SCANS,
1004
1005 IPW_ORD_CARD_DISABLED,
1006 IPW_ORD_STAT_ROAM_INHIBIT,
1007 IPW_FILLER_40,
1008 IPW_ORD_RSSI_AT_ASSN = 160,
1009 IPW_ORD_STAT_ASSN_CAUSE1,
1010
1011 IPW_ORD_STAT_ASSN_CAUSE2,
1012 IPW_ORD_STAT_ASSN_CAUSE3,
1013
1014 IPW_ORD_STAT_ASSN_CAUSE4,
1015
1016 IPW_ORD_STAT_ASSN_CAUSE5,
1017 IPW_ORD_STAT_ASSN_CAUSE6,
1018 IPW_FILLER_41,
1019 IPW_FILLER_42,
1020 IPW_FILLER_43,
1021 IPW_ORD_STAT_AUTH_FAIL,
1022 IPW_ORD_STAT_AUTH_RESP_FAIL,
1023 IPW_ORD_STATION_TABLE_CNT,
1024
1025
1026 IPW_ORD_RSSI_AVG_CURR = 173,
1027 IPW_ORD_STEST_RESULTS_CURR,
1028 IPW_ORD_STEST_RESULTS_CUM,
1029 IPW_ORD_SELF_TEST_STATUS,
1030 IPW_ORD_POWER_MGMT_MODE,
1031 IPW_ORD_POWER_MGMT_INDEX,
1032 IPW_ORD_COUNTRY_CODE,
1033 IPW_ORD_COUNTRY_CHANNELS,
1034
1035
1036
1037 IPW_ORD_RESET_CNT,
1038 IPW_ORD_BEACON_INTERVAL,
1039
1040 IPW_ORD_PRINCETON_VERSION = 184,
1041 IPW_ORD_ANTENNA_DIVERSITY,
1042 IPW_ORD_CCA_RSSI,
1043 IPW_ORD_STAT_EEPROM_UPDATE,
1044 IPW_ORD_DTIM_PERIOD,
1045 IPW_ORD_OUR_FREQ,
1046
1047 IPW_ORD_RTC_TIME = 190,
1048 IPW_ORD_PORT_TYPE,
1049 IPW_ORD_CURRENT_TX_RATE,
1050 IPW_ORD_SUPPORTED_RATES,
1051 IPW_ORD_ATIM_WINDOW,
1052 IPW_ORD_BASIC_RATES,
1053 IPW_ORD_NIC_HIGHEST_RATE,
1054 IPW_ORD_AP_HIGHEST_RATE,
1055 IPW_ORD_CAPABILITIES,
1056 IPW_ORD_AUTH_TYPE,
1057 IPW_ORD_RADIO_TYPE,
1058 IPW_ORD_RTS_THRESHOLD = 201,
1059 IPW_ORD_INT_MODE,
1060 IPW_ORD_FRAGMENTATION_THRESHOLD,
1061 IPW_ORD_EEPROM_SRAM_DB_BLOCK_START_ADDRESS,
1062 IPW_ORD_EEPROM_SRAM_DB_BLOCK_SIZE,
1063 IPW_ORD_EEPROM_SKU_CAPABILITY,
1064 IPW_ORD_EEPROM_IBSS_11B_CHANNELS,
1065
1066 IPW_ORD_MAC_VERSION = 209,
1067 IPW_ORD_MAC_REVISION,
1068 IPW_ORD_RADIO_VERSION,
1069 IPW_ORD_NIC_MANF_DATE_TIME,
1070 IPW_ORD_UCODE_VERSION,
1071 IPW_ORD_HW_RF_SWITCH_STATE = 214,
1072 } ORDINALTABLE1;
1073
1074
1075
1076 #define IPW_FIRST_VARIABLE_LENGTH_ORDINAL 1001
1077
1078 typedef enum _ORDINAL_TABLE_2 {
1079 IPW_ORD_STAT_BASE = 1000,
1080 IPW_ORD_STAT_ADAPTER_MAC = 1001,
1081 IPW_ORD_STAT_PREFERRED_BSSID = 1002,
1082 IPW_ORD_STAT_MANDATORY_BSSID = 1003,
1083 IPW_FILL_1,
1084 IPW_ORD_STAT_COUNTRY_TEXT = 1005,
1085 IPW_ORD_STAT_ASSN_SSID = 1006,
1086 IPW_ORD_STATION_TABLE = 1007,
1087 IPW_ORD_STAT_SWEEP_TABLE = 1008,
1088 IPW_ORD_STAT_ROAM_LOG = 1009,
1089 IPW_ORD_STAT_RATE_LOG = 1010,
1090 IPW_ORD_STAT_FIFO = 1011,
1091 IPW_ORD_STAT_FW_VER_NUM = 1012,
1092 IPW_ORD_STAT_FW_DATE = 1013,
1093 IPW_ORD_STAT_ASSN_AP_BSSID = 1014,
1094 IPW_ORD_STAT_DEBUG = 1015,
1095 IPW_ORD_STAT_NIC_BPA_NUM = 1016,
1096 IPW_ORD_STAT_UCODE_DATE = 1017,
1097 IPW_ORD_SECURITY_NGOTIATION_RESULT = 1018,
1098 } ORDINALTABLE2;
1099
1100 #define IPW_LAST_VARIABLE_LENGTH_ORDINAL 1018
1101
1102 #ifndef WIRELESS_SPY
1103 #define WIRELESS_SPY
1104 #endif
1105
1106 #define IPW_HOST_FW_SHARED_AREA0 0x0002f200
1107 #define IPW_HOST_FW_SHARED_AREA0_END 0x0002f510
1108
1109 #define IPW_HOST_FW_SHARED_AREA1 0x0002f610
1110 #define IPW_HOST_FW_SHARED_AREA1_END 0x0002f630
1111
1112 #define IPW_HOST_FW_SHARED_AREA2 0x0002fa00
1113 #define IPW_HOST_FW_SHARED_AREA2_END 0x0002fa20
1114
1115 #define IPW_HOST_FW_SHARED_AREA3 0x0002fc00
1116 #define IPW_HOST_FW_SHARED_AREA3_END 0x0002fc10
1117
1118 #define IPW_HOST_FW_INTERRUPT_AREA 0x0002ff80
1119 #define IPW_HOST_FW_INTERRUPT_AREA_END 0x00030000
1120
1121 struct ipw2100_fw_chunk {
1122 unsigned char *buf;
1123 long len;
1124 long pos;
1125 struct list_head list;
1126 };
1127
1128 struct ipw2100_fw_chunk_set {
1129 const void *data;
1130 unsigned long size;
1131 };
1132
1133 struct ipw2100_fw {
1134 int version;
1135 struct ipw2100_fw_chunk_set fw;
1136 struct ipw2100_fw_chunk_set uc;
1137 const struct firmware *fw_entry;
1138 };
1139
1140 #define MAX_FW_VERSION_LEN 14
1141
1142 #endif