This source file includes following definitions.
- mt7603_set_tmac_template
- mt7603_dma_sched_init
- mt7603_phy_init
- mt7603_mac_init
- mt7603_init_hardware
- mt7603_led_set_config
- mt7603_led_set_blink
- mt7603_led_set_brightness
- __mt7603_reg_addr
- mt7603_rr
- mt7603_wr
- mt7603_rmw
- mt7603_regd_notifier
- mt7603_txpower_signed
- mt7603_init_txpower
- mt7603_register_device
- mt7603_unregister_device
1
2
3 #include <linux/etherdevice.h>
4 #include "mt7603.h"
5 #include "mac.h"
6 #include "eeprom.h"
7
8 const struct mt76_driver_ops mt7603_drv_ops = {
9 .txwi_size = MT_TXD_SIZE,
10 .tx_prepare_skb = mt7603_tx_prepare_skb,
11 .tx_complete_skb = mt7603_tx_complete_skb,
12 .rx_skb = mt7603_queue_rx_skb,
13 .rx_poll_complete = mt7603_rx_poll_complete,
14 .sta_ps = mt7603_sta_ps,
15 .sta_add = mt7603_sta_add,
16 .sta_assoc = mt7603_sta_assoc,
17 .sta_remove = mt7603_sta_remove,
18 .update_survey = mt7603_update_channel,
19 };
20
21 static void
22 mt7603_set_tmac_template(struct mt7603_dev *dev)
23 {
24 u32 desc[5] = {
25 [1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf),
26 [3] = MT_TXD5_SW_POWER_MGMT
27 };
28 u32 addr;
29 int i;
30
31 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR);
32 addr += MT_CLIENT_TMAC_INFO_TEMPLATE;
33 for (i = 0; i < ARRAY_SIZE(desc); i++)
34 mt76_wr(dev, addr + 4 * i, desc[i]);
35 }
36
37 static void
38 mt7603_dma_sched_init(struct mt7603_dev *dev)
39 {
40 int page_size = 128;
41 int page_count;
42 int max_len = 1792;
43 int max_amsdu_pages = 4096 / page_size;
44 int max_mcu_len = 4096;
45 int max_beacon_len = 512 * 4 + max_len;
46 int max_mcast_pages = 4 * max_len / page_size;
47 int reserved_count = 0;
48 int beacon_pages;
49 int mcu_pages;
50 int i;
51
52 page_count = mt76_get_field(dev, MT_PSE_FC_P0,
53 MT_PSE_FC_P0_MAX_QUOTA);
54 beacon_pages = 4 * (max_beacon_len / page_size);
55 mcu_pages = max_mcu_len / page_size;
56
57 mt76_wr(dev, MT_PSE_FRP,
58 FIELD_PREP(MT_PSE_FRP_P0, 7) |
59 FIELD_PREP(MT_PSE_FRP_P1, 6) |
60 FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4));
61
62 mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553);
63 mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555);
64
65 mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e);
66 mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c);
67
68 mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff);
69
70 mt76_wr(dev, MT_SCH_1, page_count | (2 << 28));
71 mt76_wr(dev, MT_SCH_2, max_amsdu_pages);
72
73 for (i = 0; i <= 4; i++)
74 mt76_wr(dev, MT_PAGE_COUNT(i), max_amsdu_pages);
75 reserved_count += 5 * max_amsdu_pages;
76
77 mt76_wr(dev, MT_PAGE_COUNT(5), mcu_pages);
78 reserved_count += mcu_pages;
79
80 mt76_wr(dev, MT_PAGE_COUNT(7), beacon_pages);
81 reserved_count += beacon_pages;
82
83 mt76_wr(dev, MT_PAGE_COUNT(8), max_mcast_pages);
84 reserved_count += max_mcast_pages;
85
86 if (is_mt7603(dev))
87 reserved_count = 0;
88
89 mt76_wr(dev, MT_RSV_MAX_THRESH, page_count - reserved_count);
90
91 if (is_mt7603(dev) && mt76xx_rev(dev) >= MT7603_REV_E2) {
92 mt76_wr(dev, MT_GROUP_THRESH(0),
93 page_count - beacon_pages - mcu_pages);
94 mt76_wr(dev, MT_GROUP_THRESH(1), beacon_pages);
95 mt76_wr(dev, MT_BMAP_0, 0x0080ff5f);
96 mt76_wr(dev, MT_GROUP_THRESH(2), mcu_pages);
97 mt76_wr(dev, MT_BMAP_1, 0x00000020);
98 } else {
99 mt76_wr(dev, MT_GROUP_THRESH(0), page_count);
100 mt76_wr(dev, MT_BMAP_0, 0xffff);
101 }
102
103 mt76_wr(dev, MT_SCH_4, 0);
104
105 for (i = 0; i <= 15; i++)
106 mt76_wr(dev, MT_TXTIME_THRESH(i), 0xfffff);
107
108 mt76_set(dev, MT_SCH_4, BIT(6));
109 }
110
111 static void
112 mt7603_phy_init(struct mt7603_dev *dev)
113 {
114 int rx_chains = dev->mt76.antenna_mask;
115 int tx_chains = hweight8(rx_chains) - 1;
116
117 mt76_rmw(dev, MT_WF_RMAC_RMCR,
118 (MT_WF_RMAC_RMCR_SMPS_MODE |
119 MT_WF_RMAC_RMCR_RX_STREAMS),
120 (FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) |
121 FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains)));
122
123 mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS,
124 tx_chains);
125
126 dev->agc0 = mt76_rr(dev, MT_AGC(0));
127 dev->agc3 = mt76_rr(dev, MT_AGC(3));
128 }
129
130 static void
131 mt7603_mac_init(struct mt7603_dev *dev)
132 {
133 u8 bc_addr[ETH_ALEN];
134 u32 addr;
135 int i;
136
137 mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_0,
138 (MT_AGG_SIZE_LIMIT(0) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
139 (MT_AGG_SIZE_LIMIT(1) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
140 (MT_AGG_SIZE_LIMIT(2) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
141 (MT_AGG_SIZE_LIMIT(3) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT));
142
143 mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_1,
144 (MT_AGG_SIZE_LIMIT(4) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
145 (MT_AGG_SIZE_LIMIT(5) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
146 (MT_AGG_SIZE_LIMIT(6) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
147 (MT_AGG_SIZE_LIMIT(7) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT));
148
149 mt76_wr(dev, MT_AGG_LIMIT,
150 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |
151 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) |
152 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) |
153 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24));
154
155 mt76_wr(dev, MT_AGG_LIMIT_1,
156 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |
157 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) |
158 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) |
159 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24));
160
161 mt76_wr(dev, MT_AGG_CONTROL,
162 FIELD_PREP(MT_AGG_CONTROL_BAR_RATE, 0x4b) |
163 FIELD_PREP(MT_AGG_CONTROL_CFEND_RATE, 0x69) |
164 MT_AGG_CONTROL_NO_BA_AR_RULE);
165
166 mt76_wr(dev, MT_AGG_RETRY_CONTROL,
167 FIELD_PREP(MT_AGG_RETRY_CONTROL_BAR_LIMIT, 1) |
168 FIELD_PREP(MT_AGG_RETRY_CONTROL_RTS_LIMIT, 15));
169
170 mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP |
171 FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 4096));
172
173 mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13));
174 mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13));
175
176 mt76_clear(dev, MT_WF_RMAC_TMR_PA, BIT(31));
177
178 mt76_set(dev, MT_WF_RMACDR, MT_WF_RMACDR_MAXLEN_20BIT);
179 mt76_rmw(dev, MT_WF_RMAC_MAXMINLEN, 0xffffff, 0x19000);
180
181 mt76_wr(dev, MT_WF_RFCR1, 0);
182
183 mt76_set(dev, MT_TMAC_TCR, MT_TMAC_TCR_RX_RIFS_MODE);
184
185 mt7603_set_tmac_template(dev);
186
187
188 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR);
189 mt76_set(dev, addr + MT_CLIENT_RXINF, MT_CLIENT_RXINF_RXSH_GROUPS);
190
191
192 mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11));
193
194 mt76_rmw_field(dev, MT_AGG_PCR_RTS, MT_AGG_PCR_RTS_PKT_THR, 3);
195 mt76_set(dev, MT_TMAC_PCR, MT_TMAC_PCR_SPE_EN);
196
197
198 mt76_rmw_field(dev, MT_TXREQ, MT_TXREQ_CCA_SRC_SEL, 2);
199
200 mt76_wr(dev, MT_RXREQ, 4);
201
202
203 mt76_wr(dev, MT_DMA_RCFR0, 0xc0000000);
204
205
206 mt76_wr(dev, MT_DMA_TCFR0,
207 FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) |
208 MT_DMA_TCFR_TXS_AGGR_COUNT);
209
210
211 mt76_wr(dev, MT_DMA_TCFR1,
212 FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) |
213 MT_DMA_TCFR_TXS_AGGR_COUNT |
214 MT_DMA_TCFR_TXS_BIT_MAP);
215
216 mt76_wr(dev, MT_MCU_PCIE_REMAP_1, MT_PSE_WTBL_2_PHYS_ADDR);
217
218 for (i = 0; i < MT7603_WTBL_SIZE; i++)
219 mt7603_wtbl_clear(dev, i);
220
221 eth_broadcast_addr(bc_addr);
222 mt7603_wtbl_init(dev, MT7603_WTBL_RESERVED, -1, bc_addr);
223 dev->global_sta.wcid.idx = MT7603_WTBL_RESERVED;
224 rcu_assign_pointer(dev->mt76.wcid[MT7603_WTBL_RESERVED],
225 &dev->global_sta.wcid);
226
227 mt76_rmw_field(dev, MT_LPON_BTEIR, MT_LPON_BTEIR_MBSS_MODE, 2);
228 mt76_rmw_field(dev, MT_WF_RMACDR, MT_WF_RMACDR_MBSSID_MASK, 2);
229
230 mt76_wr(dev, MT_AGG_ARUCR,
231 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) |
232 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) |
233 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) |
234 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) |
235 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) |
236 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) |
237 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) |
238 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1));
239
240 mt76_wr(dev, MT_AGG_ARDCR,
241 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) |
242 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7603_RATE_RETRY - 1) |
243 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7603_RATE_RETRY - 1) |
244 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7603_RATE_RETRY - 1) |
245 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7603_RATE_RETRY - 1) |
246 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7603_RATE_RETRY - 1) |
247 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7603_RATE_RETRY - 1) |
248 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7603_RATE_RETRY - 1));
249
250 mt76_wr(dev, MT_AGG_ARCR,
251 (FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) |
252 MT_AGG_ARCR_RATE_DOWN_RATIO_EN |
253 FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) |
254 FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4)));
255
256 mt76_set(dev, MT_WTBL_RMVTCR, MT_WTBL_RMVTCR_RX_MV_MODE);
257
258 mt76_clear(dev, MT_SEC_SCR, MT_SEC_SCR_MASK_ORDER);
259 mt76_clear(dev, MT_SEC_SCR, BIT(18));
260
261
262 for (i = 0; i <= 4; i++)
263 mt76_rmw_field(dev, MT_LPON_SBTOR(i), MT_LPON_SBTOR_TIME_OFFSET,
264 (i + 1) * (20 + 4096));
265 }
266
267 static int
268 mt7603_init_hardware(struct mt7603_dev *dev)
269 {
270 int i, ret;
271
272 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
273
274 ret = mt7603_eeprom_init(dev);
275 if (ret < 0)
276 return ret;
277
278 ret = mt7603_dma_init(dev);
279 if (ret)
280 return ret;
281
282 mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850);
283 mt7603_mac_dma_start(dev);
284 dev->rxfilter = mt76_rr(dev, MT_WF_RFCR);
285 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
286
287 for (i = 0; i < MT7603_WTBL_SIZE; i++) {
288 mt76_wr(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY | MT_PSE_RTA_WRITE |
289 FIELD_PREP(MT_PSE_RTA_TAG_ID, i));
290 mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);
291 }
292
293 ret = mt7603_mcu_init(dev);
294 if (ret)
295 return ret;
296
297 mt7603_dma_sched_init(dev);
298 mt7603_mcu_set_eeprom(dev);
299 mt7603_phy_init(dev);
300 mt7603_mac_init(dev);
301
302 return 0;
303 }
304
305 #define CCK_RATE(_idx, _rate) { \
306 .bitrate = _rate, \
307 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
308 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
309 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \
310 }
311
312 #define OFDM_RATE(_idx, _rate) { \
313 .bitrate = _rate, \
314 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
315 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
316 }
317
318 static struct ieee80211_rate mt7603_rates[] = {
319 CCK_RATE(0, 10),
320 CCK_RATE(1, 20),
321 CCK_RATE(2, 55),
322 CCK_RATE(3, 110),
323 OFDM_RATE(11, 60),
324 OFDM_RATE(15, 90),
325 OFDM_RATE(10, 120),
326 OFDM_RATE(14, 180),
327 OFDM_RATE(9, 240),
328 OFDM_RATE(13, 360),
329 OFDM_RATE(8, 480),
330 OFDM_RATE(12, 540),
331 };
332
333 static const struct ieee80211_iface_limit if_limits[] = {
334 {
335 .max = 1,
336 .types = BIT(NL80211_IFTYPE_ADHOC)
337 }, {
338 .max = MT7603_MAX_INTERFACES,
339 .types = BIT(NL80211_IFTYPE_STATION) |
340 #ifdef CONFIG_MAC80211_MESH
341 BIT(NL80211_IFTYPE_MESH_POINT) |
342 #endif
343 BIT(NL80211_IFTYPE_AP)
344 },
345 };
346
347 static const struct ieee80211_iface_combination if_comb[] = {
348 {
349 .limits = if_limits,
350 .n_limits = ARRAY_SIZE(if_limits),
351 .max_interfaces = 4,
352 .num_different_channels = 1,
353 .beacon_int_infra_match = true,
354 }
355 };
356
357 static void mt7603_led_set_config(struct mt76_dev *mt76, u8 delay_on,
358 u8 delay_off)
359 {
360 struct mt7603_dev *dev = container_of(mt76, struct mt7603_dev,
361 mt76);
362 u32 val, addr;
363
364 val = MT_LED_STATUS_DURATION(0xffff) |
365 MT_LED_STATUS_OFF(delay_off) |
366 MT_LED_STATUS_ON(delay_on);
367
368 addr = mt7603_reg_map(dev, MT_LED_STATUS_0(mt76->led_pin));
369 mt76_wr(dev, addr, val);
370 addr = mt7603_reg_map(dev, MT_LED_STATUS_1(mt76->led_pin));
371 mt76_wr(dev, addr, val);
372
373 val = MT_LED_CTRL_REPLAY(mt76->led_pin) |
374 MT_LED_CTRL_KICK(mt76->led_pin);
375 if (mt76->led_al)
376 val |= MT_LED_CTRL_POLARITY(mt76->led_pin);
377 addr = mt7603_reg_map(dev, MT_LED_CTRL);
378 mt76_wr(dev, addr, val);
379 }
380
381 static int mt7603_led_set_blink(struct led_classdev *led_cdev,
382 unsigned long *delay_on,
383 unsigned long *delay_off)
384 {
385 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
386 led_cdev);
387 u8 delta_on, delta_off;
388
389 delta_off = max_t(u8, *delay_off / 10, 1);
390 delta_on = max_t(u8, *delay_on / 10, 1);
391
392 mt7603_led_set_config(mt76, delta_on, delta_off);
393 return 0;
394 }
395
396 static void mt7603_led_set_brightness(struct led_classdev *led_cdev,
397 enum led_brightness brightness)
398 {
399 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
400 led_cdev);
401
402 if (!brightness)
403 mt7603_led_set_config(mt76, 0, 0xff);
404 else
405 mt7603_led_set_config(mt76, 0xff, 0);
406 }
407
408 static u32 __mt7603_reg_addr(struct mt7603_dev *dev, u32 addr)
409 {
410 if (addr < 0x100000)
411 return addr;
412
413 return mt7603_reg_map(dev, addr);
414 }
415
416 static u32 mt7603_rr(struct mt76_dev *mdev, u32 offset)
417 {
418 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
419 u32 addr = __mt7603_reg_addr(dev, offset);
420
421 return dev->bus_ops->rr(mdev, addr);
422 }
423
424 static void mt7603_wr(struct mt76_dev *mdev, u32 offset, u32 val)
425 {
426 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
427 u32 addr = __mt7603_reg_addr(dev, offset);
428
429 dev->bus_ops->wr(mdev, addr, val);
430 }
431
432 static u32 mt7603_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
433 {
434 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
435 u32 addr = __mt7603_reg_addr(dev, offset);
436
437 return dev->bus_ops->rmw(mdev, addr, mask, val);
438 }
439
440 static void
441 mt7603_regd_notifier(struct wiphy *wiphy,
442 struct regulatory_request *request)
443 {
444 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
445 struct mt7603_dev *dev = hw->priv;
446
447 dev->mt76.region = request->dfs_region;
448 dev->ed_monitor = dev->ed_monitor_enabled &&
449 dev->mt76.region == NL80211_DFS_ETSI;
450 }
451
452 static int
453 mt7603_txpower_signed(int val)
454 {
455 bool sign = val & BIT(6);
456
457 if (!(val & BIT(7)))
458 return 0;
459
460 val &= GENMASK(5, 0);
461 if (!sign)
462 val = -val;
463
464 return val;
465 }
466
467 static void
468 mt7603_init_txpower(struct mt7603_dev *dev,
469 struct ieee80211_supported_band *sband)
470 {
471 struct ieee80211_channel *chan;
472 u8 *eeprom = (u8 *)dev->mt76.eeprom.data;
473 int target_power = eeprom[MT_EE_TX_POWER_0_START_2G + 2] & ~BIT(7);
474 u8 *rate_power = &eeprom[MT_EE_TX_POWER_CCK];
475 bool ext_pa = eeprom[MT_EE_NIC_CONF_0 + 1] & BIT(1);
476 int max_offset, cur_offset;
477 int i;
478
479 if (ext_pa && is_mt7603(dev))
480 target_power = eeprom[MT_EE_TX_POWER_TSSI_OFF] & ~BIT(7);
481
482 if (target_power & BIT(6))
483 target_power = -(target_power & GENMASK(5, 0));
484
485 max_offset = 0;
486 for (i = 0; i < 14; i++) {
487 cur_offset = mt7603_txpower_signed(rate_power[i]);
488 max_offset = max(max_offset, cur_offset);
489 }
490
491 target_power += max_offset;
492
493 dev->tx_power_limit = target_power;
494 dev->mt76.txpower_cur = target_power;
495
496 target_power = DIV_ROUND_UP(target_power, 2);
497
498
499 if (dev->mt76.antenna_mask & BIT(1))
500 target_power += 3;
501
502 for (i = 0; i < sband->n_channels; i++) {
503 chan = &sband->channels[i];
504 chan->max_power = min_t(int, chan->max_reg_power, target_power);
505 chan->orig_mpwr = target_power;
506 }
507 }
508
509 int mt7603_register_device(struct mt7603_dev *dev)
510 {
511 struct mt76_bus_ops *bus_ops;
512 struct ieee80211_hw *hw = mt76_hw(dev);
513 struct wiphy *wiphy = hw->wiphy;
514 int ret;
515
516 dev->bus_ops = dev->mt76.bus;
517 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
518 GFP_KERNEL);
519 if (!bus_ops)
520 return -ENOMEM;
521
522 bus_ops->rr = mt7603_rr;
523 bus_ops->wr = mt7603_wr;
524 bus_ops->rmw = mt7603_rmw;
525 dev->mt76.bus = bus_ops;
526
527 spin_lock_init(&dev->ps_lock);
528
529 INIT_DELAYED_WORK(&dev->mt76.mac_work, mt7603_mac_work);
530 tasklet_init(&dev->mt76.pre_tbtt_tasklet, mt7603_pre_tbtt_tasklet,
531 (unsigned long)dev);
532
533
534 dev->mt76.antenna_mask = 3;
535 if (mt76_rr(dev, MT_EFUSE_BASE + 0x64) & BIT(4))
536 dev->mt76.antenna_mask = 1;
537
538 dev->slottime = 9;
539
540 ret = mt7603_init_hardware(dev);
541 if (ret)
542 return ret;
543
544 hw->queues = 4;
545 hw->max_rates = 3;
546 hw->max_report_rates = 7;
547 hw->max_rate_tries = 11;
548
549 hw->sta_data_size = sizeof(struct mt7603_sta);
550 hw->vif_data_size = sizeof(struct mt7603_vif);
551
552 wiphy->iface_combinations = if_comb;
553 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
554
555 ieee80211_hw_set(hw, SUPPORTS_REORDERING_BUFFER);
556 ieee80211_hw_set(hw, TX_STATUS_NO_AMPDU_LEN);
557
558
559 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
560 dev->mt76.led_cdev.brightness_set = mt7603_led_set_brightness;
561 dev->mt76.led_cdev.blink_set = mt7603_led_set_blink;
562 }
563
564 wiphy->interface_modes =
565 BIT(NL80211_IFTYPE_STATION) |
566 BIT(NL80211_IFTYPE_AP) |
567 #ifdef CONFIG_MAC80211_MESH
568 BIT(NL80211_IFTYPE_MESH_POINT) |
569 #endif
570 BIT(NL80211_IFTYPE_ADHOC);
571
572 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
573
574 wiphy->reg_notifier = mt7603_regd_notifier;
575
576 ret = mt76_register_device(&dev->mt76, true, mt7603_rates,
577 ARRAY_SIZE(mt7603_rates));
578 if (ret)
579 return ret;
580
581 mt7603_init_debugfs(dev);
582 mt7603_init_txpower(dev, &dev->mt76.sband_2g.sband);
583
584 return 0;
585 }
586
587 void mt7603_unregister_device(struct mt7603_dev *dev)
588 {
589 tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
590 mt76_unregister_device(&dev->mt76);
591 mt7603_mcu_exit(dev);
592 mt7603_dma_cleanup(dev);
593 mt76_free_device(&dev->mt76);
594 }