root/drivers/net/wireless/mediatek/mt76/mt7615/mac.h

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INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. mt7615_txwi_to_txp

   1 /* SPDX-License-Identifier: ISC */
   2 /* Copyright (C) 2019 MediaTek Inc. */
   3 
   4 #ifndef __MT7615_MAC_H
   5 #define __MT7615_MAC_H
   6 
   7 #define MT_CT_PARSE_LEN                 72
   8 #define MT_CT_DMA_BUF_NUM               2
   9 
  10 #define MT_RXD0_LENGTH                  GENMASK(15, 0)
  11 #define MT_RXD0_PKT_TYPE                GENMASK(31, 29)
  12 
  13 #define MT_RXD0_NORMAL_ETH_TYPE_OFS     GENMASK(22, 16)
  14 #define MT_RXD0_NORMAL_IP_SUM           BIT(23)
  15 #define MT_RXD0_NORMAL_UDP_TCP_SUM      BIT(24)
  16 #define MT_RXD0_NORMAL_GROUP_1          BIT(25)
  17 #define MT_RXD0_NORMAL_GROUP_2          BIT(26)
  18 #define MT_RXD0_NORMAL_GROUP_3          BIT(27)
  19 #define MT_RXD0_NORMAL_GROUP_4          BIT(28)
  20 
  21 enum rx_pkt_type {
  22         PKT_TYPE_TXS,
  23         PKT_TYPE_TXRXV,
  24         PKT_TYPE_NORMAL,
  25         PKT_TYPE_RX_DUP_RFB,
  26         PKT_TYPE_RX_TMR,
  27         PKT_TYPE_RETRIEVE,
  28         PKT_TYPE_TXRX_NOTIFY,
  29         PKT_TYPE_RX_EVENT
  30 };
  31 
  32 #define MT_RXD1_NORMAL_BSSID            GENMASK(31, 26)
  33 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT   GENMASK(25, 24)
  34 #define MT_RXD1_NORMAL_HDR_TRANS        BIT(23)
  35 #define MT_RXD1_NORMAL_HDR_OFFSET       BIT(22)
  36 #define MT_RXD1_NORMAL_MAC_HDR_LEN      GENMASK(21, 16)
  37 #define MT_RXD1_NORMAL_CH_FREQ          GENMASK(15, 8)
  38 #define MT_RXD1_NORMAL_KEY_ID           GENMASK(7, 6)
  39 #define MT_RXD1_NORMAL_BEACON_UC        BIT(5)
  40 #define MT_RXD1_NORMAL_BEACON_MC        BIT(4)
  41 #define MT_RXD1_NORMAL_BF_REPORT        BIT(3)
  42 #define MT_RXD1_NORMAL_ADDR_TYPE        GENMASK(2, 1)
  43 #define MT_RXD1_NORMAL_BCAST            GENMASK(2, 1)
  44 #define MT_RXD1_NORMAL_MCAST            BIT(2)
  45 #define MT_RXD1_NORMAL_U2M              BIT(1)
  46 #define MT_RXD1_NORMAL_HTC_VLD          BIT(0)
  47 
  48 #define MT_RXD2_NORMAL_NON_AMPDU        BIT(31)
  49 #define MT_RXD2_NORMAL_NON_AMPDU_SUB    BIT(30)
  50 #define MT_RXD2_NORMAL_NDATA            BIT(29)
  51 #define MT_RXD2_NORMAL_NULL_FRAME       BIT(28)
  52 #define MT_RXD2_NORMAL_FRAG             BIT(27)
  53 #define MT_RXD2_NORMAL_INT_FRAME        BIT(26)
  54 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR  BIT(25)
  55 #define MT_RXD2_NORMAL_MAX_LEN_ERROR    BIT(24)
  56 #define MT_RXD2_NORMAL_AMSDU_ERR        BIT(23)
  57 #define MT_RXD2_NORMAL_LEN_MISMATCH     BIT(22)
  58 #define MT_RXD2_NORMAL_TKIP_MIC_ERR     BIT(21)
  59 #define MT_RXD2_NORMAL_ICV_ERR          BIT(20)
  60 #define MT_RXD2_NORMAL_CLM              BIT(19)
  61 #define MT_RXD2_NORMAL_CM               BIT(18)
  62 #define MT_RXD2_NORMAL_FCS_ERR          BIT(17)
  63 #define MT_RXD2_NORMAL_SW_BIT           BIT(16)
  64 #define MT_RXD2_NORMAL_SEC_MODE         GENMASK(15, 12)
  65 #define MT_RXD2_NORMAL_TID              GENMASK(11, 8)
  66 #define MT_RXD2_NORMAL_WLAN_IDX         GENMASK(7, 0)
  67 
  68 #define MT_RXD3_NORMAL_PF_STS           GENMASK(31, 30)
  69 #define MT_RXD3_NORMAL_PF_MODE          BIT(29)
  70 #define MT_RXD3_NORMAL_CLS_BITMAP       GENMASK(28, 19)
  71 #define MT_RXD3_NORMAL_WOL              GENMASK(18, 14)
  72 #define MT_RXD3_NORMAL_MAGIC_PKT        BIT(13)
  73 #define MT_RXD3_NORMAL_OFLD             GENMASK(12, 11)
  74 #define MT_RXD3_NORMAL_CLS              BIT(10)
  75 #define MT_RXD3_NORMAL_PATTERN_DROP     BIT(9)
  76 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(8)
  77 #define MT_RXD3_NORMAL_RXV_SEQ          GENMASK(7, 0)
  78 
  79 #define MT_RXV1_ACID_DET_H              BIT(31)
  80 #define MT_RXV1_ACID_DET_L              BIT(30)
  81 #define MT_RXV1_VHTA2_B8_B3             GENMASK(29, 24)
  82 #define MT_RXV1_NUM_RX                  GENMASK(23, 22)
  83 #define MT_RXV1_HT_NO_SOUND             BIT(21)
  84 #define MT_RXV1_HT_SMOOTH               BIT(20)
  85 #define MT_RXV1_HT_SHORT_GI             BIT(19)
  86 #define MT_RXV1_HT_AGGR                 BIT(18)
  87 #define MT_RXV1_VHTA1_B22               BIT(17)
  88 #define MT_RXV1_FRAME_MODE              GENMASK(16, 15)
  89 #define MT_RXV1_TX_MODE                 GENMASK(14, 12)
  90 #define MT_RXV1_HT_EXT_LTF              GENMASK(11, 10)
  91 #define MT_RXV1_HT_AD_CODE              BIT(9)
  92 #define MT_RXV1_HT_STBC                 GENMASK(8, 7)
  93 #define MT_RXV1_TX_RATE                 GENMASK(6, 0)
  94 
  95 #define MT_RXV2_SEL_ANT                 BIT(31)
  96 #define MT_RXV2_VALID_BIT               BIT(30)
  97 #define MT_RXV2_NSTS                    GENMASK(29, 27)
  98 #define MT_RXV2_GROUP_ID                GENMASK(26, 21)
  99 #define MT_RXV2_LENGTH                  GENMASK(20, 0)
 100 
 101 #define MT_RXV4_RCPI3                   GENMASK(31, 24)
 102 #define MT_RXV4_RCPI2                   GENMASK(23, 16)
 103 #define MT_RXV4_RCPI1                   GENMASK(15, 8)
 104 #define MT_RXV4_RCPI0                   GENMASK(7, 0)
 105 
 106 enum tx_header_format {
 107         MT_HDR_FORMAT_802_3,
 108         MT_HDR_FORMAT_CMD,
 109         MT_HDR_FORMAT_802_11,
 110         MT_HDR_FORMAT_802_11_EXT,
 111 };
 112 
 113 enum tx_pkt_type {
 114         MT_TX_TYPE_CT,
 115         MT_TX_TYPE_SF,
 116         MT_TX_TYPE_CMD,
 117         MT_TX_TYPE_FW,
 118 };
 119 
 120 enum tx_pkt_queue_idx {
 121         MT_LMAC_AC00,
 122         MT_LMAC_AC01,
 123         MT_LMAC_AC02,
 124         MT_LMAC_AC03,
 125         MT_LMAC_ALTX0 = 0x10,
 126         MT_LMAC_BMC0,
 127         MT_LMAC_BCN0,
 128         MT_LMAC_PSMP0,
 129 };
 130 
 131 enum tx_port_idx {
 132         MT_TX_PORT_IDX_LMAC,
 133         MT_TX_PORT_IDX_MCU
 134 };
 135 
 136 enum tx_mcu_port_q_idx {
 137         MT_TX_MCU_PORT_RX_Q0 = 0,
 138         MT_TX_MCU_PORT_RX_Q1,
 139         MT_TX_MCU_PORT_RX_Q2,
 140         MT_TX_MCU_PORT_RX_Q3,
 141         MT_TX_MCU_PORT_RX_FWDL = 0x1e
 142 };
 143 
 144 enum tx_phy_bandwidth {
 145         MT_PHY_BW_20,
 146         MT_PHY_BW_40,
 147         MT_PHY_BW_80,
 148         MT_PHY_BW_160,
 149 };
 150 
 151 #define MT_CT_INFO_APPLY_TXD            BIT(0)
 152 #define MT_CT_INFO_COPY_HOST_TXD_ALL    BIT(1)
 153 #define MT_CT_INFO_MGMT_FRAME           BIT(2)
 154 #define MT_CT_INFO_NONE_CIPHER_FRAME    BIT(3)
 155 #define MT_CT_INFO_HSR2_TX              BIT(4)
 156 
 157 #define MT_TXD_SIZE                     (8 * 4)
 158 
 159 #define MT_TXD0_P_IDX                   BIT(31)
 160 #define MT_TXD0_Q_IDX                   GENMASK(30, 26)
 161 #define MT_TXD0_UDP_TCP_SUM             BIT(24)
 162 #define MT_TXD0_IP_SUM                  BIT(23)
 163 #define MT_TXD0_ETH_TYPE_OFFSET         GENMASK(22, 16)
 164 #define MT_TXD0_TX_BYTES                GENMASK(15, 0)
 165 
 166 #define MT_TXD1_OWN_MAC                 GENMASK(31, 26)
 167 #define MT_TXD1_PKT_FMT                 GENMASK(25, 24)
 168 #define MT_TXD1_TID                     GENMASK(23, 21)
 169 #define MT_TXD1_AMSDU                   BIT(20)
 170 #define MT_TXD1_UNXV                    BIT(19)
 171 #define MT_TXD1_HDR_PAD                 GENMASK(18, 17)
 172 #define MT_TXD1_TXD_LEN                 BIT(16)
 173 #define MT_TXD1_LONG_FORMAT             BIT(15)
 174 #define MT_TXD1_HDR_FORMAT              GENMASK(14, 13)
 175 #define MT_TXD1_HDR_INFO                GENMASK(12, 8)
 176 #define MT_TXD1_WLAN_IDX                GENMASK(7, 0)
 177 
 178 #define MT_TXD2_FIX_RATE                BIT(31)
 179 #define MT_TXD2_TIMING_MEASURE          BIT(30)
 180 #define MT_TXD2_BA_DISABLE              BIT(29)
 181 #define MT_TXD2_POWER_OFFSET            GENMASK(28, 24)
 182 #define MT_TXD2_MAX_TX_TIME             GENMASK(23, 16)
 183 #define MT_TXD2_FRAG                    GENMASK(15, 14)
 184 #define MT_TXD2_HTC_VLD                 BIT(13)
 185 #define MT_TXD2_DURATION                BIT(12)
 186 #define MT_TXD2_BIP                     BIT(11)
 187 #define MT_TXD2_MULTICAST               BIT(10)
 188 #define MT_TXD2_RTS                     BIT(9)
 189 #define MT_TXD2_SOUNDING                BIT(8)
 190 #define MT_TXD2_NDPA                    BIT(7)
 191 #define MT_TXD2_NDP                     BIT(6)
 192 #define MT_TXD2_FRAME_TYPE              GENMASK(5, 4)
 193 #define MT_TXD2_SUB_TYPE                GENMASK(3, 0)
 194 
 195 #define MT_TXD3_SN_VALID                BIT(31)
 196 #define MT_TXD3_PN_VALID                BIT(30)
 197 #define MT_TXD3_SEQ                     GENMASK(27, 16)
 198 #define MT_TXD3_REM_TX_COUNT            GENMASK(15, 11)
 199 #define MT_TXD3_TX_COUNT                GENMASK(10, 6)
 200 #define MT_TXD3_PROTECT_FRAME           BIT(1)
 201 #define MT_TXD3_NO_ACK                  BIT(0)
 202 
 203 #define MT_TXD4_PN_LOW                  GENMASK(31, 0)
 204 
 205 #define MT_TXD5_PN_HIGH                 GENMASK(31, 16)
 206 #define MT_TXD5_SW_POWER_MGMT           BIT(13)
 207 #define MT_TXD5_DA_SELECT               BIT(11)
 208 #define MT_TXD5_TX_STATUS_HOST          BIT(10)
 209 #define MT_TXD5_TX_STATUS_MCU           BIT(9)
 210 #define MT_TXD5_TX_STATUS_FMT           BIT(8)
 211 #define MT_TXD5_PID                     GENMASK(7, 0)
 212 
 213 #define MT_TXD6_FIXED_RATE              BIT(31)
 214 #define MT_TXD6_SGI                     BIT(30)
 215 #define MT_TXD6_LDPC                    BIT(29)
 216 #define MT_TXD6_TX_BF                   BIT(28)
 217 #define MT_TXD6_TX_RATE                 GENMASK(27, 16)
 218 #define MT_TXD6_ANT_ID                  GENMASK(15, 4)
 219 #define MT_TXD6_DYN_BW                  BIT(3)
 220 #define MT_TXD6_FIXED_BW                BIT(2)
 221 #define MT_TXD6_BW                      GENMASK(1, 0)
 222 
 223 #define MT_TXD7_TYPE                    GENMASK(21, 20)
 224 #define MT_TXD7_SUB_TYPE                GENMASK(19, 16)
 225 
 226 #define MT_TX_RATE_STBC                 BIT(11)
 227 #define MT_TX_RATE_NSS                  GENMASK(10, 9)
 228 #define MT_TX_RATE_MODE                 GENMASK(8, 6)
 229 #define MT_TX_RATE_IDX                  GENMASK(5, 0)
 230 
 231 #define MT_TXP_MAX_BUF_NUM              6
 232 
 233 struct mt7615_txp {
 234         __le16 flags;
 235         __le16 token;
 236         u8 bss_idx;
 237         u8 rept_wds_wcid;
 238         u8 rsv;
 239         u8 nbuf;
 240         __le32 buf[MT_TXP_MAX_BUF_NUM];
 241         __le16 len[MT_TXP_MAX_BUF_NUM];
 242 } __packed;
 243 
 244 struct mt7615_tx_free {
 245         __le16 rx_byte_cnt;
 246         __le16 ctrl;
 247         u8 txd_cnt;
 248         u8 rsv[3];
 249         __le16 token[];
 250 } __packed;
 251 
 252 #define MT_TX_FREE_MSDU_ID_CNT          GENMASK(6, 0)
 253 
 254 #define MT_TXS0_PID                     GENMASK(31, 24)
 255 #define MT_TXS0_BA_ERROR                BIT(22)
 256 #define MT_TXS0_PS_FLAG                 BIT(21)
 257 #define MT_TXS0_TXOP_TIMEOUT            BIT(20)
 258 #define MT_TXS0_BIP_ERROR               BIT(19)
 259 
 260 #define MT_TXS0_QUEUE_TIMEOUT           BIT(18)
 261 #define MT_TXS0_RTS_TIMEOUT             BIT(17)
 262 #define MT_TXS0_ACK_TIMEOUT             BIT(16)
 263 #define MT_TXS0_ACK_ERROR_MASK          GENMASK(18, 16)
 264 
 265 #define MT_TXS0_TX_STATUS_HOST          BIT(15)
 266 #define MT_TXS0_TX_STATUS_MCU           BIT(14)
 267 #define MT_TXS0_TXS_FORMAT              BIT(13)
 268 #define MT_TXS0_FIXED_RATE              BIT(12)
 269 #define MT_TXS0_TX_RATE                 GENMASK(11, 0)
 270 
 271 #define MT_TXS1_ANT_ID                  GENMASK(31, 20)
 272 #define MT_TXS1_RESP_RATE               GENMASK(19, 16)
 273 #define MT_TXS1_BW                      GENMASK(15, 14)
 274 #define MT_TXS1_I_TXBF                  BIT(13)
 275 #define MT_TXS1_E_TXBF                  BIT(12)
 276 #define MT_TXS1_TID                     GENMASK(11, 9)
 277 #define MT_TXS1_AMPDU                   BIT(8)
 278 #define MT_TXS1_ACKED_MPDU              BIT(7)
 279 #define MT_TXS1_TX_POWER_DBM            GENMASK(6, 0)
 280 
 281 #define MT_TXS2_WCID                    GENMASK(31, 24)
 282 #define MT_TXS2_RXV_SEQNO               GENMASK(23, 16)
 283 #define MT_TXS2_TX_DELAY                GENMASK(15, 0)
 284 
 285 #define MT_TXS3_LAST_TX_RATE            GENMASK(31, 29)
 286 #define MT_TXS3_TX_COUNT                GENMASK(28, 24)
 287 #define MT_TXS3_F1_TSSI1                GENMASK(23, 12)
 288 #define MT_TXS3_F1_TSSI0                GENMASK(11, 0)
 289 #define MT_TXS3_F0_SEQNO                GENMASK(11, 0)
 290 
 291 #define MT_TXS4_F0_TIMESTAMP            GENMASK(31, 0)
 292 #define MT_TXS4_F1_TSSI3                GENMASK(23, 12)
 293 #define MT_TXS4_F1_TSSI2                GENMASK(11, 0)
 294 
 295 #define MT_TXS5_F0_FRONT_TIME           GENMASK(24, 0)
 296 #define MT_TXS5_F1_NOISE_2              GENMASK(23, 16)
 297 #define MT_TXS5_F1_NOISE_1              GENMASK(15, 8)
 298 #define MT_TXS5_F1_NOISE_0              GENMASK(7, 0)
 299 
 300 #define MT_TXS6_F1_RCPI_3               GENMASK(31, 24)
 301 #define MT_TXS6_F1_RCPI_2               GENMASK(23, 16)
 302 #define MT_TXS6_F1_RCPI_1               GENMASK(15, 8)
 303 #define MT_TXS6_F1_RCPI_0               GENMASK(7, 0)
 304 
 305 enum mt7615_cipher_type {
 306         MT_CIPHER_NONE,
 307         MT_CIPHER_WEP40,
 308         MT_CIPHER_TKIP,
 309         MT_CIPHER_TKIP_NO_MIC,
 310         MT_CIPHER_AES_CCMP,
 311         MT_CIPHER_WEP104,
 312         MT_CIPHER_BIP_CMAC_128,
 313         MT_CIPHER_WEP128,
 314         MT_CIPHER_WAPI,
 315         MT_CIPHER_CCMP_256 = 10,
 316         MT_CIPHER_GCMP,
 317         MT_CIPHER_GCMP_256,
 318 };
 319 
 320 static inline struct mt7615_txp *
 321 mt7615_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
 322 {
 323         u8 *txwi;
 324 
 325         if (!t)
 326                 return NULL;
 327 
 328         txwi = mt76_get_txwi_ptr(dev, t);
 329 
 330         return (struct mt7615_txp *)(txwi + MT_TXD_SIZE);
 331 }
 332 
 333 #endif

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