1
2
3
4 #ifndef __MT7615_REGS_H
5 #define __MT7615_REGS_H
6
7 #define MT_HW_REV 0x1000
8 #define MT_HW_CHIPID 0x1008
9 #define MT_TOP_MISC2 0x1134
10 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
11
12 #define MT_MCU_BASE 0x2000
13 #define MT_MCU(ofs) (MT_MCU_BASE + (ofs))
14
15 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
16 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
17 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
18 #define MT_PCIE_REMAP_BASE_1 0x40000
19
20 #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504)
21 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
22 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
23 #define MT_PCIE_REMAP_BASE_2 0x80000
24
25 #define MT_HIF_BASE 0x4000
26 #define MT_HIF(ofs) (MT_HIF_BASE + (ofs))
27
28 #define MT_CFG_LPCR_HOST MT_HIF(0x1f0)
29 #define MT_CFG_LPCR_HOST_FW_OWN BIT(0)
30 #define MT_CFG_LPCR_HOST_DRV_OWN BIT(1)
31
32 #define MT_INT_SOURCE_CSR MT_HIF(0x200)
33 #define MT_INT_MASK_CSR MT_HIF(0x204)
34 #define MT_DELAY_INT_CFG MT_HIF(0x210)
35
36 #define MT_INT_RX_DONE(_n) BIT(_n)
37 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
38 #define MT_INT_TX_DONE_ALL GENMASK(7, 4)
39 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
40
41 #define MT_WPDMA_GLO_CFG MT_HIF(0x208)
42 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
43 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
44 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
45 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
46 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
47 #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)
48 #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
49 #define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0 BIT(9)
50 #define MT_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10)
51 #define MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
52 #define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21 GENMASK(23, 22)
53 #define MT_WPDMA_GLO_CFG_SW_RESET BIT(24)
54 #define MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
55 #define MT_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28)
56
57 #define MT_WPDMA_RST_IDX MT_HIF(0x20c)
58
59 #define MT_TX_RING_BASE MT_HIF(0x300)
60 #define MT_RX_RING_BASE MT_HIF(0x400)
61
62 #define MT_WPDMA_GLO_CFG1 MT_HIF(0x500)
63 #define MT_WPDMA_TX_PRE_CFG MT_HIF(0x510)
64 #define MT_WPDMA_RX_PRE_CFG MT_HIF(0x520)
65 #define MT_WPDMA_ABT_CFG MT_HIF(0x530)
66 #define MT_WPDMA_ABT_CFG1 MT_HIF(0x534)
67
68 #define MT_WF_PHY_BASE 0x10000
69 #define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs))
70
71 #define MT_WF_PHY_WF2_RFCTRL0 MT_WF_PHY(0x1900)
72 #define MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN BIT(9)
73
74 #define MT_WF_PHY_R0_B0_PHYMUX_5 MT_WF_PHY(0x0614)
75
76 #define MT_WF_PHY_R0_B0_PHYCTRL_STS0 MT_WF_PHY(0x020c)
77 #define MT_WF_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16)
78 #define MT_WF_PHYCTRL_STAT_PD_CCK GENMASK(15, 0)
79
80 #define MT_WF_PHY_R0_B0_PHYCTRL_STS5 MT_WF_PHY(0x0220)
81 #define MT_WF_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16)
82 #define MT_WF_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0)
83
84 #define MT_WF_PHY_B0_MIN_PRI_PWR MT_WF_PHY(0x229c)
85 #define MT_WF_PHY_B0_PD_OFDM_MASK GENMASK(28, 20)
86 #define MT_WF_PHY_B0_PD_OFDM(v) ((v) << 20)
87 #define MT_WF_PHY_B0_PD_BLK BIT(19)
88
89 #define MT_WF_PHY_B1_MIN_PRI_PWR MT_WF_PHY(0x084)
90 #define MT_WF_PHY_B1_PD_OFDM_MASK GENMASK(24, 16)
91 #define MT_WF_PHY_B1_PD_OFDM(v) ((v) << 16)
92 #define MT_WF_PHY_B1_PD_BLK BIT(25)
93
94 #define MT_WF_PHY_B0_RXTD_CCK_PD MT_WF_PHY(0x2310)
95 #define MT_WF_PHY_B0_PD_CCK_MASK GENMASK(8, 1)
96 #define MT_WF_PHY_B0_PD_CCK(v) ((v) << 1)
97
98 #define MT_WF_PHY_B1_RXTD_CCK_PD MT_WF_PHY(0x2314)
99 #define MT_WF_PHY_B1_PD_CCK_MASK GENMASK(31, 24)
100 #define MT_WF_PHY_B1_PD_CCK(v) ((v) << 24)
101
102 #define MT_WF_CFG_BASE 0x20200
103 #define MT_WF_CFG(ofs) (MT_WF_CFG_BASE + (ofs))
104
105 #define MT_CFG_CCR MT_WF_CFG(0x000)
106 #define MT_CFG_CCR_MAC_D1_1X_GC_EN BIT(24)
107 #define MT_CFG_CCR_MAC_D0_1X_GC_EN BIT(25)
108 #define MT_CFG_CCR_MAC_D1_2X_GC_EN BIT(30)
109 #define MT_CFG_CCR_MAC_D0_2X_GC_EN BIT(31)
110
111 #define MT_WF_AGG_BASE 0x20a00
112 #define MT_WF_AGG(ofs) (MT_WF_AGG_BASE + (ofs))
113
114 #define MT_AGG_ARCR MT_WF_AGG(0x010)
115 #define MT_AGG_ARCR_INIT_RATE1 BIT(0)
116 #define MT_AGG_ARCR_RTS_RATE_THR GENMASK(12, 8)
117 #define MT_AGG_ARCR_RATE_DOWN_RATIO GENMASK(17, 16)
118 #define MT_AGG_ARCR_RATE_DOWN_RATIO_EN BIT(19)
119 #define MT_AGG_ARCR_RATE_UP_EXTRA_TH GENMASK(22, 20)
120
121 #define MT_AGG_ARUCR MT_WF_AGG(0x018)
122 #define MT_AGG_ARDCR MT_WF_AGG(0x01c)
123 #define MT_AGG_ARxCR_LIMIT_SHIFT(_n) (4 * (_n))
124 #define MT_AGG_ARxCR_LIMIT(_n) GENMASK(2 + \
125 MT_AGG_ARxCR_LIMIT_SHIFT(_n), \
126 MT_AGG_ARxCR_LIMIT_SHIFT(_n))
127
128 #define MT_AGG_ACR0 MT_WF_AGG(0x070)
129 #define MT_AGG_ACR1 MT_WF_AGG(0x170)
130 #define MT_AGG_ACR_NO_BA_RULE BIT(0)
131 #define MT_AGG_ACR_NO_BA_AR_RULE BIT(1)
132 #define MT_AGG_ACR_PKT_TIME_EN BIT(2)
133 #define MT_AGG_ACR_CFEND_RATE GENMASK(15, 4)
134 #define MT_AGG_ACR_BAR_RATE GENMASK(31, 20)
135
136 #define MT_AGG_SCR MT_WF_AGG(0x0fc)
137 #define MT_AGG_SCR_NLNAV_MID_PTEC_DIS BIT(3)
138
139 #define MT_WF_TMAC_BASE 0x21000
140 #define MT_WF_TMAC(ofs) (MT_WF_TMAC_BASE + (ofs))
141
142 #define MT_TMAC_TRCR0 MT_WF_TMAC(0x09c)
143 #define MT_TMAC_TRCR1 MT_WF_TMAC(0x070)
144 #define MT_TMAC_TRCR_CCA_SEL GENMASK(31, 30)
145 #define MT_TMAC_TRCR_SEC_CCA_SEL GENMASK(29, 28)
146
147 #define MT_TMAC_CTCR0 MT_WF_TMAC(0x0f4)
148 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
149 #define MT_TMAC_CTCR0_INS_DDLMT_DENSITY GENMASK(15, 12)
150 #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
151 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
152
153 #define MT_WF_RMAC_BASE 0x21200
154 #define MT_WF_RMAC(ofs) (MT_WF_RMAC_BASE + (ofs))
155
156 #define MT_WF_RFCR MT_WF_RMAC(0x000)
157 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
158 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
159 #define MT_WF_RFCR_DROP_VERSION BIT(3)
160 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
161 #define MT_WF_RFCR_DROP_MCAST BIT(5)
162 #define MT_WF_RFCR_DROP_BCAST BIT(6)
163 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
164 #define MT_WF_RFCR_DROP_A3_MAC BIT(8)
165 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
166 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
167 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
168 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
169 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
170 #define MT_WF_RFCR_DROP_CTS BIT(14)
171 #define MT_WF_RFCR_DROP_RTS BIT(15)
172 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
173 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
174 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
175 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
176 #define MT_WF_RFCR_DROP_NDPA BIT(20)
177 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
178
179 #define MT_WF_DMA_BASE 0x21800
180 #define MT_WF_DMA(ofs) (MT_WF_DMA_BASE + (ofs))
181
182 #define MT_DMA_DCR0 MT_WF_DMA(0x000)
183 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 2)
184 #define MT_DMA_DCR0_RX_VEC_DROP BIT(17)
185
186 #define MT_WTBL_BASE 0x30000
187 #define MT_WTBL_ENTRY_SIZE 256
188
189 #define MT_WTBL_OFF_BASE 0x23400
190 #define MT_WTBL_OFF(n) (MT_WTBL_OFF_BASE + (n))
191
192 #define MT_WTBL_W0_KEY_IDX GENMASK(24, 23)
193 #define MT_WTBL_W0_RX_KEY_VALID BIT(26)
194 #define MT_WTBL_W0_RX_IK_VALID BIT(27)
195
196 #define MT_WTBL_W2_KEY_TYPE GENMASK(7, 4)
197
198 #define MT_WTBL_UPDATE MT_WTBL_OFF(0x030)
199 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0)
200 #define MT_WTBL_UPDATE_RXINFO_UPDATE BIT(11)
201 #define MT_WTBL_UPDATE_RATE_UPDATE BIT(13)
202 #define MT_WTBL_UPDATE_TX_COUNT_CLEAR BIT(14)
203 #define MT_WTBL_UPDATE_BUSY BIT(31)
204
205 #define MT_WTBL_ON_BASE 0x23000
206 #define MT_WTBL_ON(_n) (MT_WTBL_ON_BASE + (_n))
207
208 #define MT_WTBL_RICR0 MT_WTBL_ON(0x010)
209 #define MT_WTBL_RICR1 MT_WTBL_ON(0x014)
210
211 #define MT_WTBL_RIUCR0 MT_WTBL_ON(0x020)
212
213 #define MT_WTBL_RIUCR1 MT_WTBL_ON(0x024)
214 #define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0)
215 #define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12)
216 #define MT_WTBL_RIUCR1_RATE2_LO GENMASK(31, 24)
217
218 #define MT_WTBL_RIUCR2 MT_WTBL_ON(0x028)
219 #define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0)
220 #define MT_WTBL_RIUCR2_RATE3 GENMASK(15, 4)
221 #define MT_WTBL_RIUCR2_RATE4 GENMASK(27, 16)
222 #define MT_WTBL_RIUCR2_RATE5_LO GENMASK(31, 28)
223
224 #define MT_WTBL_RIUCR3 MT_WTBL_ON(0x02c)
225 #define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0)
226 #define MT_WTBL_RIUCR3_RATE6 GENMASK(19, 8)
227 #define MT_WTBL_RIUCR3_RATE7 GENMASK(31, 20)
228
229 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
230 #define MT_WTBL_W5_SHORT_GI_20 BIT(8)
231 #define MT_WTBL_W5_SHORT_GI_40 BIT(9)
232 #define MT_WTBL_W5_SHORT_GI_80 BIT(10)
233 #define MT_WTBL_W5_SHORT_GI_160 BIT(11)
234 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
235 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
236 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
237 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
238
239 #define MT_WTBL_W27_CC_BW_SEL GENMASK(6, 5)
240
241 #define MT_LPON_BASE 0x24200
242 #define MT_LPON(_n) (MT_LPON_BASE + (_n))
243
244 #define MT_LPON_T0CR MT_LPON(0x010)
245 #define MT_LPON_T0CR_MODE GENMASK(1, 0)
246
247 #define MT_LPON_UTTR0 MT_LPON(0x018)
248 #define MT_LPON_UTTR1 MT_LPON(0x01c)
249
250 #define MT_WF_MIB_BASE 0x24800
251 #define MT_WF_MIB(ofs) (MT_WF_MIB_BASE + (ofs))
252
253 #define MT_MIB_M0_MISC_CR MT_WF_MIB(0x00c)
254 #define MT_MIB_MB_SDR0(n) MT_WF_MIB(0x100 + ((n) << 4))
255 #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
256 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
257
258 #define MT_MIB_SDR16(n) MT_WF_MIB(0x48 + ((n) << 9))
259 #define MT_MIB_BUSY_MASK GENMASK(23, 0)
260
261 #define MT_EFUSE_BASE 0x81070000
262 #define MT_EFUSE_BASE_CTRL 0x000
263 #define MT_EFUSE_BASE_CTRL_EMPTY BIT(30)
264
265 #define MT_EFUSE_CTRL 0x008
266 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
267 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
268 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
269 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
270 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
271 #define MT_EFUSE_CTRL_VALID BIT(29)
272 #define MT_EFUSE_CTRL_KICK BIT(30)
273 #define MT_EFUSE_CTRL_SEL BIT(31)
274
275 #define MT_EFUSE_WDATA(_i) (0x010 + ((_i) * 4))
276 #define MT_EFUSE_RDATA(_i) (0x030 + ((_i) * 4))
277
278 #endif