root/drivers/net/wireless/mediatek/mt76/mt7615/mac.c

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DEFINITIONS

This source file includes following definitions.
  1. to_rssi
  2. mt7615_rx_get_wcid
  3. mt7615_mac_fill_rx
  4. mt7615_sta_ps
  5. mt7615_tx_complete_skb
  6. mt7615_mac_tx_rate_val
  7. mt7615_mac_write_txwi
  8. mt7615_txp_skb_unmap
  9. mt7615_mac_wtbl_addr
  10. mt7615_mac_set_rates
  11. mt7615_mac_get_cipher
  12. mt7615_mac_wtbl_update_key
  13. mt7615_mac_wtbl_update_pk
  14. mt7615_mac_wtbl_update_cipher
  15. mt7615_mac_wtbl_set_key
  16. mt7615_tx_prepare_skb
  17. mt7615_fill_txs
  18. mt7615_mac_add_txs_skb
  19. mt7615_mac_add_txs
  20. mt7615_mac_tx_free
  21. mt7615_mac_set_default_sensitivity
  22. mt7615_mac_set_scs
  23. mt7615_mac_cca_stats_reset
  24. mt7615_mac_adjust_sensitivity
  25. mt7615_mac_scs_check
  26. mt7615_update_channel
  27. mt7615_mac_work
  28. mt7615_dfs_stop_radar_detector
  29. mt7615_dfs_start_rdd
  30. mt7615_dfs_start_radar_detector
  31. mt7615_dfs_init_radar_detector

   1 // SPDX-License-Identifier: ISC
   2 /* Copyright (C) 2019 MediaTek Inc.
   3  *
   4  * Author: Ryder Lee <ryder.lee@mediatek.com>
   5  *         Roy Luo <royluo@google.com>
   6  *         Felix Fietkau <nbd@nbd.name>
   7  *         Lorenzo Bianconi <lorenzo@kernel.org>
   8  */
   9 
  10 #include <linux/etherdevice.h>
  11 #include <linux/timekeeping.h>
  12 #include "mt7615.h"
  13 #include "../dma.h"
  14 #include "mac.h"
  15 
  16 static inline s8 to_rssi(u32 field, u32 rxv)
  17 {
  18         return (FIELD_GET(field, rxv) - 220) / 2;
  19 }
  20 
  21 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
  22                                             u8 idx, bool unicast)
  23 {
  24         struct mt7615_sta *sta;
  25         struct mt76_wcid *wcid;
  26 
  27         if (idx >= ARRAY_SIZE(dev->mt76.wcid))
  28                 return NULL;
  29 
  30         wcid = rcu_dereference(dev->mt76.wcid[idx]);
  31         if (unicast || !wcid)
  32                 return wcid;
  33 
  34         if (!wcid->sta)
  35                 return NULL;
  36 
  37         sta = container_of(wcid, struct mt7615_sta, wcid);
  38         if (!sta->vif)
  39                 return NULL;
  40 
  41         return &sta->vif->sta.wcid;
  42 }
  43 
  44 int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
  45 {
  46         struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
  47         struct ieee80211_supported_band *sband;
  48         struct ieee80211_hdr *hdr;
  49         __le32 *rxd = (__le32 *)skb->data;
  50         u32 rxd0 = le32_to_cpu(rxd[0]);
  51         u32 rxd1 = le32_to_cpu(rxd[1]);
  52         u32 rxd2 = le32_to_cpu(rxd[2]);
  53         bool unicast, remove_pad, insert_ccmp_hdr = false;
  54         int i, idx;
  55 
  56         if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state))
  57                 return -EINVAL;
  58 
  59         memset(status, 0, sizeof(*status));
  60 
  61         unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
  62         idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
  63         status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
  64 
  65         /* TODO: properly support DBDC */
  66         status->freq = dev->mt76.chandef.chan->center_freq;
  67         status->band = dev->mt76.chandef.chan->band;
  68         if (status->band == NL80211_BAND_5GHZ)
  69                 sband = &dev->mt76.sband_5g.sband;
  70         else
  71                 sband = &dev->mt76.sband_2g.sband;
  72 
  73         if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
  74                 status->flag |= RX_FLAG_FAILED_FCS_CRC;
  75 
  76         if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
  77                 status->flag |= RX_FLAG_MMIC_ERROR;
  78 
  79         if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
  80             !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
  81                 status->flag |= RX_FLAG_DECRYPTED;
  82                 status->flag |= RX_FLAG_IV_STRIPPED;
  83                 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
  84         }
  85 
  86         remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
  87 
  88         if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
  89                 return -EINVAL;
  90 
  91         if (!sband->channels)
  92                 return -EINVAL;
  93 
  94         rxd += 4;
  95         if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
  96                 rxd += 4;
  97                 if ((u8 *)rxd - skb->data >= skb->len)
  98                         return -EINVAL;
  99         }
 100 
 101         if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
 102                 u8 *data = (u8 *)rxd;
 103 
 104                 if (status->flag & RX_FLAG_DECRYPTED) {
 105                         status->iv[0] = data[5];
 106                         status->iv[1] = data[4];
 107                         status->iv[2] = data[3];
 108                         status->iv[3] = data[2];
 109                         status->iv[4] = data[1];
 110                         status->iv[5] = data[0];
 111 
 112                         insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
 113                 }
 114                 rxd += 4;
 115                 if ((u8 *)rxd - skb->data >= skb->len)
 116                         return -EINVAL;
 117         }
 118 
 119         if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
 120                 rxd += 2;
 121                 if ((u8 *)rxd - skb->data >= skb->len)
 122                         return -EINVAL;
 123         }
 124 
 125         if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
 126                 u32 rxdg0 = le32_to_cpu(rxd[0]);
 127                 u32 rxdg1 = le32_to_cpu(rxd[1]);
 128                 u32 rxdg3 = le32_to_cpu(rxd[3]);
 129                 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
 130                 bool cck = false;
 131 
 132                 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
 133                 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
 134                 case MT_PHY_TYPE_CCK:
 135                         cck = true;
 136                         /* fall through */
 137                 case MT_PHY_TYPE_OFDM:
 138                         i = mt76_get_rate(&dev->mt76, sband, i, cck);
 139                         break;
 140                 case MT_PHY_TYPE_HT_GF:
 141                 case MT_PHY_TYPE_HT:
 142                         status->encoding = RX_ENC_HT;
 143                         if (i > 31)
 144                                 return -EINVAL;
 145                         break;
 146                 case MT_PHY_TYPE_VHT:
 147                         status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
 148                         status->encoding = RX_ENC_VHT;
 149                         break;
 150                 default:
 151                         return -EINVAL;
 152                 }
 153                 status->rate_idx = i;
 154 
 155                 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
 156                 case MT_PHY_BW_20:
 157                         break;
 158                 case MT_PHY_BW_40:
 159                         status->bw = RATE_INFO_BW_40;
 160                         break;
 161                 case MT_PHY_BW_80:
 162                         status->bw = RATE_INFO_BW_80;
 163                         break;
 164                 case MT_PHY_BW_160:
 165                         status->bw = RATE_INFO_BW_160;
 166                         break;
 167                 default:
 168                         return -EINVAL;
 169                 }
 170 
 171                 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
 172                         status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
 173                 if (rxdg0 & MT_RXV1_HT_AD_CODE)
 174                         status->enc_flags |= RX_ENC_FLAG_LDPC;
 175 
 176                 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
 177 
 178                 status->chains = dev->mt76.antenna_mask;
 179                 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
 180                 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
 181                 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
 182                 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
 183                 status->signal = status->chain_signal[0];
 184 
 185                 for (i = 1; i < hweight8(dev->mt76.antenna_mask); i++) {
 186                         if (!(status->chains & BIT(i)))
 187                                 continue;
 188 
 189                         status->signal = max(status->signal,
 190                                              status->chain_signal[i]);
 191                 }
 192 
 193                 rxd += 6;
 194                 if ((u8 *)rxd - skb->data >= skb->len)
 195                         return -EINVAL;
 196         }
 197 
 198         skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
 199 
 200         if (insert_ccmp_hdr) {
 201                 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
 202 
 203                 mt76_insert_ccmp_hdr(skb, key_id);
 204         }
 205 
 206         hdr = (struct ieee80211_hdr *)skb->data;
 207         if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
 208                 return 0;
 209 
 210         status->aggr = unicast &&
 211                        !ieee80211_is_qos_nullfunc(hdr->frame_control);
 212         status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
 213         status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
 214 
 215         return 0;
 216 }
 217 
 218 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
 219 {
 220 }
 221 
 222 void mt7615_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
 223                             struct mt76_queue_entry *e)
 224 {
 225         if (!e->txwi) {
 226                 dev_kfree_skb_any(e->skb);
 227                 return;
 228         }
 229 
 230         /* error path */
 231         if (e->skb == DMA_DUMMY_DATA) {
 232                 struct mt76_txwi_cache *t;
 233                 struct mt7615_dev *dev;
 234                 struct mt7615_txp *txp;
 235 
 236                 dev = container_of(mdev, struct mt7615_dev, mt76);
 237                 txp = mt7615_txwi_to_txp(mdev, e->txwi);
 238 
 239                 spin_lock_bh(&dev->token_lock);
 240                 t = idr_remove(&dev->token, le16_to_cpu(txp->token));
 241                 spin_unlock_bh(&dev->token_lock);
 242                 e->skb = t ? t->skb : NULL;
 243         }
 244 
 245         if (e->skb)
 246                 mt76_tx_complete_skb(mdev, e->skb);
 247 }
 248 
 249 static u16
 250 mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
 251                        const struct ieee80211_tx_rate *rate,
 252                        bool stbc, u8 *bw)
 253 {
 254         u8 phy, nss, rate_idx;
 255         u16 rateval = 0;
 256 
 257         *bw = 0;
 258 
 259         if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
 260                 rate_idx = ieee80211_rate_get_vht_mcs(rate);
 261                 nss = ieee80211_rate_get_vht_nss(rate);
 262                 phy = MT_PHY_TYPE_VHT;
 263                 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
 264                         *bw = 1;
 265                 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
 266                         *bw = 2;
 267                 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
 268                         *bw = 3;
 269         } else if (rate->flags & IEEE80211_TX_RC_MCS) {
 270                 rate_idx = rate->idx;
 271                 nss = 1 + (rate->idx >> 3);
 272                 phy = MT_PHY_TYPE_HT;
 273                 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
 274                         phy = MT_PHY_TYPE_HT_GF;
 275                 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
 276                         *bw = 1;
 277         } else {
 278                 const struct ieee80211_rate *r;
 279                 int band = dev->mt76.chandef.chan->band;
 280                 u16 val;
 281 
 282                 nss = 1;
 283                 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx];
 284                 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
 285                         val = r->hw_value_short;
 286                 else
 287                         val = r->hw_value;
 288 
 289                 phy = val >> 8;
 290                 rate_idx = val & 0xff;
 291         }
 292 
 293         if (stbc && nss == 1) {
 294                 nss++;
 295                 rateval |= MT_TX_RATE_STBC;
 296         }
 297 
 298         rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
 299                     FIELD_PREP(MT_TX_RATE_MODE, phy) |
 300                     FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
 301 
 302         return rateval;
 303 }
 304 
 305 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
 306                           struct sk_buff *skb, struct mt76_wcid *wcid,
 307                           struct ieee80211_sta *sta, int pid,
 308                           struct ieee80211_key_conf *key)
 309 {
 310         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 311         struct ieee80211_tx_rate *rate = &info->control.rates[0];
 312         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
 313         bool multicast = is_multicast_ether_addr(hdr->addr1);
 314         struct ieee80211_vif *vif = info->control.vif;
 315         int tx_count = 8;
 316         u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
 317         __le16 fc = hdr->frame_control;
 318         u16 seqno = 0;
 319         u32 val;
 320 
 321         if (vif) {
 322                 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
 323 
 324                 omac_idx = mvif->omac_idx;
 325                 wmm_idx = mvif->wmm_idx;
 326         }
 327 
 328         if (sta) {
 329                 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
 330 
 331                 tx_count = msta->rate_count;
 332         }
 333 
 334         fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
 335         fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
 336 
 337         if (ieee80211_is_data(fc) || ieee80211_is_bufferable_mmpdu(fc)) {
 338                 q_idx = wmm_idx * MT7615_MAX_WMM_SETS +
 339                         skb_get_queue_mapping(skb);
 340                 p_fmt = MT_TX_TYPE_CT;
 341         } else if (ieee80211_is_beacon(fc)) {
 342                 q_idx = MT_LMAC_BCN0;
 343                 p_fmt = MT_TX_TYPE_FW;
 344         } else {
 345                 q_idx = MT_LMAC_ALTX0;
 346                 p_fmt = MT_TX_TYPE_CT;
 347         }
 348 
 349         val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
 350               FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
 351               FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
 352         txwi[0] = cpu_to_le32(val);
 353 
 354         val = MT_TXD1_LONG_FORMAT |
 355               FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
 356               FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
 357               FIELD_PREP(MT_TXD1_HDR_INFO,
 358                          ieee80211_get_hdrlen_from_skb(skb) / 2) |
 359               FIELD_PREP(MT_TXD1_TID,
 360                          skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
 361               FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
 362               FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
 363         txwi[1] = cpu_to_le32(val);
 364 
 365         val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
 366               FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
 367               FIELD_PREP(MT_TXD2_MULTICAST, multicast);
 368         if (key) {
 369                 if (multicast && ieee80211_is_robust_mgmt_frame(skb) &&
 370                     key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
 371                         val |= MT_TXD2_BIP;
 372                         txwi[3] = 0;
 373                 } else {
 374                         txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME);
 375                 }
 376         } else {
 377                 txwi[3] = 0;
 378         }
 379         txwi[2] = cpu_to_le32(val);
 380 
 381         if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
 382                 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
 383 
 384         txwi[4] = 0;
 385         txwi[6] = 0;
 386 
 387         if (rate->idx >= 0 && rate->count &&
 388             !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
 389                 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
 390                 u8 bw;
 391                 u16 rateval = mt7615_mac_tx_rate_val(dev, rate, stbc, &bw);
 392 
 393                 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
 394 
 395                 val = MT_TXD6_FIXED_BW |
 396                       FIELD_PREP(MT_TXD6_BW, bw) |
 397                       FIELD_PREP(MT_TXD6_TX_RATE, rateval);
 398                 txwi[6] |= cpu_to_le32(val);
 399 
 400                 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
 401                         txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
 402 
 403                 if (info->flags & IEEE80211_TX_CTL_LDPC)
 404                         txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
 405 
 406                 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
 407                                      IEEE80211_TX_RC_VHT_MCS)))
 408                         txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
 409 
 410                 tx_count = rate->count;
 411         }
 412 
 413         if (!ieee80211_is_beacon(fc)) {
 414                 val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
 415                       FIELD_PREP(MT_TXD5_PID, pid);
 416                 txwi[5] = cpu_to_le32(val);
 417         } else {
 418                 txwi[5] = 0;
 419                 /* use maximum tx count for beacons */
 420                 tx_count = 0x1f;
 421         }
 422 
 423         val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
 424         if (ieee80211_is_data_qos(hdr->frame_control)) {
 425                 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
 426                 val |= MT_TXD3_SN_VALID;
 427         } else if (ieee80211_is_back_req(hdr->frame_control)) {
 428                 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
 429 
 430                 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(bar->start_seq_num));
 431                 val |= MT_TXD3_SN_VALID;
 432         }
 433         val |= FIELD_PREP(MT_TXD3_SEQ, seqno);
 434 
 435         txwi[3] |= cpu_to_le32(val);
 436 
 437         if (info->flags & IEEE80211_TX_CTL_NO_ACK)
 438                 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
 439 
 440         txwi[7] = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
 441                   FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
 442 
 443         return 0;
 444 }
 445 
 446 void mt7615_txp_skb_unmap(struct mt76_dev *dev,
 447                           struct mt76_txwi_cache *t)
 448 {
 449         struct mt7615_txp *txp;
 450         int i;
 451 
 452         txp = mt7615_txwi_to_txp(dev, t);
 453         for (i = 1; i < txp->nbuf; i++)
 454                 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
 455                                  le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
 456 }
 457 
 458 static u32 mt7615_mac_wtbl_addr(int wcid)
 459 {
 460         return MT_WTBL_BASE + wcid * MT_WTBL_ENTRY_SIZE;
 461 }
 462 
 463 void mt7615_mac_set_rates(struct mt7615_dev *dev, struct mt7615_sta *sta,
 464                           struct ieee80211_tx_rate *probe_rate,
 465                           struct ieee80211_tx_rate *rates)
 466 {
 467         struct ieee80211_tx_rate *ref;
 468         int wcid = sta->wcid.idx;
 469         u32 addr = mt7615_mac_wtbl_addr(wcid);
 470         bool stbc = false;
 471         int n_rates = sta->n_rates;
 472         u8 bw, bw_prev, bw_idx = 0;
 473         u16 val[4];
 474         u16 probe_val;
 475         u32 w5, w27;
 476         bool rateset;
 477         int i, k;
 478 
 479         if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
 480                 return;
 481 
 482         for (i = n_rates; i < 4; i++)
 483                 rates[i] = rates[n_rates - 1];
 484 
 485         rateset = !(sta->rate_set_tsf & BIT(0));
 486         memcpy(sta->rateset[rateset].rates, rates,
 487                sizeof(sta->rateset[rateset].rates));
 488         if (probe_rate) {
 489                 sta->rateset[rateset].probe_rate = *probe_rate;
 490                 ref = &sta->rateset[rateset].probe_rate;
 491         } else {
 492                 sta->rateset[rateset].probe_rate.idx = -1;
 493                 ref = &sta->rateset[rateset].rates[0];
 494         }
 495 
 496         rates = sta->rateset[rateset].rates;
 497         for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
 498                 /*
 499                  * We don't support switching between short and long GI
 500                  * within the rate set. For accurate tx status reporting, we
 501                  * need to make sure that flags match.
 502                  * For improved performance, avoid duplicate entries by
 503                  * decrementing the MCS index if necessary
 504                  */
 505                 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
 506                         rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
 507 
 508                 for (k = 0; k < i; k++) {
 509                         if (rates[i].idx != rates[k].idx)
 510                                 continue;
 511                         if ((rates[i].flags ^ rates[k].flags) &
 512                             (IEEE80211_TX_RC_40_MHZ_WIDTH |
 513                              IEEE80211_TX_RC_80_MHZ_WIDTH |
 514                              IEEE80211_TX_RC_160_MHZ_WIDTH))
 515                                 continue;
 516 
 517                         if (!rates[i].idx)
 518                                 continue;
 519 
 520                         rates[i].idx--;
 521                 }
 522         }
 523 
 524         val[0] = mt7615_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
 525         bw_prev = bw;
 526 
 527         if (probe_rate) {
 528                 probe_val = mt7615_mac_tx_rate_val(dev, probe_rate, stbc, &bw);
 529                 if (bw)
 530                         bw_idx = 1;
 531                 else
 532                         bw_prev = 0;
 533         } else {
 534                 probe_val = val[0];
 535         }
 536 
 537         val[1] = mt7615_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
 538         if (bw_prev) {
 539                 bw_idx = 3;
 540                 bw_prev = bw;
 541         }
 542 
 543         val[2] = mt7615_mac_tx_rate_val(dev, &rates[2], stbc, &bw);
 544         if (bw_prev) {
 545                 bw_idx = 5;
 546                 bw_prev = bw;
 547         }
 548 
 549         val[3] = mt7615_mac_tx_rate_val(dev, &rates[3], stbc, &bw);
 550         if (bw_prev)
 551                 bw_idx = 7;
 552 
 553         w27 = mt76_rr(dev, addr + 27 * 4);
 554         w27 &= ~MT_WTBL_W27_CC_BW_SEL;
 555         w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, bw);
 556 
 557         w5 = mt76_rr(dev, addr + 5 * 4);
 558         w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
 559                 MT_WTBL_W5_MPDU_OK_COUNT |
 560                 MT_WTBL_W5_MPDU_FAIL_COUNT |
 561                 MT_WTBL_W5_RATE_IDX);
 562         w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, bw) |
 563               FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, bw_idx ? bw_idx - 1 : 7);
 564 
 565         mt76_wr(dev, MT_WTBL_RIUCR0, w5);
 566 
 567         mt76_wr(dev, MT_WTBL_RIUCR1,
 568                 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) |
 569                 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
 570                 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1]));
 571 
 572         mt76_wr(dev, MT_WTBL_RIUCR2,
 573                 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) |
 574                 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
 575                 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) |
 576                 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
 577 
 578         mt76_wr(dev, MT_WTBL_RIUCR3,
 579                 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
 580                 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) |
 581                 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
 582 
 583         mt76_wr(dev, MT_WTBL_UPDATE,
 584                 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
 585                 MT_WTBL_UPDATE_RATE_UPDATE |
 586                 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
 587 
 588         mt76_wr(dev, addr + 27 * 4, w27);
 589 
 590         mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
 591         sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset;
 592 
 593         if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
 594                 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
 595 
 596         sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
 597         sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
 598 }
 599 
 600 static enum mt7615_cipher_type
 601 mt7615_mac_get_cipher(int cipher)
 602 {
 603         switch (cipher) {
 604         case WLAN_CIPHER_SUITE_WEP40:
 605                 return MT_CIPHER_WEP40;
 606         case WLAN_CIPHER_SUITE_WEP104:
 607                 return MT_CIPHER_WEP104;
 608         case WLAN_CIPHER_SUITE_TKIP:
 609                 return MT_CIPHER_TKIP;
 610         case WLAN_CIPHER_SUITE_AES_CMAC:
 611                 return MT_CIPHER_BIP_CMAC_128;
 612         case WLAN_CIPHER_SUITE_CCMP:
 613                 return MT_CIPHER_AES_CCMP;
 614         case WLAN_CIPHER_SUITE_CCMP_256:
 615                 return MT_CIPHER_CCMP_256;
 616         case WLAN_CIPHER_SUITE_GCMP:
 617                 return MT_CIPHER_GCMP;
 618         case WLAN_CIPHER_SUITE_GCMP_256:
 619                 return MT_CIPHER_GCMP_256;
 620         case WLAN_CIPHER_SUITE_SMS4:
 621                 return MT_CIPHER_WAPI;
 622         default:
 623                 return MT_CIPHER_NONE;
 624         }
 625 }
 626 
 627 static int
 628 mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid,
 629                            struct ieee80211_key_conf *key,
 630                            enum mt7615_cipher_type cipher,
 631                            enum set_key_cmd cmd)
 632 {
 633         u32 addr = mt7615_mac_wtbl_addr(wcid->idx) + 30 * 4;
 634         u8 data[32] = {};
 635 
 636         if (key->keylen > sizeof(data))
 637                 return -EINVAL;
 638 
 639         mt76_rr_copy(dev, addr, data, sizeof(data));
 640         if (cmd == SET_KEY) {
 641                 if (cipher == MT_CIPHER_TKIP) {
 642                         /* Rx/Tx MIC keys are swapped */
 643                         memcpy(data + 16, key->key + 24, 8);
 644                         memcpy(data + 24, key->key + 16, 8);
 645                 }
 646                 if (cipher != MT_CIPHER_BIP_CMAC_128 && wcid->cipher)
 647                         memmove(data + 16, data, 16);
 648                 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
 649                         memcpy(data, key->key, key->keylen);
 650                 else if (cipher == MT_CIPHER_BIP_CMAC_128)
 651                         memcpy(data + 16, key->key, 16);
 652         } else {
 653                 if (wcid->cipher & ~BIT(cipher)) {
 654                         if (cipher != MT_CIPHER_BIP_CMAC_128)
 655                                 memmove(data, data + 16, 16);
 656                         memset(data + 16, 0, 16);
 657                 } else {
 658                         memset(data, 0, sizeof(data));
 659                 }
 660         }
 661         mt76_wr_copy(dev, addr, data, sizeof(data));
 662 
 663         return 0;
 664 }
 665 
 666 static int
 667 mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid,
 668                           enum mt7615_cipher_type cipher, int keyidx,
 669                           enum set_key_cmd cmd)
 670 {
 671         u32 addr = mt7615_mac_wtbl_addr(wcid->idx), w0, w1;
 672 
 673         if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
 674                 return -ETIMEDOUT;
 675 
 676         w0 = mt76_rr(dev, addr);
 677         w1 = mt76_rr(dev, addr + 4);
 678         if (cmd == SET_KEY) {
 679                 w0 |= MT_WTBL_W0_RX_KEY_VALID |
 680                       FIELD_PREP(MT_WTBL_W0_RX_IK_VALID,
 681                                  cipher == MT_CIPHER_BIP_CMAC_128);
 682                 if (cipher != MT_CIPHER_BIP_CMAC_128 ||
 683                     !wcid->cipher)
 684                         w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx);
 685         }  else {
 686                 if (!(wcid->cipher & ~BIT(cipher)))
 687                         w0 &= ~(MT_WTBL_W0_RX_KEY_VALID |
 688                                 MT_WTBL_W0_KEY_IDX);
 689                 if (cipher == MT_CIPHER_BIP_CMAC_128)
 690                         w0 &= ~MT_WTBL_W0_RX_IK_VALID;
 691         }
 692         mt76_wr(dev, MT_WTBL_RICR0, w0);
 693         mt76_wr(dev, MT_WTBL_RICR1, w1);
 694 
 695         mt76_wr(dev, MT_WTBL_UPDATE,
 696                 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid->idx) |
 697                 MT_WTBL_UPDATE_RXINFO_UPDATE);
 698 
 699         if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
 700                 return -ETIMEDOUT;
 701 
 702         return 0;
 703 }
 704 
 705 static void
 706 mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid,
 707                               enum mt7615_cipher_type cipher,
 708                               enum set_key_cmd cmd)
 709 {
 710         u32 addr = mt7615_mac_wtbl_addr(wcid->idx);
 711 
 712         if (cmd == SET_KEY) {
 713                 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
 714                         mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
 715                                  FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher));
 716         } else {
 717                 if (cipher != MT_CIPHER_BIP_CMAC_128 &&
 718                     wcid->cipher & BIT(MT_CIPHER_BIP_CMAC_128))
 719                         mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
 720                                  FIELD_PREP(MT_WTBL_W2_KEY_TYPE,
 721                                             MT_CIPHER_BIP_CMAC_128));
 722                 else if (!(wcid->cipher & ~BIT(cipher)))
 723                         mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE);
 724         }
 725 }
 726 
 727 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
 728                             struct mt76_wcid *wcid,
 729                             struct ieee80211_key_conf *key,
 730                             enum set_key_cmd cmd)
 731 {
 732         enum mt7615_cipher_type cipher;
 733         int err;
 734 
 735         cipher = mt7615_mac_get_cipher(key->cipher);
 736         if (cipher == MT_CIPHER_NONE)
 737                 return -EOPNOTSUPP;
 738 
 739         spin_lock_bh(&dev->mt76.lock);
 740 
 741         mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cmd);
 742         err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cmd);
 743         if (err < 0)
 744                 goto out;
 745 
 746         err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, key->keyidx,
 747                                         cmd);
 748         if (err < 0)
 749                 goto out;
 750 
 751         if (cmd == SET_KEY)
 752                 wcid->cipher |= BIT(cipher);
 753         else
 754                 wcid->cipher &= ~BIT(cipher);
 755 
 756 out:
 757         spin_unlock_bh(&dev->mt76.lock);
 758 
 759         return err;
 760 }
 761 
 762 int mt7615_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
 763                           enum mt76_txq_id qid, struct mt76_wcid *wcid,
 764                           struct ieee80211_sta *sta,
 765                           struct mt76_tx_info *tx_info)
 766 {
 767         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
 768         struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
 769         struct mt7615_sta *msta = container_of(wcid, struct mt7615_sta, wcid);
 770         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
 771         struct ieee80211_key_conf *key = info->control.hw_key;
 772         struct ieee80211_vif *vif = info->control.vif;
 773         int i, pid, id, nbuf = tx_info->nbuf - 1;
 774         u8 *txwi = (u8 *)txwi_ptr;
 775         struct mt76_txwi_cache *t;
 776         struct mt7615_txp *txp;
 777 
 778         if (!wcid)
 779                 wcid = &dev->mt76.global_wcid;
 780 
 781         pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
 782 
 783         if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
 784                 spin_lock_bh(&dev->mt76.lock);
 785                 mt7615_mac_set_rates(dev, msta, &info->control.rates[0],
 786                                      msta->rates);
 787                 msta->rate_probe = true;
 788                 spin_unlock_bh(&dev->mt76.lock);
 789         }
 790 
 791         mt7615_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, sta,
 792                               pid, key);
 793 
 794         txp = (struct mt7615_txp *)(txwi + MT_TXD_SIZE);
 795         for (i = 0; i < nbuf; i++) {
 796                 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
 797                 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
 798         }
 799         txp->nbuf = nbuf;
 800 
 801         /* pass partial skb header to fw */
 802         tx_info->buf[1].len = MT_CT_PARSE_LEN;
 803         tx_info->nbuf = MT_CT_DMA_BUF_NUM;
 804 
 805         txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD);
 806 
 807         if (!key)
 808                 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
 809 
 810         if (ieee80211_is_mgmt(hdr->frame_control))
 811                 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
 812 
 813         if (vif) {
 814                 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
 815 
 816                 txp->bss_idx = mvif->idx;
 817         }
 818 
 819         t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
 820         t->skb = tx_info->skb;
 821 
 822         spin_lock_bh(&dev->token_lock);
 823         id = idr_alloc(&dev->token, t, 0, MT7615_TOKEN_SIZE, GFP_ATOMIC);
 824         spin_unlock_bh(&dev->token_lock);
 825         if (id < 0)
 826                 return id;
 827 
 828         txp->token = cpu_to_le16(id);
 829         txp->rept_wds_wcid = 0xff;
 830         tx_info->skb = DMA_DUMMY_DATA;
 831 
 832         return 0;
 833 }
 834 
 835 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
 836                             struct ieee80211_tx_info *info, __le32 *txs_data)
 837 {
 838         struct ieee80211_supported_band *sband;
 839         struct mt7615_rate_set *rs;
 840         int first_idx = 0, last_idx;
 841         int i, idx, count;
 842         bool fixed_rate, ack_timeout;
 843         bool probe, ampdu, cck = false;
 844         bool rs_idx;
 845         u32 rate_set_tsf;
 846         u32 final_rate, final_rate_flags, final_nss, txs;
 847 
 848         fixed_rate = info->status.rates[0].count;
 849         probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
 850 
 851         txs = le32_to_cpu(txs_data[1]);
 852         ampdu = !fixed_rate && (txs & MT_TXS1_AMPDU);
 853 
 854         txs = le32_to_cpu(txs_data[3]);
 855         count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
 856         last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs);
 857 
 858         txs = le32_to_cpu(txs_data[0]);
 859         final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
 860         ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
 861 
 862         if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
 863                 return false;
 864 
 865         if (txs & MT_TXS0_QUEUE_TIMEOUT)
 866                 return false;
 867 
 868         if (!ack_timeout)
 869                 info->flags |= IEEE80211_TX_STAT_ACK;
 870 
 871         info->status.ampdu_len = 1;
 872         info->status.ampdu_ack_len = !!(info->flags &
 873                                         IEEE80211_TX_STAT_ACK);
 874 
 875         if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
 876                 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
 877 
 878         first_idx = max_t(int, 0, last_idx - (count + 1) / MT7615_RATE_RETRY);
 879 
 880         if (fixed_rate && !probe) {
 881                 info->status.rates[0].count = count;
 882                 i = 0;
 883                 goto out;
 884         }
 885 
 886         rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
 887         rs_idx = !((u32)(FIELD_GET(MT_TXS4_F0_TIMESTAMP, le32_to_cpu(txs_data[4])) -
 888                          rate_set_tsf) < 1000000);
 889         rs_idx ^= rate_set_tsf & BIT(0);
 890         rs = &sta->rateset[rs_idx];
 891 
 892         if (!first_idx && rs->probe_rate.idx >= 0) {
 893                 info->status.rates[0] = rs->probe_rate;
 894 
 895                 spin_lock_bh(&dev->mt76.lock);
 896                 if (sta->rate_probe) {
 897                         mt7615_mac_set_rates(dev, sta, NULL, sta->rates);
 898                         sta->rate_probe = false;
 899                 }
 900                 spin_unlock_bh(&dev->mt76.lock);
 901         } else {
 902                 info->status.rates[0] = rs->rates[first_idx / 2];
 903         }
 904         info->status.rates[0].count = 0;
 905 
 906         for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
 907                 struct ieee80211_tx_rate *cur_rate;
 908                 int cur_count;
 909 
 910                 cur_rate = &rs->rates[idx / 2];
 911                 cur_count = min_t(int, MT7615_RATE_RETRY, count);
 912                 count -= cur_count;
 913 
 914                 if (idx && (cur_rate->idx != info->status.rates[i].idx ||
 915                             cur_rate->flags != info->status.rates[i].flags)) {
 916                         i++;
 917                         if (i == ARRAY_SIZE(info->status.rates)) {
 918                                 i--;
 919                                 break;
 920                         }
 921 
 922                         info->status.rates[i] = *cur_rate;
 923                         info->status.rates[i].count = 0;
 924                 }
 925 
 926                 info->status.rates[i].count += cur_count;
 927         }
 928 
 929 out:
 930         final_rate_flags = info->status.rates[i].flags;
 931 
 932         switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
 933         case MT_PHY_TYPE_CCK:
 934                 cck = true;
 935                 /* fall through */
 936         case MT_PHY_TYPE_OFDM:
 937                 if (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ)
 938                         sband = &dev->mt76.sband_5g.sband;
 939                 else
 940                         sband = &dev->mt76.sband_2g.sband;
 941                 final_rate &= MT_TX_RATE_IDX;
 942                 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
 943                                            cck);
 944                 final_rate_flags = 0;
 945                 break;
 946         case MT_PHY_TYPE_HT_GF:
 947         case MT_PHY_TYPE_HT:
 948                 final_rate_flags |= IEEE80211_TX_RC_MCS;
 949                 final_rate &= MT_TX_RATE_IDX;
 950                 if (final_rate > 31)
 951                         return false;
 952                 break;
 953         case MT_PHY_TYPE_VHT:
 954                 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
 955 
 956                 if ((final_rate & MT_TX_RATE_STBC) && final_nss)
 957                         final_nss--;
 958 
 959                 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
 960                 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
 961                 break;
 962         default:
 963                 return false;
 964         }
 965 
 966         info->status.rates[i].idx = final_rate;
 967         info->status.rates[i].flags = final_rate_flags;
 968 
 969         return true;
 970 }
 971 
 972 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
 973                                    struct mt7615_sta *sta, int pid,
 974                                    __le32 *txs_data)
 975 {
 976         struct mt76_dev *mdev = &dev->mt76;
 977         struct sk_buff_head list;
 978         struct sk_buff *skb;
 979 
 980         if (pid < MT_PACKET_ID_FIRST)
 981                 return false;
 982 
 983         mt76_tx_status_lock(mdev, &list);
 984         skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
 985         if (skb) {
 986                 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 987 
 988                 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
 989                         ieee80211_tx_info_clear_status(info);
 990                         info->status.rates[0].idx = -1;
 991                 }
 992 
 993                 mt76_tx_status_skb_done(mdev, skb, &list);
 994         }
 995         mt76_tx_status_unlock(mdev, &list);
 996 
 997         return !!skb;
 998 }
 999 
1000 void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
1001 {
1002         struct ieee80211_tx_info info = {};
1003         struct ieee80211_sta *sta = NULL;
1004         struct mt7615_sta *msta = NULL;
1005         struct mt76_wcid *wcid;
1006         __le32 *txs_data = data;
1007         u32 txs;
1008         u8 wcidx;
1009         u8 pid;
1010 
1011         txs = le32_to_cpu(txs_data[0]);
1012         pid = FIELD_GET(MT_TXS0_PID, txs);
1013         txs = le32_to_cpu(txs_data[2]);
1014         wcidx = FIELD_GET(MT_TXS2_WCID, txs);
1015 
1016         if (pid == MT_PACKET_ID_NO_ACK)
1017                 return;
1018 
1019         if (wcidx >= ARRAY_SIZE(dev->mt76.wcid))
1020                 return;
1021 
1022         rcu_read_lock();
1023 
1024         wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1025         if (!wcid)
1026                 goto out;
1027 
1028         msta = container_of(wcid, struct mt7615_sta, wcid);
1029         sta = wcid_to_sta(wcid);
1030 
1031         if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
1032                 goto out;
1033 
1034         if (wcidx >= MT7615_WTBL_STA || !sta)
1035                 goto out;
1036 
1037         if (mt7615_fill_txs(dev, msta, &info, txs_data))
1038                 ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info);
1039 
1040 out:
1041         rcu_read_unlock();
1042 }
1043 
1044 void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
1045 {
1046         struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
1047         struct mt76_dev *mdev = &dev->mt76;
1048         struct mt76_txwi_cache *txwi;
1049         u8 i, count;
1050 
1051         count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
1052         for (i = 0; i < count; i++) {
1053                 spin_lock_bh(&dev->token_lock);
1054                 txwi = idr_remove(&dev->token, le16_to_cpu(free->token[i]));
1055                 spin_unlock_bh(&dev->token_lock);
1056 
1057                 if (!txwi)
1058                         continue;
1059 
1060                 mt7615_txp_skb_unmap(mdev, txwi);
1061                 if (txwi->skb) {
1062                         mt76_tx_complete_skb(mdev, txwi->skb);
1063                         txwi->skb = NULL;
1064                 }
1065 
1066                 mt76_put_txwi(mdev, txwi);
1067         }
1068         dev_kfree_skb(skb);
1069 }
1070 
1071 static void
1072 mt7615_mac_set_default_sensitivity(struct mt7615_dev *dev)
1073 {
1074         mt76_rmw(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
1075                  MT_WF_PHY_B0_PD_OFDM_MASK,
1076                  MT_WF_PHY_B0_PD_OFDM(0x13c));
1077         mt76_rmw(dev, MT_WF_PHY_B1_MIN_PRI_PWR,
1078                  MT_WF_PHY_B1_PD_OFDM_MASK,
1079                  MT_WF_PHY_B1_PD_OFDM(0x13c));
1080 
1081         mt76_rmw(dev, MT_WF_PHY_B0_RXTD_CCK_PD,
1082                  MT_WF_PHY_B0_PD_CCK_MASK,
1083                  MT_WF_PHY_B0_PD_CCK(0x92));
1084         mt76_rmw(dev, MT_WF_PHY_B1_RXTD_CCK_PD,
1085                  MT_WF_PHY_B1_PD_CCK_MASK,
1086                  MT_WF_PHY_B1_PD_CCK(0x92));
1087 
1088         dev->ofdm_sensitivity = -98;
1089         dev->cck_sensitivity = -110;
1090         dev->last_cca_adj = jiffies;
1091 }
1092 
1093 void mt7615_mac_set_scs(struct mt7615_dev *dev, bool enable)
1094 {
1095         mutex_lock(&dev->mt76.mutex);
1096 
1097         if (dev->scs_en == enable)
1098                 goto out;
1099 
1100         if (enable) {
1101                 /* DBDC not supported */
1102                 mt76_set(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
1103                          MT_WF_PHY_B0_PD_BLK);
1104                 if (is_mt7622(&dev->mt76)) {
1105                         mt76_set(dev, MT_MIB_M0_MISC_CR, 0x7 << 8);
1106                         mt76_set(dev, MT_MIB_M0_MISC_CR, 0x7);
1107                 }
1108         } else {
1109                 mt76_clear(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
1110                            MT_WF_PHY_B0_PD_BLK);
1111                 mt76_clear(dev, MT_WF_PHY_B1_MIN_PRI_PWR,
1112                            MT_WF_PHY_B1_PD_BLK);
1113         }
1114 
1115         mt7615_mac_set_default_sensitivity(dev);
1116         dev->scs_en = enable;
1117 
1118 out:
1119         mutex_unlock(&dev->mt76.mutex);
1120 }
1121 
1122 void mt7615_mac_cca_stats_reset(struct mt7615_dev *dev)
1123 {
1124         mt76_clear(dev, MT_WF_PHY_R0_B0_PHYMUX_5, GENMASK(22, 20));
1125         mt76_set(dev, MT_WF_PHY_R0_B0_PHYMUX_5, BIT(22) | BIT(20));
1126 }
1127 
1128 static void
1129 mt7615_mac_adjust_sensitivity(struct mt7615_dev *dev,
1130                               u32 rts_err_rate, bool ofdm)
1131 {
1132         int false_cca = ofdm ? dev->false_cca_ofdm : dev->false_cca_cck;
1133         u16 def_th = ofdm ? -98 : -110;
1134         bool update = false;
1135         s8 *sensitivity;
1136         int signal;
1137 
1138         sensitivity = ofdm ? &dev->ofdm_sensitivity : &dev->cck_sensitivity;
1139         signal = mt76_get_min_avg_rssi(&dev->mt76);
1140         if (!signal) {
1141                 mt7615_mac_set_default_sensitivity(dev);
1142                 return;
1143         }
1144 
1145         signal = min(signal, -72);
1146         if (false_cca > 500) {
1147                 if (rts_err_rate > MT_FRAC(40, 100))
1148                         return;
1149 
1150                 /* decrease coverage */
1151                 if (*sensitivity == def_th && signal > -90) {
1152                         *sensitivity = -90;
1153                         update = true;
1154                 } else if (*sensitivity + 2 < signal) {
1155                         *sensitivity += 2;
1156                         update = true;
1157                 }
1158         } else if ((false_cca > 0 && false_cca < 50) ||
1159                    rts_err_rate > MT_FRAC(60, 100)) {
1160                 /* increase coverage */
1161                 if (*sensitivity - 2 >= def_th) {
1162                         *sensitivity -= 2;
1163                         update = true;
1164                 }
1165         }
1166 
1167         if (*sensitivity > signal) {
1168                 *sensitivity = signal;
1169                 update = true;
1170         }
1171 
1172         if (update) {
1173                 u16 val;
1174 
1175                 if (ofdm) {
1176                         /* DBDC not supported */
1177                         val = *sensitivity * 2 + 512;
1178                         mt76_rmw(dev, MT_WF_PHY_B0_MIN_PRI_PWR,
1179                                  MT_WF_PHY_B0_PD_OFDM_MASK,
1180                                  MT_WF_PHY_B0_PD_OFDM(val));
1181                 } else {
1182                         val = *sensitivity + 256;
1183                         mt76_rmw(dev, MT_WF_PHY_B0_RXTD_CCK_PD,
1184                                  MT_WF_PHY_B0_PD_CCK_MASK,
1185                                  MT_WF_PHY_B0_PD_CCK(val));
1186                         mt76_rmw(dev, MT_WF_PHY_B1_RXTD_CCK_PD,
1187                                  MT_WF_PHY_B1_PD_CCK_MASK,
1188                                  MT_WF_PHY_B1_PD_CCK(val));
1189                 }
1190                 dev->last_cca_adj = jiffies;
1191         }
1192 }
1193 
1194 static void
1195 mt7615_mac_scs_check(struct mt7615_dev *dev)
1196 {
1197         u32 val, rts_cnt = 0, rts_retries_cnt = 0, rts_err_rate = 0;
1198         u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm;
1199         int i;
1200 
1201         if (!dev->scs_en)
1202                 return;
1203 
1204         for (i = 0; i < 4; i++) {
1205                 u32 data;
1206 
1207                 val = mt76_rr(dev, MT_MIB_MB_SDR0(i));
1208                 data = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
1209                 if (data > rts_retries_cnt) {
1210                         rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1211                         rts_retries_cnt = data;
1212                 }
1213         }
1214 
1215         val = mt76_rr(dev, MT_WF_PHY_R0_B0_PHYCTRL_STS0);
1216         pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val);
1217         pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val);
1218 
1219         val = mt76_rr(dev, MT_WF_PHY_R0_B0_PHYCTRL_STS5);
1220         mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val);
1221         mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val);
1222 
1223         dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1224         dev->false_cca_cck = pd_cck - mdrdy_cck;
1225         mt7615_mac_cca_stats_reset(dev);
1226 
1227         if (rts_cnt + rts_retries_cnt)
1228                 rts_err_rate = MT_FRAC(rts_retries_cnt,
1229                                        rts_cnt + rts_retries_cnt);
1230 
1231         /* cck */
1232         mt7615_mac_adjust_sensitivity(dev, rts_err_rate, false);
1233         /* ofdm */
1234         mt7615_mac_adjust_sensitivity(dev, rts_err_rate, true);
1235 
1236         if (time_after(jiffies, dev->last_cca_adj + 10 * HZ))
1237                 mt7615_mac_set_default_sensitivity(dev);
1238 }
1239 
1240 void mt7615_update_channel(struct mt76_dev *mdev)
1241 {
1242         struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1243         struct mt76_channel_state *state;
1244         ktime_t cur_time;
1245         u32 busy;
1246 
1247         if (!test_bit(MT76_STATE_RUNNING, &mdev->state))
1248                 return;
1249 
1250         state = mt76_channel_state(mdev, mdev->chandef.chan);
1251         /* TODO: add DBDC support */
1252         busy = mt76_get_field(dev, MT_MIB_SDR16(0), MT_MIB_BUSY_MASK);
1253 
1254         spin_lock_bh(&mdev->cc_lock);
1255         cur_time = ktime_get_boottime();
1256         state->cc_busy += busy;
1257         state->cc_active += ktime_to_us(ktime_sub(cur_time,
1258                                                   mdev->survey_time));
1259         mdev->survey_time = cur_time;
1260         spin_unlock_bh(&mdev->cc_lock);
1261 }
1262 
1263 void mt7615_mac_work(struct work_struct *work)
1264 {
1265         struct mt7615_dev *dev;
1266 
1267         dev = (struct mt7615_dev *)container_of(work, struct mt76_dev,
1268                                                 mac_work.work);
1269 
1270         mutex_lock(&dev->mt76.mutex);
1271         mt7615_update_channel(&dev->mt76);
1272         if (++dev->mac_work_count == 5) {
1273                 mt7615_mac_scs_check(dev);
1274                 dev->mac_work_count = 0;
1275         }
1276         mutex_unlock(&dev->mt76.mutex);
1277 
1278         mt76_tx_status_check(&dev->mt76, NULL, false);
1279         ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mt76.mac_work,
1280                                      MT7615_WATCHDOG_TIME);
1281 }
1282 
1283 int mt7615_dfs_stop_radar_detector(struct mt7615_dev *dev)
1284 {
1285         struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
1286         int err;
1287 
1288         err = mt7615_mcu_rdd_cmd(dev, RDD_STOP, MT_HW_RDD0,
1289                                  MT_RX_SEL0, 0);
1290         if (err < 0)
1291                 return err;
1292 
1293         if (chandef->width == NL80211_CHAN_WIDTH_160 ||
1294             chandef->width == NL80211_CHAN_WIDTH_80P80)
1295                 err = mt7615_mcu_rdd_cmd(dev, RDD_STOP, MT_HW_RDD1,
1296                                          MT_RX_SEL0, 0);
1297         return err;
1298 }
1299 
1300 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
1301 {
1302         int err;
1303 
1304         err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
1305         if (err < 0)
1306                 return err;
1307 
1308         return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain,
1309                                   MT_RX_SEL0, 1);
1310 }
1311 
1312 int mt7615_dfs_start_radar_detector(struct mt7615_dev *dev)
1313 {
1314         struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
1315         int err;
1316 
1317         /* start CAC */
1318         err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, MT_HW_RDD0,
1319                                  MT_RX_SEL0, 0);
1320         if (err < 0)
1321                 return err;
1322 
1323         /* TODO: DBDC support */
1324 
1325         err = mt7615_dfs_start_rdd(dev, MT_HW_RDD0);
1326         if (err < 0)
1327                 return err;
1328 
1329         if (chandef->width == NL80211_CHAN_WIDTH_160 ||
1330             chandef->width == NL80211_CHAN_WIDTH_80P80) {
1331                 err = mt7615_dfs_start_rdd(dev, MT_HW_RDD1);
1332                 if (err < 0)
1333                         return err;
1334         }
1335 
1336         return 0;
1337 }
1338 
1339 int mt7615_dfs_init_radar_detector(struct mt7615_dev *dev)
1340 {
1341         struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
1342         int err;
1343 
1344         if (dev->mt76.region == NL80211_DFS_UNSET)
1345                 return 0;
1346 
1347         if (test_bit(MT76_SCANNING, &dev->mt76.state))
1348                 return 0;
1349 
1350         if (dev->dfs_state == chandef->chan->dfs_state)
1351                 return 0;
1352 
1353         dev->dfs_state = chandef->chan->dfs_state;
1354 
1355         if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
1356                 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
1357                         return mt7615_dfs_start_radar_detector(dev);
1358                 else
1359                         return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, MT_HW_RDD0,
1360                                                   MT_RX_SEL0, 0);
1361         } else {
1362                 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START,
1363                                          MT_HW_RDD0, MT_RX_SEL0, 0);
1364                 if (err < 0)
1365                         return err;
1366 
1367                 return mt7615_dfs_stop_radar_detector(dev);
1368         }
1369 }

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