root/drivers/net/wireless/mediatek/mt76/mt76x02.h

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INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. is_mt76x0
  2. is_mt76x2
  3. mt76x02_irq_enable
  4. mt76x02_irq_disable
  5. mt76x02_wait_for_txrx_idle
  6. mt76x02_rx_get_sta
  7. mt76x02_rx_get_sta_wcid

   1 /* SPDX-License-Identifier: ISC */
   2 /*
   3  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
   4  * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
   5  */
   6 
   7 #ifndef __MT76x02_H
   8 #define __MT76x02_H
   9 
  10 #include <linux/kfifo.h>
  11 
  12 #include "mt76.h"
  13 #include "mt76x02_regs.h"
  14 #include "mt76x02_mac.h"
  15 #include "mt76x02_dfs.h"
  16 #include "mt76x02_dma.h"
  17 
  18 #define MT_CALIBRATE_INTERVAL   HZ
  19 #define MT_MAC_WORK_INTERVAL    (HZ / 10)
  20 
  21 #define MT_WATCHDOG_TIME        (HZ / 10)
  22 #define MT_TX_HANG_TH           10
  23 
  24 #define MT_MAX_CHAINS           2
  25 struct mt76x02_rx_freq_cal {
  26         s8 high_gain[MT_MAX_CHAINS];
  27         s8 rssi_offset[MT_MAX_CHAINS];
  28         s8 lna_gain;
  29         u32 mcu_gain;
  30         s16 temp_offset;
  31         u8 freq_offset;
  32 };
  33 
  34 struct mt76x02_calibration {
  35         struct mt76x02_rx_freq_cal rx;
  36 
  37         u8 agc_gain_init[MT_MAX_CHAINS];
  38         u8 agc_gain_cur[MT_MAX_CHAINS];
  39 
  40         u16 false_cca;
  41         s8 avg_rssi_all;
  42         s8 agc_gain_adjust;
  43         s8 agc_lowest_gain;
  44         s8 low_gain;
  45 
  46         s8 temp_vco;
  47         s8 temp;
  48 
  49         bool init_cal_done;
  50         bool tssi_cal_done;
  51         bool tssi_comp_pending;
  52         bool dpd_cal_done;
  53         bool channel_cal_done;
  54         bool gain_init_done;
  55 
  56         int tssi_target;
  57         s8 tssi_dc;
  58 };
  59 
  60 struct mt76x02_beacon_ops {
  61         unsigned int nslots;
  62         unsigned int slot_size;
  63         void (*pre_tbtt_enable)(struct mt76x02_dev *dev, bool en);
  64         void (*beacon_enable)(struct mt76x02_dev *dev, bool en);
  65 };
  66 
  67 #define mt76x02_beacon_enable(dev, enable)      \
  68         (dev)->beacon_ops->beacon_enable(dev, enable)
  69 #define mt76x02_pre_tbtt_enable(dev, enable)    \
  70         (dev)->beacon_ops->pre_tbtt_enable(dev, enable)
  71 
  72 struct mt76x02_dev {
  73         struct mt76_dev mt76; /* must be first */
  74 
  75         struct mac_address macaddr_list[8];
  76 
  77         struct mutex phy_mutex;
  78 
  79         u16 vif_mask;
  80 
  81         u8 txdone_seq;
  82         DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x02_tx_status);
  83         spinlock_t txstatus_fifo_lock;
  84 
  85         struct sk_buff *rx_head;
  86 
  87         struct delayed_work cal_work;
  88         struct delayed_work wdt_work;
  89 
  90         struct hrtimer pre_tbtt_timer;
  91         struct work_struct pre_tbtt_work;
  92 
  93         const struct mt76x02_beacon_ops *beacon_ops;
  94 
  95         u32 aggr_stats[32];
  96 
  97         struct sk_buff *beacons[8];
  98         u8 beacon_data_mask;
  99 
 100         u8 tbtt_count;
 101 
 102         u32 tx_hang_reset;
 103         u8 tx_hang_check;
 104         u8 mcu_timeout;
 105 
 106         struct mt76x02_calibration cal;
 107 
 108         s8 target_power;
 109         s8 target_power_delta[2];
 110         bool enable_tpc;
 111 
 112         bool no_2ghz;
 113 
 114         u8 coverage_class;
 115         u8 slottime;
 116 
 117         struct mt76x02_dfs_pattern_detector dfs_pd;
 118 
 119         /* edcca monitor */
 120         unsigned long ed_trigger_timeout;
 121         bool ed_tx_blocked;
 122         bool ed_monitor;
 123         u8 ed_monitor_enabled;
 124         u8 ed_monitor_learning;
 125         u8 ed_trigger;
 126         u8 ed_silent;
 127         ktime_t ed_time;
 128 };
 129 
 130 extern struct ieee80211_rate mt76x02_rates[12];
 131 
 132 void mt76x02_init_device(struct mt76x02_dev *dev);
 133 void mt76x02_configure_filter(struct ieee80211_hw *hw,
 134                               unsigned int changed_flags,
 135                               unsigned int *total_flags, u64 multicast);
 136 int mt76x02_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
 137                     struct ieee80211_sta *sta);
 138 void mt76x02_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
 139                         struct ieee80211_sta *sta);
 140 
 141 void mt76x02_config_mac_addr_list(struct mt76x02_dev *dev);
 142 
 143 int mt76x02_add_interface(struct ieee80211_hw *hw,
 144                           struct ieee80211_vif *vif);
 145 void mt76x02_remove_interface(struct ieee80211_hw *hw,
 146                               struct ieee80211_vif *vif);
 147 
 148 int mt76x02_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 149                          struct ieee80211_ampdu_params *params);
 150 int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
 151                     struct ieee80211_vif *vif, struct ieee80211_sta *sta,
 152                     struct ieee80211_key_conf *key);
 153 int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 154                     u16 queue, const struct ieee80211_tx_queue_params *params);
 155 void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw,
 156                                  struct ieee80211_vif *vif,
 157                                  struct ieee80211_sta *sta);
 158 s8 mt76x02_tx_get_max_txpwr_adj(struct mt76x02_dev *dev,
 159                                 const struct ieee80211_tx_rate *rate);
 160 s8 mt76x02_tx_get_txpwr_adj(struct mt76x02_dev *dev, s8 txpwr,
 161                             s8 max_txpwr_adj);
 162 void mt76x02_wdt_work(struct work_struct *work);
 163 void mt76x02_tx_set_txpwr_auto(struct mt76x02_dev *dev, s8 txpwr);
 164 void mt76x02_set_tx_ackto(struct mt76x02_dev *dev);
 165 void mt76x02_set_coverage_class(struct ieee80211_hw *hw,
 166                                 s16 coverage_class);
 167 int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val);
 168 void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
 169 bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
 170 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
 171                           struct sk_buff *skb);
 172 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
 173 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
 174 void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
 175                 struct sk_buff *skb);
 176 int mt76x02_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
 177                            enum mt76_txq_id qid, struct mt76_wcid *wcid,
 178                            struct ieee80211_sta *sta,
 179                            struct mt76_tx_info *tx_info);
 180 void mt76x02_sw_scan_complete(struct ieee80211_hw *hw,
 181                               struct ieee80211_vif *vif);
 182 void mt76x02_sta_ps(struct mt76_dev *dev, struct ieee80211_sta *sta, bool ps);
 183 void mt76x02_bss_info_changed(struct ieee80211_hw *hw,
 184                               struct ieee80211_vif *vif,
 185                               struct ieee80211_bss_conf *info, u32 changed);
 186 
 187 struct beacon_bc_data {
 188         struct mt76x02_dev *dev;
 189         struct sk_buff_head q;
 190         struct sk_buff *tail[8];
 191 };
 192 
 193 void mt76x02_init_beacon_config(struct mt76x02_dev *dev);
 194 void mt76x02e_init_beacon_config(struct mt76x02_dev *dev);
 195 void mt76x02_resync_beacon_timer(struct mt76x02_dev *dev);
 196 void mt76x02_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif);
 197 void mt76x02_enqueue_buffered_bc(struct mt76x02_dev *dev,
 198                                  struct beacon_bc_data *data,
 199                                  int max_nframes);
 200 
 201 void mt76x02_mac_start(struct mt76x02_dev *dev);
 202 
 203 void mt76x02_init_debugfs(struct mt76x02_dev *dev);
 204 
 205 static inline bool is_mt76x0(struct mt76x02_dev *dev)
 206 {
 207         return mt76_chip(&dev->mt76) == 0x7610 ||
 208                mt76_chip(&dev->mt76) == 0x7630 ||
 209                mt76_chip(&dev->mt76) == 0x7650;
 210 }
 211 
 212 static inline bool is_mt76x2(struct mt76x02_dev *dev)
 213 {
 214         return mt76_chip(&dev->mt76) == 0x7612 ||
 215                mt76_chip(&dev->mt76) == 0x7632 ||
 216                mt76_chip(&dev->mt76) == 0x7662 ||
 217                mt76_chip(&dev->mt76) == 0x7602;
 218 }
 219 
 220 static inline void mt76x02_irq_enable(struct mt76x02_dev *dev, u32 mask)
 221 {
 222         mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask);
 223 }
 224 
 225 static inline void mt76x02_irq_disable(struct mt76x02_dev *dev, u32 mask)
 226 {
 227         mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
 228 }
 229 
 230 static inline bool
 231 mt76x02_wait_for_txrx_idle(struct mt76_dev *dev)
 232 {
 233         return __mt76_poll_msec(dev, MT_MAC_STATUS,
 234                                 MT_MAC_STATUS_TX | MT_MAC_STATUS_RX,
 235                                 0, 100);
 236 }
 237 
 238 static inline struct mt76x02_sta *
 239 mt76x02_rx_get_sta(struct mt76_dev *dev, u8 idx)
 240 {
 241         struct mt76_wcid *wcid;
 242 
 243         if (idx >= ARRAY_SIZE(dev->wcid))
 244                 return NULL;
 245 
 246         wcid = rcu_dereference(dev->wcid[idx]);
 247         if (!wcid)
 248                 return NULL;
 249 
 250         return container_of(wcid, struct mt76x02_sta, wcid);
 251 }
 252 
 253 static inline struct mt76_wcid *
 254 mt76x02_rx_get_sta_wcid(struct mt76x02_sta *sta, bool unicast)
 255 {
 256         if (!sta)
 257                 return NULL;
 258 
 259         if (unicast)
 260                 return &sta->wcid;
 261         else
 262                 return &sta->vif->group_wcid;
 263 }
 264 
 265 #endif /* __MT76x02_H */

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