root/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h

INCLUDED FROM

DEFINITIONS

1. qtnf_non_posted_write

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* Copyright (c) 2018 Quantenna Communications, Inc. All rights reserved. */
   3 
   4 #ifndef _QTN_FMAC_PCIE_H_
   5 #define _QTN_FMAC_PCIE_H_
   6 
   7 #include <linux/pci.h>
   8 #include <linux/spinlock.h>
   9 #include <linux/io.h>
  10 #include <linux/skbuff.h>
  11 #include <linux/workqueue.h>
  12 #include <linux/interrupt.h>
  13 
  14 #include "shm_ipc.h"
  15 #include "bus.h"
  16 
  17 #define SKB_BUF_SIZE            2048
  18 
  19 #define QTN_FW_DL_TIMEOUT_MS    3000
  20 #define QTN_FW_QLINK_TIMEOUT_MS 30000
  21 #define QTN_EP_RESET_WAIT_MS    1000
  22 
  23 struct qtnf_pcie_bus_priv {
  24         struct pci_dev *pdev;
  25 
  26         int (*probe_cb)(struct qtnf_bus *bus, unsigned int tx_bd_size);
  27         void (*remove_cb)(struct qtnf_bus *bus);
  28         int (*suspend_cb)(struct qtnf_bus *bus);
  29         int (*resume_cb)(struct qtnf_bus *bus);
  30         u64 (*dma_mask_get_cb)(void);
  31 
  32         spinlock_t tx_reclaim_lock;
  33         spinlock_t tx_lock;
  34 
  35         struct workqueue_struct *workqueue;
  36         struct tasklet_struct reclaim_tq;
  37 
  38         void __iomem *sysctl_bar;
  39         void __iomem *epmem_bar;
  40         void __iomem *dmareg_bar;
  41 
  42         struct qtnf_shm_ipc shm_ipc_ep_in;
  43         struct qtnf_shm_ipc shm_ipc_ep_out;
  44 
  45         u16 tx_bd_num;
  46         u16 rx_bd_num;
  47 
  48         struct sk_buff **tx_skb;
  49         struct sk_buff **rx_skb;
  50 
  51         unsigned int fw_blksize;
  52 
  53         u32 rx_bd_w_index;
  54         u32 rx_bd_r_index;
  55 
  56         u32 tx_bd_w_index;
  57         u32 tx_bd_r_index;
  58 
  59         /* diagnostics stats */
  60         u32 pcie_irq_count;
  61         u32 tx_full_count;
  62         u32 tx_done_count;
  63         u32 tx_reclaim_done;
  64         u32 tx_reclaim_req;
  65         u32 tx_eapol;
  66 
  67         u8 msi_enabled;
  68         u8 tx_stopped;
  69         bool flashboot;
  70 };
  71 
  72 int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb);
  73 int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv);
  74 int qtnf_pcie_fw_boot_done(struct qtnf_bus *bus);
  75 void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv,
  76                             struct qtnf_shm_ipc_region __iomem *ipc_tx_reg,
  77                             struct qtnf_shm_ipc_region __iomem *ipc_rx_reg,
  78                             const struct qtnf_shm_ipc_int *ipc_int);
  79 struct qtnf_bus *qtnf_pcie_pearl_alloc(struct pci_dev *pdev);
  80 struct qtnf_bus *qtnf_pcie_topaz_alloc(struct pci_dev *pdev);
  81 
  82 static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg)
  83 {
  84         writel(val, basereg);
  85 
  86         /* flush posted write */
  87         readl(basereg);
  88 }
  89 
  90 #endif /* _QTN_FMAC_PCIE_H_ */