root/drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h

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   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16 
  17 #ifndef _BRCM_TYPES_H_
  18 #define _BRCM_TYPES_H_
  19 
  20 #include <linux/types.h>
  21 #include <linux/io.h>
  22 
  23 #define WL_CHAN_FREQ_RANGE_2G      0
  24 #define WL_CHAN_FREQ_RANGE_5GL     1
  25 #define WL_CHAN_FREQ_RANGE_5GM     2
  26 #define WL_CHAN_FREQ_RANGE_5GH     3
  27 
  28 /* boardflags */
  29 
  30 /* Board has gpio 9 controlling the PA */
  31 #define BFL_PACTRL              0x00000002
  32 /* Not ok to power down the chip pll and oscillator */
  33 #define BFL_NOPLLDOWN           0x00000020
  34 /* Board supports the Front End Module */
  35 #define BFL_FEM                 0x00000800
  36 /* Board has an external LNA in 2.4GHz band */
  37 #define BFL_EXTLNA              0x00001000
  38 /* Board has no PA */
  39 #define BFL_NOPA                0x00010000
  40 /* Power topology uses BUCKBOOST */
  41 #define BFL_BUCKBOOST           0x00200000
  42 /* Board has FEM and switch to share antenna w/ BT */
  43 #define BFL_FEM_BT              0x00400000
  44 /* Power topology doesn't use CBUCK */
  45 #define BFL_NOCBUCK             0x00800000
  46 /* Power topology uses PALDO */
  47 #define BFL_PALDO               0x02000000
  48 /* Board has an external LNA in 5GHz band */
  49 #define BFL_EXTLNA_5GHz         0x10000000
  50 
  51 /* boardflags2 */
  52 
  53 /* Board has an external rxbb regulator */
  54 #define BFL2_RXBB_INT_REG_DIS   0x00000001
  55 /* Flag to implement alternative A-band PLL settings */
  56 #define BFL2_APLL_WAR           0x00000002
  57 /* Board permits enabling TX Power Control */
  58 #define BFL2_TXPWRCTRL_EN       0x00000004
  59 /* Board supports the 2X4 diversity switch */
  60 #define BFL2_2X4_DIV            0x00000008
  61 /* Board supports 5G band power gain */
  62 #define BFL2_5G_PWRGAIN         0x00000010
  63 /* Board overrides ASPM and Clkreq settings */
  64 #define BFL2_PCIEWAR_OVR        0x00000020
  65 #define BFL2_LEGACY             0x00000080
  66 /* 4321mcm93 board uses Skyworks FEM */
  67 #define BFL2_SKWRKFEM_BRD       0x00000100
  68 /* Board has a WAR for clock-harmonic spurs */
  69 #define BFL2_SPUR_WAR           0x00000200
  70 /* Flag to narrow G-band PLL loop b/w */
  71 #define BFL2_GPLL_WAR           0x00000400
  72 /* Tx CCK pkts on Ant 0 only */
  73 #define BFL2_SINGLEANT_CCK      0x00001000
  74 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
  75 #define BFL2_2G_SPUR_WAR        0x00002000
  76 /* Flag to widen G-band PLL loop b/w */
  77 #define BFL2_GPLL_WAR2          0x00010000
  78 #define BFL2_IPALVLSHIFT_3P3    0x00020000
  79 /* Use internal envelope detector for TX IQCAL */
  80 #define BFL2_INTERNDET_TXIQCAL  0x00040000
  81 /* Keep the buffered Xtal output from radio "ON". Most drivers will turn it
  82  * off without this flag to save power. */
  83 #define BFL2_XTALBUFOUTEN       0x00080000
  84 
  85 /*
  86  * board specific GPIO assignment, gpio 0-3 are also customer-configurable
  87  * led
  88  */
  89 
  90 /* bit 9 controls the PA on new 4306 boards */
  91 #define BOARD_GPIO_PACTRL       0x200
  92 #define BOARD_GPIO_12           0x1000
  93 #define BOARD_GPIO_13           0x2000
  94 
  95 /* **** Core type/rev defaults **** */
  96 #define D11CONF         0x0fffffb0      /* Supported  D11 revs: 4, 5, 7-27
  97                                          * also need to update wlc.h MAXCOREREV
  98                                          */
  99 
 100 #define NCONF           0x000001ff      /* Supported nphy revs:
 101                                          *      0       4321a0
 102                                          *      1       4321a1
 103                                          *      2       4321b0/b1/c0/c1
 104                                          *      3       4322a0
 105                                          *      4       4322a1
 106                                          *      5       4716a0
 107                                          *      6       43222a0, 43224a0
 108                                          *      7       43226a0
 109                                          *      8       5357a0, 43236a0
 110                                          */
 111 
 112 #define LCNCONF         0x00000007      /* Supported lcnphy revs:
 113                                          *      0       4313a0, 4336a0, 4330a0
 114                                          *      1
 115                                          *      2       4330a0
 116                                          */
 117 
 118 #define SSLPNCONF       0x0000000f      /* Supported sslpnphy revs:
 119                                          *      0       4329a0/k0
 120                                          *      1       4329b0/4329C0
 121                                          *      2       4319a0
 122                                          *      3       5356a0
 123                                          */
 124 
 125 /********************************************************************
 126  * Phy/Core Configuration.  Defines macros to to check core phy/rev *
 127  * compile-time configuration.  Defines default core support.       *
 128  * ******************************************************************
 129  */
 130 
 131 /* Basic macros to check a configuration bitmask */
 132 
 133 #define CONF_HAS(config, val)   ((config) & (1 << (val)))
 134 #define CONF_MSK(config, mask)  ((config) & (mask))
 135 #define MSK_RANGE(low, hi)      ((1 << ((hi)+1)) - (1 << (low)))
 136 #define CONF_RANGE(config, low, hi) (CONF_MSK(config, MSK_RANGE(low, high)))
 137 
 138 #define CONF_IS(config, val)    ((config) == (1 << (val)))
 139 #define CONF_GE(config, val)    ((config) & (0-(1 << (val))))
 140 #define CONF_GT(config, val)    ((config) & (0-2*(1 << (val))))
 141 #define CONF_LT(config, val)    ((config) & ((1 << (val))-1))
 142 #define CONF_LE(config, val)    ((config) & (2*(1 << (val))-1))
 143 
 144 /* Wrappers for some of the above, specific to config constants */
 145 
 146 #define NCONF_HAS(val)  CONF_HAS(NCONF, val)
 147 #define NCONF_MSK(mask) CONF_MSK(NCONF, mask)
 148 #define NCONF_IS(val)   CONF_IS(NCONF, val)
 149 #define NCONF_GE(val)   CONF_GE(NCONF, val)
 150 #define NCONF_GT(val)   CONF_GT(NCONF, val)
 151 #define NCONF_LT(val)   CONF_LT(NCONF, val)
 152 #define NCONF_LE(val)   CONF_LE(NCONF, val)
 153 
 154 #define LCNCONF_HAS(val)        CONF_HAS(LCNCONF, val)
 155 #define LCNCONF_MSK(mask)       CONF_MSK(LCNCONF, mask)
 156 #define LCNCONF_IS(val)         CONF_IS(LCNCONF, val)
 157 #define LCNCONF_GE(val)         CONF_GE(LCNCONF, val)
 158 #define LCNCONF_GT(val)         CONF_GT(LCNCONF, val)
 159 #define LCNCONF_LT(val)         CONF_LT(LCNCONF, val)
 160 #define LCNCONF_LE(val)         CONF_LE(LCNCONF, val)
 161 
 162 #define D11CONF_HAS(val) CONF_HAS(D11CONF, val)
 163 #define D11CONF_MSK(mask) CONF_MSK(D11CONF, mask)
 164 #define D11CONF_IS(val) CONF_IS(D11CONF, val)
 165 #define D11CONF_GE(val) CONF_GE(D11CONF, val)
 166 #define D11CONF_GT(val) CONF_GT(D11CONF, val)
 167 #define D11CONF_LT(val) CONF_LT(D11CONF, val)
 168 #define D11CONF_LE(val) CONF_LE(D11CONF, val)
 169 
 170 #define PHYCONF_HAS(val) CONF_HAS(PHYTYPE, val)
 171 #define PHYCONF_IS(val) CONF_IS(PHYTYPE, val)
 172 
 173 #define NREV_IS(var, val) \
 174         (NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val))))
 175 
 176 #define NREV_GE(var, val) \
 177         (NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val))))
 178 
 179 #define NREV_GT(var, val) \
 180         (NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val))))
 181 
 182 #define NREV_LT(var, val) \
 183         (NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val))))
 184 
 185 #define NREV_LE(var, val) \
 186         (NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val))))
 187 
 188 #define LCNREV_IS(var, val) \
 189         (LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val))))
 190 
 191 #define LCNREV_GE(var, val) \
 192         (LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val))))
 193 
 194 #define LCNREV_GT(var, val) \
 195         (LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val))))
 196 
 197 #define LCNREV_LT(var, val) \
 198         (LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val))))
 199 
 200 #define LCNREV_LE(var, val) \
 201         (LCNCONF_LE(val) && (!LCNCONF_GT(val) || ((var) <= (val))))
 202 
 203 #define D11REV_IS(var, val) \
 204         (D11CONF_HAS(val) && (D11CONF_IS(val) || ((var) == (val))))
 205 
 206 #define D11REV_GE(var, val) \
 207         (D11CONF_GE(val) && (!D11CONF_LT(val) || ((var) >= (val))))
 208 
 209 #define D11REV_GT(var, val) \
 210         (D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val))))
 211 
 212 #define D11REV_LT(var, val) \
 213         (D11CONF_LT(val) && (!D11CONF_GE(val) || ((var) < (val))))
 214 
 215 #define D11REV_LE(var, val) \
 216         (D11CONF_LE(val) && (!D11CONF_GT(val) || ((var) <= (val))))
 217 
 218 #define PHYTYPE_IS(var, val)\
 219         (PHYCONF_HAS(val) && (PHYCONF_IS(val) || ((var) == (val))))
 220 
 221 /* Set up PHYTYPE automatically: (depends on PHY_TYPE_X, from d11.h) */
 222 
 223 #define _PHYCONF_N (1 << PHY_TYPE_N)
 224 #define _PHYCONF_LCN (1 << PHY_TYPE_LCN)
 225 #define _PHYCONF_SSLPN (1 << PHY_TYPE_SSN)
 226 
 227 #define PHYTYPE (_PHYCONF_N | _PHYCONF_LCN | _PHYCONF_SSLPN)
 228 
 229 /* Utility macro to identify 802.11n (HT) capable PHYs */
 230 #define PHYTYPE_11N_CAP(phytype) \
 231         (PHYTYPE_IS(phytype, PHY_TYPE_N) ||     \
 232          PHYTYPE_IS(phytype, PHY_TYPE_LCN) || \
 233          PHYTYPE_IS(phytype, PHY_TYPE_SSN))
 234 
 235 /* Last but not least: shorter wlc-specific var checks */
 236 #define BRCMS_ISNPHY(band)              PHYTYPE_IS((band)->phytype, PHY_TYPE_N)
 237 #define BRCMS_ISLCNPHY(band)    PHYTYPE_IS((band)->phytype, PHY_TYPE_LCN)
 238 #define BRCMS_ISSSLPNPHY(band)  PHYTYPE_IS((band)->phytype, PHY_TYPE_SSN)
 239 
 240 #define BRCMS_PHY_11N_CAP(band) PHYTYPE_11N_CAP((band)->phytype)
 241 
 242 /**********************************************************************
 243  * ------------- End of Core phy/rev configuration. ----------------- *
 244  * ********************************************************************
 245  */
 246 
 247 #define BCMMSG(dev, fmt, args...)               \
 248 do {                                            \
 249         if (brcm_msg_level & BRCM_DL_INFO)      \
 250                 wiphy_err(dev, "%s: " fmt, __func__, ##args);   \
 251 } while (0)
 252 
 253 #ifdef CONFIG_BCM47XX
 254 /*
 255  * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
 256  * transactions. As a fix, a read after write is performed on certain places
 257  * in the code. Older chips and the newer 5357 family don't require this fix.
 258  */
 259 #define bcma_wflush16(c, o, v) \
 260         ({ bcma_write16(c, o, v); (void)bcma_read16(c, o); })
 261 #else
 262 #define bcma_wflush16(c, o, v)  bcma_write16(c, o, v)
 263 #endif                          /* CONFIG_BCM47XX */
 264 
 265 /* multi-bool data type: set of bools, mbool is true if any is set */
 266 
 267 /* set one bool */
 268 #define mboolset(mb, bit)               ((mb) |= (bit))
 269 /* clear one bool */
 270 #define mboolclr(mb, bit)               ((mb) &= ~(bit))
 271 /* true if one bool is set */
 272 #define mboolisset(mb, bit)             (((mb) & (bit)) != 0)
 273 #define mboolmaskset(mb, mask, val)     ((mb) = (((mb) & ~(mask)) | (val)))
 274 
 275 #define CEIL(x, y)              (((x) + ((y)-1)) / (y))
 276 
 277 /* forward declarations */
 278 struct wiphy;
 279 struct ieee80211_sta;
 280 struct ieee80211_tx_queue_params;
 281 struct brcms_info;
 282 struct brcms_c_info;
 283 struct brcms_hardware;
 284 struct brcms_band;
 285 struct dma_pub;
 286 struct si_pub;
 287 struct tx_status;
 288 struct d11rxhdr;
 289 struct txpwr_limits;
 290 
 291 /* iovar structure */
 292 struct brcmu_iovar {
 293         const char *name;       /* name for lookup and display */
 294         u16 varid;      /* id for switch */
 295         u16 flags;      /* driver-specific flag bits */
 296         u16 type;       /* base type of argument */
 297         u16 minlen;     /* min length for buffer vars */
 298 };
 299 
 300 /* brcm_msg_level is a bit vector with defs in defs.h */
 301 extern u32 brcm_msg_level;
 302 
 303 #endif                          /* _BRCM_TYPES_H_ */
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