drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h

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This source file includes following definitions.
brcmf_sdiod_freezing
brcmf_sdiod_try_freeze
brcmf_sdiod_freezer_count
brcmf_sdiod_freezer_uncount
   1 // SPDX-License-Identifier: ISC
   2 /*
   3  * Copyright (c) 2010 Broadcom Corporation
   4  */
   5 
   6 #ifndef BRCMFMAC_SDIO_H
   7 #define BRCMFMAC_SDIO_H
   8 
   9 #include <linux/skbuff.h>
  10 #include <linux/firmware.h>
  11 #include "firmware.h"
  12 
  13 #define SDIOD_FBR_SIZE          0x100
  14 
  15 /* io_en */
  16 #define SDIO_FUNC_ENABLE_1      0x02
  17 #define SDIO_FUNC_ENABLE_2      0x04
  18 
  19 /* io_rdys */
  20 #define SDIO_FUNC_READY_1       0x02
  21 #define SDIO_FUNC_READY_2       0x04
  22 
  23 /* intr_status */
  24 #define INTR_STATUS_FUNC1       0x2
  25 #define INTR_STATUS_FUNC2       0x4
  26 
  27 /* mask of register map */
  28 #define REG_F0_REG_MASK         0x7FF
  29 #define REG_F1_MISC_MASK        0x1FFFF
  30 
  31 /* function 0 vendor specific CCCR registers */
  32 
  33 #define SDIO_CCCR_BRCM_CARDCAP                  0xf0
  34 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT    BIT(1)
  35 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT        BIT(2)
  36 #define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC        BIT(3)
  37 
  38 /* Interrupt enable bits for each function */
  39 #define SDIO_CCCR_IEN_FUNC0                     BIT(0)
  40 #define SDIO_CCCR_IEN_FUNC1                     BIT(1)
  41 #define SDIO_CCCR_IEN_FUNC2                     BIT(2)
  42 
  43 #define SDIO_CCCR_BRCM_CARDCTRL                 0xf1
  44 #define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET       BIT(1)
  45 
  46 #define SDIO_CCCR_BRCM_SEPINT                   0xf2
  47 #define SDIO_CCCR_BRCM_SEPINT_MASK              BIT(0)
  48 #define SDIO_CCCR_BRCM_SEPINT_OE                BIT(1)
  49 #define SDIO_CCCR_BRCM_SEPINT_ACT_HI            BIT(2)
  50 
  51 /* function 1 miscellaneous registers */
  52 
  53 /* sprom command and status */
  54 #define SBSDIO_SPROM_CS                 0x10000
  55 /* sprom info register */
  56 #define SBSDIO_SPROM_INFO               0x10001
  57 /* sprom indirect access data byte 0 */
  58 #define SBSDIO_SPROM_DATA_LOW           0x10002
  59 /* sprom indirect access data byte 1 */
  60 #define SBSDIO_SPROM_DATA_HIGH          0x10003
  61 /* sprom indirect access addr byte 0 */
  62 #define SBSDIO_SPROM_ADDR_LOW           0x10004
  63 /* gpio select */
  64 #define SBSDIO_GPIO_SELECT              0x10005
  65 /* gpio output */
  66 #define SBSDIO_GPIO_OUT                 0x10006
  67 /* gpio enable */
  68 #define SBSDIO_GPIO_EN                  0x10007
  69 /* rev < 7, watermark for sdio device TX path */
  70 #define SBSDIO_WATERMARK                0x10008
  71 /* control busy signal generation */
  72 #define SBSDIO_DEVICE_CTL               0x10009
  73 
  74 /* SB Address Window Low (b15) */
  75 #define SBSDIO_FUNC1_SBADDRLOW          0x1000A
  76 /* SB Address Window Mid (b23:b16) */
  77 #define SBSDIO_FUNC1_SBADDRMID          0x1000B
  78 /* SB Address Window High (b31:b24)    */
  79 #define SBSDIO_FUNC1_SBADDRHIGH         0x1000C
  80 /* Frame Control (frame term/abort) */
  81 #define SBSDIO_FUNC1_FRAMECTRL          0x1000D
  82 /* ChipClockCSR (ALP/HT ctl/status) */
  83 #define SBSDIO_FUNC1_CHIPCLKCSR         0x1000E
  84 /* SdioPullUp (on cmd, d0-d2) */
  85 #define SBSDIO_FUNC1_SDIOPULLUP         0x1000F
  86 /* Write Frame Byte Count Low */
  87 #define SBSDIO_FUNC1_WFRAMEBCLO         0x10019
  88 /* Write Frame Byte Count High */
  89 #define SBSDIO_FUNC1_WFRAMEBCHI         0x1001A
  90 /* Read Frame Byte Count Low */
  91 #define SBSDIO_FUNC1_RFRAMEBCLO         0x1001B
  92 /* Read Frame Byte Count High */
  93 #define SBSDIO_FUNC1_RFRAMEBCHI         0x1001C
  94 /* MesBusyCtl (rev 11) */
  95 #define SBSDIO_FUNC1_MESBUSYCTRL        0x1001D
  96 /* Watermark for sdio device RX path */
  97 #define SBSDIO_MESBUSY_RXFIFO_WM_MASK   0x7F
  98 #define SBSDIO_MESBUSY_RXFIFO_WM_SHIFT  0
  99 /* Enable busy capability for MES access */
 100 #define SBSDIO_MESBUSYCTRL_ENAB         0x80
 101 #define SBSDIO_MESBUSYCTRL_ENAB_SHIFT   7
 102 
 103 /* Sdio Core Rev 12 */
 104 #define SBSDIO_FUNC1_WAKEUPCTRL         0x1001E
 105 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK         0x1
 106 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT        0
 107 #define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK          0x2
 108 #define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT         1
 109 #define SBSDIO_FUNC1_SLEEPCSR           0x1001F
 110 #define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK          0x1
 111 #define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT         0
 112 #define SBSDIO_FUNC1_SLEEPCSR_KSO_EN            1
 113 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK        0x2
 114 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT       1
 115 
 116 #define SBSDIO_FUNC1_MISC_REG_START     0x10000 /* f1 misc register start */
 117 #define SBSDIO_FUNC1_MISC_REG_LIMIT     0x1001F /* f1 misc register end */
 118 
 119 /* function 1 OCP space */
 120 
 121 /* sb offset addr is <= 15 bits, 32k */
 122 #define SBSDIO_SB_OFT_ADDR_MASK         0x07FFF
 123 #define SBSDIO_SB_OFT_ADDR_LIMIT        0x08000
 124 /* with b15, maps to 32-bit SB access */
 125 #define SBSDIO_SB_ACCESS_2_4B_FLAG      0x08000
 126 
 127 /* Address bits from SBADDR regs */
 128 #define SBSDIO_SBWINDOW_MASK            0xffff8000
 129 
 130 #define SDIOH_READ              0       /* Read request */
 131 #define SDIOH_WRITE             1       /* Write request */
 132 
 133 #define SDIOH_DATA_FIX          0       /* Fixed addressing */
 134 #define SDIOH_DATA_INC          1       /* Incremental addressing */
 135 
 136 /* internal return code */
 137 #define SUCCESS 0
 138 #define ERROR   1
 139 
 140 /* Packet alignment for most efficient SDIO (can change based on platform) */
 141 #define BRCMF_SDALIGN   (1 << 6)
 142 
 143 /* watchdog polling interval */
 144 #define BRCMF_WD_POLL   msecs_to_jiffies(10)
 145 
 146 /**
 147  * enum brcmf_sdiod_state - the state of the bus.
 148  *
 149  * @BRCMF_SDIOD_DOWN: Device can be accessed, no DPC.
 150  * @BRCMF_SDIOD_DATA: Ready for data transfers, DPC enabled.
 151  * @BRCMF_SDIOD_NOMEDIUM: No medium access to dongle possible.
 152  */
 153 enum brcmf_sdiod_state {
 154         BRCMF_SDIOD_DOWN,
 155         BRCMF_SDIOD_DATA,
 156         BRCMF_SDIOD_NOMEDIUM
 157 };
 158 
 159 struct brcmf_sdreg {
 160         int func;
 161         int offset;
 162         int value;
 163 };
 164 
 165 struct brcmf_sdio;
 166 struct brcmf_sdiod_freezer;
 167 
 168 struct brcmf_sdio_dev {
 169         struct sdio_func *func1;
 170         struct sdio_func *func2;
 171         u32 sbwad;                      /* Save backplane window address */
 172         struct brcmf_core *cc_core;     /* chipcommon core info struct */
 173         struct brcmf_sdio *bus;
 174         struct device *dev;
 175         struct brcmf_bus *bus_if;
 176         struct brcmf_mp_device *settings;
 177         bool oob_irq_requested;
 178         bool sd_irq_requested;
 179         bool irq_en;                    /* irq enable flags */
 180         spinlock_t irq_en_lock;
 181         bool irq_wake;                  /* irq wake enable flags */
 182         bool sg_support;
 183         uint max_request_size;
 184         ushort max_segment_count;
 185         uint max_segment_size;
 186         uint txglomsz;
 187         struct sg_table sgtable;
 188         char fw_name[BRCMF_FW_NAME_LEN];
 189         char nvram_name[BRCMF_FW_NAME_LEN];
 190         bool wowl_enabled;
 191         enum brcmf_sdiod_state state;
 192         struct brcmf_sdiod_freezer *freezer;
 193 };
 194 
 195 /* sdio core registers */
 196 struct sdpcmd_regs {
 197         u32 corecontrol;                /* 0x00, rev8 */
 198         u32 corestatus;                 /* rev8 */
 199         u32 PAD[1];
 200         u32 biststatus;                 /* rev8 */
 201 
 202         /* PCMCIA access */
 203         u16 pcmciamesportaladdr;        /* 0x010, rev8 */
 204         u16 PAD[1];
 205         u16 pcmciamesportalmask;        /* rev8 */
 206         u16 PAD[1];
 207         u16 pcmciawrframebc;            /* rev8 */
 208         u16 PAD[1];
 209         u16 pcmciaunderflowtimer;       /* rev8 */
 210         u16 PAD[1];
 211 
 212         /* interrupt */
 213         u32 intstatus;                  /* 0x020, rev8 */
 214         u32 hostintmask;                /* rev8 */
 215         u32 intmask;                    /* rev8 */
 216         u32 sbintstatus;                /* rev8 */
 217         u32 sbintmask;                  /* rev8 */
 218         u32 funcintmask;                /* rev4 */
 219         u32 PAD[2];
 220         u32 tosbmailbox;                /* 0x040, rev8 */
 221         u32 tohostmailbox;              /* rev8 */
 222         u32 tosbmailboxdata;            /* rev8 */
 223         u32 tohostmailboxdata;          /* rev8 */
 224 
 225         /* synchronized access to registers in SDIO clock domain */
 226         u32 sdioaccess;                 /* 0x050, rev8 */
 227         u32 PAD[3];
 228 
 229         /* PCMCIA frame control */
 230         u8 pcmciaframectrl;             /* 0x060, rev8 */
 231         u8 PAD[3];
 232         u8 pcmciawatermark;             /* rev8 */
 233         u8 PAD[155];
 234 
 235         /* interrupt batching control */
 236         u32 intrcvlazy;                 /* 0x100, rev8 */
 237         u32 PAD[3];
 238 
 239         /* counters */
 240         u32 cmd52rd;                    /* 0x110, rev8 */
 241         u32 cmd52wr;                    /* rev8 */
 242         u32 cmd53rd;                    /* rev8 */
 243         u32 cmd53wr;                    /* rev8 */
 244         u32 abort;                      /* rev8 */
 245         u32 datacrcerror;               /* rev8 */
 246         u32 rdoutofsync;                /* rev8 */
 247         u32 wroutofsync;                /* rev8 */
 248         u32 writebusy;                  /* rev8 */
 249         u32 readwait;                   /* rev8 */
 250         u32 readterm;                   /* rev8 */
 251         u32 writeterm;                  /* rev8 */
 252         u32 PAD[40];
 253         u32 clockctlstatus;             /* rev8 */
 254         u32 PAD[7];
 255 
 256         u32 PAD[128];                   /* DMA engines */
 257 
 258         /* SDIO/PCMCIA CIS region */
 259         char cis[512];                  /* 0x400-0x5ff, rev6 */
 260 
 261         /* PCMCIA function control registers */
 262         char pcmciafcr[256];            /* 0x600-6ff, rev6 */
 263         u16 PAD[55];
 264 
 265         /* PCMCIA backplane access */
 266         u16 backplanecsr;               /* 0x76E, rev6 */
 267         u16 backplaneaddr0;             /* rev6 */
 268         u16 backplaneaddr1;             /* rev6 */
 269         u16 backplaneaddr2;             /* rev6 */
 270         u16 backplaneaddr3;             /* rev6 */
 271         u16 backplanedata0;             /* rev6 */
 272         u16 backplanedata1;             /* rev6 */
 273         u16 backplanedata2;             /* rev6 */
 274         u16 backplanedata3;             /* rev6 */
 275         u16 PAD[31];
 276 
 277         /* sprom "size" & "blank" info */
 278         u16 spromstatus;                /* 0x7BE, rev2 */
 279         u32 PAD[464];
 280 
 281         u16 PAD[0x80];
 282 };
 283 
 284 /* Register/deregister interrupt handler. */
 285 int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev);
 286 void brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev);
 287 
 288 /* SDIO device register access interface */
 289 /* Accessors for SDIO Function 0 */
 290 #define brcmf_sdiod_func0_rb(sdiodev, addr, r) \
 291         sdio_f0_readb((sdiodev)->func1, (addr), (r))
 292 
 293 #define brcmf_sdiod_func0_wb(sdiodev, addr, v, ret) \
 294         sdio_f0_writeb((sdiodev)->func1, (v), (addr), (ret))
 295 
 296 /* Accessors for SDIO Function 1 */
 297 #define brcmf_sdiod_readb(sdiodev, addr, r) \
 298         sdio_readb((sdiodev)->func1, (addr), (r))
 299 
 300 #define brcmf_sdiod_writeb(sdiodev, addr, v, ret) \
 301         sdio_writeb((sdiodev)->func1, (v), (addr), (ret))
 302 
 303 u32 brcmf_sdiod_readl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
 304 void brcmf_sdiod_writel(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data,
 305                         int *ret);
 306 
 307 /* Buffer transfer to/from device (client) core via cmd53.
 308  *   fn:       function number
 309  *   flags:    backplane width, address increment, sync/async
 310  *   buf:      pointer to memory data buffer
 311  *   nbytes:   number of bytes to transfer to/from buf
 312  *   pkt:      pointer to packet associated with buf (if any)
 313  *   complete: callback function for command completion (async only)
 314  *   handle:   handle for completion callback (first arg in callback)
 315  * Returns 0 or error code.
 316  * NOTE: Async operation is not currently supported.
 317  */
 318 int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev,
 319                          struct sk_buff_head *pktq);
 320 int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
 321 
 322 int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt);
 323 int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
 324 int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev,
 325                            struct sk_buff_head *pktq, uint totlen);
 326 
 327 /* Flags bits */
 328 
 329 /* Four-byte target (backplane) width (vs. two-byte) */
 330 #define SDIO_REQ_4BYTE  0x1
 331 /* Fixed address (FIFO) (vs. incrementing address) */
 332 #define SDIO_REQ_FIXED  0x2
 333 
 334 /* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
 335  *   rw:       read or write (0/1)
 336  *   addr:     direct SDIO address
 337  *   buf:      pointer to memory data buffer
 338  *   nbytes:   number of bytes to transfer to/from buf
 339  * Returns 0 or error code.
 340  */
 341 int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address,
 342                       u8 *data, uint size);
 343 
 344 /* Issue an abort to the specified function */
 345 int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, struct sdio_func *func);
 346 
 347 void brcmf_sdiod_sgtable_alloc(struct brcmf_sdio_dev *sdiodev);
 348 void brcmf_sdiod_change_state(struct brcmf_sdio_dev *sdiodev,
 349                               enum brcmf_sdiod_state state);
 350 #ifdef CONFIG_PM_SLEEP
 351 bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev);
 352 void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev);
 353 void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev);
 354 void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev);
 355 #else
 356 static inline bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev)
 357 {
 358         return false;
 359 }
 360 static inline void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev)
 361 {
 362 }
 363 static inline void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev)
 364 {
 365 }
 366 static inline void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev)
 367 {
 368 }
 369 #endif /* CONFIG_PM_SLEEP */
 370 
 371 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
 372 void brcmf_sdio_remove(struct brcmf_sdio *bus);
 373 void brcmf_sdio_isr(struct brcmf_sdio *bus);
 374 
 375 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active);
 376 void brcmf_sdio_wowl_config(struct device *dev, bool enabled);
 377 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep);
 378 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus);
 379 
 380 #endif /* BRCMFMAC_SDIO_H */
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h

INCLUDED FROM

DEFINITIONS
