This source file includes following definitions.
- brcmf_chip_sb_corerev
- brcmf_chip_sb_iscoreup
- brcmf_chip_ai_iscoreup
- brcmf_chip_sb_coredisable
- brcmf_chip_ai_coredisable
- brcmf_chip_sb_resetcore
- brcmf_chip_ai_resetcore
- brcmf_chip_name
- brcmf_chip_add_core
- brcmf_chip_cores_check
- brcmf_chip_core_read32
- brcmf_chip_core_write32
- brcmf_chip_socram_banksize
- brcmf_chip_socram_ramsize
- brcmf_chip_sysmem_ramsize
- brcmf_chip_tcm_ramsize
- brcmf_chip_tcm_rambase
- brcmf_chip_get_raminfo
- brcmf_chip_dmp_get_desc
- brcmf_chip_dmp_get_regaddr
- brcmf_chip_dmp_erom_scan
- brcmf_chip_recognition
- brcmf_chip_disable_arm
- brcmf_chip_setup
- brcmf_chip_attach
- brcmf_chip_detach
- brcmf_chip_get_core
- brcmf_chip_get_chipcommon
- brcmf_chip_get_pmu
- brcmf_chip_iscoreup
- brcmf_chip_coredisable
- brcmf_chip_resetcore
- brcmf_chip_cm3_set_passive
- brcmf_chip_cm3_set_active
- brcmf_chip_cr4_set_passive
- brcmf_chip_cr4_set_active
- brcmf_chip_ca7_set_passive
- brcmf_chip_ca7_set_active
- brcmf_chip_set_passive
- brcmf_chip_set_active
- brcmf_chip_sr_capable
1
2
3
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/list.h>
8 #include <linux/ssb/ssb_regs.h>
9 #include <linux/bcma/bcma.h>
10 #include <linux/bcma/bcma_regs.h>
11
12 #include <defs.h>
13 #include <soc.h>
14 #include <brcm_hw_ids.h>
15 #include <brcmu_utils.h>
16 #include <chipcommon.h>
17 #include "debug.h"
18 #include "chip.h"
19
20
21 #define SOCI_SB 0
22 #define SOCI_AI 1
23
24
25 #define DMP_DESC_TYPE_MSK 0x0000000F
26 #define DMP_DESC_EMPTY 0x00000000
27 #define DMP_DESC_VALID 0x00000001
28 #define DMP_DESC_COMPONENT 0x00000001
29 #define DMP_DESC_MASTER_PORT 0x00000003
30 #define DMP_DESC_ADDRESS 0x00000005
31 #define DMP_DESC_ADDRSIZE_GT32 0x00000008
32 #define DMP_DESC_EOT 0x0000000F
33
34 #define DMP_COMP_DESIGNER 0xFFF00000
35 #define DMP_COMP_DESIGNER_S 20
36 #define DMP_COMP_PARTNUM 0x000FFF00
37 #define DMP_COMP_PARTNUM_S 8
38 #define DMP_COMP_CLASS 0x000000F0
39 #define DMP_COMP_CLASS_S 4
40 #define DMP_COMP_REVISION 0xFF000000
41 #define DMP_COMP_REVISION_S 24
42 #define DMP_COMP_NUM_SWRAP 0x00F80000
43 #define DMP_COMP_NUM_SWRAP_S 19
44 #define DMP_COMP_NUM_MWRAP 0x0007C000
45 #define DMP_COMP_NUM_MWRAP_S 14
46 #define DMP_COMP_NUM_SPORT 0x00003E00
47 #define DMP_COMP_NUM_SPORT_S 9
48 #define DMP_COMP_NUM_MPORT 0x000001F0
49 #define DMP_COMP_NUM_MPORT_S 4
50
51 #define DMP_MASTER_PORT_UID 0x0000FF00
52 #define DMP_MASTER_PORT_UID_S 8
53 #define DMP_MASTER_PORT_NUM 0x000000F0
54 #define DMP_MASTER_PORT_NUM_S 4
55
56 #define DMP_SLAVE_ADDR_BASE 0xFFFFF000
57 #define DMP_SLAVE_ADDR_BASE_S 12
58 #define DMP_SLAVE_PORT_NUM 0x00000F00
59 #define DMP_SLAVE_PORT_NUM_S 8
60 #define DMP_SLAVE_TYPE 0x000000C0
61 #define DMP_SLAVE_TYPE_S 6
62 #define DMP_SLAVE_TYPE_SLAVE 0
63 #define DMP_SLAVE_TYPE_BRIDGE 1
64 #define DMP_SLAVE_TYPE_SWRAP 2
65 #define DMP_SLAVE_TYPE_MWRAP 3
66 #define DMP_SLAVE_SIZE_TYPE 0x00000030
67 #define DMP_SLAVE_SIZE_TYPE_S 4
68 #define DMP_SLAVE_SIZE_4K 0
69 #define DMP_SLAVE_SIZE_8K 1
70 #define DMP_SLAVE_SIZE_16K 2
71 #define DMP_SLAVE_SIZE_DESC 3
72
73
74 #define CIB_REV_MASK 0xff000000
75 #define CIB_REV_SHIFT 24
76
77
78 #define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
79
80
81 #define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
82 #define D11_BCMA_IOCTL_PHYRESET 0x0008
83
84
85
86
87 #define BCM4329_CORE_BUS_BASE 0x18011000
88
89 #define BCM4329_CORE_SOCRAM_BASE 0x18003000
90
91 #define BCM4329_CORE_ARM_BASE 0x18002000
92
93
94 #define BRCMF_CHIP_MAX_MEMSIZE (4 * 1024 * 1024)
95
96 #define CORE_SB(base, field) \
97 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
98 #define SBCOREREV(sbidh) \
99 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
100 ((sbidh) & SSB_IDHIGH_RCLO))
101
102 struct sbconfig {
103 u32 PAD[2];
104 u32 sbipsflag;
105 u32 PAD[3];
106 u32 sbtpsflag;
107 u32 PAD[11];
108 u32 sbtmerrloga;
109 u32 PAD;
110 u32 sbtmerrlog;
111 u32 PAD[3];
112 u32 sbadmatch3;
113 u32 PAD;
114 u32 sbadmatch2;
115 u32 PAD;
116 u32 sbadmatch1;
117 u32 PAD[7];
118 u32 sbimstate;
119 u32 sbintvec;
120 u32 sbtmstatelow;
121 u32 sbtmstatehigh;
122 u32 sbbwa0;
123 u32 PAD;
124 u32 sbimconfiglow;
125 u32 sbimconfighigh;
126 u32 sbadmatch0;
127 u32 PAD;
128 u32 sbtmconfiglow;
129 u32 sbtmconfighigh;
130 u32 sbbconfig;
131 u32 PAD;
132 u32 sbbstate;
133 u32 PAD[3];
134 u32 sbactcnfg;
135 u32 PAD[3];
136 u32 sbflagst;
137 u32 PAD[3];
138 u32 sbidlow;
139 u32 sbidhigh;
140 };
141
142
143 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
144 #define SOCRAM_BANKINFO_SZMASK 0x0000007f
145 #define SOCRAM_BANKIDX_ROM_MASK 0x00000100
146
147 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
148
149 #define SOCRAM_MEMTYPE_RAM 0
150 #define SOCRAM_MEMTYPE_R0M 1
151 #define SOCRAM_MEMTYPE_DEVRAM 2
152
153 #define SOCRAM_BANKINFO_SZBASE 8192
154 #define SRCI_LSS_MASK 0x00f00000
155 #define SRCI_LSS_SHIFT 20
156 #define SRCI_SRNB_MASK 0xf0
157 #define SRCI_SRNB_MASK_EXT 0x100
158 #define SRCI_SRNB_SHIFT 4
159 #define SRCI_SRBSZ_MASK 0xf
160 #define SRCI_SRBSZ_SHIFT 0
161 #define SR_BSZ_BASE 14
162
163 struct sbsocramregs {
164 u32 coreinfo;
165 u32 bwalloc;
166 u32 extracoreinfo;
167 u32 biststat;
168 u32 bankidx;
169 u32 standbyctrl;
170
171 u32 errlogstatus;
172 u32 errlogaddr;
173
174 u32 cambankidx;
175 u32 cambankstandbyctrl;
176 u32 cambankpatchctrl;
177 u32 cambankpatchtblbaseaddr;
178 u32 cambankcmdreg;
179 u32 cambankdatareg;
180 u32 cambankmaskreg;
181 u32 PAD[1];
182 u32 bankinfo;
183 u32 bankpda;
184 u32 PAD[14];
185 u32 extmemconfig;
186 u32 extmemparitycsr;
187 u32 extmemparityerrdata;
188 u32 extmemparityerrcnt;
189 u32 extmemwrctrlandsize;
190 u32 PAD[84];
191 u32 workaround;
192 u32 pwrctl;
193 u32 PAD[133];
194 u32 sr_control;
195 u32 sr_status;
196 u32 sr_address;
197 u32 sr_data;
198 };
199
200 #define SOCRAMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
201 #define SYSMEMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
202
203 #define ARMCR4_CAP (0x04)
204 #define ARMCR4_BANKIDX (0x40)
205 #define ARMCR4_BANKINFO (0x44)
206 #define ARMCR4_BANKPDA (0x4C)
207
208 #define ARMCR4_TCBBNB_MASK 0xf0
209 #define ARMCR4_TCBBNB_SHIFT 4
210 #define ARMCR4_TCBANB_MASK 0xf
211 #define ARMCR4_TCBANB_SHIFT 0
212
213 #define ARMCR4_BSZ_MASK 0x3f
214 #define ARMCR4_BSZ_MULT 8192
215
216 struct brcmf_core_priv {
217 struct brcmf_core pub;
218 u32 wrapbase;
219 struct list_head list;
220 struct brcmf_chip_priv *chip;
221 };
222
223 struct brcmf_chip_priv {
224 struct brcmf_chip pub;
225 const struct brcmf_buscore_ops *ops;
226 void *ctx;
227
228 struct list_head cores;
229 u16 num_cores;
230
231 bool (*iscoreup)(struct brcmf_core_priv *core);
232 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
233 u32 reset);
234 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
235 u32 postreset);
236 };
237
238 static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
239 struct brcmf_core *core)
240 {
241 u32 regdata;
242
243 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
244 core->rev = SBCOREREV(regdata);
245 }
246
247 static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
248 {
249 struct brcmf_chip_priv *ci;
250 u32 regdata;
251 u32 address;
252
253 ci = core->chip;
254 address = CORE_SB(core->pub.base, sbtmstatelow);
255 regdata = ci->ops->read32(ci->ctx, address);
256 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
257 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
258 return SSB_TMSLOW_CLOCK == regdata;
259 }
260
261 static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
262 {
263 struct brcmf_chip_priv *ci;
264 u32 regdata;
265 bool ret;
266
267 ci = core->chip;
268 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
269 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
270
271 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
272 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
273
274 return ret;
275 }
276
277 static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
278 u32 prereset, u32 reset)
279 {
280 struct brcmf_chip_priv *ci;
281 u32 val, base;
282
283 ci = core->chip;
284 base = core->pub.base;
285 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
286 if (val & SSB_TMSLOW_RESET)
287 return;
288
289 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
290 if ((val & SSB_TMSLOW_CLOCK) != 0) {
291
292
293
294
295 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
296 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
297 val | SSB_TMSLOW_REJECT);
298
299 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
300 udelay(1);
301 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
302 & SSB_TMSHIGH_BUSY), 100000);
303
304 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
305 if (val & SSB_TMSHIGH_BUSY)
306 brcmf_err("core state still busy\n");
307
308 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
309 if (val & SSB_IDLOW_INITIATOR) {
310 val = ci->ops->read32(ci->ctx,
311 CORE_SB(base, sbimstate));
312 val |= SSB_IMSTATE_REJECT;
313 ci->ops->write32(ci->ctx,
314 CORE_SB(base, sbimstate), val);
315 val = ci->ops->read32(ci->ctx,
316 CORE_SB(base, sbimstate));
317 udelay(1);
318 SPINWAIT((ci->ops->read32(ci->ctx,
319 CORE_SB(base, sbimstate)) &
320 SSB_IMSTATE_BUSY), 100000);
321 }
322
323
324 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
325 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
326 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
327 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
328 udelay(10);
329
330
331 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
332 if (val & SSB_IDLOW_INITIATOR) {
333 val = ci->ops->read32(ci->ctx,
334 CORE_SB(base, sbimstate));
335 val &= ~SSB_IMSTATE_REJECT;
336 ci->ops->write32(ci->ctx,
337 CORE_SB(base, sbimstate), val);
338 }
339 }
340
341
342 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
343 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
344 udelay(1);
345 }
346
347 static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
348 u32 prereset, u32 reset)
349 {
350 struct brcmf_chip_priv *ci;
351 u32 regdata;
352
353 ci = core->chip;
354
355
356 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
357 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
358 goto in_reset_configure;
359
360
361 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
362 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
363 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
364
365
366 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
367 BCMA_RESET_CTL_RESET);
368 usleep_range(10, 20);
369
370
371 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
372 BCMA_RESET_CTL_RESET, 300);
373
374 in_reset_configure:
375
376 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
377 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
378 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
379 }
380
381 static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
382 u32 reset, u32 postreset)
383 {
384 struct brcmf_chip_priv *ci;
385 u32 regdata;
386 u32 base;
387
388 ci = core->chip;
389 base = core->pub.base;
390
391
392
393
394 brcmf_chip_sb_coredisable(core, 0, 0);
395
396
397
398
399
400
401 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
402 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
403 SSB_TMSLOW_RESET);
404 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
405 udelay(1);
406
407
408 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
409 if (regdata & SSB_TMSHIGH_SERR)
410 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
411
412 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
413 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
414 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
415 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
416 }
417
418
419 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
420 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
421 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
422 udelay(1);
423
424
425 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
426 SSB_TMSLOW_CLOCK);
427 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
428 udelay(1);
429 }
430
431 static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
432 u32 reset, u32 postreset)
433 {
434 struct brcmf_chip_priv *ci;
435 int count;
436
437 ci = core->chip;
438
439
440 brcmf_chip_ai_coredisable(core, prereset, reset);
441
442 count = 0;
443 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
444 BCMA_RESET_CTL_RESET) {
445 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
446 count++;
447 if (count > 50)
448 break;
449 usleep_range(40, 60);
450 }
451
452 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
453 postreset | BCMA_IOCTL_CLK);
454 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
455 }
456
457 char *brcmf_chip_name(u32 id, u32 rev, char *buf, uint len)
458 {
459 const char *fmt;
460
461 fmt = ((id > 0xa000) || (id < 0x4000)) ? "BCM%d/%u" : "BCM%x/%u";
462 snprintf(buf, len, fmt, id, rev);
463 return buf;
464 }
465
466 static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
467 u16 coreid, u32 base,
468 u32 wrapbase)
469 {
470 struct brcmf_core_priv *core;
471
472 core = kzalloc(sizeof(*core), GFP_KERNEL);
473 if (!core)
474 return ERR_PTR(-ENOMEM);
475
476 core->pub.id = coreid;
477 core->pub.base = base;
478 core->chip = ci;
479 core->wrapbase = wrapbase;
480
481 list_add_tail(&core->list, &ci->cores);
482 return &core->pub;
483 }
484
485
486 static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
487 {
488 struct brcmf_core_priv *core;
489 bool need_socram = false;
490 bool has_socram = false;
491 bool cpu_found = false;
492 int idx = 1;
493
494 list_for_each_entry(core, &ci->cores, list) {
495 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
496 idx++, core->pub.id, core->pub.rev, core->pub.base,
497 core->wrapbase);
498
499 switch (core->pub.id) {
500 case BCMA_CORE_ARM_CM3:
501 cpu_found = true;
502 need_socram = true;
503 break;
504 case BCMA_CORE_INTERNAL_MEM:
505 has_socram = true;
506 break;
507 case BCMA_CORE_ARM_CR4:
508 cpu_found = true;
509 break;
510 case BCMA_CORE_ARM_CA7:
511 cpu_found = true;
512 break;
513 default:
514 break;
515 }
516 }
517
518 if (!cpu_found) {
519 brcmf_err("CPU core not detected\n");
520 return -ENXIO;
521 }
522
523 if (need_socram && !has_socram) {
524 brcmf_err("RAM core not provided with ARM CM3 core\n");
525 return -ENODEV;
526 }
527 return 0;
528 }
529
530 static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg)
531 {
532 return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
533 }
534
535 static void brcmf_chip_core_write32(struct brcmf_core_priv *core,
536 u16 reg, u32 val)
537 {
538 core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val);
539 }
540
541 static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx,
542 u32 *banksize)
543 {
544 u32 bankinfo;
545 u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
546
547 bankidx |= idx;
548 brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx);
549 bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo));
550 *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1;
551 *banksize *= SOCRAM_BANKINFO_SZBASE;
552 return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK);
553 }
554
555 static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize,
556 u32 *srsize)
557 {
558 u32 coreinfo;
559 uint nb, banksize, lss;
560 bool retent;
561 int i;
562
563 *ramsize = 0;
564 *srsize = 0;
565
566 if (WARN_ON(sr->pub.rev < 4))
567 return;
568
569 if (!brcmf_chip_iscoreup(&sr->pub))
570 brcmf_chip_resetcore(&sr->pub, 0, 0, 0);
571
572
573 coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo));
574 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
575
576 if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) {
577 banksize = (coreinfo & SRCI_SRBSZ_MASK);
578 lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
579 if (lss != 0)
580 nb--;
581 *ramsize = nb * (1 << (banksize + SR_BSZ_BASE));
582 if (lss != 0)
583 *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
584 } else {
585
586 if (sr->pub.rev >= 23) {
587 nb = (coreinfo & (SRCI_SRNB_MASK | SRCI_SRNB_MASK_EXT))
588 >> SRCI_SRNB_SHIFT;
589 } else {
590 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
591 }
592 for (i = 0; i < nb; i++) {
593 retent = brcmf_chip_socram_banksize(sr, i, &banksize);
594 *ramsize += banksize;
595 if (retent)
596 *srsize += banksize;
597 }
598 }
599
600
601 switch (sr->chip->pub.chip) {
602 case BRCM_CC_4334_CHIP_ID:
603 if (sr->chip->pub.chiprev < 2)
604 *srsize = (32 * 1024);
605 break;
606 case BRCM_CC_43430_CHIP_ID:
607
608
609
610 *srsize = (64 * 1024);
611 break;
612 default:
613 break;
614 }
615 }
616
617
618 static u32 brcmf_chip_sysmem_ramsize(struct brcmf_core_priv *sysmem)
619 {
620 u32 memsize = 0;
621 u32 coreinfo;
622 u32 idx;
623 u32 nb;
624 u32 banksize;
625
626 if (!brcmf_chip_iscoreup(&sysmem->pub))
627 brcmf_chip_resetcore(&sysmem->pub, 0, 0, 0);
628
629 coreinfo = brcmf_chip_core_read32(sysmem, SYSMEMREGOFFS(coreinfo));
630 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
631
632 for (idx = 0; idx < nb; idx++) {
633 brcmf_chip_socram_banksize(sysmem, idx, &banksize);
634 memsize += banksize;
635 }
636
637 return memsize;
638 }
639
640
641 static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
642 {
643 u32 corecap;
644 u32 memsize = 0;
645 u32 nab;
646 u32 nbb;
647 u32 totb;
648 u32 bxinfo;
649 u32 idx;
650
651 corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP);
652
653 nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
654 nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
655 totb = nab + nbb;
656
657 for (idx = 0; idx < totb; idx++) {
658 brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx);
659 bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO);
660 memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
661 }
662
663 return memsize;
664 }
665
666 static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
667 {
668 switch (ci->pub.chip) {
669 case BRCM_CC_4345_CHIP_ID:
670 return 0x198000;
671 case BRCM_CC_4335_CHIP_ID:
672 case BRCM_CC_4339_CHIP_ID:
673 case BRCM_CC_4350_CHIP_ID:
674 case BRCM_CC_4354_CHIP_ID:
675 case BRCM_CC_4356_CHIP_ID:
676 case BRCM_CC_43567_CHIP_ID:
677 case BRCM_CC_43569_CHIP_ID:
678 case BRCM_CC_43570_CHIP_ID:
679 case BRCM_CC_4358_CHIP_ID:
680 case BRCM_CC_4359_CHIP_ID:
681 case BRCM_CC_43602_CHIP_ID:
682 case BRCM_CC_4371_CHIP_ID:
683 return 0x180000;
684 case BRCM_CC_43465_CHIP_ID:
685 case BRCM_CC_43525_CHIP_ID:
686 case BRCM_CC_4365_CHIP_ID:
687 case BRCM_CC_4366_CHIP_ID:
688 case BRCM_CC_43664_CHIP_ID:
689 return 0x200000;
690 case CY_CC_4373_CHIP_ID:
691 return 0x160000;
692 default:
693 brcmf_err("unknown chip: %s\n", ci->pub.name);
694 break;
695 }
696 return 0;
697 }
698
699 int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
700 {
701 struct brcmf_chip_priv *ci = container_of(pub, struct brcmf_chip_priv,
702 pub);
703 struct brcmf_core_priv *mem_core;
704 struct brcmf_core *mem;
705
706 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
707 if (mem) {
708 mem_core = container_of(mem, struct brcmf_core_priv, pub);
709 ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
710 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
711 if (!ci->pub.rambase) {
712 brcmf_err("RAM base not provided with ARM CR4 core\n");
713 return -EINVAL;
714 }
715 } else {
716 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_SYS_MEM);
717 if (mem) {
718 mem_core = container_of(mem, struct brcmf_core_priv,
719 pub);
720 ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core);
721 ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
722 if (!ci->pub.rambase) {
723 brcmf_err("RAM base not provided with ARM CA7 core\n");
724 return -EINVAL;
725 }
726 } else {
727 mem = brcmf_chip_get_core(&ci->pub,
728 BCMA_CORE_INTERNAL_MEM);
729 if (!mem) {
730 brcmf_err("No memory cores found\n");
731 return -ENOMEM;
732 }
733 mem_core = container_of(mem, struct brcmf_core_priv,
734 pub);
735 brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize,
736 &ci->pub.srsize);
737 }
738 }
739 brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n",
740 ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize,
741 ci->pub.srsize, ci->pub.srsize);
742
743 if (!ci->pub.ramsize) {
744 brcmf_err("RAM size is undetermined\n");
745 return -ENOMEM;
746 }
747
748 if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) {
749 brcmf_err("RAM size is incorrect\n");
750 return -ENOMEM;
751 }
752
753 return 0;
754 }
755
756 static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
757 u8 *type)
758 {
759 u32 val;
760
761
762 val = ci->ops->read32(ci->ctx, *eromaddr);
763 *eromaddr += 4;
764
765 if (!type)
766 return val;
767
768
769 *type = (val & DMP_DESC_TYPE_MSK);
770 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
771 *type = DMP_DESC_ADDRESS;
772
773 return val;
774 }
775
776 static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
777 u32 *regbase, u32 *wrapbase)
778 {
779 u8 desc;
780 u32 val, szdesc;
781 u8 mpnum = 0;
782 u8 stype, sztype, wraptype;
783
784 *regbase = 0;
785 *wrapbase = 0;
786
787 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
788 if (desc == DMP_DESC_MASTER_PORT) {
789 mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S;
790 wraptype = DMP_SLAVE_TYPE_MWRAP;
791 } else if (desc == DMP_DESC_ADDRESS) {
792
793 *eromaddr -= 4;
794 wraptype = DMP_SLAVE_TYPE_SWRAP;
795 } else {
796 *eromaddr -= 4;
797 return -EILSEQ;
798 }
799
800 do {
801
802 do {
803 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
804
805 if (desc == DMP_DESC_EOT) {
806 *eromaddr -= 4;
807 return -EFAULT;
808 }
809 } while (desc != DMP_DESC_ADDRESS &&
810 desc != DMP_DESC_COMPONENT);
811
812
813 if (desc == DMP_DESC_COMPONENT) {
814 *eromaddr -= 4;
815 return 0;
816 }
817
818
819 if (val & DMP_DESC_ADDRSIZE_GT32)
820 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
821
822 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
823
824
825 if (sztype == DMP_SLAVE_SIZE_DESC) {
826 szdesc = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
827
828 if (szdesc & DMP_DESC_ADDRSIZE_GT32)
829 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
830 }
831
832
833 if (sztype != DMP_SLAVE_SIZE_4K &&
834 sztype != DMP_SLAVE_SIZE_8K)
835 continue;
836
837 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
838
839
840 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
841 *regbase = val & DMP_SLAVE_ADDR_BASE;
842 if (*wrapbase == 0 && stype == wraptype)
843 *wrapbase = val & DMP_SLAVE_ADDR_BASE;
844 } while (*regbase == 0 || *wrapbase == 0);
845
846 return 0;
847 }
848
849 static
850 int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
851 {
852 struct brcmf_core *core;
853 u32 eromaddr;
854 u8 desc_type = 0;
855 u32 val;
856 u16 id;
857 u8 nmp, nsp, nmw, nsw, rev;
858 u32 base, wrap;
859 int err;
860
861 eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
862
863 while (desc_type != DMP_DESC_EOT) {
864 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
865 if (!(val & DMP_DESC_VALID))
866 continue;
867
868 if (desc_type == DMP_DESC_EMPTY)
869 continue;
870
871
872 if (desc_type != DMP_DESC_COMPONENT)
873 continue;
874
875 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
876
877
878 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
879 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
880 return -EFAULT;
881
882
883 nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S;
884 nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S;
885 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
886 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
887 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
888
889
890 if (nmw + nsw == 0 &&
891 id != BCMA_CORE_PMU &&
892 id != BCMA_CORE_GCI)
893 continue;
894
895
896 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
897 if (err)
898 continue;
899
900
901 core = brcmf_chip_add_core(ci, id, base, wrap);
902 if (IS_ERR(core))
903 return PTR_ERR(core);
904
905 core->rev = rev;
906 }
907
908 return 0;
909 }
910
911 static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
912 {
913 struct brcmf_core *core;
914 u32 regdata;
915 u32 socitype;
916 int ret;
917
918
919
920
921
922
923 regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
924 ci->pub.chip = regdata & CID_ID_MASK;
925 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
926 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
927
928 brcmf_chip_name(ci->pub.chip, ci->pub.chiprev,
929 ci->pub.name, sizeof(ci->pub.name));
930 brcmf_dbg(INFO, "found %s chip: %s\n",
931 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name);
932
933 if (socitype == SOCI_SB) {
934 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
935 brcmf_err("SB chip is not supported\n");
936 return -ENODEV;
937 }
938 ci->iscoreup = brcmf_chip_sb_iscoreup;
939 ci->coredisable = brcmf_chip_sb_coredisable;
940 ci->resetcore = brcmf_chip_sb_resetcore;
941
942 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
943 SI_ENUM_BASE, 0);
944 brcmf_chip_sb_corerev(ci, core);
945 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
946 BCM4329_CORE_BUS_BASE, 0);
947 brcmf_chip_sb_corerev(ci, core);
948 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
949 BCM4329_CORE_SOCRAM_BASE, 0);
950 brcmf_chip_sb_corerev(ci, core);
951 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
952 BCM4329_CORE_ARM_BASE, 0);
953 brcmf_chip_sb_corerev(ci, core);
954
955 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
956 brcmf_chip_sb_corerev(ci, core);
957 } else if (socitype == SOCI_AI) {
958 ci->iscoreup = brcmf_chip_ai_iscoreup;
959 ci->coredisable = brcmf_chip_ai_coredisable;
960 ci->resetcore = brcmf_chip_ai_resetcore;
961
962 brcmf_chip_dmp_erom_scan(ci);
963 } else {
964 brcmf_err("chip backplane type %u is not supported\n",
965 socitype);
966 return -ENODEV;
967 }
968
969 ret = brcmf_chip_cores_check(ci);
970 if (ret)
971 return ret;
972
973
974 brcmf_chip_set_passive(&ci->pub);
975
976
977
978
979 if (ci->ops->reset) {
980 ci->ops->reset(ci->ctx, &ci->pub);
981 brcmf_chip_set_passive(&ci->pub);
982 }
983
984 return brcmf_chip_get_raminfo(&ci->pub);
985 }
986
987 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
988 {
989 struct brcmf_core *core;
990 struct brcmf_core_priv *cpu;
991 u32 val;
992
993
994 core = brcmf_chip_get_core(&chip->pub, id);
995 if (!core)
996 return;
997
998 switch (id) {
999 case BCMA_CORE_ARM_CM3:
1000 brcmf_chip_coredisable(core, 0, 0);
1001 break;
1002 case BCMA_CORE_ARM_CR4:
1003 case BCMA_CORE_ARM_CA7:
1004 cpu = container_of(core, struct brcmf_core_priv, pub);
1005
1006
1007 val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL);
1008 val &= ARMCR4_BCMA_IOCTL_CPUHALT;
1009 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
1010 ARMCR4_BCMA_IOCTL_CPUHALT);
1011 break;
1012 default:
1013 brcmf_err("unknown id: %u\n", id);
1014 break;
1015 }
1016 }
1017
1018 static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
1019 {
1020 struct brcmf_chip *pub;
1021 struct brcmf_core_priv *cc;
1022 struct brcmf_core *pmu;
1023 u32 base;
1024 u32 val;
1025 int ret = 0;
1026
1027 pub = &chip->pub;
1028 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1029 base = cc->pub.base;
1030
1031
1032 pub->cc_caps = chip->ops->read32(chip->ctx,
1033 CORE_CC_REG(base, capabilities));
1034 pub->cc_caps_ext = chip->ops->read32(chip->ctx,
1035 CORE_CC_REG(base,
1036 capabilities_ext));
1037
1038
1039 pmu = brcmf_chip_get_pmu(pub);
1040 if (pub->cc_caps & CC_CAP_PMU) {
1041 val = chip->ops->read32(chip->ctx,
1042 CORE_CC_REG(pmu->base, pmucapabilities));
1043 pub->pmurev = val & PCAP_REV_MASK;
1044 pub->pmucaps = val;
1045 }
1046
1047 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
1048 cc->pub.rev, pub->pmurev, pub->pmucaps);
1049
1050
1051 if (chip->ops->setup)
1052 ret = chip->ops->setup(chip->ctx, pub);
1053
1054 return ret;
1055 }
1056
1057 struct brcmf_chip *brcmf_chip_attach(void *ctx,
1058 const struct brcmf_buscore_ops *ops)
1059 {
1060 struct brcmf_chip_priv *chip;
1061 int err = 0;
1062
1063 if (WARN_ON(!ops->read32))
1064 err = -EINVAL;
1065 if (WARN_ON(!ops->write32))
1066 err = -EINVAL;
1067 if (WARN_ON(!ops->prepare))
1068 err = -EINVAL;
1069 if (WARN_ON(!ops->activate))
1070 err = -EINVAL;
1071 if (err < 0)
1072 return ERR_PTR(-EINVAL);
1073
1074 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1075 if (!chip)
1076 return ERR_PTR(-ENOMEM);
1077
1078 INIT_LIST_HEAD(&chip->cores);
1079 chip->num_cores = 0;
1080 chip->ops = ops;
1081 chip->ctx = ctx;
1082
1083 err = ops->prepare(ctx);
1084 if (err < 0)
1085 goto fail;
1086
1087 err = brcmf_chip_recognition(chip);
1088 if (err < 0)
1089 goto fail;
1090
1091 err = brcmf_chip_setup(chip);
1092 if (err < 0)
1093 goto fail;
1094
1095 return &chip->pub;
1096
1097 fail:
1098 brcmf_chip_detach(&chip->pub);
1099 return ERR_PTR(err);
1100 }
1101
1102 void brcmf_chip_detach(struct brcmf_chip *pub)
1103 {
1104 struct brcmf_chip_priv *chip;
1105 struct brcmf_core_priv *core;
1106 struct brcmf_core_priv *tmp;
1107
1108 chip = container_of(pub, struct brcmf_chip_priv, pub);
1109 list_for_each_entry_safe(core, tmp, &chip->cores, list) {
1110 list_del(&core->list);
1111 kfree(core);
1112 }
1113 kfree(chip);
1114 }
1115
1116 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
1117 {
1118 struct brcmf_chip_priv *chip;
1119 struct brcmf_core_priv *core;
1120
1121 chip = container_of(pub, struct brcmf_chip_priv, pub);
1122 list_for_each_entry(core, &chip->cores, list)
1123 if (core->pub.id == coreid)
1124 return &core->pub;
1125
1126 return NULL;
1127 }
1128
1129 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
1130 {
1131 struct brcmf_chip_priv *chip;
1132 struct brcmf_core_priv *cc;
1133
1134 chip = container_of(pub, struct brcmf_chip_priv, pub);
1135 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1136 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
1137 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
1138 return &cc->pub;
1139 }
1140
1141 struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub)
1142 {
1143 struct brcmf_core *cc = brcmf_chip_get_chipcommon(pub);
1144 struct brcmf_core *pmu;
1145
1146
1147 if (cc->rev >= 35 &&
1148 pub->cc_caps_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
1149 pmu = brcmf_chip_get_core(pub, BCMA_CORE_PMU);
1150 if (pmu)
1151 return pmu;
1152 }
1153
1154
1155 return cc;
1156 }
1157
1158 bool brcmf_chip_iscoreup(struct brcmf_core *pub)
1159 {
1160 struct brcmf_core_priv *core;
1161
1162 core = container_of(pub, struct brcmf_core_priv, pub);
1163 return core->chip->iscoreup(core);
1164 }
1165
1166 void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
1167 {
1168 struct brcmf_core_priv *core;
1169
1170 core = container_of(pub, struct brcmf_core_priv, pub);
1171 core->chip->coredisable(core, prereset, reset);
1172 }
1173
1174 void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
1175 u32 postreset)
1176 {
1177 struct brcmf_core_priv *core;
1178
1179 core = container_of(pub, struct brcmf_core_priv, pub);
1180 core->chip->resetcore(core, prereset, reset, postreset);
1181 }
1182
1183 static void
1184 brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip)
1185 {
1186 struct brcmf_core *core;
1187 struct brcmf_core_priv *sr;
1188
1189 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
1190 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1191 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1192 D11_BCMA_IOCTL_PHYCLOCKEN,
1193 D11_BCMA_IOCTL_PHYCLOCKEN,
1194 D11_BCMA_IOCTL_PHYCLOCKEN);
1195 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1196 brcmf_chip_resetcore(core, 0, 0, 0);
1197
1198
1199 if (chip->pub.chip == BRCM_CC_43430_CHIP_ID) {
1200 sr = container_of(core, struct brcmf_core_priv, pub);
1201 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankidx), 3);
1202 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankpda), 0);
1203 }
1204 }
1205
1206 static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip)
1207 {
1208 struct brcmf_core *core;
1209
1210 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1211 if (!brcmf_chip_iscoreup(core)) {
1212 brcmf_err("SOCRAM core is down after reset?\n");
1213 return false;
1214 }
1215
1216 chip->ops->activate(chip->ctx, &chip->pub, 0);
1217
1218 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
1219 brcmf_chip_resetcore(core, 0, 0, 0);
1220
1221 return true;
1222 }
1223
1224 static inline void
1225 brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip)
1226 {
1227 struct brcmf_core *core;
1228
1229 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
1230
1231 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1232 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1233 D11_BCMA_IOCTL_PHYCLOCKEN,
1234 D11_BCMA_IOCTL_PHYCLOCKEN,
1235 D11_BCMA_IOCTL_PHYCLOCKEN);
1236 }
1237
1238 static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1239 {
1240 struct brcmf_core *core;
1241
1242 chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1243
1244
1245 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
1246 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1247
1248 return true;
1249 }
1250
1251 static inline void
1252 brcmf_chip_ca7_set_passive(struct brcmf_chip_priv *chip)
1253 {
1254 struct brcmf_core *core;
1255
1256 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CA7);
1257
1258 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1259 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1260 D11_BCMA_IOCTL_PHYCLOCKEN,
1261 D11_BCMA_IOCTL_PHYCLOCKEN,
1262 D11_BCMA_IOCTL_PHYCLOCKEN);
1263 }
1264
1265 static bool brcmf_chip_ca7_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1266 {
1267 struct brcmf_core *core;
1268
1269 chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1270
1271
1272 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CA7);
1273 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1274
1275 return true;
1276 }
1277
1278 void brcmf_chip_set_passive(struct brcmf_chip *pub)
1279 {
1280 struct brcmf_chip_priv *chip;
1281 struct brcmf_core *arm;
1282
1283 brcmf_dbg(TRACE, "Enter\n");
1284
1285 chip = container_of(pub, struct brcmf_chip_priv, pub);
1286 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1287 if (arm) {
1288 brcmf_chip_cr4_set_passive(chip);
1289 return;
1290 }
1291 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1292 if (arm) {
1293 brcmf_chip_ca7_set_passive(chip);
1294 return;
1295 }
1296 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1297 if (arm) {
1298 brcmf_chip_cm3_set_passive(chip);
1299 return;
1300 }
1301 }
1302
1303 bool brcmf_chip_set_active(struct brcmf_chip *pub, u32 rstvec)
1304 {
1305 struct brcmf_chip_priv *chip;
1306 struct brcmf_core *arm;
1307
1308 brcmf_dbg(TRACE, "Enter\n");
1309
1310 chip = container_of(pub, struct brcmf_chip_priv, pub);
1311 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1312 if (arm)
1313 return brcmf_chip_cr4_set_active(chip, rstvec);
1314 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1315 if (arm)
1316 return brcmf_chip_ca7_set_active(chip, rstvec);
1317 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1318 if (arm)
1319 return brcmf_chip_cm3_set_active(chip);
1320
1321 return false;
1322 }
1323
1324 bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
1325 {
1326 u32 base, addr, reg, pmu_cc3_mask = ~0;
1327 struct brcmf_chip_priv *chip;
1328 struct brcmf_core *pmu = brcmf_chip_get_pmu(pub);
1329
1330 brcmf_dbg(TRACE, "Enter\n");
1331
1332
1333 if (pub->pmurev < 17)
1334 return false;
1335
1336 base = brcmf_chip_get_chipcommon(pub)->base;
1337 chip = container_of(pub, struct brcmf_chip_priv, pub);
1338
1339 switch (pub->chip) {
1340 case BRCM_CC_4354_CHIP_ID:
1341 case BRCM_CC_4356_CHIP_ID:
1342 case BRCM_CC_4345_CHIP_ID:
1343
1344 pmu_cc3_mask = BIT(2);
1345
1346 case BRCM_CC_43241_CHIP_ID:
1347 case BRCM_CC_4335_CHIP_ID:
1348 case BRCM_CC_4339_CHIP_ID:
1349
1350 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
1351 chip->ops->write32(chip->ctx, addr, 3);
1352 addr = CORE_CC_REG(pmu->base, chipcontrol_data);
1353 reg = chip->ops->read32(chip->ctx, addr);
1354 return (reg & pmu_cc3_mask) != 0;
1355 case BRCM_CC_43430_CHIP_ID:
1356 addr = CORE_CC_REG(base, sr_control1);
1357 reg = chip->ops->read32(chip->ctx, addr);
1358 return reg != 0;
1359 case CY_CC_4373_CHIP_ID:
1360
1361 addr = CORE_CC_REG(base, sr_control0);
1362 reg = chip->ops->read32(chip->ctx, addr);
1363 return (reg & CC_SR_CTL0_ENABLE_MASK) != 0;
1364 case CY_CC_43012_CHIP_ID:
1365 addr = CORE_CC_REG(pmu->base, retention_ctl);
1366 reg = chip->ops->read32(chip->ctx, addr);
1367 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1368 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1369 default:
1370 addr = CORE_CC_REG(pmu->base, pmucapabilities_ext);
1371 reg = chip->ops->read32(chip->ctx, addr);
1372 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
1373 return false;
1374
1375 addr = CORE_CC_REG(pmu->base, retention_ctl);
1376 reg = chip->ops->read32(chip->ctx, addr);
1377 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1378 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1379 }
1380 }