1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef LINUX_B43_PHY_COMMON_H_
3 #define LINUX_B43_PHY_COMMON_H_
4
5 #include <linux/types.h>
6 #include <linux/nl80211.h>
7
8 struct b43_wldev;
9
10 /* PHY register routing bits */
11 #define B43_PHYROUTE 0x0C00 /* PHY register routing bits mask */
12 #define B43_PHYROUTE_BASE 0x0000 /* Base registers */
13 #define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */
14 #define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */
15 #define B43_PHYROUTE_N_BMODE 0x0C00 /* N-PHY BMODE registers */
16
17 /* CCK (B-PHY) registers. */
18 #define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE)
19 /* N-PHY registers. */
20 #define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE)
21 /* N-PHY BMODE registers. */
22 #define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE)
23 /* OFDM (A-PHY) registers. */
24 #define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY)
25 /* Extended G-PHY registers. */
26 #define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY)
27
28
29 /* Masks for the PHY versioning registers. */
30 #define B43_PHYVER_ANALOG 0xF000
31 #define B43_PHYVER_ANALOG_SHIFT 12
32 #define B43_PHYVER_TYPE 0x0F00
33 #define B43_PHYVER_TYPE_SHIFT 8
34 #define B43_PHYVER_VERSION 0x00FF
35
36 /* PHY writes need to be flushed if we reach limit */
37 #define B43_MAX_WRITES_IN_ROW 24
38
39 /**
40 * enum b43_interference_mitigation - Interference Mitigation mode
41 *
42 * @B43_INTERFMODE_NONE: Disabled
43 * @B43_INTERFMODE_NONWLAN: Non-WLAN Interference Mitigation
44 * @B43_INTERFMODE_MANUALWLAN: WLAN Interference Mitigation
45 * @B43_INTERFMODE_AUTOWLAN: Automatic WLAN Interference Mitigation
46 */
47 enum b43_interference_mitigation {
48 B43_INTERFMODE_NONE,
49 B43_INTERFMODE_NONWLAN,
50 B43_INTERFMODE_MANUALWLAN,
51 B43_INTERFMODE_AUTOWLAN,
52 };
53
54 /* Antenna identifiers */
55 enum {
56 B43_ANTENNA0 = 0, /* Antenna 0 */
57 B43_ANTENNA1 = 1, /* Antenna 1 */
58 B43_ANTENNA_AUTO0 = 2, /* Automatic, starting with antenna 0 */
59 B43_ANTENNA_AUTO1 = 3, /* Automatic, starting with antenna 1 */
60 B43_ANTENNA2 = 4,
61 B43_ANTENNA3 = 8,
62
63 B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
64 B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
65 };
66
67 /**
68 * enum b43_txpwr_result - Return value for the recalc_txpower PHY op.
69 *
70 * @B43_TXPWR_RES_NEED_ADJUST: Values changed. Hardware adjustment is needed.
71 * @B43_TXPWR_RES_DONE: No more work to do. Everything is done.
72 */
73 enum b43_txpwr_result {
74 B43_TXPWR_RES_NEED_ADJUST,
75 B43_TXPWR_RES_DONE,
76 };
77
78 /**
79 * struct b43_phy_operations - Function pointers for PHY ops.
80 *
81 * @allocate: Allocate and initialise the PHY data structures.
82 * Must not be NULL.
83 * @free: Destroy and free the PHY data structures.
84 * Must not be NULL.
85 *
86 * @prepare_structs: Prepare the PHY data structures.
87 * The data structures allocated in @allocate are
88 * initialized here.
89 * Must not be NULL.
90 * @prepare_hardware: Prepare the PHY. This is called before b43_chip_init to
91 * do some early early PHY hardware init.
92 * Can be NULL, if not required.
93 * @init: Initialize the PHY.
94 * Must not be NULL.
95 * @exit: Shutdown the PHY.
96 * Can be NULL, if not required.
97 *
98 * @phy_read: Read from a PHY register.
99 * Must not be NULL.
100 * @phy_write: Write to a PHY register.
101 * Must not be NULL.
102 * @phy_maskset: Maskset a PHY register, taking shortcuts.
103 * If it is NULL, a generic algorithm is used.
104 * @radio_read: Read from a Radio register.
105 * Must not be NULL.
106 * @radio_write: Write to a Radio register.
107 * Must not be NULL.
108 *
109 * @supports_hwpctl: Returns a boolean whether Hardware Power Control
110 * is supported or not.
111 * If NULL, hwpctl is assumed to be never supported.
112 * @software_rfkill: Turn the radio ON or OFF.
113 * Possible state values are
114 * RFKILL_STATE_SOFT_BLOCKED or
115 * RFKILL_STATE_UNBLOCKED
116 * Must not be NULL.
117 * @switch_analog: Turn the Analog on/off.
118 * Must not be NULL.
119 * @switch_channel: Switch the radio to another channel.
120 * Must not be NULL.
121 * @get_default_chan: Just returns the default channel number.
122 * Must not be NULL.
123 * @set_rx_antenna: Set the antenna used for RX.
124 * Can be NULL, if not supported.
125 * @interf_mitigation: Switch the Interference Mitigation mode.
126 * Can be NULL, if not supported.
127 *
128 * @recalc_txpower: Recalculate the transmission power parameters.
129 * This callback has to recalculate the TX power settings,
130 * but does not need to write them to the hardware, yet.
131 * Returns enum b43_txpwr_result to indicate whether the hardware
132 * needs to be adjusted.
133 * If B43_TXPWR_NEED_ADJUST is returned, @adjust_txpower
134 * will be called later.
135 * If the parameter "ignore_tssi" is true, the TSSI values should
136 * be ignored and a recalculation of the power settings should be
137 * done even if the TSSI values did not change.
138 * This function may sleep, but should not.
139 * Must not be NULL.
140 * @adjust_txpower: Write the previously calculated TX power settings
141 * (from @recalc_txpower) to the hardware.
142 * This function may sleep.
143 * Can be NULL, if (and ONLY if) @recalc_txpower _always_
144 * returns B43_TXPWR_RES_DONE.
145 *
146 * @pwork_15sec: Periodic work. Called every 15 seconds.
147 * Can be NULL, if not required.
148 * @pwork_60sec: Periodic work. Called every 60 seconds.
149 * Can be NULL, if not required.
150 */
151 struct b43_phy_operations {
152 /* Initialisation */
153 int (*allocate)(struct b43_wldev *dev);
154 void (*free)(struct b43_wldev *dev);
155 void (*prepare_structs)(struct b43_wldev *dev);
156 int (*prepare_hardware)(struct b43_wldev *dev);
157 int (*init)(struct b43_wldev *dev);
158 void (*exit)(struct b43_wldev *dev);
159
160 /* Register access */
161 u16 (*phy_read)(struct b43_wldev *dev, u16 reg);
162 void (*phy_write)(struct b43_wldev *dev, u16 reg, u16 value);
163 void (*phy_maskset)(struct b43_wldev *dev, u16 reg, u16 mask, u16 set);
164 u16 (*radio_read)(struct b43_wldev *dev, u16 reg);
165 void (*radio_write)(struct b43_wldev *dev, u16 reg, u16 value);
166
167 /* Radio */
168 bool (*supports_hwpctl)(struct b43_wldev *dev);
169 void (*software_rfkill)(struct b43_wldev *dev, bool blocked);
170 void (*switch_analog)(struct b43_wldev *dev, bool on);
171 int (*switch_channel)(struct b43_wldev *dev, unsigned int new_channel);
172 unsigned int (*get_default_chan)(struct b43_wldev *dev);
173 void (*set_rx_antenna)(struct b43_wldev *dev, int antenna);
174 int (*interf_mitigation)(struct b43_wldev *dev,
175 enum b43_interference_mitigation new_mode);
176
177 /* Transmission power adjustment */
178 enum b43_txpwr_result (*recalc_txpower)(struct b43_wldev *dev,
179 bool ignore_tssi);
180 void (*adjust_txpower)(struct b43_wldev *dev);
181
182 /* Misc */
183 void (*pwork_15sec)(struct b43_wldev *dev);
184 void (*pwork_60sec)(struct b43_wldev *dev);
185 };
186
187 struct b43_phy_g;
188 struct b43_phy_n;
189 struct b43_phy_lp;
190 struct b43_phy_ht;
191 struct b43_phy_lcn;
192
193 struct b43_phy {
194 /* Hardware operation callbacks. */
195 const struct b43_phy_operations *ops;
196
197 /* Most hardware context information is stored in the standard-
198 * specific data structures pointed to by the pointers below.
199 * Only one of them is valid (the currently enabled PHY). */
200 #ifdef CONFIG_B43_DEBUG
201 /* No union for debug build to force NULL derefs in buggy code. */
202 struct {
203 #else
204 union {
205 #endif
206 /* G-PHY specific information */
207 struct b43_phy_g *g;
208 /* N-PHY specific information */
209 struct b43_phy_n *n;
210 /* LP-PHY specific information */
211 struct b43_phy_lp *lp;
212 /* HT-PHY specific information */
213 struct b43_phy_ht *ht;
214 /* LCN-PHY specific information */
215 struct b43_phy_lcn *lcn;
216 /* AC-PHY specific information */
217 struct b43_phy_ac *ac;
218 };
219
220 /* Band support flags. */
221 bool supports_2ghz;
222 bool supports_5ghz;
223
224 /* Is GMODE (2 GHz mode) bit enabled? */
225 bool gmode;
226
227 /* After power reset full init has to be performed */
228 bool do_full_init;
229
230 /* Analog Type */
231 u8 analog;
232 /* B43_PHYTYPE_ */
233 u8 type;
234 /* PHY revision number. */
235 u8 rev;
236
237 /* Count writes since last read */
238 u8 writes_counter;
239
240 /* Radio versioning */
241 u16 radio_manuf; /* Radio manufacturer */
242 u16 radio_ver; /* Radio version */
243 u8 radio_rev; /* Radio revision */
244
245 /* Software state of the radio */
246 bool radio_on;
247
248 /* Desired TX power level (in dBm).
249 * This is set by the user and adjusted in b43_phy_xmitpower(). */
250 int desired_txpower;
251
252 /* Hardware Power Control enabled? */
253 bool hardware_power_control;
254
255 /* The time (in absolute jiffies) when the next TX power output
256 * check is needed. */
257 unsigned long next_txpwr_check_time;
258
259 /* Current channel */
260 struct cfg80211_chan_def *chandef;
261 unsigned int channel;
262
263 /* PHY TX errors counter. */
264 atomic_t txerr_cnt;
265
266 #ifdef CONFIG_B43_DEBUG
267 /* PHY registers locked (w.r.t. firmware) */
268 bool phy_locked;
269 /* Radio registers locked (w.r.t. firmware) */
270 bool radio_locked;
271 #endif /* B43_DEBUG */
272 };
273
274
275 /**
276 * b43_phy_allocate - Allocate PHY structs
277 * Allocate the PHY data structures, based on the current dev->phy.type
278 */
279 int b43_phy_allocate(struct b43_wldev *dev);
280
281 /**
282 * b43_phy_free - Free PHY structs
283 */
284 void b43_phy_free(struct b43_wldev *dev);
285
286 /**
287 * b43_phy_init - Initialise the PHY
288 */
289 int b43_phy_init(struct b43_wldev *dev);
290
291 /**
292 * b43_phy_exit - Cleanup PHY
293 */
294 void b43_phy_exit(struct b43_wldev *dev);
295
296 /**
297 * b43_has_hardware_pctl - Hardware Power Control supported?
298 * Returns a boolean, whether hardware power control is supported.
299 */
300 bool b43_has_hardware_pctl(struct b43_wldev *dev);
301
302 /**
303 * b43_phy_read - 16bit PHY register read access
304 */
305 u16 b43_phy_read(struct b43_wldev *dev, u16 reg);
306
307 /**
308 * b43_phy_write - 16bit PHY register write access
309 */
310 void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value);
311
312 /**
313 * b43_phy_copy - copy contents of 16bit PHY register to another
314 */
315 void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg);
316
317 /**
318 * b43_phy_mask - Mask a PHY register with a mask
319 */
320 void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask);
321
322 /**
323 * b43_phy_set - OR a PHY register with a bitmap
324 */
325 void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set);
326
327 /**
328 * b43_phy_maskset - Mask and OR a PHY register with a mask and bitmap
329 */
330 void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
331
332 /**
333 * b43_radio_read - 16bit Radio register read access
334 */
335 u16 b43_radio_read(struct b43_wldev *dev, u16 reg);
336 #define b43_radio_read16 b43_radio_read /* DEPRECATED */
337
338 /**
339 * b43_radio_write - 16bit Radio register write access
340 */
341 void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value);
342 #define b43_radio_write16 b43_radio_write /* DEPRECATED */
343
344 /**
345 * b43_radio_mask - Mask a 16bit radio register with a mask
346 */
347 void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask);
348
349 /**
350 * b43_radio_set - OR a 16bit radio register with a bitmap
351 */
352 void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set);
353
354 /**
355 * b43_radio_maskset - Mask and OR a radio register with a mask and bitmap
356 */
357 void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
358
359 /**
360 * b43_radio_wait_value - Waits for a given value in masked register read
361 */
362 bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
363 u16 value, int delay, int timeout);
364
365 /**
366 * b43_radio_lock - Lock firmware radio register access
367 */
368 void b43_radio_lock(struct b43_wldev *dev);
369
370 /**
371 * b43_radio_unlock - Unlock firmware radio register access
372 */
373 void b43_radio_unlock(struct b43_wldev *dev);
374
375 /**
376 * b43_phy_lock - Lock firmware PHY register access
377 */
378 void b43_phy_lock(struct b43_wldev *dev);
379
380 /**
381 * b43_phy_unlock - Unlock firmware PHY register access
382 */
383 void b43_phy_unlock(struct b43_wldev *dev);
384
385 void b43_phy_put_into_reset(struct b43_wldev *dev);
386 void b43_phy_take_out_of_reset(struct b43_wldev *dev);
387
388 /**
389 * b43_switch_channel - Switch to another channel
390 */
391 int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel);
392
393 /**
394 * b43_software_rfkill - Turn the radio ON or OFF in software.
395 */
396 void b43_software_rfkill(struct b43_wldev *dev, bool blocked);
397
398 /**
399 * b43_phy_txpower_check - Check TX power output.
400 *
401 * Compare the current TX power output to the desired power emission
402 * and schedule an adjustment in case it mismatches.
403 *
404 * @flags: OR'ed enum b43_phy_txpower_check_flags flags.
405 * See the docs below.
406 */
407 void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags);
408 /**
409 * enum b43_phy_txpower_check_flags - Flags for b43_phy_txpower_check()
410 *
411 * @B43_TXPWR_IGNORE_TIME: Ignore the schedule time and force-redo
412 * the check now.
413 * @B43_TXPWR_IGNORE_TSSI: Redo the recalculation, even if the average
414 * TSSI did not change.
415 */
416 enum b43_phy_txpower_check_flags {
417 B43_TXPWR_IGNORE_TIME = (1 << 0),
418 B43_TXPWR_IGNORE_TSSI = (1 << 1),
419 };
420
421 struct work_struct;
422 void b43_phy_txpower_adjust_work(struct work_struct *work);
423
424 /**
425 * b43_phy_shm_tssi_read - Read the average of the last 4 TSSI from SHM.
426 *
427 * @shm_offset: The SHM address to read the values from.
428 *
429 * Returns the average of the 4 TSSI values, or a negative error code.
430 */
431 int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset);
432
433 /**
434 * b43_phy_switch_analog_generic - Generic PHY operation for switching the Analog.
435 *
436 * It does the switching based on the PHY0 core register.
437 * Do _not_ call this directly. Only use it as a switch_analog callback
438 * for struct b43_phy_operations.
439 */
440 void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on);
441
442 bool b43_is_40mhz(struct b43_wldev *dev);
443
444 void b43_phy_force_clock(struct b43_wldev *dev, bool force);
445
446 #endif /* LINUX_B43_PHY_COMMON_H_ */