root/drivers/net/wireless/broadcom/b43/dma.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. b43_dma_read
  2. b43_dma_write
   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef B43_DMA_H_
   3 #define B43_DMA_H_
   4 
   5 #include <linux/err.h>
   6 
   7 #include "b43.h"
   8 
   9 
  10 /* DMA-Interrupt reasons. */
  11 #define B43_DMAIRQ_FATALMASK    ((1 << 10) | (1 << 11) | (1 << 12) \
  12                                          | (1 << 14) | (1 << 15))
  13 #define B43_DMAIRQ_RDESC_UFLOW          (1 << 13)
  14 #define B43_DMAIRQ_RX_DONE              (1 << 16)
  15 
  16 /*** 32-bit DMA Engine. ***/
  17 
  18 /* 32-bit DMA controller registers. */
  19 #define B43_DMA32_TXCTL                         0x00
  20 #define         B43_DMA32_TXENABLE                      0x00000001
  21 #define         B43_DMA32_TXSUSPEND                     0x00000002
  22 #define         B43_DMA32_TXLOOPBACK            0x00000004
  23 #define         B43_DMA32_TXFLUSH                       0x00000010
  24 #define         B43_DMA32_TXPARITYDISABLE               0x00000800
  25 #define         B43_DMA32_TXADDREXT_MASK                0x00030000
  26 #define         B43_DMA32_TXADDREXT_SHIFT               16
  27 #define B43_DMA32_TXRING                                0x04
  28 #define B43_DMA32_TXINDEX                               0x08
  29 #define B43_DMA32_TXSTATUS                              0x0C
  30 #define         B43_DMA32_TXDPTR                        0x00000FFF
  31 #define         B43_DMA32_TXSTATE                       0x0000F000
  32 #define                 B43_DMA32_TXSTAT_DISABLED       0x00000000
  33 #define                 B43_DMA32_TXSTAT_ACTIVE 0x00001000
  34 #define                 B43_DMA32_TXSTAT_IDLEWAIT       0x00002000
  35 #define                 B43_DMA32_TXSTAT_STOPPED        0x00003000
  36 #define                 B43_DMA32_TXSTAT_SUSP   0x00004000
  37 #define         B43_DMA32_TXERROR                       0x000F0000
  38 #define                 B43_DMA32_TXERR_NOERR   0x00000000
  39 #define                 B43_DMA32_TXERR_PROT    0x00010000
  40 #define                 B43_DMA32_TXERR_UNDERRUN        0x00020000
  41 #define                 B43_DMA32_TXERR_BUFREAD 0x00030000
  42 #define                 B43_DMA32_TXERR_DESCREAD        0x00040000
  43 #define         B43_DMA32_TXACTIVE                      0xFFF00000
  44 #define B43_DMA32_RXCTL                         0x10
  45 #define         B43_DMA32_RXENABLE                      0x00000001
  46 #define         B43_DMA32_RXFROFF_MASK          0x000000FE
  47 #define         B43_DMA32_RXFROFF_SHIFT         1
  48 #define         B43_DMA32_RXDIRECTFIFO          0x00000100
  49 #define         B43_DMA32_RXPARITYDISABLE               0x00000800
  50 #define         B43_DMA32_RXADDREXT_MASK                0x00030000
  51 #define         B43_DMA32_RXADDREXT_SHIFT               16
  52 #define B43_DMA32_RXRING                                0x14
  53 #define B43_DMA32_RXINDEX                               0x18
  54 #define B43_DMA32_RXSTATUS                              0x1C
  55 #define         B43_DMA32_RXDPTR                        0x00000FFF
  56 #define         B43_DMA32_RXSTATE                       0x0000F000
  57 #define                 B43_DMA32_RXSTAT_DISABLED       0x00000000
  58 #define                 B43_DMA32_RXSTAT_ACTIVE 0x00001000
  59 #define                 B43_DMA32_RXSTAT_IDLEWAIT       0x00002000
  60 #define                 B43_DMA32_RXSTAT_STOPPED        0x00003000
  61 #define         B43_DMA32_RXERROR                       0x000F0000
  62 #define                 B43_DMA32_RXERR_NOERR   0x00000000
  63 #define                 B43_DMA32_RXERR_PROT    0x00010000
  64 #define                 B43_DMA32_RXERR_OVERFLOW        0x00020000
  65 #define                 B43_DMA32_RXERR_BUFWRITE        0x00030000
  66 #define                 B43_DMA32_RXERR_DESCREAD        0x00040000
  67 #define         B43_DMA32_RXACTIVE                      0xFFF00000
  68 
  69 /* 32-bit DMA descriptor. */
  70 struct b43_dmadesc32 {
  71         __le32 control;
  72         __le32 address;
  73 } __packed;
  74 #define B43_DMA32_DCTL_BYTECNT          0x00001FFF
  75 #define B43_DMA32_DCTL_ADDREXT_MASK             0x00030000
  76 #define B43_DMA32_DCTL_ADDREXT_SHIFT    16
  77 #define B43_DMA32_DCTL_DTABLEEND                0x10000000
  78 #define B43_DMA32_DCTL_IRQ                      0x20000000
  79 #define B43_DMA32_DCTL_FRAMEEND         0x40000000
  80 #define B43_DMA32_DCTL_FRAMESTART               0x80000000
  81 
  82 /*** 64-bit DMA Engine. ***/
  83 
  84 /* 64-bit DMA controller registers. */
  85 #define B43_DMA64_TXCTL                         0x00
  86 #define         B43_DMA64_TXENABLE                      0x00000001
  87 #define         B43_DMA64_TXSUSPEND                     0x00000002
  88 #define         B43_DMA64_TXLOOPBACK            0x00000004
  89 #define         B43_DMA64_TXFLUSH                       0x00000010
  90 #define         B43_DMA64_TXPARITYDISABLE               0x00000800
  91 #define         B43_DMA64_TXADDREXT_MASK                0x00030000
  92 #define         B43_DMA64_TXADDREXT_SHIFT               16
  93 #define B43_DMA64_TXINDEX                               0x04
  94 #define B43_DMA64_TXRINGLO                              0x08
  95 #define B43_DMA64_TXRINGHI                              0x0C
  96 #define B43_DMA64_TXSTATUS                              0x10
  97 #define         B43_DMA64_TXSTATDPTR            0x00001FFF
  98 #define         B43_DMA64_TXSTAT                        0xF0000000
  99 #define                 B43_DMA64_TXSTAT_DISABLED       0x00000000
 100 #define                 B43_DMA64_TXSTAT_ACTIVE 0x10000000
 101 #define                 B43_DMA64_TXSTAT_IDLEWAIT       0x20000000
 102 #define                 B43_DMA64_TXSTAT_STOPPED        0x30000000
 103 #define                 B43_DMA64_TXSTAT_SUSP   0x40000000
 104 #define B43_DMA64_TXERROR                               0x14
 105 #define         B43_DMA64_TXERRDPTR                     0x0001FFFF
 106 #define         B43_DMA64_TXERR                 0xF0000000
 107 #define                 B43_DMA64_TXERR_NOERR   0x00000000
 108 #define                 B43_DMA64_TXERR_PROT    0x10000000
 109 #define                 B43_DMA64_TXERR_UNDERRUN        0x20000000
 110 #define                 B43_DMA64_TXERR_TRANSFER        0x30000000
 111 #define                 B43_DMA64_TXERR_DESCREAD        0x40000000
 112 #define                 B43_DMA64_TXERR_CORE    0x50000000
 113 #define B43_DMA64_RXCTL                         0x20
 114 #define         B43_DMA64_RXENABLE                      0x00000001
 115 #define         B43_DMA64_RXFROFF_MASK          0x000000FE
 116 #define         B43_DMA64_RXFROFF_SHIFT         1
 117 #define         B43_DMA64_RXDIRECTFIFO          0x00000100
 118 #define         B43_DMA64_RXPARITYDISABLE               0x00000800
 119 #define         B43_DMA64_RXADDREXT_MASK                0x00030000
 120 #define         B43_DMA64_RXADDREXT_SHIFT               16
 121 #define B43_DMA64_RXINDEX                               0x24
 122 #define B43_DMA64_RXRINGLO                              0x28
 123 #define B43_DMA64_RXRINGHI                              0x2C
 124 #define B43_DMA64_RXSTATUS                              0x30
 125 #define         B43_DMA64_RXSTATDPTR            0x00001FFF
 126 #define         B43_DMA64_RXSTAT                        0xF0000000
 127 #define                 B43_DMA64_RXSTAT_DISABLED       0x00000000
 128 #define                 B43_DMA64_RXSTAT_ACTIVE 0x10000000
 129 #define                 B43_DMA64_RXSTAT_IDLEWAIT       0x20000000
 130 #define                 B43_DMA64_RXSTAT_STOPPED        0x30000000
 131 #define                 B43_DMA64_RXSTAT_SUSP   0x40000000
 132 #define B43_DMA64_RXERROR                               0x34
 133 #define         B43_DMA64_RXERRDPTR                     0x0001FFFF
 134 #define         B43_DMA64_RXERR                 0xF0000000
 135 #define                 B43_DMA64_RXERR_NOERR   0x00000000
 136 #define                 B43_DMA64_RXERR_PROT    0x10000000
 137 #define                 B43_DMA64_RXERR_UNDERRUN        0x20000000
 138 #define                 B43_DMA64_RXERR_TRANSFER        0x30000000
 139 #define                 B43_DMA64_RXERR_DESCREAD        0x40000000
 140 #define                 B43_DMA64_RXERR_CORE    0x50000000
 141 
 142 /* 64-bit DMA descriptor. */
 143 struct b43_dmadesc64 {
 144         __le32 control0;
 145         __le32 control1;
 146         __le32 address_low;
 147         __le32 address_high;
 148 } __packed;
 149 #define B43_DMA64_DCTL0_DTABLEEND               0x10000000
 150 #define B43_DMA64_DCTL0_IRQ                     0x20000000
 151 #define B43_DMA64_DCTL0_FRAMEEND                0x40000000
 152 #define B43_DMA64_DCTL0_FRAMESTART              0x80000000
 153 #define B43_DMA64_DCTL1_BYTECNT         0x00001FFF
 154 #define B43_DMA64_DCTL1_ADDREXT_MASK    0x00030000
 155 #define B43_DMA64_DCTL1_ADDREXT_SHIFT   16
 156 
 157 struct b43_dmadesc_generic {
 158         union {
 159                 struct b43_dmadesc32 dma32;
 160                 struct b43_dmadesc64 dma64;
 161         } __packed;
 162 } __packed;
 163 
 164 /* Misc DMA constants */
 165 #define B43_DMA32_RINGMEMSIZE           4096
 166 #define B43_DMA64_RINGMEMSIZE           8192
 167 /* Offset of frame with actual data */
 168 #define B43_DMA0_RX_FW598_FO            38
 169 #define B43_DMA0_RX_FW351_FO            30
 170 
 171 /* DMA engine tuning knobs */
 172 #define B43_TXRING_SLOTS                256
 173 #define B43_RXRING_SLOTS                256
 174 #define B43_DMA0_RX_FW598_BUFSIZE       (B43_DMA0_RX_FW598_FO + IEEE80211_MAX_FRAME_LEN)
 175 #define B43_DMA0_RX_FW351_BUFSIZE       (B43_DMA0_RX_FW351_FO + IEEE80211_MAX_FRAME_LEN)
 176 
 177 /* Pointer poison */
 178 #define B43_DMA_PTR_POISON              ((void *)ERR_PTR(-ENOMEM))
 179 #define b43_dma_ptr_is_poisoned(ptr)    (unlikely((ptr) == B43_DMA_PTR_POISON))
 180 
 181 
 182 struct sk_buff;
 183 struct b43_private;
 184 struct b43_txstatus;
 185 
 186 struct b43_dmadesc_meta {
 187         /* The kernel DMA-able buffer. */
 188         struct sk_buff *skb;
 189         /* DMA base bus-address of the descriptor buffer. */
 190         dma_addr_t dmaaddr;
 191         /* ieee80211 TX status. Only used once per 802.11 frag. */
 192         bool is_last_fragment;
 193 };
 194 
 195 struct b43_dmaring;
 196 
 197 /* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
 198 struct b43_dma_ops {
 199         struct b43_dmadesc_generic *(*idx2desc) (struct b43_dmaring * ring,
 200                                                  int slot,
 201                                                  struct b43_dmadesc_meta **
 202                                                  meta);
 203         void (*fill_descriptor) (struct b43_dmaring * ring,
 204                                  struct b43_dmadesc_generic * desc,
 205                                  dma_addr_t dmaaddr, u16 bufsize, int start,
 206                                  int end, int irq);
 207         void (*poke_tx) (struct b43_dmaring * ring, int slot);
 208         void (*tx_suspend) (struct b43_dmaring * ring);
 209         void (*tx_resume) (struct b43_dmaring * ring);
 210         int (*get_current_rxslot) (struct b43_dmaring * ring);
 211         void (*set_current_rxslot) (struct b43_dmaring * ring, int slot);
 212 };
 213 
 214 enum b43_dmatype {
 215         B43_DMA_30BIT   = 30,
 216         B43_DMA_32BIT   = 32,
 217         B43_DMA_64BIT   = 64,
 218 };
 219 
 220 enum b43_addrtype {
 221         B43_DMA_ADDR_LOW,
 222         B43_DMA_ADDR_HIGH,
 223         B43_DMA_ADDR_EXT,
 224 };
 225 
 226 struct b43_dmaring {
 227         /* Lowlevel DMA ops. */
 228         const struct b43_dma_ops *ops;
 229         /* Kernel virtual base address of the ring memory. */
 230         void *descbase;
 231         /* Meta data about all descriptors. */
 232         struct b43_dmadesc_meta *meta;
 233         /* Cache of TX headers for each TX frame.
 234          * This is to avoid an allocation on each TX.
 235          * This is NULL for an RX ring.
 236          */
 237         u8 *txhdr_cache;
 238         /* (Unadjusted) DMA base bus-address of the ring memory. */
 239         dma_addr_t dmabase;
 240         /* Number of descriptor slots in the ring. */
 241         int nr_slots;
 242         /* Number of used descriptor slots. */
 243         int used_slots;
 244         /* Currently used slot in the ring. */
 245         int current_slot;
 246         /* Frameoffset in octets. */
 247         u32 frameoffset;
 248         /* Descriptor buffer size. */
 249         u16 rx_buffersize;
 250         /* The MMIO base register of the DMA controller. */
 251         u16 mmio_base;
 252         /* DMA controller index number (0-5). */
 253         int index;
 254         /* Boolean. Is this a TX ring? */
 255         bool tx;
 256         /* The type of DMA engine used. */
 257         enum b43_dmatype type;
 258         /* Boolean. Is this ring stopped at ieee80211 level? */
 259         bool stopped;
 260         /* The QOS priority assigned to this ring. Only used for TX rings.
 261          * This is the mac80211 "queue" value. */
 262         u8 queue_prio;
 263         struct b43_wldev *dev;
 264 #ifdef CONFIG_B43_DEBUG
 265         /* Maximum number of used slots. */
 266         int max_used_slots;
 267         /* Last time we injected a ring overflow. */
 268         unsigned long last_injected_overflow;
 269         /* Statistics: Number of successfully transmitted packets */
 270         u64 nr_succeed_tx_packets;
 271         /* Statistics: Number of failed TX packets */
 272         u64 nr_failed_tx_packets;
 273         /* Statistics: Total number of TX plus all retries. */
 274         u64 nr_total_packet_tries;
 275 #endif /* CONFIG_B43_DEBUG */
 276 };
 277 
 278 static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset)
 279 {
 280         return b43_read32(ring->dev, ring->mmio_base + offset);
 281 }
 282 
 283 static inline void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value)
 284 {
 285         b43_write32(ring->dev, ring->mmio_base + offset, value);
 286 }
 287 
 288 int b43_dma_init(struct b43_wldev *dev);
 289 void b43_dma_free(struct b43_wldev *dev);
 290 
 291 void b43_dma_tx_suspend(struct b43_wldev *dev);
 292 void b43_dma_tx_resume(struct b43_wldev *dev);
 293 
 294 int b43_dma_tx(struct b43_wldev *dev,
 295                struct sk_buff *skb);
 296 void b43_dma_handle_txstatus(struct b43_wldev *dev,
 297                              const struct b43_txstatus *status);
 298 
 299 void b43_dma_handle_rx_overflow(struct b43_dmaring *ring);
 300 
 301 void b43_dma_rx(struct b43_dmaring *ring);
 302 
 303 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
 304                             unsigned int engine_index, bool enable);
 305 
 306 #endif /* B43_DMA_H_ */
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